JPS53136452A - Constituting method of pla - Google Patents

Constituting method of pla

Info

Publication number
JPS53136452A
JPS53136452A JP5072077A JP5072077A JPS53136452A JP S53136452 A JPS53136452 A JP S53136452A JP 5072077 A JP5072077 A JP 5072077A JP 5072077 A JP5072077 A JP 5072077A JP S53136452 A JPS53136452 A JP S53136452A
Authority
JP
Japan
Prior art keywords
pla
constituting method
signal
picking
inversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5072077A
Other languages
Japanese (ja)
Inventor
Toshimasa Kihara
Kiyoshi Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5072077A priority Critical patent/JPS53136452A/en
Publication of JPS53136452A publication Critical patent/JPS53136452A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the occupied area, by making the timing signal exclusive mutually and giving an OR function to the signal through inversion and addition to the AND circuit group, in a PLA picking up control outputs including time element with the AND and OR circuit groups.
JP5072077A 1977-05-04 1977-05-04 Constituting method of pla Pending JPS53136452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5072077A JPS53136452A (en) 1977-05-04 1977-05-04 Constituting method of pla

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5072077A JPS53136452A (en) 1977-05-04 1977-05-04 Constituting method of pla

Publications (1)

Publication Number Publication Date
JPS53136452A true JPS53136452A (en) 1978-11-29

Family

ID=12866706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5072077A Pending JPS53136452A (en) 1977-05-04 1977-05-04 Constituting method of pla

Country Status (1)

Country Link
JP (1) JPS53136452A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409499A (en) * 1982-06-14 1983-10-11 Standard Microsystems Corporation High-speed merged plane logic function array
US4516040A (en) * 1982-06-14 1985-05-07 Standard Microsystems Corporation High-speed merged plane logic function array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409499A (en) * 1982-06-14 1983-10-11 Standard Microsystems Corporation High-speed merged plane logic function array
US4516040A (en) * 1982-06-14 1985-05-07 Standard Microsystems Corporation High-speed merged plane logic function array

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