JPH1187651A - Semiconductor integrated circuit device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a storage electric charge amount of an information storage capacity element. SOLUTION: A capacitor C for information starage comprises a lower part electrode 27, a capacity insulating film 28 and a plate electrode 29, while the lower part electrode 27 comprises a blocking layer 27a, a lower part conductive layer 27b, and a pillar part 27c. The lower part conductive layer 27b is an amorphous iridium oxide, formed under a relatively low pressure (5mTorr) by a reaction spattering method with iridium as a target, while a mixed gas of argon and oxygen (1:1) as a raw material, and the pillar part 27c is a crystalline iridium formed under a relatively high pressure (20mTorr) by the same reactive sputtering method as above and selectively grown with a main orientation plane as plane (101). In the capacity insulating film 28, a tantalium oxide film formed by CVD method is heat treated in an oxygen atmosphere at 800 deg.C for 3 minutes for crystallization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
The present invention relates to a technology that is effective when applied to an increase in storage capacity of a random access memory (c).

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memory)
The ry) memory cells are arranged at intersections of a plurality of word lines and a plurality of bit lines arranged in a matrix on the main surface of the semiconductor substrate, and one memory cell selecting MISFET (M
etal Insulator SemiconductorField Effect Transisto
r) and one information storage capacitance element (capacitor) connected in series to this. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Have been. The bit line is arranged above the memory cell selecting MISFET,
Two memory cell selecting MISs adjacent in the extending direction
It is electrically connected to one of the source and drain shared by the FET. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

[0003] Japanese Patent Application Laid-Open No. 7-7084 discloses a capacitor over bit line (Capacitor Over Bitline) structure in which an information storage capacitor is arranged above a bit line.
A RAM is disclosed. DRAM described in this publication
The lower electrode (storage electrode) of the information storage capacitor disposed above the bit line is formed in a cylindrical shape in order to compensate for the decrease in the storage charge (Cs) of the information storage capacitor accompanying the miniaturization of the memory cell. The capacitance insulating film and the upper electrode (plate electrode) are formed thereon.

In Japanese Patent Application Nos. 62-198043 and 63-10635, a polycrystalline silicon film is used as a lower electrode of an information storage capacitor, and the polycrystalline silicon film is formed by a CVD method. At the initial stage of film formation, the phenomenon that granular silicon polycrystal grows depending on the surface condition of the base, or the phenomenon that unevenness occurs on the surface without wet etching of polycrystalline silicon film proceeding uniformly A technique has been disclosed in which minute irregularities are formed on the surface of an electrode to increase the surface area thereof and to secure a storage capacity.

[0005]

However, a method of increasing the surface area by forming the lower electrode of the information storage capacitor element into a cylindrical shape and increasing the surface area by forming minute irregularities on the surface is used. Even so, the demand for an increase in the degree of integration demands a further reduction in the memory cell area, which makes it difficult to secure a storage capacitance value. For this reason, it is necessary to further increase the surface area of the lower electrode. However, the increase in the height of the cylindrical shape makes it difficult to secure the mechanical strength of the lower electrode and the lower electrode between the memory cell array region and the peripheral circuit region. There is a problem due to the occurrence of a step due to the height of the surface, and there is naturally a limit. Also, the method of forming fine irregularities on the surface also has a limit depending on the surface state or physical properties of silicon.

As described above, there is a limit in coping with the shape of the lower electrode, so it is necessary to cope with the material. In other words, this is a measure to use a material having a higher dielectric constant than the silicon oxynitride film conventionally used for the capacitive insulating film of the information storage capacitive element. For example, a measure to use a tantalum oxide film for the capacitive insulating film has been studied. I have.

However, a tantalum oxide film is formed by a CVD method, and in an as-deposited state (a state immediately after the film formation), a large number of oxygen defects are present and a leak current is remarkable. Therefore, it is necessary to recover the oxygen deficiency of the tantalum oxide film by performing a heat treatment in an oxygen atmosphere after the film formation, and to reduce the leak current.

However, when such a heat treatment in an oxidizing atmosphere is applied to a case where a silicon material is used as the lower electrode, the silicon surface, which is a base material of the tantalum oxide film, is also oxidized and becomes a lower electrode. A silicon oxide film is formed between the polycrystalline silicon film and the tantalum oxide film serving as the capacitor insulating film. Such a silicon oxide film acts as a low-dielectric-constant insulating film, increases the substantial thickness of the capacitive insulating film, and lowers the substantial dielectric constant of the capacitive insulating film, thereby reducing the amount of accumulated charges. There is a problem.

It is an object of the present invention to increase the amount of charge stored in an information storage capacitor.

Another object of the present invention is to use a tantalum oxide film as a capacitive insulating film of an information storage capacitor element and to effectively reduce the dielectric constant of the capacitive insulating film and reduce the film thickness even when heat treatment is performed in an oxygen atmosphere. It is to provide a technology that does not increase.

Another object of the present invention is to provide a technique for increasing the surface area of the lower electrode of the information storage capacitor.

Another object of the present invention is to provide a technique capable of simplifying the process of forming the lower electrode of the information storage capacitor.

Another object of the present invention is to reduce the voltage and power of a semiconductor integrated circuit device by increasing the amount of charge stored in an information storage capacitor and increasing the refresh margin of a DRAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention provides a memory cell selecting MIS formed on a main surface of a semiconductor substrate.
Information comprising a lower electrode connected in series to the FET, a lower electrode, a capacitive insulating film mainly composed of tantalum oxide formed in contact with the lower electrode, and an upper electrode formed opposite the lower electrode via the capacitive insulating film. A semiconductor integrated circuit device having a storage capacitor element, wherein a lower electrode has a plurality of columnar portions made of iridium oxide and a conductive film located at the bottom of the columnar portion.

According to such a semiconductor integrated circuit device,
The lower electrode is composed of a plurality of columnar portions made of iridium oxide and a conductive film located at the bottom of the columnar portion. By forming the columnar portions, the surface area of the lower electrode is improved, and the amount of charge stored in the information storage capacitor element is increased. Can be increased.

Also, the conductive film can be made of the same iridium oxide as the columnar portion, and in this case, the lower electrode can be made of iridium oxide. By forming the lower electrode from a metal oxide instead of a silicon material in this way, as described later, a tantalum oxide film is used as a capacitive insulating film, and the lower electrode is not oxidized even if heat treatment is performed in an oxygen atmosphere of the tantalum oxide film. No insulating film such as silicon oxide is formed at the interface with the tantalum film, the dielectric constant of the capacitive insulating film is maintained at a high dielectric constant inherent to tantalum oxide, and the substantial thickness of the capacitive insulating film is also oxidized. The thickness of the tantalum film can be maintained at a specific value, and the amount of charge stored in the information storage capacitor can be increased.

Incidentally, such a columnar portion can be made of polycrystalline iridium oxide whose main orientation plane is the (101) plane.

Further, such a columnar polycrystalline iridium oxide can be formed by a reactive sputtering method using iridium as a target and a gas containing oxygen.

A blocking film containing titanium nitride or tungsten nitride as a main component can be formed between the plug and the conductive film that connect the memory cell selection MISFET and the lower electrode. In this case, even when a plug mainly composed of polycrystalline silicon is formed, the blocking film mainly composed of titanium nitride or tungsten nitride is formed. It is not oxidized. Further, the plug connecting the memory cell selection MISFET and the lower electrode can be made of a conductor mainly composed of titanium nitride or tungsten nitride. In such a case,
During the heat treatment of the tantalum oxide film in an oxygen atmosphere,
Since the plug is made of a conductor mainly containing titanium nitride or tungsten nitride, it is not necessary to consider oxidation of the plug. Thus, electrical connection between the plug and the lower electrode of the information storage capacitor can be ensured.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a lower electrode, a capacitor insulating film, and an upper electrode which are connected in series to a memory cell selecting MISFET formed on a main surface of a semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device having an information storage capacitor element, comprising: (a) a memory cell selecting MISF on an interlayer insulating film on an upper layer of a semiconductor substrate;
A plug connected to the ET is formed, and an iridium oxide film is deposited on the entire surface of the interlayer insulating film where the surface of the plug is exposed by a reactive sputtering method using iridium as a target and a gas containing oxygen under the first pressure condition. And (b) oxidizing at least a plurality of columnar bodies made of polycrystalline iridium oxide by a reactive sputtering method using iridium as a target and oxygen-containing gas under a second pressure condition higher than the first pressure condition. And (c) depositing a tantalum oxide film on at least the columnar body and forming a capacitive insulating film by heat treatment of the tantalum oxide film in an oxygen atmosphere.

According to such a method of manufacturing a semiconductor integrated circuit device, an iridium oxide film is formed by a reactive sputtering method using an iridium target and a gas containing oxygen under a first pressure condition, for example, a relatively low pressure condition such as 5 mTorr. By depositing, an amorphous iridium oxide film having high conductivity but low crystallinity can be deposited. Such an iridium oxide film is flat,
The conductive film may form the bottom of the lower electrode.
In addition, a plurality of columnar bodies made of polycrystalline iridium oxide are formed by performing a reactive sputtering method using iridium as a target and oxygen-containing gas under a second pressure condition higher than the first pressure condition, for example, 20 mTorr. Can be formed on the conductive film constituting the bottom of the lower electrode. The fact that iridium oxide becomes a polycrystalline columnar body at a relatively high pressure has been clarified by experimental studies by the present inventors, and the improvement of iridium oxide crystallinity due to an increase in oxygen partial pressure has been clarified. This is considered to be the result of selective crystal growth caused by In such crystal growth, the main orientation plane of polycrystalline iridium oxide is the (101) plane. Under such sputtering conditions, a columnar body of polycrystalline iridium oxide can be formed. Such a columnar body constitutes a lower electrode to increase its surface area and increase the amount of charge stored in the information storage capacitor. be able to.

The patterning step for forming the lower electrode may be performed after the step (a) or after the step (b).
Any after the step may be used.

In the method of manufacturing a semiconductor integrated circuit device, the plug may be made of a conductor made of titanium nitride or tungsten nitride, and the plug may be made of polycrystalline silicon, and the interlayer insulating film may be formed before depositing the iridium oxide film. The method may include a step of depositing a titanium nitride film or a tungsten nitride film on the entire surface of the film. In such a case,
In the heat treatment of the tantalum oxide film in the oxygen atmosphere in the step (c), oxidation of the plug is prevented, and the electrical connection between the information storage capacitor and the memory cell selection MISFET can be ensured.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM of the present embodiment is formed. As shown in the drawing, the main surface of the semiconductor chip 1A made of single crystal silicon has X
A large number of memory arrays MARY are arranged in a matrix along the direction (the long side direction of the semiconductor chip 1A) and the Y direction (the short side direction of the semiconductor chip 1A). A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. In the center of the main surface of the semiconductor chip 1A, control circuits such as a word driver WD and a data line selection circuit, input / output circuits, and bonding pads are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WL _n−1 , WL _n , WL _{n + 1} ...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one capacitor C and one memory cell selecting MISFET connected in series with the capacitor C.
Qs. MISFE for memory cell selection
One of a source and a drain of TQs is electrically connected to the capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD.
And one end of the bit line BL is connected to the sense amplifier SA.
It is connected to the.

FIG. 3 is a sectional view of the DRAM of the present embodiment. On a main surface of a semiconductor substrate 1 made of p-type single crystal silicon, a p-type well 2 in a memory cell array region, a p-type well 3 in a peripheral circuit region, and an n-type well 4 are formed. Further, an n-type deep well 6 is formed so as to surround the p-type well 2. Note that a threshold voltage adjustment layer may be formed in each well.

An isolation region 7 is formed on the main surface of each well. The isolation region 7 is made of a silicon oxide film and is formed in a shallow groove 8 formed on the main surface of the semiconductor substrate 1 via a thermally oxidized silicon oxide film 9.

On the main surface of the p-type well 2, a MISFET Qs for selecting a memory cell of a DRAM is formed. Also,
The main surfaces of the p-type well 3 and the n-type well 4 are respectively provided with an n-channel MISFET Qn and a p-channel MISFET Q
p is formed.

The memory cell selection MISFET Qs is p
A gate electrode 11 is formed on the main surface of the p-type well 2 via a gate insulating film 10, and an impurity semiconductor region 12 is formed on the main surface of the p-type well 2 on both sides of the gate electrode 11. Gate insulating film 10 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation. The gate electrode 11 is made of, for example, a polycrystalline silicon film 11a having a thickness of 70 nm and a titanium nitride film 11b having a thickness of 50 nm.
And a stacked film of the tungsten film 11c having a thickness of 100 nm. In addition, an n-type impurity, for example, arsenic or phosphorus is introduced into impurity semiconductor region 12.

A cap insulating film 13 made of a silicon nitride film is formed on the gate electrode 11 of the memory cell selection MISFET Qs, and the upper layer is covered with a silicon nitride film 14. The silicon nitride film 14 is also formed on the side wall of the gate electrode 11, and is used for a self-alignment process when forming a connection hole described later. The gate electrode 11 of the memory cell selection MISFET Qs functions as a DRAM word line, and a word line WL is formed on the upper surface of the isolation region 7.

On the other hand, n-channel MISFET Qn and p-channel MISFET Qp are formed on the main surfaces of p-type well 3 and n-type well 4, respectively.
A gate electrode 11 formed through the gate electrode 11
And impurity semiconductor regions 15 formed on the main surface of each well on both sides of the semiconductor device. The gate insulating film 10 and the gate electrode 11 are the same as described above. The impurity semiconductor region 15 includes a low-concentration impurity region 15a and a high-concentration impurity region 15b, and forms a so-called LDD (Lightly Doped Drain) structure. As the impurity introduced into the impurity semiconductor region 15, an n-type or p-type impurity is introduced depending on the conductivity type of the MISFET.

A cap insulating film 13 made of a silicon nitride film is formed on the gate electrode 11 of the n-channel MISFET Qn and the p-channel MISFET Qp, and a sidewall spacer 16 made of, for example, a silicon nitride film is formed on the side surface. .

Memory cell selecting MISFET Qs, n-channel MISFET Qn and p-channel MISFET
Qp is covered with an interlayer insulating film 17. Interlayer insulating film 1
7 is, for example, an SOG (Spin On Glass) film 17a, T
A silicon oxide film (hereinafter referred to as TE) formed by a plasma CVD method using EOS (tetramethoxysilane) as a source gas.
OS oxide film) is a CMP (Chemical Mechanical Po
TEOS oxide film 17b planarized by the lishing) method
And a laminated film of TEOS oxide films 17c and 17d.

On the interlayer insulating film 17, a bit line BL and a first layer wiring 18 are formed. The bit line BL and the first layer wiring 18 can be, for example, a laminated film of a titanium film 18a, a titanium nitride film 18b, and a tungsten film 18c. As a result, the resistance of the bit line BL and the first layer wiring 18 can be reduced, and the performance of the DRAM can be improved. The bit line BL and the first layer wiring 18 are
They are formed at the same time as described later. Thereby, the process can be simplified.

The bit line BL is connected via a plug 19 to the impurity semiconductor region 12 shared by a pair of memory cell selecting MISFETs Qs. Plug 19 can be, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. In addition, a titanium silicide layer 20 is formed at a connection between the plug 19 and the bit line BL. Thereby, the connection resistance between the bit line BL and the plug 19 can be reduced, and the connection reliability can be improved.

The first layer wiring 18 is connected to the n
Channel MISFET Qn and p channel MISFE
It is connected to impurity semiconductor region 15 of TQp. Further, a titanium silicide layer 20 is formed at a connection portion between the first-layer wiring 18 and the impurity semiconductor region 15. Thereby, the connection resistance between the first layer wiring 18 and the impurity semiconductor region 15 can be reduced, and the connection reliability can be improved.

The bit line BL and the first layer wiring 18 are covered with a cap insulating film 22a and a sidewall spacer 22b made of a silicon nitride film.
Covered with 3. The interlayer insulating film 23 is made of, for example, SOG
The film 23a can be a laminated film of the TEOS oxide film 23b and the TEOS oxide film 23c planarized by the CMP method.

A capacitor C for storing information is formed in the memory cell array region above the interlayer insulating film 23.
An insulating film 24 is formed on the interlayer insulating film 23 in the peripheral circuit region in the same layer as the capacitor C. Insulating film 2
Numeral 4 may be, for example, a silicon oxide film. By forming the silicon oxide film in the same layer as the capacitor C, it is possible to prevent a step from occurring between the memory cell array region and the peripheral circuit region due to the elevation of the capacitor C. As a result, a sufficient depth of focus can be provided for photolithography, and the process can be stabilized to cope with fine processing.

The capacitor C is connected to a memory cell selecting MIS.
A lower electrode 27 connected via a plug 26 to a plug 25 connected to the impurity semiconductor region 12 opposite to the impurity semiconductor region 12 connected to the bit line BL of the FET Qs.
And a capacitance insulating film 28 made of, for example, tantalum oxide;
For example, a plate electrode 29 made of titanium nitride is used. The plate electrode 29 may be a laminated film of a titanium nitride film and a tungsten film.

The lower electrode 27 includes a blocking layer 27a made of, for example, a titanium nitride film, and a lower conductive layer 27 made of amorphous iridium oxide having high conductivity but low crystallinity.
and a columnar portion 27c made of polycrystalline iridium oxide having a high crystallinity and a (101) main orientation plane formed on the lower conductive layer 27b. Blocking layer 27
“a” has a function of preventing oxidation of the plug 26 during heat treatment of the tantalum oxide film in an oxygen atmosphere in a process of manufacturing the capacitive insulating film 28 described later. The columnar portion 27c made of polycrystalline iridium oxide has a diameter of about 0.05.
μm, and the height is 0.1 to 0.5 μm.

In the upper layer of the capacitor C, for example, TEO
An insulating film 30a made of an S oxide film is formed, and an SOG film 30b is further deposited thereon to planarize the surface. Note that the SOG film 30b has self-flatness and does not need to be particularly flattened by the CMP method or the like.
MP polishing may be performed. Further, instead of the SOG film 30b, a TEOS oxide film or the like may be deposited and polished by the CMP method.

In the upper layer of the SOG film 30b, the second layer wiring 3
1 is formed. The second layer wiring 31 can be a laminated film of, for example, a titanium film 31a, an aluminum film 31b, and a titanium nitride film 31c.

The second-layer wiring 31 is connected to the first-layer wiring 18 via a plug 32 and to the plate electrode 29 of the capacitor C via a plug 33. Plug 3
Each of the layers 2 and 33 can be, for example, a laminated film of adhesive layers 32a and 33a formed of a laminated film of a titanium film and titanium nitride and tungsten films 32b and 33b formed by a CVD method.

Although not shown, the second layer wiring 31 is not shown.
Is covered with an interlayer insulating film, and a third-layer wiring similar to the second-layer wiring 31 can be formed above the interlayer insulating film. The interlayer insulating film includes, for example, a TEOS oxide film, an SOG film, and a TEOS
The third layer wiring and the second layer wiring 31 can be connected by plugs similar to the plugs 32 and 33.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS. 4 and 2
1 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

First, a p-type semiconductor substrate 1 is prepared, and a shallow groove 8 is formed in the main surface of the semiconductor substrate 1. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 9.
Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 8, thereby forming the isolation region 7 (FIG. 4).

Next, impurities are ion-implanted using the photoresist as a mask to form p-type wells 2 and 3, n-type well 4 and deep well 6 (FIG. 5).

Next, the gate insulating film 10 is formed in the active region in which the p-type wells 2 and 3 and the n-type well 4 are formed by thermal oxidation.
Is formed, and a polycrystalline silicon film doped with impurities, a titanium nitride film, a tungsten film, and a silicon nitride film are sequentially deposited on the entire surface of the semiconductor substrate 1. Thereafter, the silicon nitride film, the tungsten film, the titanium nitride film, and the polycrystalline silicon film are patterned by using a photolithography technique and an etching technique, so that a gate electrode 11 (word line WL) and a cap insulating film 13 are formed. Further, impurities are ion-implanted using the cap insulating film 13, the gate electrode 11, and the photoresist as a mask to form an impurity semiconductor region 12 and a low-concentration impurity region 15a (FIG. 6).

Next, a silicon nitride film (not shown) is deposited on the entire surface of the semiconductor substrate 1, and a photoresist film (not shown) is formed only in a region where a memory cell is to be formed (memory cell array region). Thereafter, using the photoresist film as a mask, the silicon nitride film is anisotropically etched to form a silicon nitride film 14 only on the semiconductor substrate 1 in the memory cell array region and at the same time to form a side wall on the side wall of the gate electrode 11 in the peripheral circuit region. A wall spacer 16 is formed. Further, impurities are ion-implanted in a self-aligned manner using the sidewall spacers 16 as a mask to form the high-concentration impurity regions 15b (FIG. 7).

Next, the SOG film 17 is formed on the entire surface of the semiconductor substrate 1.
After a is applied and cured, a TEOS oxide film 17b is deposited by a plasma CVD method. This TEOS oxide film is polished by the CMP method to flatten the surface. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, a TEOS oxide film 17c is further deposited to form an interlayer insulating film 17 (FIG. 8). This TEOS oxide film 17c is for repairing damage due to scratches on the TEOS oxide film 17b caused by CMP.

Next, a connection hole is opened in the TEOS oxide films 17c and 17b and the SOG film 17a, a plug-in implantation is performed, a polycrystalline silicon film doped with impurities is deposited, and this polycrystalline silicon film is subjected to a CMP method. To form plugs 19 and 25 (FIG. 9). This connection hole can be opened by two-stage etching. That is, the first etching is performed under the condition that the silicon oxide film is easily etched and the silicon nitride film is hardly etched, whereby the TEOS oxide films 17c and 17b and the SOG film 17a made of the silicon oxide film are formed.
Only the silicon nitride film 14 is left by etching only. Thereafter, etching is performed under the condition that the silicon nitride film is etched, and the silicon nitride film 14 is removed. Even if the silicon nitride film 14 is sufficiently over-etched by etching in two stages in this manner, the semiconductor substrate 1 is not excessively etched, and a sufficient process margin is realized while realizing a sufficient process margin. Reliability can be improved. In addition, the silicon nitride film 1
Since the gate electrode 4 completely covers the gate electrode 11, the opening of the connection hole can be opened in a self-aligned manner with respect to the gate electrode 11, and high-level fine processing can be performed.

Next, after forming the TEOS oxide film 17d, an opening is formed in the TEOS oxide film 17d so that the plug 19 to which the bit line BL is connected is exposed, and the impurity semiconductor regions of the n-channel MISFET Qn and the p-channel MISFET Qp are formed. 15 so that the interlayer insulating film 17 is exposed.
A connection hole 21 is formed (FIG. 10).

Next, after a titanium film is deposited on the entire surface of the semiconductor substrate 1, the semiconductor substrate 1 is annealed, and the surface of the plug 19 and the n-channel MISFET Qn and the p-channel MI
A titanium silicide layer 20 is formed in the impurity semiconductor region 15 of the SFET Qp. Thereafter, a titanium nitride film, a tungsten film, and a silicon nitride film are sequentially deposited on the entire surface of the semiconductor substrate 1, and are patterned to form the bit lines BL and the first-layer wirings 18, and a cap insulating film 22a is formed thereon. Form. Further, a silicon nitride film is deposited, and the silicon nitride film is anisotropically etched to form a sidewall spacer 22b (FIG. 11). The titanium film and the titanium nitride film can be deposited by, for example, a sputtering method, and the tungsten film can be deposited by, for example, a blanket CVD method.

Next, the SOG film 23 is formed on the entire surface of the semiconductor substrate 1.
After a is applied and cured, a TEOS oxide film 23b is deposited by a plasma CVD method. This TEOS oxide film 23b is polished by the CMP method, and its surface is flattened. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, a TEOS oxide film 23c is further deposited for the purpose of repairing the damage of the surface of the TEOS oxide film 23b due to the CMP polishing. Then TE
OS oxide films 23c and 23b, SOG film 23a and TE
A connection hole is opened in the OS oxide film 17d, a polycrystalline silicon film doped with impurities is deposited, and the polycrystalline silicon film is polished by a CMP method to form a plug 26 (FIG. 1).
2). Plug 26 is connected to plug 25.

Next, a titanium nitride film 34 serving as a blocking layer 27a is deposited on the entire surface of the semiconductor substrate 1, and an iridium oxide film 35 serving as a lower conductive layer 27b is further deposited.
Thereafter, a photoresist film 36 is formed in a region where the capacitor C is formed (FIG. 13).

The titanium nitride film 34 can be formed by, for example, a sputtering method, but may also be formed by a CVD method. The titanium nitride film 34 is deposited to prevent oxidation of the plug 26 as described later.

The iridium oxide film 35 can be deposited by reactive sputtering using iridium as a target. The iridium oxide film 35 is deposited at a relatively low pressure, for example, at a pressure of 5 mTorr. By depositing at such a low pressure, the iridium oxide film 35 can be formed with high conductivity. Also, under such low pressure conditions, the iridium oxide film 35 has insufficient crystallinity and is close to amorphous, and thus has a high flatness. If other deposition conditions are exemplified, argon and oxygen mixed at a ratio of 1: 1 can be exemplified as the source gas, and 50 W can be exemplified as the high frequency power.

Next, using the photoresist film 36 as a mask, the titanium nitride film 3 is removed except for the region where the capacitor C is formed.
4 and the iridium oxide film 35 are removed by etching to form a blocking layer 27a of the lower electrode 27 and a lower conductive layer 27b. Further, crystalline iridium oxide 37 to be the columnar portion 27c is formed (FIG. 14).

The crystalline iridium oxide 37 is deposited by reactive sputtering using iridium as a target similarly to the iridium oxide film 35, but is deposited at a relatively high pressure, for example, a pressure of 20 mTorr. By performing reactive sputtering at such a high pressure, columnar crystalline iridium oxide can be grown unlike the case of the iridium oxide film 35. As an example, the average size of the crystalline iridium oxide 37 is about 0.05 μm in diameter and several times as high. The growth of the columnar crystalline iridium oxide is achieved by increasing the reaction pressure and increasing the amount of oxygen to promote the oxidation reaction, thereby improving the crystallinity of the iridium oxide and selectively growing the crystal. It is considered that this occurs. In addition, such selective growth
It is considered that the growth in which the main orientation plane of the crystalline iridium oxide becomes the (101) plane is promoted, and the columnar crystal is grown. The other deposition conditions are as follows: the iridium oxide film 35
Can be the same as in the case of

Next, as shown in FIG. 15, a photoresist film 38 is formed in the memory cell array region, and the crystal iridium oxide 37 in the peripheral circuit region is removed. Alternatively, FIG.
As shown in FIG. 6, a photoresist film 39 is formed in a region where the capacitor C is to be formed, and the crystalline iridium oxide 37 in other regions is removed. After that, the photoresist film 3
8 or the photoresist film 39 is removed, and as shown in FIG. 17, the blocking layer 27a and the lower conductive layer 27b are removed.
And columnar portion 27c composed of crystalline iridium oxide
Is completed. In such a lower electrode 27, since the diameter of the columnar portion 27c is 0.05 μm, a plurality of columnar portions 27c are formed on the lower conductive layer 27b, and the surface area of the lower electrode 27 can be significantly increased. it can. As described above, the columnar portion 2
7c can be formed only by depositing iridium oxide by reactive sputtering at a relatively high pressure, and can be easily formed without going through complicated steps using photolithography and etching techniques. . Thereby, the lower electrode 2 having an increased surface area due to the fine structure
7 can be easily formed.

Next, the capacitor insulating film 2 is formed on the entire surface of the semiconductor substrate 1.
8, a tantalum oxide film is deposited and modified, and then a titanium nitride film is deposited on the entire surface of the semiconductor substrate 1, a photoresist film (not shown) is formed, and this is used as a mask. The tantalum oxide film and the titanium nitride film in the region are removed by etching to form a capacitor insulating film 28 and a plate electrode 29 (FIG. 18).

The tantalum oxide film serving as the capacitance insulating film 28 is deposited, for example, in an isothermal atmosphere at 450 ° C. by CVD using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a raw material.
It can be formed by a method. The tantalum oxide film thus deposited is in an amorphous state and does not have a sufficiently high dielectric constant. Therefore, it is necessary to subsequently perform a heat treatment (modification) to obtain a high dielectric constant crystalline tantalum oxide.

The heat treatment can be performed, for example, under the conditions of a heat treatment in an oxygen atmosphere at 800 ° C. for 3 minutes. During this heat treatment, oxygen diffuses through the tantalum oxide film and diffuses into the lower electrode 27. However, since the columnar portions 27c and the lower conductive layer 27b are made of iridium oxide, which is an oxide, they are conductive even if they are further oxidized. Does not affect gender. Therefore, an insulating film such as silicon oxide when a silicon material is used for the lower electrode is not formed at the interface between the capacitive insulating film 28 and the lower electrode 27, and the film thickness of the capacitive insulating film 28 is substantially reduced. Also, the capacitance value can be kept high by using only the thickness of the tantalum oxide film. Further, since an insulating film having a low dielectric constant such as silicon oxide is not formed, the dielectric constant of the capacitance insulating film 28 can be kept high, and the capacitance value can be kept high.

In this embodiment, since the blocking layer 27a is formed, oxygen diffused in the main heat treatment step is blocked by the blocking layer 27a and the plug 2
Never reach 6. For this reason, even if the plug 26 is formed of a polycrystalline silicon film, the plug 26 is not oxidized, and the connection reliability can be improved. Note that even when oxygen diffuses to the blocking layer 27a, since the blocking layer 27a is formed of a titanium nitride film, its oxide, titanium oxide, has conductivity and does not interfere with electrical connection. .

The titanium nitride film serving as the plate electrode 29 is
For example, it can be deposited by a CVD method or a sputtering method. Further, the plate electrode 29 may be a laminated film of a titanium nitride film and a tungsten film.

In this way, the capacitor C comprising the lower electrode 27, the capacitor insulating film 28 and the plate electrode 29 is formed, and the DRAM memory comprising the memory cell selecting MISFET Qs and the capacitor C connected in series thereto. The cell is completed.

Next, as shown in FIG.
A silicon oxide film 40 having a thickness of about the same height as above is formed on the entire surface of semiconductor substrate 1 by, for example, a CVD method. The silicon oxide film 40 can be formed by, for example, a CVD method using ozone and TEOS as raw materials.

Next, as shown in FIG. 20, a photoresist film 41 is formed in the peripheral circuit region, and using the photoresist film 41 as a mask, the silicon oxide film 40 in the memory cell array region is made of, for example, hydrofluoric acid (HF) and ammonium fluoride (NH). ₄ F) 1
Etching is removed by immersion in a mixed solution of 20 pairs. Thus, the insulating film 30a is formed only in the peripheral circuit region.

This photoresist film 41 is 5 μm from the capacitor C located at the outermost end of the memory cell array region.
There is no problem even if it is far away. Therefore, an advanced photolithography technique is not required to form the photoresist film 41. Thereby, the load on the manufacturing process can be reduced and the manufacturing method can be simplified. Further, a dry etching method can be used to remove the silicon oxide film 40 in the memory cell array region. However, in order to make the etching end of the silicon oxide film 40 an inclined surface, wet etching in which etching proceeds isotropically Is more convenient. Preferably, a silicon nitride film is formed above or below the capacitor C as an etching stopper film for the silicon oxide film 40.

Next, after the photoresist film 41 is removed, as shown in FIG.
An insulating film 30a of about 0 nm is deposited. The insulating film 30a
For example, ozone (O ₃ ) and tetraethoxysilane (TEO)
S) is deposited by a plasma CVD method using a source gas. Thereafter, a thick SOG film 30b that does not cause cracking even when formed thickly is formed by spin coating to flatten the surface.

Since the SOG film 30b is a film having excellent self-flatness, the SOG film 30b is formed in the peripheral circuit region without any special flattening means.
0b can be almost completely flattened.
Here, the flattening means using the SOG film 30b is illustrated, but the flattening may be further completed by using the CMP method. Further, instead of the SOG film 30b, TE
An OS oxide film or the like may be deposited and subjected to CMP polishing to planarize the surface.

Finally, a connection hole is opened, and a film thickness of 10 is formed on the SOG film 30b including the connection hole by sputtering.
A titanium nitride film 33a of about 0 nm is deposited, and a tungsten film 33 of about 500 nm thickness is further formed thereon by CVD.
b is deposited. Thereafter, the titanium nitride film 33a and the tungsten film 33b are etched back to form plugs 32, 33.
Is formed, and a TiN film having a thickness of about 50 nm is formed by a sputtering method.
After sequentially depositing a film, an Al (aluminum) film having a thickness of about 500 nm, and a Ti film having a thickness of about 50 nm, the second layer wiring 31 is formed by patterning these films by dry etching using a photoresist film as a mask. . Thereby, the DRAM shown in FIG. 3 is almost completed. The openings of the connection holes can be formed by known photolithography and etching techniques. Etching back of the titanium nitride film 33a and the tungsten film 33b can be performed by plasma etching or polishing by a CMP method.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the plug 2
FIG. 22 shows an example in which polycrystalline silicon is used as 6.
The plug 42 may be made of titanium nitride as shown in FIG. In this case, the blocking layer 27a is not required.
The plug 42 made of titanium nitride can be formed by etching back a titanium nitride film deposited by a CVD method.

Although the blocking layer 27a or the plug 42 is made of a titanium nitride film, it may be made of tungsten nitride (WN) instead of titanium nitride.

[0079]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The amount of charge stored in the information storage capacitance element can be increased.

(2) Even if a tantalum oxide film is used as the capacitive insulating film of the information storage capacitive element and heat treatment is performed in an oxygen atmosphere, the effective dielectric constant of the capacitive insulating film is reduced and the film thickness is increased. There is no technology available.

(3) The surface area of the lower electrode of the information storage capacitor can be easily increased.

(4) The process of forming the lower electrode of the information storage capacitor can be simplified.

(5) It is possible to increase the amount of charge stored in the information storage capacitor element, increase the refresh margin of the DRAM, and reduce the voltage and power of the semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM of the embodiment.

FIG. 3 is a cross-sectional view of the DRAM according to the embodiment;

FIG. 4 is a cross-sectional view showing an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 5 is a sectional view illustrating an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 6 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 7 is a sectional view illustrating an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 8 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 9 is a sectional view illustrating an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 10 is a sectional view illustrating an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 11 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 12 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 13 is a cross-sectional view showing an example of the method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 14 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 15 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the embodiment in the order of steps;

FIG. 17 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 18 is a cross-sectional view showing an example of the method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 19 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 20 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 21 is a sectional view illustrating an example of a method of manufacturing the DRAM of the embodiment in the order of steps;

FIG. 22 is a cross-sectional view showing another example of a DRAM according to an embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 1A semiconductor chip 2 p-type well 3 p-type well 4 n-type well 6 deep well 7 isolation region 8 shallow groove 9 silicon oxide film 10 gate insulating film 11 gate electrode 11a polycrystalline silicon film 11b titanium nitride film 11c tungsten film REFERENCE SIGNS LIST 12 impurity semiconductor region 13 cap insulating film 14 silicon nitride film 15 impurity semiconductor region 15 a low-concentration impurity region 15 b high-concentration impurity region 16 sidewall spacer 17 interlayer insulating film 17 a SOG film 17 b TEOS oxide film 17 c TEOS oxide film 17 d TEOS oxide film 18 First layer wiring 18a Titanium film 18b Titanium nitride film 18c Tungsten film 19 Plug 20 Titanium silicide layer 21 Connection hole 22a Cap insulating film 22b Sidewall spacer 23 Interlayer insulating film 23a SOG Film 23b TEOS oxide film 23c TEOS oxide film 24 Insulating film 25 Plug 26 Plug 27 Lower electrode 27a Blocking layer 27b Lower conductive layer 27c Columnar portion 28 Capacitive insulating film 29 Plate electrode 30a Insulating film 30b SOG film 31 Second layer wiring 31a Titanium film 31b Aluminum film 31c Titanium nitride film 32, 33 Plug 32a, 33a Adhesive layer (titanium nitride film) 32b, 33b Tungsten film 34 Titanium nitride film 35 Iridium oxide film 36, 38, 39 Photoresist film 37 Crystalline iridium oxide 40 Silicon oxide film 41 Photoresist film 42 Plug BL Bit line C Capacitor MARY Memory array Qn N-channel MISFET Qp P-channel MIS
FET Qs MISFET for memory cell selection SA Sense amplifier WD Word driver WL Word line

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Misuzu Kanai 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (6)

[Claims] A first electrode connected to a memory cell selection MISFET formed on a main surface of a semiconductor substrate;
A semiconductor having a capacitive insulating film mainly composed of tantalum oxide formed in contact with the lower electrode and an information storage capacitive element including an upper electrode formed to face the lower electrode via the capacitive insulating film An integrated circuit device, wherein the lower electrode includes a plurality of columnar portions made of iridium oxide and a conductive film located at a bottom of the columnar portion. 2. The semiconductor integrated circuit device according to claim 1, wherein said columnar portion is made of polycrystalline iridium oxide whose main orientation plane is a (101) plane. 3. The semiconductor integrated circuit device according to claim 1, wherein the columnar portion is formed by a reactive sputtering method using iridium as a target and a gas containing oxygen. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein titanium nitride or nitride is provided between a plug connecting the memory cell selecting MISFET and the lower electrode and the conductive film. A first configuration in which a blocking film containing tungsten as a main component is formed, the memory cell selecting MIS
A semiconductor integrated circuit device, wherein a plug for connecting an FET and the lower electrode has any one of a second configuration made of a conductor containing titanium nitride or tungsten nitride as a main component. 5. A lower electrode, which is connected in series to a memory cell selecting MISFET formed on a main surface of a semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device having an information storage capacitance element having a capacitance insulating film and an upper electrode,
(A) forming a plug connected to the memory cell selecting MISFET in an upper interlayer insulating film of the semiconductor substrate;
On the entire surface of the interlayer insulating film where the surface of the plug is exposed,
Depositing an iridium oxide film by a reactive sputtering method using iridium as a target and oxygen-containing gas under a first pressure condition; (b) under a second pressure condition higher than the first pressure condition, Forming a plurality of columnar bodies made of polycrystalline iridium oxide on at least a part of the iridium oxide film by a reactive sputtering method using iridium as a target and a gas containing oxygen; and (c) oxidizing at least the columnar bodies. Depositing a tantalum film and forming the capacitive insulating film by heat treatment of the tantalum oxide film in an oxygen atmosphere. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said plug is a first structure in which said plug is a conductor made of titanium nitride or tungsten nitride, or said plug is made of polycrystalline silicon. A second configuration including a step of depositing a titanium nitride film or a tungsten nitride film on the entire surface of the interlayer insulating film before depositing the iridium oxide film. Manufacturing method.