JPH1126713A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of the step difference between a memory array region and a surrounding circuit region, by forming an insulating film on a memory-cell selecting MISFET and the like, forming a groove in the insulating film, forming a conducting film in the groove or the like, etching the conducting film, and forming a lower electrode so that the conducting film remains only in the groove and so on. SOLUTION: On a memory-cell selecting MISFET and a surrounding circuit region, a silicon oxide film 45, a silicon nitride film 46, a silicon oxide film 53 are deposited. A groove is formed at the upper part of a through hole 48. Polycrystal silicon is formed in the groove. Then, a photoresist film covering the silicon oxide film 53 is formed in the surrounding circuit region. Then, the silicon oxide 53 and the like are etched, and a slant surface is formed. Thereafter, a lower electrode 60 is formed from polycrystalline silicon 56. Then, a Ta2 O3 film 61 and a TiN film 62 are formed, and an information storing capacitor element C, which is constituted of the lower electrode 60, is formed by patterning and the like. Then, a silicon oxide film 64 is deposited. An SOG film 65 is formed, and the surface is flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
The present invention relates to a technique which is effective when applied to an increase in the storage capacity of a random access memory (CRandom Access Memory) and a reduction in a step between a memory cell array region and a peripheral circuit region caused by the increase.

[0002]

2. Description of the Related Art A memory cell of a DRAM is arranged at an intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. Insulator Semiconductor Fie
ld Effect Transistor) and one information storage capacitor (capacitor) connected in series to the ld effect transistor. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region, and mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. Have been. The bit line is arranged above the memory cell selecting MISFET, and is electrically connected to one of a source and a drain shared by two memory cell selecting MISFETs adjacent in the extending direction. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

[0003] Japanese Patent Application Laid-Open No. 7-7084 discloses a capacitor over bit line (Capacitor Over Bitline) structure in which an information storage capacitor is arranged above a bit line.
A RAM is disclosed. DRAM described in this publication
The lower electrode (storage electrode) of the information storage capacitor disposed above the bit line is formed in a cylindrical shape in order to compensate for the decrease in the storage charge (Cs) of the information storage capacitor accompanying the miniaturization of the memory cell. The capacitance insulating film and the upper electrode (plate electrode) are formed thereon.

However, in a memory cell having a COB structure, the reliability of operation of a capacitor formed in a memory cell array region as a semiconductor memory device must be ensured, so that the degree of integration of the device is improved and the cell area is reduced. It is also necessary to make a considerable three-dimensional. When an interlayer insulating film is formed after forming such a three-dimensional capacitor, a step corresponding to the height of the capacitor is generated between the memory cell array region and the peripheral circuit region.

As the level of integration of DRAMs increases, it is necessary to secure a certain capacitance of the capacitors, and such steps are increasing. In addition, the demand for improvement in the degree of integration of the DRAM demands an improvement in the exposure accuracy of photolithography, and the value of the depth of focus allowed to satisfy such a demand becomes increasingly severe. There is a problem that it is difficult to form a wiring layer formed on the interlayer insulating film due to such an increase in the level difference and a decrease in the margin of exposure focus in photolithography.

[0006] The reduction in workability in the photolithography can be dealt with by reducing the steps. The following techniques are known as techniques that can reduce such steps.

[0007] For example, Japanese Patent Application Laid-Open No. 4-10651,
Alternatively, a technique as described in JP-A-7-7084 is known. This technology is briefly described as follows. That is, the technique described in the above-mentioned publication discloses that the memory cell array region and the peripheral circuit region
A vertical wall (peripheral wall) or a channel formed simultaneously with the lower electrode (storage node) of the capacitor is formed.

A DRAM having such a standing wall or channel is formed as follows. First, DRA
After forming the M selection MISFET and the MISFET of the peripheral circuit by a predetermined method, a bit line is formed via an interlayer insulating film, and further an interlayer insulating film covering the bit line is formed. Next, after depositing an insulating film having a thickness corresponding to the height of the three-dimensional capacitor, holes are formed in the insulating film in the region where the lower electrode of the capacitor is formed, and at the same time, the memory cell array region and the peripheral circuit region are formed. A groove for forming a standing wall (peripheral wall) or a channel is formed in a boundary region with the above. afterwards,
A conductive film is deposited on the entire surface, and only the conductive film on the insulating film is removed. If the insulating film is further removed, the conductive film in the hole becomes a lower electrode of a three-dimensional capacitor, and the conductive film in the groove is formed as a standing wall or a channel. If an insulating film to be removed when forming the lower electrode and the standing wall or the channel of this capacitor is left only in the peripheral circuit region, no step is formed between the memory cell array region and the peripheral circuit region, and the capacitor is deposited on the capacitor. The interlayer insulating film is planarized. The above-mentioned publication discloses a method using a resist mask or a method using the conductive film as a mask to form an insulating film remaining only in such a peripheral circuit region. That is, according to the technology disclosed in the above-mentioned publication, the formation end portion of the mask can be located at an arbitrary position in the region where the single or plural standing walls or channels are formed by the presence of the standing walls or channels. In addition, it is intended that a mask can be easily formed by increasing a photolithography margin.

For example, on October 26, 1993,
Published by the Industrial Research Council, "Easy ULSI Technology", p. 155
~ P.164, SOG (Spin On
Glass) film or low melting point glass coating and melting application method, heat treatment method by glass flow, CVD (Chem
There is known a method of applying a surface reaction mechanism of ical vapor deposition (SPM) to perform self-planarization. For example, Japanese Patent Application Laid-Open No. 7-122654 discloses a BPSG (Boron-dope).
A technology for reducing the level difference by combining flattening by reflow of a dPhospho-Silicate Glass) film and flattening by a spin-on-glass film (SOG film) is disclosed.

Further, for example, on May 1, 1996, published by the Industrial Research Council, "Electronic Materials", May 1996, p.
Pp. 27 to 27, a method combining the deposition of a sacrificial photoresist film, an SOG film or a self-planarizing CVD film with an etch-back method, and a CMP (Chemic
al Mechanical Polishing) method is known.

[0011]

However, the above-mentioned prior art has the following problems.

That is, JP-A-4-10651,
Alternatively, in the technique described in Japanese Patent Application Laid-Open No. 7-7084, a region for forming a standing wall or a channel is occupied between a memory cell array region and a peripheral circuit region in order to form a standing wall or a channel. However, there is a problem that the chip size is increased.

Further, in the application method by applying and melting an SOG film or a low melting point glass, it is possible to embed (flatten) fine irregularities, but it is not possible to embed a recess having a large area such as a peripheral circuit region. Therefore, a remarkable effect cannot be expected in reducing the step as described above.

Further, a heat treatment method using a glass flow, for example, a reflow film of BPSG requires a high-temperature heat treatment, and a metal material is used as a gate, plug or capacitor material in a highly integrated DRAM in the future. In consideration of the above, there is a possibility that an undesirable reaction of the metal-based material occurs by adopting such a high-temperature process, and the performance of the DRAM cannot be improved.

Further, the method of applying the surface reaction mechanism of CVD to perform the self-planarization complicates the process and is not preferable from the viewpoint of realizing a stable process.

Further, in the technique for reducing the level difference by combining the flattening by reflow of the BPSG film and the flattening by the spin-on-glass film (SOG film), it is not possible to eliminate the disadvantages caused by the use of the high-temperature process described above.

Further, the method of combining the deposition of the photoresist sacrificial film, the SOG film or the self-planarizing CVD film with the etch-back method, or the CMP method is not preferable because the process becomes complicated.

An object of the present invention is to provide a technique that does not cause a step between a memory cell array region and a peripheral circuit region even when a three-dimensional capacitor is formed.

Another object of the present invention is to provide a technique for eliminating a step between a memory cell array region and a peripheral circuit region due to the formation of a three-dimensional capacitor, and to eliminate the difficulty of photolithography.

It is another object of the present invention to provide a technique for eliminating a step between a memory cell array region and a peripheral circuit region due to formation of a three-dimensional capacitor, and to perform disconnection or patterning of a wiring layer formed thereover. An object of the present invention is to prevent a short circuit due to a defect.

It is another object of the present invention to provide a semiconductor integrated circuit device which realizes both the securing of the capacity of a capacitor and high reliability.

Another object of the present invention is to provide a technique for preventing a capacitor electrode from being collapsed during a manufacturing process due to an increase in a three-dimensional capacitor, and to improve the manufacturing yield of a semiconductor integrated circuit device.

It is another object of the present invention to provide a three-dimensional capacitor having a high storage capacitance value, to reduce the height of the three-dimensional capacitor, to secure the capacitance of the capacitor, and to realize both high reliability. It is to provide a device.

It is another object of the present invention to eliminate the step between the memory cell array region and the peripheral circuit region to reduce the aspect ratio of the connection hole in the peripheral circuit region which is deepened and to reduce the aspect ratio of the connection hole in the peripheral circuit region. An object of the present invention is to provide a technique for facilitating processing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0026]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a memory cell selecting MISFET and a cylindrical lower electrode connected in series to the memory cell selecting MISFET and having an opening above. A memory is formed by a capacitance insulating film formed in contact with the cylindrical inner surface of the lower electrode and an information storage capacitive element having at least an upper electrode formed so as to face the cylindrical inner surface of the lower electrode via the capacitive insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising a memory cell array region in which cells are arranged and in which memory cells are arranged, and a peripheral circuit region around the memory cell array region, comprising:
After forming a memory cell selecting MISFET in the memory cell array region on the main surface of the semiconductor substrate and a peripheral circuit MISFET in the peripheral circuit region on the main surface of the semiconductor substrate, a lower portion is formed above the memory cell selecting MISFET and the MISFET of the peripheral circuit. Depositing a first insulating film having a thickness corresponding to the height of the electrode, (b) forming a groove by opening the first insulating film on the memory cell selecting MISFET, and (c).
Depositing a first conductive film to be a part of a lower electrode with a film thickness that does not fill the groove, on the first insulating film including the inside of the groove;
(D) forming a second insulating film filling the concave portion of the first conductive film formed in the groove, exposing the first conductive film on the first insulating film, and (e) forming the first conductive film. Etching, leaving the first conductive film only inside the groove, (f) removing the second insulating film filling the concave portion, and forming a lower electrode, (g)
Forming a capacitive insulating film on the surface of the lower electrode; and (h) depositing a second conductive film on the capacitive insulating film and patterning the second conductive film to form an upper electrode.

According to such a method of manufacturing a semiconductor integrated circuit device, the first insulating film deposited for forming the information storage capacitance element is left in the peripheral circuit region, so that the memory cell array region and the peripheral circuit region are not separated. No step is formed between them. As a result, it is possible to increase the margin of photolithography in the subsequent steps, and to stably process the openings of the connection holes to cope with further miniaturization.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after the step (f) of the method of manufacturing a semiconductor integrated circuit device described in (1), an upper layer portion of the first insulating film is removed. Exposing a portion above the lower electrode, and (h), forming a third insulating film over the entire surface of the semiconductor substrate and flattening the surface.

According to such a method of manufacturing a semiconductor integrated circuit device, the first insulating film remains below the lower electrode because a portion above the lower electrode is exposed. For this reason, the first insulating film acts as a mechanical reinforcing member for the lower electrode, so that the lower electrode does not easily collapse even when the height of the lower electrode is increased, and the lower electrode can be formed stably. As a result, it is possible to increase the information storage capacitor and increase the amount of stored charge.

(3) In the method of manufacturing a semiconductor integrated circuit device according to (2), a connection hole is opened in a peripheral circuit region of the first insulating film from which the upper layer has been removed, and a second conductive film is formed. A plug or a wiring can also be formed by filling the connection hole at the same time as the deposition and patterning the second conductive film in the peripheral circuit region at the same time as patterning the second conductive film.

According to such a method of manufacturing a semiconductor integrated circuit device, a plug or wiring having a height corresponding to the height of the remaining first insulating film and the thickness of the upper electrode is formed. In this case, the depth of the connection hole in the peripheral circuit region can be reduced, and the difficulty of processing the connection hole can be reduced. This is because when the insulating film is left in the peripheral circuit region or the insulating film is formed to eliminate a step with the memory cell array region, the thickness of the insulating film in the peripheral circuit region becomes relatively large, It becomes difficult to open the connection hole in the region, which contributes to alleviating the difficulty.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after the step (e) of the method of manufacturing a semiconductor integrated circuit device described in (1), the first insulating film in the peripheral circuit region is covered. Forming the photoresist film to be formed, and removing the second insulating film in the step (f) simultaneously with the removal of the first insulating film in the memory cell array region by a wet etching method using the photoresist film as a mask. After a step of forming a cylindrical lower electrode having an opening above while leaving a part of the first insulating film, and after the step (h), a third insulating film is formed on the entire surface of the semiconductor substrate and the surface is formed. It includes a step of flattening.

According to such a method of manufacturing a semiconductor integrated circuit device, since the first insulating film is left in the peripheral circuit region, no step is formed between the memory cell array region and the peripheral circuit region. In this step, it is possible to increase the margin of photolithography and to stably process the opening of the connection hole to cope with further miniaturization. Further, since the first insulating film in the memory cell array region is removed by the wet etching method, a cylindrical lower electrode having an opening above is formed, and the surface area of the lower electrode may be increased to increase the amount of accumulated charges. it can.

(5) In the method of manufacturing a semiconductor integrated circuit device according to (4), before the first insulating film is deposited, the fourth insulating film is different in etching rate from the first insulating film and the second insulating film. May be deposited on the entire surface of the semiconductor substrate, and after the lower electrode is formed, the fourth insulating film in the memory cell array region may be removed by etching.

According to such a method of manufacturing a semiconductor integrated circuit device, the region where the fourth insulating film has been formed (a part of the plug connecting to the MISFET for selecting a memory cell) can also function as a capacitive element. And the charge storage amount can be increased. The information storage capacitor thus formed is connected to a columnar electrode formed by a part of a plug connecting the lower electrode and the memory cell selection MISFET, and a capacitor insulating film formed on the outer periphery thereof. As a cylindrical capacitive element including the formed concentric cylindrical electrode, it is formed integrally with a cylindrical capacitive element having an upper opening formed thereabove.

(6) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a memory cell selecting MISFET and a cylindrical lower electrode connected in series to the memory cell selecting MISFET and having an opening above. A memory cell was constituted by a capacitor insulating film formed on the surface of the lower electrode and an information storage capacitor having an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween, and the memory cell was arranged. A method of manufacturing a semiconductor integrated circuit device having a memory cell array region and a peripheral circuit region around the memory cell array region, comprising: (a) a memory cell selection MIS on a main surface of a semiconductor substrate;
Forming an FET and then forming an information storage capacitor on the FET; (b) forming a first insulating film on the main surface of the semiconductor substrate with a thickness equal to or greater than the height of the information storage capacitor; Depositing a film, (c) forming a photoresist film covering the first insulating film in the peripheral circuit region, and then removing the first insulating film in the memory cell array region by wet etching using the photoresist film as a mask. (D) forming a third insulating film over the entire surface of the semiconductor substrate and flattening the surface.

According to such a method of manufacturing a semiconductor integrated circuit device, since the first insulating film is formed only in the peripheral circuit region, a step between the memory cell array region and the peripheral circuit region is eliminated. In this case, the margin of photolithography can be increased, and the opening of the connection hole can be processed stably to cope with further miniaturization.

(7) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to any one of (2) to (6), wherein the surface of the third insulating film is flat. The step of forming is a flattening step by applying an SOG film.

Alternatively, the step of flattening the surface of the third insulating film is performed by etching the insulating film deposited by the vapor phase growth method to a thickness equal to or larger than the height of the information storage capacitor element by the CMP method. This is a flattening step.

According to such a method of manufacturing a semiconductor integrated circuit device, it is possible to bury a groove (recess) formed by wet etching between the peripheral circuit region and the memory cell array region and to make it almost completely flat. . In particular, in the method based on the application of the SOG film, the steps are simple and the production can be facilitated.

(8) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of (1) to (7), wherein the second conductive film is deposited. Is performed so as to fill the concave portion formed by the cylindrical shape of the lower electrode, and the surface is flattened.

According to such a method of manufacturing a semiconductor integrated circuit device, no concave portion is formed on the surface of the second conductive film. If a concave portion is formed, the concave portion is formed at the bottom of the concave portion of the insulating film filling the concave portion. Prevent the occurrence of voids, etc.
The reliability of the semiconductor integrated circuit device can be improved.
When the semiconductor integrated circuit device is miniaturized and the information storage capacitor element is miniaturized, the concave portion on the surface of the second conductive film is also considerably small, and there is a situation where voids and the like are likely to occur, The present invention is particularly effective in consideration of the future tendency of miniaturization.

(9) The semiconductor integrated circuit device of the present invention comprises a memory cell selecting MISFET and a memory cell selecting MIFET.
A cylindrical lower electrode connected in series to the SFET and having an opening above, a capacitor insulating film formed in contact with at least the cylindrical inner surface of the lower electrode, and at least a cylindrical electrode of the lower electrode via the capacitor insulating film. A memory cell is constituted by an information storage capacitor having an upper electrode formed facing the inner surface,
A semiconductor integrated circuit device having a memory cell array region in which memory cells are arranged, and a peripheral circuit region around the memory cell array region, wherein an insulating film having a thickness corresponding to the height of an information storage capacitor is provided on the peripheral circuit. In this case, a step between the memory cell array region and the peripheral circuit region is eliminated.

Further, in the semiconductor integrated circuit device,
The recess formed by the lower electrode forming the information storage capacitor is filled with the upper electrode forming the information storage capacitor.

Further, in the semiconductor integrated circuit device,
An information storage capacitance element is formed above the memory cell selection MISFET, and the information storage capacitance element is formed on a cylindrical electrode comprising a part of a plug connecting the lower electrode and the memory cell selection MISFET, and on an outer periphery thereof. It is formed integrally with a cylindrical capacitance element including a concentric cylindrical electrode formed via a capacitance insulating film.

Such a semiconductor integrated circuit device can be manufactured by the above-described manufacturing methods (1) to (8).

(10) The semiconductor integrated circuit device of the present invention
MISFET for memory cell selection and M for memory cell selection
Including a lower electrode, a capacitive insulating film formed in contact with the lower electrode, and an information storage capacitive element having an upper electrode formed opposite to the lower electrode via the capacitive insulating film and connected in series to the ISFET. In a semiconductor integrated circuit device having a memory cell, both a lower electrode and an upper electrode are made of a conductive material containing at least titanium nitride, and a capacitive insulating film is made of an insulating film containing at least polycrystalline tantalum oxide.

According to such a semiconductor integrated circuit device,
Since both the lower electrode and the upper electrode are made of a conductive material containing at least titanium nitride, and the capacitive insulating film is made of an insulating film containing at least polycrystalline tantalum oxide, the amount of accumulated charges can be increased. That is, polycrystalline tantalum oxide is a high dielectric constant material, and the oxide of titanium nitride in the lower electrode is a conductor, and the capacitance due to the formation of a silicon oxide film as if a silicon material was used for the lower electrode. This is because there is no substantial increase in the thickness of the insulating film, and it is not necessary to form a silicon nitride film for preventing generation of a silicon oxide film.

(11) In the semiconductor integrated circuit device according to the above (10), the memory cell selecting MISFET
The plug connecting the electrode and the lower electrode can be made of a conductive material containing titanium nitride as a main component.

According to such a semiconductor integrated circuit device,
The response speed (memory read / write speed) of the semiconductor integrated circuit device can be improved by reducing the resistance of the plug. In addition, since the main component of the plug is the same as that of the lower electrode material, titanium nitride, the affinity can be improved.

(12) The above (10) or (1)
In the semiconductor integrated circuit device described in 1), a titanium oxide film having a thickness of 10 nm or less can be formed at the interface between the lower electrode and the capacitor insulating film.

There are two types of such a titanium oxide film: a case where the tantalum oxide film serving as a capacitive insulating film is formed by a heat treatment in an oxygen atmosphere, and a case where the titanium oxide film is formed before the tantalum oxide film is deposited. In any case, the titanium oxide film is a conductive film, and the capacitance value can be increased to increase the amount of accumulated charge regardless of the increase in the thickness of the capacitor insulating film.

(13) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a memory cell selecting MISFET, a lower electrode, and a capacitor insulating film formed in contact with the lower electrode are connected in series to the memory cell selecting MISFET. And a method for manufacturing a semiconductor integrated circuit device having a memory cell including an information storage capacitor element having an upper electrode formed opposite to a lower electrode with a capacitor insulating film interposed therebetween. Depositing a titanium nitride film to be a lower electrode and subjecting the titanium nitride film to a heat treatment in a non-oxidizing atmosphere; (b) CV
Depositing a tantalum oxide film by a method D, heat treating in a non-oxidizing atmosphere to crystallize the tantalum oxide film and convert it to a polycrystalline tantalum oxide film, and (c) heat treating the polycrystalline tantalum oxide film in an oxidizing atmosphere. Forming a titanium oxide film at the interface between the titanium nitride film and the polycrystalline tantalum oxide film while modifying the polycrystalline tantalum oxide film, and (d) depositing a titanium nitride film to be an upper electrode by a CVD method. It is a thing.

According to such a method of manufacturing a semiconductor integrated circuit device, the above-described semiconductor integrated circuit devices (10) to (12) can be manufactured.

(14) In the method of manufacturing a semiconductor integrated circuit device according to (13), after the step (a),
The method may include forming a titanium oxide film on the surface of the titanium nitride film.

According to such a method of manufacturing a semiconductor integrated circuit device, since the titanium nitride oxide film is formed before the tantalum oxide film is deposited, the polycrystalline tantalum oxide film is subjected to the heat treatment in an oxidizing atmosphere. In the step of modifying the polycrystalline tantalum oxide film, entry of oxygen can be suppressed. If the oxide of titanium nitride is not formed, the volume of the titanium oxide film formed at the interface between the titanium nitride film and the polycrystalline tantalum oxide film becomes large, and stress is applied to the polycrystalline tantalum oxide film. Although it is conceivable that the insulation property is impaired, in the case of the present invention, such a problem can be suppressed.

(15) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a MISFET for selecting a memory cell, and a lower electrode, a capacitor insulating film formed in contact with the lower electrode, connected in series with the MISFET for selecting a memory cell. And a method of manufacturing a semiconductor integrated circuit device having a memory cell including an information storage capacitive element having an upper electrode formed opposite to a lower electrode via a capacitive insulating film, comprising: a memory cell selecting MISFET; Part of the plug that connects to the lower electrode,
It is formed simultaneously with the bit line arranged above the memory cell selection MISFET.

According to such a method of manufacturing a semiconductor integrated circuit device, the plug can be formed by the step of forming the bit line, and the process can be simplified.

[0060]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to the present embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one information storage capacitor C
And one memory cell selecting MI connected in series
SFET Qs. M for memory cell selection
One of a source and a drain of the ISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on its surface. CV is formed on the silicon oxide film 2
A silicon nitride film 3 having a thickness of about 140 nm is deposited by a D (Chemical Vapor Deposition) method. Silicon oxide film 2
Is formed to alleviate the stress applied to the substrate when sintering (burning) a silicon oxide film embedded in the element isolation groove in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface below (the active region).

Next, as shown in FIG. 4, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. In order to form the groove 5a, the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, the photoresist film 4 is removed, and then the silicon oxide film 2 and the semiconductor substrate are etched using the silicon nitride film 3 as a mask. 1 may be dry-etched.

Next, after removing the photoresist film 4,
As shown in FIG. 5, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-described etching, the semiconductor substrate 1 is wet-oxidized at about 850 to 900 ° C. and the inner wall of the groove 5a has a film thickness of about 10 nm. A thin silicon oxide film 6 is formed.

Next, as shown in FIG. 6, after a silicon oxide film 7 having a thickness of about 300 to 400 nm is deposited on the semiconductor substrate 1, the semiconductor substrate 1 is dry-oxidized at about 1000 ° C., thereby forming the trench 5a. Silicon oxide film 7 embedded in
(Sintering) is performed to improve the film quality. The silicon oxide film 7 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 7, a silicon nitride film 8 having a thickness of about 140 nm is deposited on the silicon oxide film 7 by a CVD method, and then, as shown in FIG. Then, the silicon nitride film 8 is dry-etched to leave the silicon nitride film 8 only on the upper portion of the groove 5a having a relatively large area such as the boundary between the memory array and the peripheral circuit. When the silicon nitride film 8 remaining on the groove 5a is planarized by polishing the silicon oxide film 7 by a CMP method in the next step, the silicon oxide film 7 inside the groove 5a having a relatively large area is removed. It is formed in order to prevent a phenomenon (dishing) that is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area.

Next, after removing the photoresist film 9,
As shown in FIG. 9, the element isolation groove 5 is formed by polishing the silicon oxide film 7 by a CMP method using the silicon nitride films 3 and 8 as stoppers and leaving the silicon oxide film 7 inside the groove 5a.

Next, after the silicon nitride films 3 and 8 are removed by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, P (phosphorus), and a p-type impurity, for example, B (boron) is added to a part of the memory array and peripheral circuits (a region for forming an n-channel MISFET). The p-type well 11 is formed by ion implantation, and n is formed in another part of the peripheral circuit (the region where the p-channel MISFET is formed).
An n-type well 12 is formed by ion implantation of a type impurity, for example, P (phosphorus). Subsequent to the ion implantation, impurities for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) are ion-implanted into the p-type well 11 and the n-type well 12. The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit and the like through the semiconductor substrate 1.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the semiconductor substrate 1 using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a p-type well 11 and an n-type well 1.
Then, a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of No. 2.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere to form the gate oxide film. Nitrogen may be segregated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 (oxynitriding treatment). When the thickness of the gate oxide film 13 is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion.
The above oxynitriding process can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG. 11, gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A is provided with a memory cell selecting MISF.
It forms a part of the ET, and is used as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length is the minimum dimension (for example, within an allowable range) in which the short channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. (About 0.24 μm). The distance between the adjacent gate electrodes 14A (word lines WL) is the minimum dimension (for example, 0.2) determined by the resolution limit of photolithography.
2 μm). The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

The gate electrode 14A (word line WL) and the gate electrodes 14B and 14C are formed by depositing a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further deposited thereon. After deposition by the CVD method, these films are formed by patterning these films using the photoresist film 16 as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN (titanium nitride) film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that the word line delay is reduced. Can be reduced. Also, the gate electrode 1
Since the word line delay can be reduced without backing 4 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film 16, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate oxide film 13 in a region other than the region under the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is formed.
At the same time that the gate oxide film 1 under the gate sidewall is removed.
3 is also isotropically etched and an undercut occurs, so that the breakdown voltage of the gate oxide film 13 is reduced as it is. Therefore, the film quality of the shaved gate oxide film 13 is improved by wet oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, as shown in FIG.
A p ^- type semiconductor region 17 is formed in the n-type well 12 on both sides of the gate electrode 14C by ion implantation of a p-type impurity, for example, B (boron) into the gate electrode 14C. In addition, the p-type well 11 has n
An n ^- type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting a p-type impurity, for example, P (phosphorus), and an n ^- type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. To form As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG.
After a silicon nitride film 20 having a thickness of about 50 to 100 nm is deposited thereon by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 as shown in FIG. Is anisotropically etched to form sidewall spacers 20a on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do.
The silicon nitride film 1 on the gate electrodes 14B and 14C
In order to minimize the shaving amount of No. 5, the amount of over-etching is kept to a necessary minimum.

Next, after removing the photoresist film 21, as shown in FIG. 15, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 22 of a p-channel MISFET.
(Source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. I do. This allows
A p-channel MISFET Qp and an n-channel MISFET Qn having an LDD (Lightly Doped Drain) structure are formed in the peripheral circuit region.

Next, as shown in FIG.
After spin coating an SOG (spin-on-glass) film 24 having a thickness of about 300 nm on the semiconductor substrate 1,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 25, the silicon oxide film 25 is polished by a CMP method to flatten the surface. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the gate electrode 14A (word line WL) and the gate electrodes 14B,
Apply SOG film 24 with high reflow properties on top of 4C,
Further, the silicon oxide film 25 deposited on the
Flattening by the method. Thereby, the gap fill property of the fine gap between the gate electrodes 14A (word lines WL) is improved, and the flattening of the insulating film on the gate electrodes 14A (word lines WL) and the gate electrodes 14B and 14C is realized. be able to.

Next, as shown in FIG. 18, a silicon oxide film 26 having a thickness of about 100 nm
Is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. Silicon oxide film 2
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. On top of the silicon oxide film 25, a PSG (Phospho Silicate Glas
s) A film or the like may be deposited.

Next, as shown in FIG. 19, the silicon oxide films 26, 25 on the n-type semiconductor region 19 (source, drain) of the memory cell selecting MISFET Qs are dry-etched using the photoresist film 27 as a mask. The SOG film 24 is removed. This etching is performed under such a condition that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased, and the silicon nitride film covering the n-type semiconductor region 19 and the upper part of the element isolation trench 5 is formed. 20 is not completely removed.

The silicon oxide film 26 shown in FIG.
The surface of the resist film 27 has a dip (step) along the surface of the silicon oxide film 25 in the peripheral circuit region as shown in FIG. FIG. 19 omits its shape.

Subsequently, as shown in FIG. 20, the n-type semiconductor region 19 of the memory cell selecting MISFET Qs is dry-etched using the photoresist film 27 as a mask.
By removing the silicon nitride film 20 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed.

This etching is performed under such conditions that the etching rate of the silicon nitride film 15 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. The element isolation groove 5 is prevented from being cut deeply. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after the photoresist film 27 is removed, dry etching residues or photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At that time, the contact hole 28,
The SOG film 24 exposed on the side wall of the S.sub.29 is also exposed to the etching solution. However, the SOG film 24 has a reduced etching rate with respect to a hydrofluoric acid-based etching solution by the above-described sintering at about 800.degree. The sidewalls of the contact holes 28 and 29 are not largely undercut by the etching process. As a result, it is possible to reliably prevent a short circuit between plugs embedded in the contact holes 28 and 29 in the next step.

Next, as shown in FIG. 21, plugs 30 are formed inside the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by CVD.
After the deposition by the method, the polycrystalline silicon film is polished by the CMP method and is formed by being left inside the contact holes 28 and 29.

Next, as shown in FIG. 22, a silicon oxide film 31 having a thickness of about 200 nm is formed on the silicon oxide film 26.
Is deposited, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. By this heat treatment,
An n-type impurity in the polycrystalline silicon film forming the plug 30 is supplied from the bottom of the contact holes 28 and 29 to the n-type semiconductor region 19 (source,
Drain) and the resistance of the n-type semiconductor region 19 is reduced.

Next, as shown in FIG. 23, the silicon oxide film 31 above the contact hole 28 is removed by dry etching using the photoresist film 32 as a mask to expose the surface of the plug 30. Next, after removing the photoresist film 32, as shown in FIG. 24, the silicon oxide films 31, 26, 25 and the SOG film 24 in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask.
By removing the gate oxide film 13 and contact holes 34 and 35 above the n ⁺ -type semiconductor region 23 (source and drain) of the n-channel MISFET Qn, the p ⁺ -type semiconductor region 22 of the p-channel MISFET Qp Contact holes 36 and 37 are formed above (source, drain).

Next, after removing the photoresist film 33, as shown in FIG. 25, the bit lines BL and the first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. In order to form the bit line BL and the first layer wirings 38 and 39, first, a film thickness 5
A Ti film of about 0 nm is deposited by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 800 ° C. Next, a TiN film having a thickness of about 50 nm is deposited on the Ti film by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are patterned using the photoresist film 41 as a mask.

After a Ti film is deposited on the silicon oxide film 31, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C., whereby the Ti film reacts with the underlying Si to form an n-channel type M.
Surface of n ⁺ -type semiconductor region 23 (source, drain) of ISFET Qn, surface of p ⁺ -type semiconductor region 22 (source, drain) of p-channel MISFET Qp, and plug 3
0 surface and low resistance TiSi2 (titanium silicide)
Layer 42 is formed. Thereby, the n ⁺ type semiconductor region 2
3. The contact resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to p ⁺ type semiconductor region 22 and plug 30 can be reduced. In addition, bit line B
By configuring L with a W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the information reading speed and the writing speed can be improved, and the bit line BL and the periphery can be improved. Since the first layer wirings 38 and 39 of the circuit can be formed simultaneously in one step, the DRAM manufacturing steps can be shortened.
Further, when the first layer wirings (38, 39) of the peripheral circuit are formed of the same layer as the bit line BL, the peripheral wiring is more peripheral than the case where the first layer wiring is formed of the upper layer Al wiring of the memory cell. MISFET (n-channel MISFETQ)
Since the aspect ratio of the contact holes (34 to 37) connecting the n-channel and p-channel MISFETs Qp) to the first layer wiring is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width thereof is, for example, about 0.22 μm.

Next, after removing the photoresist film 41, as shown in FIG. 26, side wall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39.
To form The side wall spacer 43 is formed by depositing a silicon nitride film on the bit line BL and the first layer wirings 38 and 39 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG.
Then, an SOG film 44 having a thickness of about 300 nm is spin-coated on the first layer wirings 38 and 39. Next, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 44.

Since the SOG film 44 has a higher reflow property than the BPSG film and is superior in the gap fill property between fine wirings, the gap between the bit lines BL miniaturized to the resolution limit of photolithography. Can be satisfactorily embedded. In addition, since the SOG film 44 can obtain high reflow properties without performing a high-temperature and long-time heat treatment required for the BPSG film, the source and drain of the memory cell selection MISFET Qs formed under the bit line BL are formed. And MISFETs for peripheral circuits (n-channel MISFE
TQn, the p-channel type MISFET Qp) can suppress the thermal diffusion of the impurities contained in the source and drain, and can achieve a shallow junction. Further, since the deterioration of the metal (W film) forming the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C can be suppressed, the performance of the MISFET forming the memory cell and the peripheral circuit of the DRAM can be improved. Can be. Further, a Ti film, a TiN film, and a W film constituting the bit line BL and the first layer wirings 38 and 39 are formed.
Wiring resistance can be reduced by suppressing film deterioration.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 45 is polished by a CMP method to flatten the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the SOG film 44 having good flatness is applied to the bit line BL and the first layer wirings 38 and 39 immediately after the film formation, and the oxidation deposited on the SOG film 44 is further formed thereon. The silicon film 45 is planarized by the CMP method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the flattening of the insulating film on the bit lines BL and the first layer wirings 38 and 39 can be realized. Further, since heat treatment at a high temperature for a long time is not performed, the MISFE forming the memory cell and the peripheral circuit is not required.
It is possible to achieve high performance by preventing the characteristic deterioration of T, and to reduce the resistance of the bit line BL and the first layer wirings 38 and 39.

Note that a film thickness of 1
A silicon oxide film of about 00 nm may be deposited. This silicon oxide film can repair fine scratches on the surface of the silicon oxide film generated when the silicon oxide film is polished by the CMP method. Such a silicon oxide film is made of, for example, ozone (O
₃ ) and tetraethoxysilane (TEOS) can be deposited by a plasma CVD method using a source gas.

Next, as shown in FIG. 29, a silicon nitride film 46 having a thickness of about 50 nm is deposited on the silicon oxide film 45. The silicon nitride film 46 is used as an etching stopper when etching the silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later. Therefore, the silicon nitride film 4
Numeral 6 is made of a silicon nitride material whose etching rate is lower than the etching rate of the silicon oxide film between the lower electrodes described later.

Next, as shown in FIG. 30, the silicon nitride film 46, the silicon oxide film 45, the SOG film 44 and the silicon oxide film 31 above the contact hole 29 are removed by dry etching using the photoresist film 47 as a mask. Then, a through hole 48 reaching the surface of the plug 30 is formed. This etching is performed under the condition that the silicon nitride film 46 is etched under the condition that the silicon nitride is etched, and then under the condition that the etching rate of the silicon nitride film with respect to the silicon oxide films 45 and 31 and the SOG film 44 is reduced. Even if misalignment between the silicon nitride film 40 and the bit line BL occurs, the silicon nitride film 40 and the sidewall spacer 43 above the bit line BL are not deeply shaved. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after the photoresist film 47 is removed, a dry etching residue or a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At this time, the SOG film 44 exposed on the side wall of the through hole 48 is also exposed to the etching solution.
Since the etching rate of the OG film 44 with respect to the hydrofluoric acid-based etchant is reduced by the sintering at about 800 ° C., the side wall of the through hole 48 is not largely undercut by the wet etching process. Accordingly, a short circuit between the plug buried in the through hole 48 and the bit line BL in the next step can be reliably prevented. Also, since the plug and the bit line BL can be sufficiently separated from each other,
An increase in the parasitic capacitance of the bit line BL can be suppressed.

Next, as shown in FIG. 31, a plug 49 is formed inside the through hole 48. The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon nitride film 46 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside.

Next, as shown in FIG. 32, a silicon oxide film 53 having a thickness of about 0.5 μm is formed on the silicon nitride film 46.
After the silicon oxide film 53 is removed by dry etching using the photoresist film 54 as a mask, a groove 55 is formed above the through hole 48 in which the plug 49 is embedded. The silicon oxide film 53 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, after removing the photoresist film 54, as shown in FIG. 33, an upper portion of the silicon oxide film 53 is doped with an n-type impurity (for example, P (phosphorus)) to a thickness of 50 nm.
A polycrystalline silicon film 56 of about nm is deposited by a CVD method.
This polycrystalline silicon film 56 is used as a lower electrode material of the information storage capacitor.

Next, as shown in FIG. 34, a silicon oxide film 57 having a thickness (for example, about 0.4 μm) sufficient to fill the trench 55 is formed on the polycrystalline silicon film 56 by, for example, CV.
After the formation by the method D, as shown in FIG. 35, the silicon oxide film 57 is etched back by using, for example, a dry etching method to leave the silicon oxide film 57 only in the groove 55,
Further, the polycrystalline silicon film 5 on the silicon oxide film 53
By etching back 6, the polycrystalline silicon film 56 is left inside the groove 55 (the inner wall and the bottom).

Next, as shown in FIG. 36, a photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region is formed. There is no problem even if this photoresist film 58 is separated from the polycrystalline silicon film 56 which is the lower electrode of the information storage capacitor located at the outermost end of the memory cell array region by about 5 μm. Therefore, an advanced photolithography technique is not required to form the photoresist film 58. Thereby, the load on the manufacturing process can be reduced and the manufacturing method can be simplified.

Next, as shown in FIG. 37, the silicon oxide film 53 and the silicon oxide film 57 in the region where the surface is exposed are removed by wet etching. The wet etching is performed, for example, by using hydrofluoric acid (HF) and ammonium fluoride (N
H ₄ F) can be performed by immersion in a 1:20 mixed solution until the underlying silicon nitride film 46 is exposed.

The silicon oxide film 53 and the silicon oxide film 57 in the region where the surface is exposed can be removed by a dry etching method.
In order to make the etching end of 3 an inclined surface, wet etching in which etching proceeds isotropically is more convenient.
Further, the silicon nitride film 46 and the polycrystalline silicon film 56
The wet etching is more advantageous in that the etching selectivity can be ensured.

Thus, lower electrode 60 made of polycrystalline silicon film 56 is formed. Since the silicon oxide film 53 remains in the peripheral circuit region, flattening described later can be easily performed.

Although the present embodiment has exemplified the photoresist film 58, the present invention is not limited to this.

Next, the photoresist film 58 is removed, and then the polycrystalline silicon film (56) constituting the lower electrode 60 is formed.
In order to prevent oxidation of the semiconductor substrate 1, the surface of the polycrystalline silicon film (56) is nitrided by heat-treating the semiconductor substrate 1 at about 800 ° C. in an ammonia atmosphere to form a silicon nitride film (not shown) having a thickness of about 1.5 nm. ) Is formed, as shown in FIG.
A Ta ₂ O ₅ (tantalum oxide) film 61 having a film thickness of about 10 nm is deposited on the entire surface of the semiconductor substrate 1 by a CVD method, and then the semiconductor substrate 1 is heat-treated at about 800 ° C. to modify the Ta ₂ O ₅ film 61. I do. This Ta ₂ O ₅ film 61 is used as a material of a capacitive insulating film of the information storage capacitor.

Next, as shown in FIG. 39, a Ti film having a thickness of about 50 nm is formed on the Ta ₂ O ₅ film 61 by, eg, CVD.
After depositing the N film 62, the TiN film 62 and the Ta ₂ O are dry-etched using the photoresist film 63 as a mask.
₅ By patterning the film 61, the TiN film 62
, An information storage capacitor C composed of a capacitor insulating film made of a Ta ₂ O ₅ film 61 and a lower electrode 60 made of a polycrystalline silicon film 56 is formed. Thus, the DR composed of the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs is provided.
The AM memory cell is completed.

Next, after removing the photoresist film 63, a silicon oxide film 64 having a thickness of about 40 nm is deposited on the information storage capacitor C as shown in FIG. The silicon oxide film 64 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Thereafter, a thick SOG film 65 which does not cause cracking even when formed thickly is formed by spin coating to flatten the surface. An example of an SOG film that can be applied to this thick film is described in Japanese Patent Application No. 3-245499, and for example, a product name type 8 manufactured by Tokyo Ohkasha can be used.

Next, as shown in FIG. 41, first etching of the peripheral circuit is performed by dry etching using a photoresist film as a mask.
SOG film 65 and silicon oxide film 6 above layer wiring 38
4, 53, a silicon nitride film 46, a silicon oxide film 45,
By removing the SOG film 44 and the silicon nitride film 40, a through hole 66a is formed. Similarly, the through-hole 66b is formed by removing the SOG film 65 and the silicon oxide film 64 above the TiN film 62 as the upper electrode. Then, the through holes 66a, 66
A plug 67 is formed inside b, and then a second layer wiring 68 is formed above the SOG film 65. Plug 67 is an SO
A TiN film having a thickness of about 100 nm is deposited on the G film 65 by a sputtering method, and a W film having a thickness of about 500 nm is further deposited on the TiN film by a CVD method. , 66b. The second layer wiring 68 is formed by sputtering a TiN film having a thickness of about 50 nm on the SOG film 65,
Al (aluminum) film with thickness of about 500 nm, film thickness of 50
After depositing a Ti film of about nm, these films are patterned and formed by dry etching using a photoresist film as a mask.

Thereafter, a third layer wiring is formed via an interlayer insulating film, and a passivation film composed of a silicon oxide film and a silicon nitride film is deposited thereon, but is not shown. Through the above steps, the DR of the present embodiment
AM is almost completed.

The third layer wiring and the plugs connected to it can be formed in the same manner as the second layer wiring.
The interlayer insulating film can be composed of, for example, a silicon oxide film having a thickness of about 300 nm, an SOG film having a thickness of about 400 nm, and a silicon oxide film having a thickness of about 300 nm. Silicon oxide film is
For example, ozone (O ₃ ) and tetraethoxysilane (TEO)
S) can be deposited by a plasma CVD method using a source gas.

According to the present embodiment, the surface can be flattened after forming the information storage capacitive element. Conventionally, when there is a step between the memory cell array region and the peripheral circuit region, the exposure focus in the photolithography process is increased. The problem that the pattern formation becomes difficult due to a decrease in the depth margin can be solved. As a result, the capacitance can be increased by increasing the height of the lower electrode 60.

In this embodiment, the bit line BL is formed of a laminated film containing a metal, and the tantalum oxide film 61c is used as the capacitor insulating film 61 even if the heat resistance of the contact with the silicon substrate or the like becomes poor. Therefore, there is an advantage that the temperature of the heat treatment can be lowered and the conduction failure at the contact portion can be avoided.

(Embodiment 2) FIG. 42 is a sectional view showing an example of a DRAM of the present embodiment. In the DRAM of the present embodiment, a part of the capacitance insulating film 61 and the upper electrode 62 is also arranged around the upper part of the plug 49. As a result, the amount of accumulated charges can be increased.
In other words, the upper part of the plug 49 is a cylindrical electrode connected to the lower electrode 60, and the upper electrode 62 is arranged as a concentric cylindrical electrode disposed therearound, so that a cylindrical capacitive element and a cylindrical capacitive element having an opening in the upper part are provided. Are integrally formed to form an information storage capacitor.

The method of manufacturing the DRAM of the present embodiment is the same as that of the first embodiment up to the step shown in FIG.

Thereafter, as shown in FIG. 43, the silicon nitride film 46 is etched by, for example, a wet etching method using hot phosphoric acid. At this time, the silicon oxide film is not etched. Therefore, the silicon oxide film 53 functions as a kind of mask, and it is possible to prevent the entire silicon nitride film 46 in the peripheral circuit region from being etched.

Thereafter, as shown in FIG. 44, a capacitance insulating film 61 and an upper electrode 62 are formed as in the first embodiment.

The subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated. In this way, D of the present embodiment
The RAM is almost completed.

(Embodiment 3) In this embodiment, a more effective method of flattening the surface with an SOG film after forming an information storage capacitor will be described with reference to FIG.

After the formation of the information storage capacitor, a thick SO
When the G film is formed, the following problems may occur. That is, the lower electrode 60 according to the first embodiment has a cylindrical shape having an opening upward, and a concave portion is also formed on the surface of the upper electrode 62 reflecting this shape. A thick SOG film 65 is applied to the recess to flatten the surface. The thick SOG film 65 is formed by a spin coating method, and the surface is formed by forming an information storage capacitor. The unevenness generated on the surface becomes large. That is, when the width of the groove is narrow and deep, the inside of the groove may not be able to be completely filled. In such a case, voids are generated at the center, bottom, or side surfaces of the groove, and these voids may expand due to heat treatment received in a later step and break the thick SOG film 65, which is not preferable. Note that such a problem does not occur because the groove (concave portion) generated in the boundary region between the memory cell array region and the peripheral circuit region described in the first embodiment has a margin in width.

Therefore, in the present embodiment, the generation of voids is avoided by the following method. FIG. 45 is a cross-sectional view illustrating an example of the manufacturing method according to the present embodiment.

That is, the upper electrode 69 of the information storage capacitance element is formed so as to fill the groove, and the memory cell array region is previously flattened by the upper electrode 69 itself before forming the SOG. The flattening by the upper electrode is performed by depositing an upper electrode material having a thickness equal to or more than half of the longest part of the interval between the information storage capacitor elements regularly arranged in the memory cell array region by the CVD method. Can be achieved by As the upper electrode material, titanium nitride produced using titanium tetrachloride and ammonia as raw materials, well-known polycrystalline silicon, or the like can be used.

According to the present embodiment, the groove formed by forming the information storage capacitance element can be filled with the upper electrode 69 itself, which is a component of the information storage capacitance element. Can be prevented from being reduced due to voids or the like generated when the semiconductor device is filled with SOG.

(Embodiment 4) In this embodiment, a structure of a plug in the case where a metal or a metal compound is used for a lower electrode of an information storage capacitor will be described with reference to FIG.

FIG. 46 is a sectional view showing a DRAM of the fourth embodiment. In the present embodiment, a metal plug 70 formed simultaneously with the bit line BL is formed instead of the plug 30 of the first embodiment. In the present embodiment, the plug 49 formed below the lower electrode 60 can also be a metal plug. Further, the lower electrode 60 can also be formed of a metal film. Examples of the material of the metal plug and the metal film include titanium nitride or titanium nitride and tungsten.

The method of manufacturing the DRAM of the present embodiment is similar to that of the first embodiment shown in FIG.
It is the same up to 9 openings. Next, the bit line BL is formed without forming the plug 30 in the first embodiment. At this time, contact holes 3 in the peripheral circuit
The opening of the holes 4, 35, 36 and 37 in advance is the same as in the first embodiment.

Thus, the metal plug 70 can be formed simultaneously with the bit line BL and the first layer wiring 38.

Thereafter, the steps up to FIG. 30 of the first embodiment are the same, and a metal plug 71 made of titanium nitride is formed instead of the plug 49 formed in FIG.

Further, a titanium nitride film is deposited in place of the polycrystalline silicon film 56 in FIG.
A lower electrode 72 made of titanium nitride is formed by the same steps as in the first embodiment. Other steps are the same as in the first embodiment.

According to the present embodiment, since the lower electrode 72 of the information storage capacitor is made of titanium nitride, the underlying metal plug 71 can be made of a metal or a metal compound. There is an advantage that the resistance can be reduced as compared with the case of forming, and a part of the plug can be formed in the same process as the bit line.

(Embodiment 5) In this embodiment, a method of flattening the surface when the lower electrode of the information storage capacitor is formed in an island shape will be described with reference to FIGS. 47 to 51 are partial cross-sectional views illustrating the manufacturing method of the fifth embodiment in the order of steps.

The manufacturing method according to the present embodiment is similar to the manufacturing method according to the first embodiment.
This is the same for the steps up to FIG. Note that FIG.
The plug 49 in 1 is a metal plug 71 made of titanium nitride in the present embodiment. The metal plug 71 can be formed by a well-known method in which a titanium nitride film is deposited on the entire surface by a CVD method so as to fill the through hole 48, and then etched away by the deposited film thickness.

Next, as shown in FIG.
After a tungsten film is formed on the entire surface by a sputtering method, a patterned photoresist film 73 is formed at a predetermined position, and the tungsten film is processed by a dry etching method to form a lower electrode 74.

Next, as shown in FIG. 48, after removing the photoresist film 73, a tantalum oxide film (not shown) having a thickness of 15 nm is formed as a capacitive insulating film by a CVD method and heat-treated. A titanium nitride film is formed on the entire surface so as to fill the gap between the lower electrodes, and the titanium nitride film in the peripheral circuit region is removed by well-known lithography and dry etching to form an upper electrode 75.

Next, as shown in FIG.
Is formed on the entire surface by a CVD method. The silicon oxide film 76 is made of, for example, ozone and TEOS.
Can be formed by a CVD method using as a raw material.

Next, as shown in FIG. 50, a photoresist film 77 is formed in the peripheral circuit region, and using the photoresist film as a mask, the silicon oxide film 76 in the memory cell array region is etched and removed using, for example, a hydrofluoric acid solution. The effect of etching by wet etching is the same as that described in the first embodiment.

Next, as shown in FIG. 51, after removing the photoresist film 77, the silicon oxide film 7 having a thickness of 50 nm is formed.
8 is formed on the entire surface of the semiconductor substrate 1 and a thick SOG film 79 is formed.
Is applied and formed to flatten the entire surface. Silicon oxide film 7
8 and the thick SOG film 79 are the same as the silicon oxide film 64 and the thick SOG film 65 in the first embodiment.

The subsequent steps are the same as in the first embodiment.

According to the present embodiment, even if the lower electrode 74 of the information storage capacitor element has an island shape, the surface can be flattened. As a result, restrictions on photolithography can be eliminated, and the height of the island-shaped lower electrode 74 can be increased to secure a desired amount of accumulated charge.

In this embodiment, the example in which the concave portion between the memory cell array region and the peripheral circuit region is flattened by applying a thick SOG film 79 in FIG. 51 is shown. As shown in FIG. 53, after removing the photoresist film 77, a silicon oxide film 80 having a thickness of 700 nm is formed by a CVD method (FIG. 52).
The surface of the silicon oxide film 80 may be polished by a CMP method to be planarized (FIG. 53). Note that the silicon oxide film 80 is set to be thicker than the height of the island-shaped lower electrode 74. Subsequent steps can be performed in the same manner as in Embodiment 1.

In the present embodiment, the island-shaped lower electrode 7 is formed.
4 shows an example using tungsten, but the present invention is not limited to this, and titanium nitride or another metal or metal compound may be used. Also, the forming method is not limited to the sputtering method, but may be a CVD method.

(Embodiment 6) In this embodiment, a method for forming an information storage capacitor will be described with reference to FIGS. 54 and 55 are cross-sectional views showing an example of a cylindrical information storage capacitor having an opening at the top.

The DRAM of the present embodiment is similar to that of the first embodiment.
Are almost the same as those of the DRAM except for the information storage capacitor element. Therefore, description of the same part is omitted.

FIG. 54 (a) shows a titanium nitride film 82 serving as a cylindrical lower electrode having an opening at the top formed on a metal plug 81 made of titanium nitride formed on a silicon nitride film 46, and the surface thereof is formed. This shows a state where the titanium oxide film 83 is formed by oxidation. The formation of the metal plug 81 and the titanium nitride film 82 is performed by using the metal plug 71 of the above-described embodiment.
And the lower electrode 72 made of titanium nitride.

FIG. 54B further shows a tantalum oxide film 8.
4 shows a state in which 4 is formed.

An important point in realizing a cylindrical information storage capacitor having an opening at the top is the method of forming a cylindrical lower electrode having an opening at the top. As described in the first embodiment, when the lower electrode 60 is formed in a cylindrical shape, first, a groove 55 is formed in the silicon oxide film 53 serving as a base material, and a lower electrode material is formed on a side wall and a bottom of the groove 55. It is formed by leaving it. At this time, the quality of the step coverage of the lower electrode material depends on whether or not the cylindrical lower electrode 60 has an opening at the top.
Determines the realization of That is, if the step coverage is poor, the thickness of the bottom region of the groove 55 becomes thin, and the lower electrode 60 collapses when the base material is removed by etching.
Its formation becomes difficult. Therefore, in order to realize a cylindrical lower electrode having an opening in the upper part, good step coverage during electrode material deposition is an essential condition. An example of an electrode material having such characteristics is a titanium nitride film formed by a CVD method using titanium tetrachloride and ammonia as raw materials.

Therefore, in this embodiment, the lower electrode is formed by the titanium nitride film 82. The manufacturing method will be described below.

After the formation of the titanium nitride film 82, heat treatment is performed in a nitrogen atmosphere at 750 ° C. for 3 minutes. This heat treatment is intended to promote the recrystallization of titanium nitride, and is desirably performed at a temperature higher than the heat treatment temperature for the tantalum oxide film to be performed later. Then, the titanium nitride film 8
Then, a titanium oxide film 83 having a thickness of 5 nm is formed on the surface of Step 2.

Next, a tantalum oxide film 84 having a thickness of 15 nm is formed as a dielectric by a CVD method. Then 725
Heat treatment in an argon atmosphere at 3 ° C. for 3 minutes to crystallize the tantalum oxide. Further, heat treatment is performed for 5 minutes in an ozone atmosphere at 400 ° C. to oxidize and reform tantalum oxide. After this,
As in Embodiment 1, an information storage capacitor can be formed by forming a titanium nitride film and forming an upper electrode.

FIG. 55 shows a procedure for performing a process of forming a titanium oxide film on the surface of a titanium nitride film serving as a lower electrode after forming a tantalum oxide film.

After forming a cylindrical lower electrode having an opening in the upper portion with the titanium nitride film 85, the lower electrode is heated at 750 ° C. in a nitrogen atmosphere.
Heat treatment for 3 minutes, tantalum oxide film 8 with a thickness of 15 nm
6 is deposited.

Next, a heat treatment is performed for 3 minutes in an argon atmosphere at 725 ° C. to crystallize the tantalum oxide film 86.
Heat treatment was performed in an ozone atmosphere at 00 ° C. At this time, the heat treatment time can be controlled so that the titanium oxide film 87 having a thickness of 3 to 5 nm is formed on the surface of the underlying titanium nitride film 85 simultaneously with the modification of the tantalum oxide film 86. Thereafter, an upper electrode similar to the above is formed to form an information storage capacitor.

FIG. 56 shows an example of the characteristics of the information storage capacitor obtained by the above method. One of the important characteristics required for an information storage capacitor used in a semiconductor memory device is an effective film thickness. The effective film thickness indicates the electric film thickness obtained from the capacitance of the information storage capacitor, assuming that the film is made of silicon dioxide regardless of the material of the capacitor insulating film. As the effective film thickness becomes smaller, a larger capacity is obtained.

FIG. 56 shows the relationship between the heat treatment temperature (horizontal axis) and the effective film thickness (vertical axis) when tantalum oxide is heat-treated in an argon atmosphere. In the figure, A shows the case where the physical film thickness of tantalum oxide is 20 nm, and B shows the case where it is 10 nm. In each case, the effective film thickness is reduced as the heat treatment temperature is increased. At 725 ° C., the effective film thickness of B is 0.9 nm in the case of B. This is because, for example, assuming that the effective film thickness of the conventional information storage capacitor element is 3 nm and the height of the cylindrical electrode required at that time is 600 nm, the height of the cylindrical electrode is reduced by about 0.9 nm at the effective film thickness. 200nm
This means that it can be reduced to as low as this, which is an extremely great advantage in the construction of a manufacturing process as a semiconductor memory device. That is, it is possible to reduce the height of the information storage capacitor and reduce the difficulty of processing in the manufacturing process.

According to the present embodiment, since the titanium nitride films 82 and 85 formed by the CVD method are used as the lower electrodes, it is easy to form a cylindrical lower electrode having an opening above, and the titanium nitride Since silicon does not contain silicon, even if heat treatment is performed in a state where the tantalum oxide films 84 and 86 are formed thereon, silicon dioxide having a low dielectric constant is not generated. Therefore, the effective film thickness can be reduced, and a large capacity can be obtained.

(Embodiment 7) In this embodiment, a method for preventing the information storage capacitor from collapsing when the height of the information storage capacitor is increased will be described with reference to FIGS. 57 and 58. FIG.

FIGS. 57 and 58 are partial cross-sectional views illustrating the manufacturing method of this embodiment in the order of steps.

The manufacturing method of the present embodiment is similar to that of the first embodiment.
This is the same for the steps up to FIG.

Next, as shown in FIG. 57, a groove 55 is formed in the silicon oxide 53 so as to connect to a metal plug 71 embedded in a predetermined region of the silicon nitride film 46, and then the above-described titanium nitride film is formed. A groove 88 is formed on the front surface, and the inside of the groove 55 is filled with an organic substance 89. Examples of the organic material 89 include a photoresist and a polyimide resin such as polyimide isoindolo-cunazolinedione.

Next, as shown in FIG. 58, the titanium nitride film 88 exposed on the silicon oxide 53 is removed, and the trench 5 is removed.
5, the titanium nitride film 88 is left. Also, groove 5
After removing the organic material 89 filling the inside of the semiconductor device 5, a capacitive insulating film (not shown) made of tantalum oxide is formed in the same manner as in the above-described embodiment, and a titanium nitride film 90 is formed as an upper electrode to store information. A capacitive element for use is formed.

Thereafter, an interlayer insulating film is formed in the same manner as in the first embodiment, and the plug 67 and the second
The layer wiring 68 can be formed. In this embodiment, since no recess is formed between the memory cell array region and the peripheral circuit region, the SOG is partially formed in the interlayer insulating film.
There is no need to use a membrane.

According to the present embodiment, the silicon oxide film 53 which is the base material used for forming the cylindrical lower electrode having the opening at the upper portion is not removed, but is left as it is as a support. Is not collapsed. Further, a step at the boundary between the memory cell array region and the peripheral circuit region is caused by the titanium nitride film 9 serving as the upper electrode.
The film thickness of 0 is at most 100 nm, which is almost no problem in photolithography for forming an upper wiring. Further, since the base material is left as a support, the information storage capacitor element does not collapse even if it becomes relatively thin, so that the height can be increased and the capacity can be increased.

(Embodiment 8) In this embodiment, a method for increasing the capacitance while increasing the height of the information storage capacitor will be described with reference to FIGS.

FIGS. 59 to 63 are partial cross-sectional views illustrating the manufacturing method of the present embodiment in the order of steps.

The manufacturing method according to the present embodiment corresponds to the method according to the seventh embodiment.
This is the same up to the formation of the titanium nitride film 88 as the lower electrode (FIG. 59).

Thereafter, as shown in FIG. 60, the silicon oxide film 53 used as the base material is removed by etching so that about 30% of the original thickness remains. Further, a tantalum oxide film (not shown) was formed and heat-treated based on the above-described method of forming the capacitive insulating film. In this state, a connection hole 91 is provided at a predetermined position in the peripheral circuit region using lithography and dry etching. After removing the photoresist film, a titanium nitride film is formed on the entire surface to form an upper electrode of the information storage capacitor. 9
0 and the plug 92 of the peripheral circuit are formed at the same time.

Next, as shown in FIG. 61, a silicon nitride film 93 having a thickness of about 50 nm is formed on the entire surface, and a new silicon oxide film having a thickness corresponding to the removed film thickness of the silicon oxide film 53 previously removed is formed. A film 94 is deposited on the entire surface of the semiconductor substrate 1 by a CVD method.

Thereafter, as in the first embodiment, a photoresist film 95 is formed, and the silicon oxide film 94 in the memory cell array region is removed.

Next, as shown in FIG. 62, after removing the photoresist film 95, an SOG film 96 is formed to flatten the surface. The formation of the SOG film 96 can be performed in the same manner as the formation of the thick SOG film 65 of the first embodiment.

Finally, a silicon oxide film 9 having a thickness of 100 nm
After 7 is formed by the CVD method, a through hole 98 is formed in a predetermined region, a plug 99 is formed, and a second-layer wiring 100 is formed. The formation of the through hole 98, the plug 99, and the second-layer wiring 100 can be performed in the same manner as in the first embodiment.

According to the present embodiment, by leaving the insulating film serving as the base material only in the bottom region of the information storage capacitance element, the bottom region of the information storage capacitance element in which the base material remains remains the groove-shaped information storage element. The upper region from which the base material has been removed can be configured as a cylindrical information storage capacitor having an opening at the top, so that even if the height of the information storage capacitor is increased, it can be prevented from collapsing. In addition, there is an effect that the capacity can be increased. Also, since the plug 92 in the peripheral circuit region can be formed in the same step as the upper electrode 90, the through hole 9 can be formed.
8 can be made shallower, and there is also an effect that dry etching can be performed more easily.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, an example was shown in which a polycrystalline silicon film was used as the lower electrode.
A lower electrode having hemispherical silicon 101 on the surface as shown in FIG. In this case, the height of the lower electrode can be reduced to facilitate the process, or the amount of accumulated charge can be increased.

[0182]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Even if a three-dimensional capacitor is formed, a technique can be provided that does not cause a step between the memory cell array region and the peripheral circuit region.

(2) A technique for eliminating a step between the memory cell array region and the peripheral circuit region due to the formation of a three-dimensional capacitor can be provided, and the difficulty of photolithography can be eliminated.

(3) A technique for eliminating a step between the memory cell array region and the peripheral circuit region due to the formation of a three-dimensional capacitor is provided to prevent a short circuit due to a disconnection of a wiring layer formed thereon or a defective patterning. it can.

(4) It is possible to provide a semiconductor integrated circuit device realizing both the securing of the capacity of the capacitor and the high reliability.

(5) A technique for preventing the collapse of the capacitor electrode during the manufacturing process due to the increase in the height of the three-dimensional capacitor is provided, and the manufacturing yield of the semiconductor integrated circuit device can be improved.

(6) It is possible to provide a three-dimensional capacitor having a high storage capacitance value, and to provide a semiconductor integrated circuit device in which the height of the three-dimensional capacitor is reduced to secure the capacitance of the capacitor and achieve both high reliability.

(7) By eliminating the step between the memory cell array region and the peripheral circuit region, the aspect ratio of the connection hole in the peripheral circuit region, which becomes deeper, is reduced, and the processing of the connection hole in the peripheral circuit region is facilitated. Can be

(8) Since the upper and lower electrodes are composed of titanium nitride having excellent step coverage and the dielectric is also composed of tantalum oxide having excellent step coverage, the information storage capacitance element is constituted. The information storage capacitor can be realized without restricting the size.

(9) Even if the degree of integration of the semiconductor memory device is improved and the planar area allowed for each memory cell is reduced, the capacitance is ensured by increasing the height of the information storage capacitor. And a highly reliable semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 39 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 40 is an essential part cross sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 41 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view of the semiconductor substrate showing the DRAM according to the second embodiment of the present invention;

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the third embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of a semiconductor substrate showing a DRAM according to a fourth embodiment of the present invention;

FIG. 47 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 48 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 49 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 50 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 51 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 52 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIG. 53 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the fifth embodiment of the present invention;

FIGS. 54A and 54B are partial cross-sectional views of a semiconductor substrate showing a method for manufacturing a DRAM according to a sixth embodiment of the present invention;

FIGS. 55A and 55B are partial cross-sectional views of a semiconductor substrate showing a method for manufacturing a DRAM according to a sixth embodiment of the present invention;

FIG. 56 is a graph showing the performance of a capacitance insulating film forming the information storage capacitance element of the DRAM according to the sixth embodiment of the present invention.

FIG. 57 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the seventh embodiment of the present invention;

FIG. 58 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the seventh embodiment of the present invention;

FIG. 59 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 60 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 61 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 62 is a partial cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 63 is a partial cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 64 is a partially enlarged cross-sectional view illustrating an example of a lower electrode included in the information storage capacitor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 thin silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well Reference Signs List 12 n-type well 13 gate oxide film 14 gate electrode 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacers 21 the photoresist film 22 p ⁺ -type semiconductor region 23 n ⁺ -type semiconductor region 24 SOG film 25 a silicon oxide film 26 a silicon oxide film 27 a photoresist film 28 contact hole 29 the contact hole 30 plug 31 oxidized Con film 32 Photo resist film 33 Photo resist film 34 Contact hole 35 Contact hole 36 Contact hole 37 Contact hole 38 First layer wiring 40 Silicon nitride film 41 Photo resist film 42 Silicon oxide film 43 Side wall spacer 44 SOG film 45 Silicon oxide film Reference Signs List 46 silicon nitride film 47 photoresist film 48 through hole 49 plug 53 silicon oxide film 54 photoresist film 55 groove 56 polycrystalline silicon film 57 silicon oxide film 58 photoresist film 60 lower electrode (Ta ₂ O ₅ film) 61 capacitance insulating film (Tantalum oxide film) 62 TiN film (upper electrode) 63 Photoresist film 64 Silicon oxide film 65 SOG film 66a, 66b Through hole 67 Plug 68 Second layer wiring 69 Second layer wiring 70 Metal plug 71 metal plug 72 lower electrode 73 photoresist film 74 lower electrode 75 upper electrode 76 silicon oxide film 77 photoresist film 78 silicon oxide film 79 SOG film 80 silicon oxide film 81 metal plug 82 titanium nitride film 83 titanium oxide film 84 oxidation Tantalum film 85 Titanium nitride film 86 Tantalum oxide film 87 Titanium oxide film 88 Titanium nitride film 89 Organic material 90 Upper electrode (Titanium nitride film) 91 Connection hole 92 Plug 93 Silicon nitride film 94 Silicon oxide film 95 Photoresist film 96 SOG film 97 Oxidation Silicon film 98 Through hole 99 Plug 100 Second layer wiring 101 Hemispherical silicon BL Bit line C Information storage capacitor MARY Memory array Qn N-channel MISFET Qp P-channel MISFET Qs Memo MISFET for recell selection SA Sense amplifier WD Word driver

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Misuzu Kanai 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (15)

[Claims] 1. A MISFET for selecting a memory cell, a cylindrical lower electrode connected in series to the MISFET for selecting a memory cell and having an opening above, and in contact with at least the inner surface of the cylindrical shape of the lower electrode. Forming a memory cell with the formed capacitive insulating film and an information storage capacitive element having at least an upper electrode formed to face the cylindrical inner surface of the lower electrode with the capacitive insulating film interposed therebetween; A method of manufacturing a semiconductor integrated circuit device having a memory cell array region in which cells are arranged and a peripheral circuit region around the memory cell array region, wherein (a) the memory is provided in the memory cell array region on a main surface of a semiconductor substrate. After forming a MISFET for cell selection and a MISFET of a peripheral circuit in the peripheral circuit region on the main surface of the semiconductor substrate, the memory cell selection MISFET is formed. MIS of ISFET and peripheral circuit
Depositing a first insulating film having a thickness corresponding to the height of the lower electrode above the FET; (b) opening the first insulating film above the memory cell selecting MISFET to form a groove; Forming (c) depositing a first conductive film that is to be a part of the lower electrode and has a film thickness that does not fill the groove, on the first insulating film including the inside of the groove; (d) Forming a second insulating film filling a recess of the first conductive film formed in the groove, exposing the first conductive film on the first insulating film; and (e) exposing the first conductive film. Etch the film,
Leaving the first conductive film only inside the groove, (f)
Removing the second insulating film filling the recess and forming the lower electrode; (g) forming the capacitive insulating film on the surface of the lower electrode; and (h) forming the second insulating film on the capacitive insulating film. Forming a second conductive film and patterning the second conductive film to form the upper electrode. 2. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the step (f), an upper layer portion of the first insulating film is removed, and a part of the upper portion of the lower electrode is removed. A method of manufacturing a semiconductor integrated circuit device, comprising: exposing; and, after the step (h), a step of forming a third insulating film over the entire surface of the semiconductor substrate and flattening the surface. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein a connection hole is opened in said peripheral circuit region of said first insulating film from which an upper layer portion has been removed, and wherein said second conductive film is formed. Forming a plug or a wiring by patterning the second conductive film in the peripheral circuit region simultaneously with patterning of the second conductive film at the same time as the deposition of the second conductive film. Method. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein after the step (e), a step of forming a photoresist film covering the first insulating film in the peripheral circuit region, In the step (f), the removal of the second insulation film is performed simultaneously with the removal of the first insulation film in the memory cell array region by a wet etching method using the photoresist film as a mask, and the removal of the second insulation film is performed in the peripheral circuit region. (1) forming a cylindrical lower electrode having an opening above while leaving a part of the insulating film; and, after the step (h), forming a third insulating film on the entire surface of the semiconductor substrate. And a step of flattening the surface. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the fourth insulating film has a different etching rate from the first insulating film and the second insulating film before depositing the first insulating film. Depositing a film on the entire surface of the semiconductor substrate and etching and removing the fourth insulating film in the memory cell array region after the lower electrode is formed. . 6. A memory cell selecting MISFET, a cylindrical lower electrode connected in series to the memory cell selecting MISFET and having an opening above, a capacitor insulating film formed on the surface of the lower electrode, and A memory cell comprising an information storage capacitive element having an upper electrode formed opposite to the lower electrode with the capacitive insulating film interposed therebetween, and a memory cell array region in which the memory cell is arranged; and a memory cell array region (A) forming the memory cell selecting MISFET on a main surface of a semiconductor substrate, and then forming an information storage capacitor on the main surface of the semiconductor integrated circuit device. Process,
(B) depositing a first insulating film on the main surface of the semiconductor substrate so as to have a thickness equal to or greater than the height of the information storage capacitor; and (c) depositing a first insulating film in the peripheral circuit region. Forming a photoresist film covering the insulating film, removing the first insulating film in the memory cell array region by wet etching using the photoresist film as a mask, and (d) forming a third insulating film on the entire surface of the semiconductor substrate. Forming an insulating film and flattening the surface. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of flattening the surface of the third insulating film is a first step of applying an SOG film, Or a second step of etching, by a CMP method, an insulating film deposited by a vapor deposition method so as to have a thickness equal to or greater than the height of the information storage capacitor. Of manufacturing a semiconductor integrated circuit device. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second conductive film is deposited by filling a concave portion formed by a cylindrical shape of said lower electrode. And manufacturing the semiconductor integrated circuit device by flattening the surface. 9. A memory cell selecting MISFET, a cylindrical lower electrode connected in series to the memory cell selecting MISFET and having an opening above, and in contact with at least the cylindrical inner surface of the lower electrode. Forming a memory cell with the formed capacitive insulating film and an information storage capacitive element including an upper electrode formed at least in opposition to the cylindrical inner surface of the lower electrode with the capacitive insulating film interposed therebetween; A semiconductor integrated circuit device having a memory cell array region in which cells are arranged, and a peripheral circuit region around the memory cell array region, wherein the insulating film having a thickness corresponding to a height of the information storage capacitor element is provided. A first configuration provided in a peripheral circuit region, wherein a step between the memory cell array region and the peripheral circuit region is eliminated; The recesses produced, the second structure embedded by the upper electrode, wherein the information storage capacitor is MIS for the memory cell selecting constituting the information storage capacitor
The information storage capacitor formed on the top of the FET,
A cylindrical electrode comprising a part of a plug connecting the lower electrode and the memory cell selecting MISFET, and a cylindrical capacitance element including a concentric cylindrical electrode formed on the outer periphery thereof through a capacitance insulating film, The third formed in
A semiconductor integrated circuit device having any one of the above configurations. 10. A MISFET for selecting a memory cell, a lower electrode, a capacitor insulating film formed in contact with the lower electrode, connected in series with the MISFET for selecting a memory cell,
A semiconductor integrated circuit device having a memory cell including: an information storage capacitance element having an upper electrode formed to face the lower electrode with the capacitance insulating film interposed therebetween, wherein the lower electrode and the upper electrode A semiconductor integrated circuit device, wherein both are made of a conductive material containing at least titanium nitride, and the capacitive insulating film is made of an insulating film containing at least polycrystalline tantalum oxide. 11. The semiconductor integrated circuit device according to claim 10, wherein a plug connecting the memory cell selecting MISFET and the lower electrode is made of a conductive material containing titanium nitride as a main component. Semiconductor integrated circuit device. 12. The semiconductor integrated circuit device according to claim 10, wherein a titanium oxide film having a thickness of 10 nm or less is formed at an interface between said lower electrode and said capacitor insulating film. Semiconductor integrated circuit device. 13. A MISFET for selecting a memory cell, a lower electrode, a capacitor insulating film formed in contact with the lower electrode and connected in series to the MISFET for selecting a memory cell,
And a method of manufacturing a semiconductor integrated circuit device having a memory cell including an information storage capacitor having an upper electrode formed opposite to the lower electrode with the capacitor insulating film interposed therebetween. Depositing a titanium nitride film serving as the lower electrode by heat treatment in a non-oxidizing atmosphere, and (b) depositing a tantalum oxide film by a CVD method and heat treating the titanium nitride film in a non-oxidizing atmosphere. Crystallizing the tantalum film to convert it to a polycrystalline tantalum oxide film; (c) heat treating the polycrystalline tantalum oxide film in an oxidizing atmosphere to modify the polycrystalline tantalum oxide film and simultaneously form the titanium nitride film and the polycrystalline tantalum oxide film. Forming a titanium oxide film at an interface with the polycrystalline tantalum oxide film, and (d) depositing a titanium nitride film to be the upper electrode by a CVD method. Method for producing a conductive integrated circuit device. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, further comprising, after the step (a), a step of forming a titanium oxide film on a surface of the titanium nitride film. A method for manufacturing a semiconductor integrated circuit device. 15. A memory cell selecting MISFET, a lower electrode connected in series with the memory cell selecting MISFET, a capacitive insulating film formed in contact with the lower electrode,
And a method of manufacturing a semiconductor integrated circuit device having a memory cell including: an information storage capacitance element having an upper electrode formed opposite to the lower electrode with the capacitance insulating film interposed therebetween. A part of the plug connecting the MISFET and the lower electrode is replaced with the memory cell selecting MIS.
A method for manufacturing a semiconductor integrated circuit device, wherein the method is formed simultaneously with a bit line disposed above a FET.