JPH118295A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH118295A JPH118295A JP9158791A JP15879197A JPH118295A JP H118295 A JPH118295 A JP H118295A JP 9158791 A JP9158791 A JP 9158791A JP 15879197 A JP15879197 A JP 15879197A JP H118295 A JPH118295 A JP H118295A
- Authority
- JP
- Japan
- Prior art keywords
- trench isolation
- insulating film
- film
- isolation groove
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に素子分離構造に特徴を有する半
導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device characterized by an element isolation structure and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、集積回路では、デバイス間の電気
的分離を行うために、厚い酸化膜等の絶縁膜を形成する
構造を用いて、素子分離を行っていた。2. Description of the Related Art Conventionally, in an integrated circuit, element isolation has been performed by using a structure in which an insulating film such as a thick oxide film is formed in order to electrically isolate devices.
【０００３】素子分離法としては、ＬＯＣＯＳ法とトレ
ンチ分離法が報告されているが、微細化にはトレンチ分
離法が適している。[0003] As element isolation methods, a LOCOS method and a trench isolation method have been reported, but the trench isolation method is suitable for miniaturization.
【０００４】従来の技術としては、特開平４−２７１４
１号公報または特開平５−２９９４９７号公報に開示さ
れたものがある。[0004] The prior art is disclosed in Japanese Patent Laid-Open No. 4-2714.
No. 1 or JP-A-5-299497.
【０００５】[0005]
【発明が解決しようとする課題】上述した従来の技術
は、以下の問題点がある。The above-mentioned prior art has the following problems.
【０００６】図９は、従来の半導体装置のトレンチ分離
において、コンタクト配線金属位置９がずれて、コンタ
クト配線金属９とシリコン基板１が電気的短絡を生じた
模式図である。第１の課題として、トレンチ分離法で
は、図９に示すように、分離端が垂直であるために、コ
ンタクトエッチングがマスク位置からずれた場合に、基
板リークが生じやすいという問題がある。FIG. 9 is a schematic diagram in which a contact wiring metal position 9 is displaced and an electrical short circuit occurs between the contact wiring metal 9 and the silicon substrate 1 in trench isolation of a conventional semiconductor device. As a first problem, in the trench isolation method, as shown in FIG. 9, since the isolation end is vertical, there is a problem that a substrate leak easily occurs when contact etching is shifted from a mask position.
【０００７】図１０は、膜応力の大きい絶縁膜でトレン
チ分離溝内部を埋め込み、熱処理した後に結晶欠陥が生
じる模式図である。即ち、第２の課題として、図１０に
示すように、膜応力の大きい絶縁膜でトレンチ内部を埋
め込むと、結晶欠陥１３が生じる為に、基板リークが生
じやすいという問題がある。FIG. 10 is a schematic view showing a state in which crystal defects occur after the trench isolation trench is filled with an insulating film having a large film stress and heat-treated. That is, as shown in FIG. 10, when the inside of the trench is filled with an insulating film having a large film stress, as shown in FIG.
【０００８】本発明の目的は、基板リークが生じない素
子分離構造を有する半導体装置及びその製造方法を提供
することにある。An object of the present invention is to provide a semiconductor device having an element isolation structure that does not cause substrate leakage, and a method of manufacturing the same.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板の一主面に設けられたトレンチ分離溝と、ト
レンチ分離溝に埋め込まれた第１の絶縁膜と、トレンチ
分離溝の上端部に埋め込まれた第２の絶縁膜とにより形
成される素子分離構造を有する。According to the present invention, there is provided a semiconductor device comprising:
An element formed by a trench isolation groove provided on one main surface of a semiconductor substrate, a first insulating film embedded in the trench isolation groove, and a second insulating film embedded in an upper end of the trench isolation groove. Has a separation structure.
【００１０】また、半導体基板の一主面に設けられたト
レンチ分離溝と、トレンチ分離溝に埋め込まれた第１の
絶縁膜と、トレンチ分離溝に埋め込まれた半導体膜と、
トレンチ分離溝の上端部に埋め込まれた第２の絶縁膜と
により形成される素子分離構造を有してもよい。A trench isolation groove provided on one main surface of the semiconductor substrate; a first insulating film embedded in the trench isolation groove; a semiconductor film embedded in the trench isolation groove;
An element isolation structure formed by a second insulating film buried in the upper end of the trench isolation groove may be provided.
【００１１】また、トレンチ分離溝に埋め込まれた半導
体膜がシリコン膜で構成されてもよい。Further, the semiconductor film buried in the trench isolation groove may be constituted by a silicon film.
【００１２】本発明の半導体装置の製造方法は、半導体
基板の一主面に第３の絶縁膜と第４の絶縁膜とを形成し
た後、トレンチ分離溝を形成する工程と、トレンチ分離
溝に第１の絶縁膜を埋め込む工程と、第１の絶縁膜の表
面を平坦化した後、第３の絶縁膜と第４の絶縁膜とを除
去する工程と、第２の絶縁膜をトレンチ分離溝の上端部
に堆積する工程とを含む。In a method of manufacturing a semiconductor device according to the present invention, a step of forming a third insulating film and a fourth insulating film on one principal surface of a semiconductor substrate and then forming a trench isolation groove; Embedding the first insulating film, removing the third insulating film and the fourth insulating film after planarizing the surface of the first insulating film, and forming the second insulating film into a trench isolation trench. And depositing it on the upper end.
【００１３】また、半導体基板の一主面に第３の絶縁膜
と第４の絶縁膜とを形成した後、トレンチ分離溝を形成
する工程と、トレンチ分離溝に第１の絶縁膜と半導体膜
とを埋め込む工程と、第１の絶縁膜の表面を平坦化した
後、第３の絶縁膜と第４の絶縁膜とを除去する工程と、
第２の絶縁膜をトレンチ分離溝の上端部に堆積する工程
とを含んでもよい。A step of forming a third insulating film and a fourth insulating film on one main surface of the semiconductor substrate and then forming a trench isolation groove; and forming the first insulating film and the semiconductor film in the trench isolation groove. And a step of planarizing the surface of the first insulating film and then removing the third insulating film and the fourth insulating film,
Depositing a second insulating film on the upper end of the trench isolation groove.
【００１４】また、第１の絶縁膜の表面を平坦化する方
法として、化学機械的ポリッシング法を用いてもよい。As a method for flattening the surface of the first insulating film, a chemical mechanical polishing method may be used.
【００１５】また、第１の絶縁膜がシリコン酸化膜で構
成され、第２の絶縁膜がシリコン窒化膜で構成されても
よい。Further, the first insulating film may be composed of a silicon oxide film and the second insulating film may be composed of a silicon nitride film.
【００１６】また、トレンチ分離溝に埋め込まれた半導
体膜がシリコン膜で構成されてもよい。Further, the semiconductor film embedded in the trench isolation trench may be constituted by a silicon film.
【００１７】従って、トレンチ分離溝上端に局部的に形
成された凹部を、埋め込み絶縁膜とは異なる絶縁膜によ
り埋め込むことにより、所望のトレンチ構造を形成でき
る。Therefore, a desired trench structure can be formed by burying the concave portion locally formed at the upper end of the trench isolation groove with an insulating film different from the buried insulating film.
【００１８】また、コンタクトエッチングがずれた場合
にも、トレンチ分離溝を埋め込んだ絶縁膜をエッチング
することなく、コンタクト配線金属を形成できる。Further, even when the contact etching is shifted, the contact wiring metal can be formed without etching the insulating film filling the trench isolation trench.
【００１９】[0019]
【発明の実施の形態】次に、本発明の第一の実施の形態
について図面を参照して説明する。Next, a first embodiment of the present invention will be described with reference to the drawings.
【００２０】図１は、本発明の半導体装置の第一の実施
の形態を示すトレンチ分離溝の断面図である。図中のト
レンチ分離溝２では、第１の絶縁膜３はトレンチ分離溝
２全体を埋め込む絶縁膜であり、第２の絶縁膜８はトレ
ンチ分離溝２上端部のみを埋め込む絶縁膜で構成され
る。この構造により、トレンチ分離溝２近傍に形成され
るコンタクト配線金属がトレンチ分離溝２上に形成され
る場合にも、第２の絶縁膜８がエッチングされにくい為
に、コンタクト配線金属が半導体基板１と電気的に短絡
しない利点がある。FIG. 1 is a sectional view of a trench isolation groove showing a first embodiment of the semiconductor device of the present invention. In the trench isolation groove 2 in the figure, the first insulating film 3 is an insulation film that fills the entire trench isolation groove 2, and the second insulation film 8 is an insulation film that fills only the upper end of the trench isolation groove 2. . With this structure, even when the contact wiring metal formed near the trench isolation groove 2 is formed on the trench isolation groove 2, the second insulating film 8 is hardly etched. And has the advantage of not being electrically short-circuited.
【００２１】図２は、本発明の半導体装置の第二の実施
の形態を示すトレンチ分離溝の断面図である。図中のト
レンチ分離溝２では、第１の絶縁膜３はトレンチ外周を
埋め込む絶縁膜であり、半導体膜４は、トレンチ分離溝
２内周を埋め込む薄膜であり、第２の絶縁膜８はトレン
チ分離溝２上端部のみを埋め込む絶縁膜で構成される。
この構造により、第一の実施の形態と同様に、トレンチ
分離溝２近傍に形成されるコンタクト配線金属がトレン
チ分離溝２上に形成される場合にも、コンタクト配線金
属が半導体基板１と電気的に短絡しない利点がある。FIG. 2 is a sectional view of a trench isolation groove showing a second embodiment of the semiconductor device of the present invention. In the trench isolation groove 2 in the figure, the first insulation film 3 is an insulation film filling the outer periphery of the trench, the semiconductor film 4 is a thin film filling the inner periphery of the trench isolation groove 2, and the second insulation film 8 is a trench. It is composed of an insulating film filling only the upper end of the isolation groove 2.
With this structure, similarly to the first embodiment, even when the contact wiring metal formed near the trench isolation groove 2 is formed on the trench isolation groove 2, the contact wiring metal is electrically connected to the semiconductor substrate 1. Has the advantage of not shorting.
【００２２】次に、図３を用いて、本発明の半導体装置
の製造方法の第一の実施の形態を説明する。図３（ａ）
は、半導体基板１上に、パッド用シリコン酸化膜５とパ
ッド用シリコン窒化膜６を形成した後、通常のリソグラ
フィ工程とエッチング工程により、トレンチ分離溝２を
形成した状態を示す。次に図３（ｂ）に示すように、ト
レンチ分離溝２をシリコン酸化膜３により埋め込んだ状
態を示す。次に図３（ｃ）に示すように、化学機械的ポ
リッシング法によりシリコン酸化膜３をポリッシング
し、表面を平坦化した後、さらにダミーであるパッド用
シリコン窒化膜６とパッド用シリコン酸化膜５をウェッ
トエッチングにて除去する。前記化学機械的ポリッシン
グ法では、パッド用シリコン窒化膜６でポリッシングは
自動的に止まり、表面は平坦となると共に、トレンチ分
離溝２埋め込みのシリコン酸化膜３の上端部は凹部形状
７になる。さらに図３（ｄ）に示すように、シリコン窒
化膜８を堆積した後、エッチバックを行い、トレンチ分
離溝２上端凹部７にのみ、シリコン窒化膜８を残し、本
発明のトレンチ分離を完成する。Next, a first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 3 (a)
FIG. 3 shows a state in which a silicon oxide film 5 for a pad and a silicon nitride film 6 for a pad are formed on a semiconductor substrate 1 and then a trench isolation groove 2 is formed by a normal lithography process and an etching process. Next, as shown in FIG. 3B, a state in which the trench isolation trench 2 is buried with the silicon oxide film 3 is shown. Next, as shown in FIG. 3 (c), the silicon oxide film 3 is polished by a chemical mechanical polishing method to planarize the surface, and furthermore, the pad silicon nitride film 6 and the pad silicon oxide film 5 are dummy. Is removed by wet etching. In the chemical mechanical polishing method, the polishing is automatically stopped at the pad silicon nitride film 6, the surface becomes flat, and the upper end of the silicon oxide film 3 embedded in the trench 2 becomes a concave shape 7. Further, as shown in FIG. 3D, after the silicon nitride film 8 is deposited, the silicon nitride film 8 is etched back to leave the silicon nitride film 8 only in the recess 7 at the upper end of the trench isolation groove 2, thereby completing the trench isolation of the present invention. .
【００２３】次に図４を用いて、本発明の半導体装置の
製造方法の第二の実施の形態を説明する。図４（ａ）
は、半導体基板１上に、パッド用シリコン酸化膜５とパ
ッド用シリコン窒化膜６を形成した後、通常のリソグラ
フィ工程とエッチング工程により、トレンチ分離溝２を
形成した状態を示す。次に図４（ｂ）に示すように、ト
レンチ分離溝２をシリコン酸化膜３とシリコン膜４によ
り埋め込んだ状態を示す。次に図４（ｃ）に示すよう
に、化学機械的ポリッシング法によりシリコン酸化膜３
をポリッシングし、表面を平坦化した後、さらにダミー
であるパッド用シリコン窒化膜６とパッド用シリコン酸
化膜５をウェットエッチングにて除去する。前記化学機
械的ポリッシング法では、パッド用シリコン窒化膜６で
エッチングは自動的に止まり、表面は平坦となると共
に、トレンチ分離溝２埋め込みのシリコン酸化膜３の上
端部は凹部形状７になる。さらに図４（ｄ）に示すよう
に、シリコン窒化膜８を堆積した後、エッチバックを行
い、トレンチ分離溝２上端凹部７にのみ、シリコン窒化
膜８を残し、本発明のトレンチ分離を完成する。Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 4 (a)
FIG. 3 shows a state in which a silicon oxide film 5 for a pad and a silicon nitride film 6 for a pad are formed on a semiconductor substrate 1 and then a trench isolation groove 2 is formed by a normal lithography process and an etching process. Next, as shown in FIG. 4B, a state in which the trench isolation trench 2 is buried with the silicon oxide film 3 and the silicon film 4 is shown. Next, as shown in FIG. 4C, the silicon oxide film 3 is formed by a chemical mechanical polishing method.
Then, the silicon nitride film 6 for pad and the silicon oxide film 5 for pad are removed by wet etching. In the chemical mechanical polishing method, the etching is automatically stopped at the pad silicon nitride film 6, the surface becomes flat, and the upper end of the silicon oxide film 3 embedded in the trench 2 is formed into a concave shape 7. Further, as shown in FIG. 4D, after the silicon nitride film 8 is deposited, the silicon nitride film 8 is etched back to leave the silicon nitride film 8 only in the recess 7 at the upper end of the trench isolation groove 2, thereby completing the trench isolation of the present invention. .
【００２４】次に図５を用いて、本発明の半導体装置の
製造方法の第三の実施の形態を説明する。図５（ａ）
は、半導体基板１上に、パッド用シリコン酸化膜５とパ
ッド用シリコン窒化膜６を形成した後、通常のリソグラ
フィ工程とエッチング工程により、トレンチ分離溝２を
形成した状態を示す。次に図５（ｂ）に示すように、ト
レンチ分離溝２をシリコン酸化膜３とシリコン膜４によ
り埋め込んだ状態を示す。次に図５（ｃ）に示すよう
に、レジスト膜を塗布した後、ドライエッチングにより
シリコン酸化膜３をエッチバックし、表面を平坦化し、
さらにダミーであるパッド用シリコン窒化膜６とパッド
用シリコン酸化膜５をウェットエッチングにて除去す
る。前記ドライエッチングでは、パッド用シリコン窒化
膜６でエッチングは自動的に止まり、表面は平坦となる
と共に、トレンチ分離溝２埋め込みのシリコン酸化膜３
の上端部は凹部形状７になる。さらに図５（ｄ）に示す
ように、シリコン窒化膜８を堆積した後、エッチバック
を行い、トレンチ分離溝２上端凹部７にのみ、シリコン
窒化膜８を残し、本発明のトレンチ分離を完成する。Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 5 (a)
FIG. 3 shows a state in which a silicon oxide film 5 for a pad and a silicon nitride film 6 for a pad are formed on a semiconductor substrate 1 and then a trench isolation groove 2 is formed by a normal lithography process and an etching process. Next, as shown in FIG. 5B, a state in which the trench isolation trench 2 is buried with the silicon oxide film 3 and the silicon film 4 is shown. Next, as shown in FIG. 5C, after applying a resist film, the silicon oxide film 3 is etched back by dry etching to flatten the surface.
Further, the pad silicon nitride film 6 and the pad silicon oxide film 5 which are dummy are removed by wet etching. In the dry etching, the etching is automatically stopped at the pad silicon nitride film 6, the surface becomes flat, and the silicon oxide film 3 embedded in the trench isolation trench 2 is formed.
Has a concave shape 7 at its upper end. Further, as shown in FIG. 5D, after the silicon nitride film 8 is deposited, etch back is performed to leave the silicon nitride film 8 only in the upper concave portion 7 of the trench isolation groove 2, thereby completing the trench isolation of the present invention. .
【００２５】本発明は、トレンチ分離構造を形成する実
験結果および絶縁膜エッチングの実験結果に基づくもの
である。まず、トレンチ分離構造を形成する場合に、酸
化膜と窒化膜をダミー絶縁膜とすることにより、図６に
示すように、ウェットエッチング法によりトレンチ分離
溝上端に局部的に凹部を形成できる。この凹部を埋め込
み絶縁膜とは異なる絶縁膜により埋め込むことにより、
所望のトレンチ構造を形成できる。また、シリコン酸化
膜とシリコン窒化膜のエッチングでは、従来技術では、
エッチング速度がほぼ同じであった。しかし、ＣＦｘガ
スを用いたエッチングにより、図７に示すように、シリ
コン酸化膜とシリコン窒化膜のエッチング速度比を１０
倍程度とすることが可能である。従って、図６と図７の
結果を用いることにより、コンタクトエッチングがずれ
た場合にも、トレンチ分離溝を埋め込んだ絶縁膜をエッ
チングすることなく、コンタクト配線金属を形成でき
る。The present invention is based on the experimental results of forming a trench isolation structure and the experimental results of insulating film etching. First, when forming a trench isolation structure, by using an oxide film and a nitride film as dummy insulating films, a concave portion can be locally formed at the upper end of the trench isolation groove by wet etching as shown in FIG. By embedding this concave portion with an insulating film different from the embedded insulating film,
A desired trench structure can be formed. Further, in the etching of the silicon oxide film and the silicon nitride film, in the related art,
The etching rates were almost the same. However, as shown in FIG. 7, the etching rate ratio between the silicon oxide film and the silicon nitride film is reduced to 10 by etching using CFx gas.
It can be about twice. Therefore, by using the results of FIGS. 6 and 7, even if the contact etching is shifted, the contact wiring metal can be formed without etching the insulating film filling the trench isolation trench.
【００２６】本発明では図８に示すように、コンタクト
配線金属９が素子分離上にずれた場合にも、分離端での
絶縁膜がエッチングされないので、コンタクト配線金属
９が半導体基板１と電気的短絡を生じない。In the present invention, as shown in FIG. 8, even when the contact wiring metal 9 is shifted on the element isolation, the insulating film at the separation end is not etched, so that the contact wiring metal 9 is electrically connected to the semiconductor substrate 1. No short circuit occurs.
【００２７】[0027]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００２８】図１は、本発明の半導体装置の第一の実施
例を示す。図中のトレンチ分離溝２の幅は０．３μｍ、
深さは０．５μｍである。トレンチ分離溝２を埋め込む
第１の絶縁膜はシリコン酸化膜３であり、ＣＶＤ法によ
り形成される。トレンチ分離溝２の上端部を埋め込む第
２の絶縁膜はシリコン窒化膜８であり、ＣＶＤ法により
形成される。この構造により、トレンチ分離溝２近傍に
形成されるコンタクトがトレンチ分離溝２上に形成され
る場合にも、シリコン窒化膜８がエッチングされにくい
為に、コンタクトがシリコン基板１と電気的に短絡する
ことはない。FIG. 1 shows a first embodiment of the semiconductor device of the present invention. The width of the trench isolation groove 2 in the figure is 0.3 μm,
The depth is 0.5 μm. The first insulating film that fills the trench isolation groove 2 is a silicon oxide film 3 and is formed by a CVD method. The second insulating film filling the upper end of the trench isolation groove 2 is a silicon nitride film 8 and is formed by a CVD method. With this structure, even when a contact formed in the vicinity of trench isolation groove 2 is formed on trench isolation groove 2, the contact is electrically short-circuited with silicon substrate 1 because silicon nitride film 8 is not easily etched. Never.
【００２９】図２は、本発明の半導体装置の第二の実施
例を示すトレンチ分離溝の断面図である。図中のトレン
チ分離溝２の幅は０．１μｍ、深さは、０．２μｍであ
る。トレンチ分離溝２の外周を埋め込む第１の絶縁膜は
シリコン酸化膜３であり、トレンチ分離溝２の内周を埋
め込む半導体膜はシリコン膜４であり、トレンチ分離溝
２上端部を埋め込む第２の絶縁膜はシリコン窒化膜８で
構成される。この構造により、第一の実施例と同様に、
トレンチ分離溝２近傍に形成されるコンタクト配線金属
はシリコン基板１と電気的に短絡しにくい利点がある。FIG. 2 is a sectional view of a trench isolation groove showing a second embodiment of the semiconductor device of the present invention. The width of the trench isolation groove 2 in the figure is 0.1 μm and the depth is 0.2 μm. The first insulating film filling the outer periphery of the trench isolation groove 2 is a silicon oxide film 3, the semiconductor film filling the inner periphery of the trench isolation groove 2 is a silicon film 4, and the second filling the upper end of the trench isolation groove 2. The insulating film is composed of the silicon nitride film 8. With this structure, similar to the first embodiment,
The contact wiring metal formed in the vicinity of the trench isolation groove 2 has an advantage that it is difficult to electrically short-circuit with the silicon substrate 1.
【００３０】次に、図３を用いて、本発明の半導体装置
の製造方法の第一の実施例を説明する。図３（ａ）は、
シリコン半導体基板１上に、１０ｎｍ厚のパッド用シリ
コン酸化膜５と３０ｎｍ厚のパッド用シリコン窒化膜６
を形成した後、通常のリソグラフィ工程とエッチング工
程により、０．３μｍ幅、０．５μｍ深さのトレンチ分
離溝２を形成した状態を示す。次に図３（ｂ）に示すよ
うに、トレンチ分離溝２をＣＶＤ法により０．２μｍ厚
のシリコン酸化膜３により埋め込んだ状態を示す。次に
図３（ｃ）に示すように、化学機械的ポリッシング法に
よりシリコン酸化膜３を０．１５μｍだけポリッシング
し、表面を平坦化する。その後、さらにダミーであるパ
ッド用シリコン窒化膜６とパッド用シリコン酸化膜５を
ウェットエッチングにて除去する。前記化学機械的ポリ
ッシング法では、パッド用シリコン窒化膜６でポリッシ
ングは自動的に止まり、表面は平坦となると共に、トレ
ンチ分離溝２を埋め込むシリコン酸化膜３の上端部は
０．０３μｍほど凹部形状７になる。さらに図３（ｄ）
に示すように、シリコン窒化膜８を０．０６μｍ程度堆
積した後、エッチングを行い、トレンチ分離溝上端凹部
７にのみ、シリコン窒化膜８を残し、本発明のトレンチ
分離を完成する。Next, a first embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 3 (a)
10 nm thick pad silicon oxide film 5 and 30 nm thick pad silicon nitride film 6 on silicon semiconductor substrate 1
Is formed, a trench isolation groove 2 having a width of 0.3 μm and a depth of 0.5 μm is formed by a normal lithography process and an etching process. Next, as shown in FIG. 3B, a state is shown in which the trench isolation groove 2 is buried with a 0.2 μm thick silicon oxide film 3 by the CVD method. Next, as shown in FIG. 3C, the silicon oxide film 3 is polished by 0.15 μm by a chemical mechanical polishing method to flatten the surface. Then, the pad silicon nitride film 6 and the pad silicon oxide film 5 which are dummy are further removed by wet etching. In the chemical mechanical polishing method, the polishing is automatically stopped at the pad silicon nitride film 6, the surface is flattened, and the upper end of the silicon oxide film 3 filling the trench isolation trench 2 has a recessed portion 7 of about 0.03 μm. become. Further, FIG.
As shown in FIG. 7, after a silicon nitride film 8 is deposited to a thickness of about 0.06 μm, etching is performed to leave the silicon nitride film 8 only in the recess 7 at the upper end of the trench isolation groove, thereby completing the trench isolation of the present invention.
【００３１】次に図４を用いて、本発明半導体装置の製
造方法の第二の実施例を説明する。図４（ａ）は、シリ
コン半導体基板１上に、７ｎｍのパッド用シリコン酸化
膜５と２０ｎｍのパッド用シリコン窒化膜６を形成した
後、通常のリソグラフィ工程とエッチング工程により、
０．２μｍ幅、０．４μｍ深さのトレンチ分離溝２を形
成した状態を示す。次に図４（ｂ）に示すように、トレ
ンチ分離溝２を０．１５μｍ厚のシリコン酸化膜３と
０．０５μｍ厚のシリコン膜４により埋め込んだ状態を
示す。次に図４（ｃ）に示すように、表面のシリコン膜
４をエッチバックした後、化学機械的ポリッシング法に
よりシリコン酸化膜３を０．１５μｍだけポリッシング
し、表面を平坦化する。さらにダミーであるパッド用シ
リコン窒化膜６とパッド用シリコン酸化膜５をウェット
エッチングにて除去する。前記化学機械的ポリッシング
法では、パッド用シリコン窒化膜６でエッチングは自動
的に止まり、表面は平坦となると共に、ウェットエッチ
ングによりトレンチ分離溝２を埋め込むシリコン酸化膜
３の上端部は０．０２μｍの凹部形状７になる。さらに
図４（ｄ）に示すように、０．０４μｍのシリコン窒化
膜８を堆積した後、エッチバックを行い、トレンチ分離
溝上端凹部７にのみ、シリコン窒化膜８を残し、本発明
のトレンチ分離を完成する。Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 4A shows that a 7 nm pad silicon oxide film 5 and a 20 nm pad silicon nitride film 6 are formed on a silicon semiconductor substrate 1 and then subjected to a normal lithography process and an etching process.
This shows a state where a trench isolation groove 2 having a width of 0.2 μm and a depth of 0.4 μm is formed. Next, as shown in FIG. 4B, a state is shown in which the trench isolation groove 2 is buried with a silicon oxide film 3 having a thickness of 0.15 μm and a silicon film 4 having a thickness of 0.05 μm. Next, as shown in FIG. 4C, after the surface silicon film 4 is etched back, the silicon oxide film 3 is polished by 0.15 μm by a chemical mechanical polishing method to flatten the surface. Further, the pad silicon nitride film 6 and the pad silicon oxide film 5 which are dummy are removed by wet etching. In the chemical mechanical polishing method, the etching automatically stops at the pad silicon nitride film 6, the surface becomes flat, and the upper end of the silicon oxide film 3 filling the trench isolation trench 2 by wet etching has a thickness of 0.02 μm. The concave shape 7 is obtained. Further, as shown in FIG. 4D, after depositing a silicon nitride film 8 of 0.04 μm, etch back is performed, and the silicon nitride film 8 is left only in the recess 7 at the upper end of the trench isolation groove. To complete.
【００３２】次に図５を用いて、本発明の半導体装置の
製造方法の第三の実施例を説明する。図５（ａ）は、シ
リコン半導体基板１上に、１０ｎｍのパッド用シリコン
酸化膜５と４０ｎｍのパッド用シリコン窒化膜６を形成
した後、通常のリソグラフィ工程とエッチング工程によ
り、０．４μｍ幅、０．５μｍ深さのトレンチ分離溝２
を形成した状態を示す。次に図５（ｂ）に示すように、
トレンチ分離溝２を０．１５μｍ厚のシリコン酸化膜３
と０．０５μｍ厚のシリコン膜４により埋め込んだ状態
を示す。次に図５（ｃ）に示すように、５０ｎｍのレジ
スト膜を塗布した後、ドライエッチングにより０．１５
μｍのシリコン酸化膜３をエッチバックし、表面を平坦
化し、さらにダミーであるパッド用シリコン窒化膜６と
パッド用シリコン酸化膜５をウェットエッチングにて除
去する。前記ドライエッチングでは、パッド用シリコン
窒化膜６でエッチングは自動的に止まる。また、ウェッ
トエッチングによりトレンチ分離溝２を埋め込むシリコ
ン酸化膜３の上端部は０．０５μｍの凹部形状７にな
る。さらに図５（ｄ）に示すように、０．０８μｍのシ
リコン窒化膜８を堆積した後、エッチバックを行い、ト
レンチ分離溝上端凹部７にのみ、シリコン窒化膜８を残
し、本発明のトレンチ分離を完成する。Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 5A shows that after a 10-nm pad silicon oxide film 5 and a 40-nm pad silicon nitride film 6 are formed on a silicon semiconductor substrate 1, a 0.4-μm wide silicon oxide film 5 is formed by a normal lithography process and an etching process. 0.5 μm deep trench isolation groove 2
Shows a state in which is formed. Next, as shown in FIG.
A trench isolation groove 2 is formed with a silicon oxide film 3 having a thickness of 0.15 μm.
And a state in which the silicon film 4 is buried with a 0.05 μm thick silicon film 4. Next, as shown in FIG. 5C, a 50 nm resist film is applied, and then 0.15% by dry etching.
The .mu.m silicon oxide film 3 is etched back to flatten the surface, and the dummy pad silicon nitride film 6 and pad silicon oxide film 5 are removed by wet etching. In the dry etching, the etching is automatically stopped at the pad silicon nitride film 6. The upper end of the silicon oxide film 3 filling the trench isolation trench 2 by wet etching has a concave shape 7 of 0.05 μm. Further, as shown in FIG. 5 (d), after depositing a silicon nitride film 8 of 0.08 μm, etch back is performed to leave the silicon nitride film 8 only in the recess 7 at the upper end of the trench isolation groove. To complete.
【００３３】[0033]
【発明の効果】以上説明したように本発明は、以下の効
果がある。As described above, the present invention has the following effects.
【００３４】本発明の第１の効果は、コンタクト配線金
属が素子分離上にずれた場合にも、分離端での絶縁膜が
エッチングされないので、コンタクト配線金属が半導体
基板と電気的短絡を生じない効果がある。The first effect of the present invention is that even when the contact wiring metal is shifted on the element isolation, the insulating film at the separation end is not etched, so that the contact wiring metal does not cause an electrical short circuit with the semiconductor substrate. effective.
【００３５】本発明の第２の効果は、本発明では、シリ
コン窒化膜をトレンチ分離端のみに形成することによ
り、窒化の膜応力により発生しやすい結晶欠陥を抑制で
き、基板リークを生じない利点がある。The second effect of the present invention is that, in the present invention, by forming a silicon nitride film only at the trench isolation end, crystal defects which are likely to be generated due to nitride film stress can be suppressed, and no substrate leak occurs. There is.
【図１】本発明の半導体装置の第一の実施の形態（実施
例）を示した模式的断面図である。FIG. 1 is a schematic cross-sectional view showing a first embodiment (example) of a semiconductor device of the present invention.
【図２】本発明の半導体装置の第二の実施の形態（実施
例）を示した模式的断面図である。FIG. 2 is a schematic sectional view showing a second embodiment (example) of the semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の第一の実施の
形態（実施例）を示した模式的断面図である。 （ａ）半導体基板上に、パッド用シリコン酸化膜とパッ
ド用シリコン窒化膜を形成した後、トレンチ分離溝を形
成した状態を示す。 （ｂ）トレンチ分離溝をシリコン酸化膜により埋め込ん
だ状態を示す。 （ｃ）シリコン酸化膜をポリッシングし、表面を平坦化
した後、パッド用シリコン窒化膜とパッド用シリコン酸
化膜を除去した状態を示す。 （ｄ）シリコン窒化膜を堆積した後、トレンチ分離溝上
端凹部にのみ、シリコン窒化膜を残した状態を示す。FIG. 3 is a schematic sectional view showing a first embodiment (example) of the method for manufacturing a semiconductor device according to the present invention. (A) A state in which a silicon oxide film for a pad and a silicon nitride film for a pad are formed on a semiconductor substrate, and then a trench isolation groove is formed. (B) shows a state where the trench isolation trench is buried with a silicon oxide film. (C) A state in which the silicon oxide film for pads and the silicon oxide film for pads are removed after polishing and flattening the surface of the silicon oxide film. (D) A state in which the silicon nitride film is left only in the recess at the upper end of the trench isolation groove after the silicon nitride film is deposited.
【図４】本発明の半導体装置の製造方法の第二の実施の
形態（実施例）を示した模式的断面図である。 （ａ）半導体基板上に、パッド用シリコン酸化膜とパッ
ド用シリコン窒化膜を形成した後、トレンチ分離溝を形
成した状態を示す。 （ｂ）トレンチ分離溝をシリコン酸化膜とシリコン膜に
より埋め込んだ状態を示す。 （ｃ）シリコン酸化膜をポリッシングし、表面を平坦化
した後、パッド用シリコン窒化膜とパッド用シリコン酸
化膜を除去した状態を示す。 （ｄ）シリコン窒化膜を堆積した後、トレンチ分離溝上
端凹部にのみ、シリコン窒化膜を残した状態を示す。FIG. 4 is a schematic sectional view showing a second embodiment (example) of the method for manufacturing a semiconductor device according to the present invention. (A) A state in which a silicon oxide film for a pad and a silicon nitride film for a pad are formed on a semiconductor substrate, and then a trench isolation groove is formed. (B) shows a state where the trench isolation trench is filled with a silicon oxide film and a silicon film. (C) A state in which the silicon oxide film for pads and the silicon oxide film for pads are removed after polishing and flattening the surface of the silicon oxide film. (D) A state in which the silicon nitride film is left only in the recess at the upper end of the trench isolation groove after the silicon nitride film is deposited.
【図５】本発明の半導体装置の製造方法の第三の実施の
形態（実施例）を示した模式的断面図である。 （ａ）半導体基板上に、パッド用シリコン酸化膜とパッ
ド用シリコン窒化膜を形成した後、トレンチ分離溝を形
成した状態を示す。 （ｂ）トレンチ分離溝をシリコン酸化膜とシリコン膜に
より埋め込んだ状態を示す。 （ｃ）シリコン酸化膜をエッチバックし、表面を平坦化
した後、パッド用シリコン窒化膜とパッド用シリコン酸
化膜を除去した状態を示す。 （ｄ）シリコン窒化膜を堆積した後、トレンチ分離溝上
端凹部にのみ、シリコン窒化膜を残した状態を示す。FIG. 5 is a schematic sectional view showing a third embodiment (example) of the method for manufacturing a semiconductor device according to the present invention. (A) A state in which a silicon oxide film for a pad and a silicon nitride film for a pad are formed on a semiconductor substrate, and then a trench isolation groove is formed. (B) shows a state where the trench isolation trench is filled with a silicon oxide film and a silicon film. (C) A state in which the silicon oxide film is etched back, the surface is flattened, and then the pad silicon nitride film and the pad silicon oxide film are removed. (D) A state in which the silicon nitride film is left only in the recess at the upper end of the trench isolation groove after the silicon nitride film is deposited.
【図６】ウェットエッチング法によりトレンチ分離溝上
端に局部的に凹部を形成する工程を示す模式図である。FIG. 6 is a schematic view showing a step of locally forming a concave portion at an upper end of a trench isolation groove by a wet etching method.
【図７】従来技術およびＣＦｘガスを用いた新技術での
シリコン酸化膜とシリコン窒化膜のエッチング速度を示
す図である。FIG. 7 is a diagram showing etching rates of a silicon oxide film and a silicon nitride film in a conventional technique and a new technique using CFx gas.
【図８】本発明の半導体装置のトレンチ分離において、
コンタクト配線金属の位置がずれた場合のコンタクト配
線金属と拡散層との関係を示した模式図である。FIG. 8 shows a trench isolation of the semiconductor device of the present invention.
FIG. 4 is a schematic diagram showing a relationship between a contact wiring metal and a diffusion layer when the position of the contact wiring metal is shifted.
【図９】従来の半導体装置のトレンチ分離において、コ
ンタクト配線金属の位置がずれて、コンタクト配線金属
とシリコン基板が電気的短絡を生じた模式図である。FIG. 9 is a schematic diagram in which a contact wiring metal is displaced in a trench isolation of a conventional semiconductor device, causing an electrical short circuit between the contact wiring metal and a silicon substrate.
【図１０】膜応力の大きい絶縁膜でトレンチ分離溝内部
を埋め込み、熱処理した後に結晶欠陥が生じる模式図で
ある。FIG. 10 is a schematic diagram in which crystal defects occur after the trench isolation trench is filled with an insulating film having a large film stress and subjected to a heat treatment.
１ 半導体基板（シリコン基板） ２ トレンチ分離溝 ３ 第１の絶縁膜（シリコン酸化膜） ４ 半導体膜（シリコン膜） ５ パッド用シリコン酸化膜 ６ パッド用シリコン窒化膜 ７ トレンチ分離溝上端凹部 ８ 第２の絶縁膜（シリコン窒化膜） ９ コンタクト配線金属 １０ 層間絶縁膜 １１ 拡散層 １２ コンタクト配線金属と基板の電気的短絡路 １３ 結晶欠陥 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate (silicon substrate) 2 Trench isolation groove 3 First insulating film (silicon oxide film) 4 Semiconductor film (silicon film) 5 Silicon oxide film for pad 6 Silicon nitride film for pad 7 Trench isolation groove upper concave part 8 Second Insulating film (silicon nitride film) 9 Contact wiring metal 10 Interlayer insulating film 11 Diffusion layer 12 Electrical short circuit between contact wiring metal and substrate 13 Crystal defect
Claims (9)
チ分離溝と、該トレンチ分離溝に埋め込まれた第１の絶
縁膜と、前記トレンチ分離溝の上端部に埋め込まれた第
２の絶縁膜とにより形成される素子分離構造を有するこ
とを特徴とする半導体装置。1. A trench isolation groove provided on one main surface of a semiconductor substrate, a first insulating film embedded in the trench isolation groove, and a second insulation film embedded in an upper end of the trench isolation groove. A semiconductor device having an element isolation structure formed by a film.
チ分離溝と、該トレンチ分離溝に埋め込まれた第１の絶
縁膜と、前記トレンチ分離溝に埋め込まれた半導体膜
と、前記トレンチ分離溝の上端部に埋め込まれた第２の
絶縁膜とにより形成される素子分離構造を有することを
特徴とする半導体装置。2. A trench isolation trench provided on one main surface of a semiconductor substrate, a first insulating film embedded in the trench isolation trench, a semiconductor film embedded in the trench isolation trench, and the trench isolation. A semiconductor device having an element isolation structure formed by a second insulating film embedded in an upper end portion of a groove.
４の絶縁膜とを形成した後、トレンチ分離溝を形成する
工程と、前記トレンチ分離溝に第１の絶縁膜を埋め込む
工程と、前記第１の絶縁膜の表面を平坦化した後、前記
第３の絶縁膜と前記第４の絶縁膜とを除去する工程と、
第２の絶縁膜を前記トレンチ分離溝の上端部に堆積する
工程とを含むことを特徴とする半導体装置の製造方法。3. A step of forming a third insulating film and a fourth insulating film on one main surface of a semiconductor substrate and then forming a trench isolation groove, and embedding the first insulating film in the trench isolation groove. Removing the third insulating film and the fourth insulating film after flattening the surface of the first insulating film;
Depositing a second insulating film on the upper end of the trench isolation groove.
４の絶縁膜とを形成した後、トレンチ分離溝を形成する
工程と、前記トレンチ分離溝に第１の絶縁膜と半導体膜
とを埋め込む工程と、前記第１の絶縁膜の表面を平坦化
した後、前記第３の絶縁膜と前記第４の絶縁膜とを除去
する工程と、第２の絶縁膜を前記トレンチ分離溝の上端
部に堆積する工程とを含むことを特徴とする半導体装置
の製造方法。4. A step of forming a third insulating film and a fourth insulating film on one main surface of a semiconductor substrate and then forming a trench isolation groove, and forming a first insulating film and a semiconductor in the trench isolation groove. Burying a film, planarizing the surface of the first insulating film, removing the third insulating film and the fourth insulating film, and separating the second insulating film by the trench isolation. Depositing on the upper end of the groove.
法として、化学機械的ポリッシング法を用いることを特
徴とする請求項３または請求項４に記載の半導体装置の
製造方法。5. The method of manufacturing a semiconductor device according to claim 3, wherein a chemical mechanical polishing method is used as a method of planarizing a surface of the first insulating film.
成され、前記第２の絶縁膜がシリコン窒化膜で構成され
ることを特徴とする請求項１または請求項２に記載の半
導体装置。6. The semiconductor device according to claim 1, wherein said first insulating film is made of a silicon oxide film, and said second insulating film is made of a silicon nitride film. .
成され、前記第２の絶縁膜がシリコン窒化膜で構成され
ることを特徴とする請求項３または請求項４に記載の半
導体装置の製造方法。7. The semiconductor device according to claim 3, wherein said first insulating film is made of a silicon oxide film, and said second insulating film is made of a silicon nitride film. Manufacturing method.
体膜がシリコン膜で構成されることを特徴とする請求項
１または請求項２に記載の半導体装置。8. The semiconductor device according to claim 1, wherein the semiconductor film buried in the trench isolation groove is made of a silicon film.
体膜がシリコン膜で構成されることを特徴とする請求項
３または請求項４に記載の半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor film embedded in the trench isolation groove is formed of a silicon film.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158791A JPH118295A (en) | 1997-06-16 | 1997-06-16 | Semiconductor device and its manufacture |
| GB9813008A GB2326526B (en) | 1997-06-16 | 1998-06-16 | Semiconductor device with trench isolation structure and fabrication method thereof |
| KR1019980022530A KR19990007026A (en) | 1997-06-16 | 1998-06-16 | Semiconductor device having trench isolation structure and method of manufacturing the same |
| CNB981147836A CN1155072C (en) | 1997-06-16 | 1998-06-16 | Semiconductor device with trench isolation structure and fabrication method thereof |
| US09/097,664 US5929504A (en) | 1997-06-16 | 1998-06-16 | Semiconductor device with trench isolation structure and fabrication method thereof |
| US09/300,441 US6197661B1 (en) | 1997-06-16 | 1999-04-28 | Semiconductor device with trench isolation structure and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158791A JPH118295A (en) | 1997-06-16 | 1997-06-16 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH118295A true JPH118295A (en) | 1999-01-12 |
Family
ID=15679429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9158791A Pending JPH118295A (en) | 1997-06-16 | 1997-06-16 | Semiconductor device and its manufacture |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5929504A (en) |
| JP (1) | JPH118295A (en) |
| KR (1) | KR19990007026A (en) |
| CN (1) | CN1155072C (en) |
| GB (1) | GB2326526B (en) |
Cited By (2)
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|---|---|---|---|---|
| KR100344766B1 (en) * | 1999-10-26 | 2002-07-19 | 주식회사 하이닉스반도체 | Method for isolating semiconductor devices |
| JP2006013341A (en) * | 2004-06-29 | 2006-01-12 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
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-
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-
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- 1998-06-16 CN CNB981147836A patent/CN1155072C/en not_active Expired - Lifetime
- 1998-06-16 GB GB9813008A patent/GB2326526B/en not_active Expired - Fee Related
- 1998-06-16 US US09/097,664 patent/US5929504A/en not_active Expired - Lifetime
-
1999
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100344766B1 (en) * | 1999-10-26 | 2002-07-19 | 주식회사 하이닉스반도체 | Method for isolating semiconductor devices |
| JP2006013341A (en) * | 2004-06-29 | 2006-01-12 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
| JP4592340B2 (en) * | 2004-06-29 | 2010-12-01 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990007026A (en) | 1999-01-25 |
| CN1204147A (en) | 1999-01-06 |
| US5929504A (en) | 1999-07-27 |
| GB2326526A (en) | 1998-12-23 |
| GB2326526B (en) | 2001-12-19 |
| US6197661B1 (en) | 2001-03-06 |
| GB9813008D0 (en) | 1998-08-12 |
| CN1155072C (en) | 2004-06-23 |
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