JPH1174857A - Method and system for switching transmission line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and system for switching transmission lines that is useful for making an application specific integrated circuit ASIC package small and for simplifying pattern wiring because the number of switch drive circuits and control lines is small. SOLUTION: A changeover circuit 2 has 64 changeover switches SW inserted to, e.g. 64 transmission lines that are arranged into (8×8) matrices and a matrix circuit where each drive circuit DV corresponding to each changeover switch SW is arranged to each row and each column is formed. Column designation drive circuits 11-1n are driven by a changeover control signal from a control circuit 1 and when a drive circuit 21 designated by a 1st row is driven, 8 changeover switches 111, 112,...,11N of the 1st row receiving the drive signal simultaneously from the column designation drive circuits 11-1n and the drive circuit 21 designated by the 1st row are closed and a signal on a transmission line to each changeover switch inserted is selected as an output SO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line switching method and apparatus for selecting and switching a predetermined number of transmission lines from a plurality of transmission lines. The present invention relates to a transmission line switching method and apparatus suitable for switching between an active system and a standby system on a transmission line between interfaces.

[0002]

2. Description of the Related Art FIG. 7 shows an SDH (Synchronous Digital).
FIG. 1 is a schematic configuration diagram of a 600M multiplex terminal termination device adapted to a Hierarchy) transmission system. This device 50 is an existing digital hierarchy signal PDH (Plesiochro
Nous Digital Hierarchy) is a device that multiplexes a signal into an SDH signal and outputs a 600 Mbps optical signal.
Terminal low-speed part (T-LS) that performs multiplexing up to 50 Mbps
Unit) 51, a terminal low-speed unit (L-LS unit) 52 that relays and terminates a 50 Mbps or 150 Mbps signal, 600 Mbps signals from the terminal low-speed unit 51 and the terminal low-speed unit 52
The system includes a high-speed unit (HS unit) 53 for multiplexing into s optical signals and a control unit (COM unit) 54 for controlling and monitoring the entire system.

[0003] The terminal low-speed section 51 is a PDH signal (existing 1.
5 Mbps system, 2 Mbps system, 6.3 Mbps system, and 8 Mbps system) and the SDH signal,
This unit has a function of interfacing with the high-speed unit 53 of 600 Mbps. The terminal low-speed section 51 is provided with an interface switch package having a function of switching between the active system and the standby system in the low-speed main signal path in order to increase the reliability of the transmission path.

FIG. 8 is a diagram showing a more detailed configuration of the terminal low-speed section 51. As shown in FIG. In the figure, the interface switch package is included in the low-speed interface unit. The switching system between the active and standby low-speed main signals is 4
N1 to N4 (reference numerals: 3a, to, 3)
d), one backup board E1 (symbol: 3e) and eight transmission lines (S) and eight reception lines (R) accommodated in the four working boards N1,..., N4. , A switching circuit 200 for selecting a set of transmission line (S) and reception line (R) and switching connection to the standby board E1; and a control circuit 100 for controlling the switching of the switching circuit 200. The low-speed interface unit is connected at one end to an information terminal or the like via each of the transmission lines (the transmission line (S) and the reception line (R)). The high-speed section 53 is connected via the section 5.

In a conventional device of this type, a switching circuit 200 in a low-speed interface unit includes, for example, changeover switches 901, 902,.
0N, and these changeover switches 901, 901
902,..., 90N corresponding to the driving circuits 91, 92,
, 9N, and the corresponding changeover switches 901, 902,..., 9 through the respective drive circuits 91, 92,.
0N is individually switched.

Accordingly, for example, as shown in FIG. 8, one of the active substrates N1,..., N4 accommodating eight output lines (S) and eight input lines (R) is connected to the standby substrate E.
The switching circuit 200 used for switching to 1 requires 64 [(8 × 2) × 4] changeover switches corresponding to the number of all transmission paths and the same number of drive circuits. It was necessary to arrange 64 control lines for each of the changeover switches.

By the way, in the switching circuit 200 used in this type of device, a register of a switching control command for each switching switch is stored in an ASIC (applicant) such as an FPGA.
It is generally built in an ion-specific integrated circuit. In this case, if the number of control lines increases, it becomes difficult to accommodate the control lines in the ASIC due to the limitation of the number of input / output pins, and when these control lines are formed, the pattern wiring on the substrate becomes complicated. . In addition, in the conventional switching circuit 200 requiring as many as 64 control lines by adopting the structure as shown in FIG. 9, it is extremely difficult to perform pattern wiring in the ASIC including the auxiliary circuits such as monitoring and control. Package size is increased. Furthermore, in the conventional switching circuit 200, when a relay is used as a switching switch, the number of components such as a drive transistor for driving the relay is required as much as the number of the switching switches, and the number of components cannot be avoided.

[0008]

As described above, for example, a switching circuit used for switching between an active system and a standby system on a transmission path between a low-speed interface and a high-speed interface in a multiplexing unit of a communication device. As a conventional configuration, a changeover switch is provided for each transmission line and a drive circuit is arranged corresponding to each changeover switch, while each drive circuit is activated through a control line corresponding to one to one. Generally, the configuration is such that the switches to be switched are individually switched. When the number of transmission paths to be switched increases, the number of drive circuits and control lines for each of the switches increases in proportion to the increase in the number of switches. Was. For this reason, this type of switching circuit, which is usually realized by being housed in an ASIC, causes an increase in the size of the ASIC package, an increase in the number of parts, and an increase in the number of parts on the substrate when forming control lines. There is a problem that the pattern wiring becomes complicated.

The present invention solves the above problems, reduces the number of switch drive circuits and control lines associated with the increase in the number of changeover switches, reduces the size of an ASIC package, reduces the number of parts, and reduces the number of control lines. It is an object of the present invention to provide a transmission line switching method and apparatus capable of preventing the pattern wiring from being complicated when forming.

[0010]

According to a first aspect of the present invention, there is provided a transmission line switching method for selecting and switching a predetermined number of transmission lines from a plurality of transmission lines. A switch circuit in which a plurality of changeover switches inserted therein are arranged in a matrix of N rows and M columns, and a row designating switch drive for supplying a drive signal to each changeover switch in the switch circuit in row units Circuit, and a column designating switch drive circuit for supplying a drive signal to each of the changeover switches in the switch circuit on a column basis. The (N × M) changeover switches arranged in the matrix are (N + M) ) Using a plurality of switch drive circuits to control the conduction state in units of rows or columns, and collectively switch the transmission paths through which the respective changeover switches in units of rows or columns are inserted. And butterflies.

According to a second aspect of the present invention, there is provided a transmission line switching device for selecting and switching a predetermined number of transmission lines from among a plurality of transmission lines, wherein each of the transmission line switching devices is interposed in the transmission line and the first drive signal and the And a switch circuit in which a plurality of changeover switches that are turned on by being simultaneously supplied with the two drive signals are arranged in a matrix of N rows and M columns, and the first changeover switch is provided for each of the changeover switches in a row unit. N row designating switch driving circuits for providing drive signals, M column designating switch drive circuits for supplying the second drive signal to each of the changeover switches in column units, the row designating switch drive circuits, A switching control circuit that selectively activates a column designating switch drive circuit and controls the respective switching switches to be in a conducting state collectively in row units or column units.

According to a third aspect of the present invention, in the second aspect of the present invention, an abnormality detecting means for detecting an abnormality of the row designation switch driving circuit and the column designation switch driving circuit, and the abnormality is detected by the abnormality detecting means. And an abnormality notifying means for notifying the occurrence of the abnormality.

According to a fourth aspect of the present invention, in the second or third aspect, the changeover switch is constituted by a relay, and the row designation switch drive circuit is connected to one input terminal of a drive coil of the relay. The column designating switch driving circuit is constituted by a first transistor, and the column designating switch driving circuit is constituted by a second transistor connected to the other input terminal of the driving coil of the relay.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the abnormality detecting means outputs an exclusive OR operation result of a base-emitter potential of each of the first transistor and the second transistor. An exclusive OR circuit, an OR circuit for outputting a result of an OR operation of the outputs of the exclusive OR circuits, and an output corresponding to an abnormality of each of the transistors in the OR circuit as an alarm output. And a latch circuit.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a schematic configuration of a terminating low-speed section 51 of a multiple terminal station terminating apparatus 50 according to an embodiment of the present invention. This terminal low speed part 5
Reference numeral 1 is an improved version of the switching circuit 2 as described below, and the other basic configuration is the same as that of the conventional terminal low-speed section 51 shown in FIG.

That is, the terminal low-speed section 51 includes a low-speed interface section, a multiplexing section 4, and a high-speed interface section 5.
In particular, the low-speed interface unit is provided with a function of switching between the active system and the standby system in the low-speed main signal path in order to increase the reliability of the transmission path. As components of the switching function, four active boards N1,.
(Reference numerals: 3a to 3d), one backup board E1 (reference sign: 3e), a switching circuit 2 interposed between the transmission lines accommodated in the active boards N1, to N4 and the backup board E1, And a control circuit 1 for controlling the switching of the switching circuit 2.

Each of the four active boards N1,..., N4 has eight transmission lines (S1,..., S4) and eight reception lines (R).
1,..., R4). These transmission paths are connected to an information terminal or the like at one end, and are branched and connected to the standby board E1 via the switching circuit 2. The control circuit 1 controls switching of the switching circuit 2. Further, the multiplexing unit 4 uses the existing 1.5M
bps system, 2Mbps system, 6.3Mbps system, and 8M
The high-speed interface unit 5 performs bidirectional conversion between a bps-based PDH signal and an SDH signal.
(Shown in FIG. 7).

First, the general operation of the terminal low-speed section 51 will be described. When all of the active boards N1,..., N4 are in a normal state, signals output from the information terminals and the like are transmitted through transmission lines (S1,..., S4) corresponding to these active boards N1,. The data is transmitted to the multiplexing unit 4. The multiplexing unit 4 multiplexes the signals sent from each of the active boards N1,.
, And the high-speed interface section 5 outputs the multiplexed signal to the high-speed section 53.

The high-speed interface unit 5 transfers the multiplexed signal sent from the high-speed unit 53 to the multiplexing unit 4. The multiplexing unit 4 converts the multiplexed signal into a non-multiplexed signal by a process reverse to the above-described multiplexing, and converts the signal into the active system boards N1,.
4 Each working system board N1, ..., N4
Transmits the non-multiplexed signal sent from the multiplexing unit 4 to the information terminal or the like of each destination through the respective receiving lines (R1,..., R4).

During the execution of the communication, if any of the active boards N1,..., N4 or the transmission line has a fault, the control circuit 1 determines whether the faulty active board N1,.
The switching control of the switching circuit 2 is performed so that the standby system board E1 is inserted into the transmission line in place of the active system substrates N1 to N4 accommodating the transmission line N4 or the failed transmission line. The switching control of the switching circuit 2 by the control circuit 1 is performed, for example, by monitoring the failure of the active boards N1,..., N4 or each transmission line in the COM unit 54 of the multiplex terminal termination device 50, and checking the monitoring result. Based on the switching control command output from the COM unit 54 based on the command, the control circuit 1 performs the switching control on the switching circuit 2 according to the command.

In this embodiment, the switching circuit 2 that receives the above switching control is configured as shown in FIG. 2, for example.
That is, the switching circuit 2 includes the above-mentioned active boards N1,
.., N4, each of which has eight output lines and four input lines, ie, [(8 + 8) × 4 = 64] switches SW arranged in an (8 × 8) matrix. A matrix circuit is formed for each of the changeover switches SW by arranging a drive circuit DV for driving each of the changeover switches SW in units of rows and columns. Hereinafter, the driving circuits DV (11,
To 1n) are referred to as column designating drive circuits, and the drive circuits DV (21, to 2n) arranged in row units are referred to as row designating drive circuits.

In this switching circuit (matrix circuit) 2, the column designating drive circuits 11,.
, And the row designation drive circuits 21,..., 2n are commonly connected to each of the eight changeover switches in each row. Here, the column designation drive circuits 11,..., 1n and the row designation drive circuits 21,.
A drive signal is sent to each switch SW of the connection destination based on a switch control signal given from the control circuit 1. Each changeover switch SW is connected to the column designating drive circuit 1
The switches are turned on (conducting state) when the drive signals are simultaneously supplied from both the first,..., 1n and the row designation drive circuits 21,.

FIG. 3 is a circuit diagram showing a specific configuration of the matrix circuit 2 in FIG. This matrix circuit 2
Are the changeover switches 111, 112,..., 1 in FIG.
1N, 121, 122, ..., 12N, ..., 1N1, 1N
2,..., 1NN as relays S100, S102,.
S114, S101, S103,..., S115,.
, S415, the transistors Tr21, Tr28, and Tr28 as the column designation driving circuits 11,..., 1n in FIG.
, 2n as transistors Tr2A,.
This is realized by using r2H.

The principle of operation of the matrix circuit 2 in FIG. 3 will be described with reference to FIG. FIG. 4 is a circuit diagram showing a conceptual configuration of a drive circuit for one relay in the matrix circuit 2 in FIG.
The row designating transistor 41 (Tr21, Tr22,...) And the column designating transistor 42 (Tr2A, Tr2B,...) Are connected to the drive coil 40 of 0, S102,. In this circuit, the row designating transistor 4
By inputting the “L” level to the base input (a) of 1 and the “H” level to the base input (b) of the column designating transistor 42, the point (c) becomes the “H” level and the point (d) becomes It becomes “L” level, a current flows through the relay drive coil 40, and the relay is turned on.

Based on the operation principle of the relay,
Returning to FIG. 2, the switching operation of the entire matrix circuit 2 will be described. In the figure, it is assumed that each changeover switch SW is realized by a relay as shown in FIGS. 3 and 4, and each drive circuit DV is realized by a transistor as shown in FIGS. 3 and 4.

In the matrix circuit 2 shown in FIG. 2, when the column designating drive circuits 11,..., 1n are driven by the switching control signal generated by the control circuit 1, the drive circuits 11,.
, 1n, a positive voltage (or a negative voltage) is applied to one end of the coil of the changeover switch SW.
In this state, when the drive circuit 21, for example, of the first row designation among the row designation drive circuits 21,..., 2n is driven, the changeover switches 111, 11 connected to this drive circuit 21
A negative voltage (or a positive voltage) is applied to the other end of each of the coils 2,..., 11N. At this time, a positive voltage is applied to one end of the coil by the column designation driving circuits 11,..., 1n, and at the same time, a negative voltage is applied to the other end of the coil by the row designation driving circuit 21. Changeover switches 111, 1
, 11N are turned on, and the signal on the transmission path through which the changeover switches 111, 112,..., 11N are inserted is selected as the output SO1.

Similarly, the column designating drive circuits 11,..., 1n are driven by the switching control signal generated by the control circuit 1, and one end of the coil of the changeover switch SW connected to the drive circuits 11,. In the state where a positive voltage (or a negative voltage) is applied to each of the driving circuits 22 specified in the second row,
, A negative voltage (or a positive voltage) is applied to the other ends of the coils of the changeover switches 121, 122,..., 12N connected to the drive circuit 22. At this time, a positive voltage is applied to one end of the coil by the column designation driving circuits 11,..., 1n, and at the same time, a negative voltage is applied to the other end of the coil by the row designation driving circuit 22. , 12N are turned on, and the signal on the transmission line through which the switches 121, 122, ..., 12N are inserted is selected as the output SO2.

According to the configuration example of FIG.
, 11N are respectively inserted into the respective transmission lines (S1) of the active board N1, and the selector switches 121, 122,..., 12N are respectively connected to the respective reception lines (R1) of the active board N1. ) Is inserted. Therefore, as a result of the switching control, the switching switches 111 and 11
, 11N are turned on, the respective signals S on the eight transmission lines (S1) of the active board N1 are passed through the respective changeover switches 111, 112,.
S11,..., SS18 are output.
When 1, 122,..., 12N are turned on,
Each of the signals S on the eight reception lines (R1) of the active board N1 is passed through the respective changeover switches 121, 122,.
R11,..., SR18 are output.

As described above, in the matrix circuit 2 of the present invention, the column designating drive circuits 11,.
For example, a drive circuit 21 designated in the first row among 1, 2, and 3n
, The signals on the eight transmission lines (S1) of the active board N1 can be switched collectively.
By simultaneously driving the drive circuit 22 specified in the second row, the signals on the eight reception lines (R1) of the active board N1 can be switched collectively. With the same control, the driving circuits 23 and 24, 25 and 26, and 27 and 28 are simultaneously driven in a state where the column designating driving circuits 11,..., 1n are driven, so that the active substrates N2, N3, N
4, the signals on the transmission line and the reception line can be switched collectively.

That is, according to the present invention, the active substrate N1,
, N4, and when the output and input of the active system board in which the fault has occurred are switched to the standby system board E1, the control circuit 1 sends a signal to, for example, the column designation drive circuit 1
1,..., 1n and the row designation drive circuits 21,.
Of these, the switching control signal may be simultaneously sent to the two drive circuits DV corresponding to the two rows of changeover switches SW interposed between the transmission line and the reception line of the active board in which the fault has occurred.

As shown in FIG. 2, four active boards N
According to the configuration of the matrix circuit 2 for realizing the switching of the 64 transmission lines accommodated in 1, to N4, the number of drive circuits DV for the 64 changeover switches SW interposed for each transmission line Is equal to (the number of rows + the number of columns) in the matrix arrangement of the 64 changeover switches SW, that is, (8)
+ 8 = 16) is sufficient. In this case, the number of control lines from the control circuit 1 to each of the drive circuits DV is inevitably 16.
For example, when the same function is realized by a conventional circuit having a structure as shown in FIG. 9, a drive circuit DV is provided for each of the 64 changeover switches SW, and a control line is provided for each drive circuit DV. According to the configuration of the present invention, the driving circuit DV and the control lines are greatly reduced, so that the ASIC package size can be reduced.
The pattern wiring for forming the control line can be simplified.

FIG. 5 is a diagram showing an example of a specific circuit structure of the matrix circuit 2 shown in FIG. The matrix circuit 2 is composed of eight matrix circuits M1,..., M8 including eight changeover switches SW, and each of the matrix circuits M1,.
The transmission line (S) and the reception line (R) of N4 are pulled in.
Specifically, for example, for the matrix circuit M1,
A total of eight transmission lines of the first transmission lines (total of four lines) of the working boards N1, to N4 and the first reception lines (total of four lines) of each of the boards N1, to N4 are drawn. It is. Hereinafter, similarly, the matrix circuits M2, M3, M4,
For each of M5, M6, M7, and M8, each active system substrate N
1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th transmission lines (total of 4 lines) of N4 and 2nd, 3rd lines of the same substrate N1, ..., N4 , Fourth,
A total of eight transmission lines of the fifth, sixth, seventh, and eighth reception lines (four in total) are drawn in. As a result, each of the changeover switches SW in each of the matrix circuits M1,.
Signals SS11, SS21, SS31, SS41, SR11, SR2
1, SR31, SR41, ..., SS18, SS28, SS38, S
S48, SR18, SR28, SR38 and SR48 are respectively input. Here, the signal SS11 means a signal on the first transmission line of the substrate N1, and the signal SR11 means a signal on the first reception line of the substrate N1. Other signals have the same meaning. For example, the signal SS48 means a signal on the eighth transmission line of the substrate N4, and the signal SR48 means a signal on the eighth reception line of the substrate N4. ing.

The matrix circuits M1,..., M
8 and the control circuit 1, the matrix circuits M1,
8 control lines (row control lines) LA1,..., L for driving eight changeover switches SW in M8 in units of rows.
A8 is connected to eight control lines (column control lines) LB1, ..., LB8 for driving in column units.

In order to control the switching of the matrix circuits M1,..., M8, the control circuit 1 sends the control lines LA1,
, LA8 and the column control lines LB1,. As a method for supplying this drive signal, for example,
The control circuit 1 sends drive signals to all of the control lines LB1,..., LB8 in the columns of the matrix circuits M1,..., M8, and at the same time, any one of the control lines LA1,. And sends a drive signal to the controller. At this time, in each of the matrix circuits M1,..., M8, the eight changeover switches SW connected to the control lines of the row to which the drive signal has been sent out.
Are turned on, and the signal input to each of the changeover switches SW in the row unit is an 8-bit output signal SO11,.
It is output as SO18 (or SO21,..., SO28).

As a specific example, if a drive signal is sent to the control line LA1 in the row corresponding to the first row while the drive signal is sent to all of the control lines LB1,... The output signals SO11, SO12,
, SO18 as signals SS11, SS12,.
SS18 can be obtained. At the same time, by sending a drive signal to the control line LA5 in the row corresponding to the fifth row,
Output signals SO2 from the matrix circuits M1,.
1, SO22,..., SO28 as signals SR11,
, SR18 can be obtained. Here, the former 8-bit signals SS11, SS12,..., SS18 are signals on the eight transmission lines of the active board N1, respectively.
The bit signals SR11, SR12,..., SR18 are signals on the eight receiving lines of the active board N1. From this, it can be seen that by providing the drive signal in the above-described pattern, eight transmission lines and eight reception lines of the active board N1 can be switched collectively. Other active substrate N
Similar control is possible for the switching of 2, 4, and N4.

Next, the function of detecting an abnormality in the matrix circuit 2 according to the present invention will be described. FIG. 6 is a circuit diagram showing an example of the abnormality monitoring circuit 60 provided in the matrix circuit 2 of the multiple terminal unit 50 according to the present invention. This circuit 60 uses, for example, a relay as the changeover switch SW, and in the matrix circuit 2 (see FIG. 3) that drives the relay with a transistor, whether the transistor that drives the relay operates normally in response to the switching control command. It is to monitor whether or not. As constituent elements, a plurality of exclusive NOR (EXNOR) gates for outputting the exclusive OR operation result of the base input and the collector output for each of the row designating transistor (Tr1) and the column designating transistor (Tr2) in the matrix circuit 2 61, a logical sum (OR) gate 62 for outputting a logical sum operation result of the outputs of these EXNOR gates 61,
An alarm latch circuit (ALM LATCH) 63 for latching the output of the R gate 62 and generating an alarm output is provided.
In FIG. 10, EXNO for a pair of transistors is shown.
Although only the R gate 61 is shown, actually, an EXNOR gate 61 is provided for every transistor pair in the matrix circuit 2.

In the abnormality monitoring circuit 60, the abnormality of each of the transistors Tr1, Tr21,... Is detected by comparing the base and collector levels of the transistors Tr1, Tr21,. If the transistor Tr is normal, its base and collector levels are always in an inverted relationship. That is, when there is no inversion relationship, the transistor Tr is abnormal.

According to the relationship between the two inputs of the base and the collector, each EXNOR gate 61 outputs an "L" level because the two inputs do not match when the transistor Tr is normal. Since the two inputs match, an "H" level is output. The above-described monitoring is performed on all the transistors Tr, and the OR gate 62 detects the presence or absence of the abnormality of the transistor Tr by taking the logical sum (OR) of the monitoring result (the output of the EXNOR gate 61).

If all the transistors Tr are normal,
The output of the OR gate 62 becomes "L" level and is latched by the alarm latch circuit 63, and the latch result is sent to a register (not shown) as an alarm output. At this time, the control circuit 1 recognizes that the transistor Tr is normal because the alarm output held in the register is at “L” level, and does not perform the abnormality notification. On the other hand, if at least one of the transistors Tr is abnormal, the output of the OR gate 62 becomes "H" level and is latched by the alarm latch circuit 63, and the latch result is sent to the register as an alarm output. At this time, the control circuit 1 recognizes that the transistor Tr is abnormal due to the “H” level of the alarm output held in the register, and notifies the abnormality of the transistor.

The abnormality monitoring circuit 60 shown in FIG. 6 is provided with an alarm latch circuit 63 between the alarm detection unit and the reading register, in order to capture an instantaneous alarm which recovers in a short time.
Is provided. On the other hand, in this type of transistor abnormality detection processing, a hazard may occur as a transient phenomenon of switching of the transistor Tr due to the instantaneous determination that the levels on the base side and the collector side are the same. In this case, in the alarm latch circuit 63, there is a risk that a hazard generated in the alarm detection unit is held as an alarm. As a countermeasure against the hazard, for example, a configuration can be adopted in which a register write signal (at the time of switching control writing) is used as a trigger to generate a mask signal during a period in which the hazard occurs, thereby preventing erroneous occurrence of an alarm. The alarm latch in the alarm latch circuit 63 is cleared by inputting a clear signal to a clear terminal in response to the register read signal.

[0041]

As described above, according to the present invention,
By arranging the changeover switches in a matrix, arranging switch drive circuits for each of the changeover switches in row units and column units, and selectively activating the switch drive circuits, the changeover switches are arranged in row units or Since switching is performed in column units, it is sufficient to provide (N + M) switch drive circuits and control lines for (N × M) changeover switches, and a switch drive circuit and control line are provided for each changeover switch. ASI compared to the conventional configuration
The size of the C package can be reduced, the number of components can be reduced, and the pattern wiring on the substrate for forming the control lines can be greatly simplified.

Further, according to the matrix switch structure of the present invention, a plurality of transmission paths to be switched are led to the switch for each row or column for each group, so that the plurality of transmission paths are collectively divided for each group. As the number of transmission line groups increases, the switching efficiency improves, and the merits of reducing the package size and simplifying the pattern wiring also increase.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a terminating low-speed section of a multiple terminal station terminating apparatus according to the present invention.

FIG. 2 is a diagram showing a configuration example of a matrix circuit used as a switching circuit in FIG.

FIG. 3 is a diagram showing a specific configuration example of a matrix circuit in FIG. 2;

FIG. 4 is a diagram showing the operation principle of the matrix circuit in FIG.

5 is a diagram showing an example of a specific circuit structure of the matrix circuit in FIG.

FIG. 6 is a diagram showing a configuration of an abnormality monitoring circuit of the matrix circuit in FIG. 2;

FIG. 7 is a schematic diagram showing a general configuration of a multiplex terminal unit.

FIG. 8 is a diagram showing a configuration of a terminal low-speed section of a conventional multiple terminal station terminal device.

FIG. 9 is a diagram showing a structure of a conventional switching circuit used for a terminal low-speed section.

[Explanation of symbols]

 Reference Signs List 50 multiplex terminal station termination device 51 terminal low-speed section (T-LS section) 1 control circuit 2 switching circuit (matrix circuit) 3a,..., 3d working system boards N1,. Interface section 52 Terminal low-speed section (L-LS section) 53 High-speed section (HS section) 54 Control section (COM section) 40 Relay drive coil 41 Row specifying transistor 42 Column specifying transistor 60 Error monitoring circuit 61 Exclusive NOR (EXNOR) gate 62 OR gate 63 Alarm latch circuit (ALM LATCH)

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hideaki Sakai 3-1-1 Asahigaoka, Hino-shi, Tokyo Toshiba Communication Systems Engineering Co., Ltd.

Claims (5)

[Claims] 1. A transmission line switching method for selecting and switching a predetermined number of transmission lines from a plurality of transmission lines, wherein a plurality of changeover switches interposed in the transmission lines are arranged in a matrix of N rows and M columns. A row-designated switch drive circuit that applies a drive signal to each change-over switch in the switch circuit in units of rows, and a drive signal arranged in columns for each change-over switch in the switch circuit. And a column designating switch drive circuit that provides
The (N × M) changeover switches arranged in a matrix are controlled to be conductive in a row unit or a column unit by using (N + M) switch drive circuits, and each changeover switch in the row unit or the column unit is controlled. Transmission line switching method, wherein the transmission lines through which are interposed are collectively switched. 2. A transmission line switching device for selecting and switching a predetermined number of transmission lines from a plurality of transmission lines, wherein each of the transmission line switching devices includes a first driving signal and a second driving signal. A switch circuit in which a plurality of changeover switches that are turned on by being applied simultaneously are arranged in a matrix of N rows and M columns; and N is a circuit that supplies the first drive signal to each of the changeover switches in row units. Row designation switch drive circuits, M column designation switch drive circuits that provide the second drive signal to the changeover switches in column units, the row designation switch drive circuit and the column designation switch drive circuit And a switching control circuit that selectively activates each of the switches and controls each of the changeover switches to be in a conducting state collectively in a row unit or a column unit. 3. An abnormality detecting means for detecting an abnormality of the row designation switch driving circuit and the column designation switch driving circuit, and an abnormality notifying means for notifying the occurrence of the abnormality by detecting the abnormality by the abnormality detecting means. The transmission line switching device according to claim 2, comprising: 4. The changeover switch is constituted by a relay, and the row designation switch drive circuit is constituted by a first transistor connected to one input terminal of a drive coil of the relay, and the column designation switch drive circuit is provided. Is
4. The transmission line switching device according to claim 2, wherein the transmission line switching device is configured by a second transistor connected to the other input terminal of the drive coil of the relay. 5. An exclusive-OR circuit for outputting an exclusive-OR operation result of a base-emitter potential of each of the first transistor and the second transistor; A logical sum circuit that outputs a logical sum operation result of an output of the logical sum circuit; and a latch circuit that latches an output corresponding to an abnormality of each of the transistors in the logical sum circuit as an alarm output. The transmission line switching device according to claim 4.