JP3046118B2 - Time division channel method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division communication path of a digital exchange, and more particularly, to a time-division communication path having a duplex system configuration and controlling a time switch and a space switch. About the method.

[0002]

2. Description of the Related Art As a prior art relating to this type of time division communication system, there is known a technology described in, for example, "Outline of D70 type digital exchange" in a telecommunications facility (issued in May, 1982.5).

[0003] This prior art is provided with a duplexed time-division communication channel device and a duplexed concentrator. The devices are connected to each other by a single circuit in the interface unit. That is,
The time-division channel device is connected by a single time-division connector, and the concentrator is connected by a single highway interface circuit.

[0004]

In the above prior art, the connection between the duplicated devices is made by a single circuit, which lacks reliability. Except for the single circuit located at the interface of the above, even when the connection between the devices is duplicated, the reliability cannot be significantly improved with a simple two-sided configuration. Have a point.

Further, in the prior art, when a plurality of duplexed common control units connected to a duplexed speech path switch are operated as independent systems, a failure of a system confounding unit is also detected. It is necessary to switch the system by using a switch, and when the system is switched when a failure occurs, it is necessary to switch the system selection in the device on the opposite side. However, if the switching is performed by software control, a time loss occurs. There is a problem that.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, so that a plurality of common control units can operate as independent systems, and the time loss of system selection of the opposing device can be minimized. It is an object of the present invention to provide a time-division communication channel method that can be used.

[0007] In general, elements constituting a time division communication path include a time switch, a space switch, an elastic store function for absorbing a phase difference to enable high-speed operation, and a low-speed highway housed in a single unit. Multiplexing / demultiplexing function for connecting the high-speed highway accommodated in the communication path switch and the normality of the highway in the system confounding section between the communication path switch and the common control device for controlling the single unit. Frame synchronization function between devices, pattern generation check function, etc. The above-described prior art has a problem that, when an attempt is made to integrate these elements into an integrated circuit, it is necessary to develop many types of LSIs, which is disadvantageous in terms of cost.

[0008] It is an object of the present invention to convert the above functions other than the time switch and the space switch into one LS by mode switching.
It is another object of the present invention to provide a time-division communication channel system which can be performed by the I.

Further, in a time division communication device comprising a plurality of time switches and a plurality of space switches, the information of one channel is converted into 8-bit parallel data by using the time division communication device as a time switch (T) -space. Switch (S)
If the time switch (T) is used, the number of multi-connections increases and the number of junk highways increases.

For example, 4096 multiplexed time switches LS
Assuming that a TST communication path is configured using 32 I and a 16 × 16 space switch, and that the speed of the junk highway is 32.768 Mbps, eight switches are provided from each of the 16 time switches. The junta highway is multiplied 16 times, and an enormous high-speed pattern is routed between the card constituting the time switch and the card constituting the space switch. Such an enormous number of high-speed pattern routing lowers the reliability of the operation and causes a problem of increasing the unit cost due to an increase in the number of patterns.

SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost time-division communication channel system capable of improving reliability by minimizing multiple connections and pattern routing that cause malfunctions.

The time switch comprises a speech path memory and a control memory for controlling the speech path memory, and the space switch comprises a plurality of selectors and a control memory for controlling the selectors. In general, a time switch can be configured by one integrated circuit and has a wide range of applications in other fields, but a space switch can be configured by one integrated circuit but is applicable to other fields. Absent. Further, an integrated circuit having a large-capacity memory built therein requires very advanced technology, and there is no cost advantage even if two types of time switch and space switch are developed as an integrated circuit.

An object of the present invention is to provide a space switch which can be constructed at a low cost in view of the above.

If the junk highway connecting the time switch-space switch-time switch transfers information in a serial pattern, 8 bits are 1 bit.
Because of the channel, the switching speed of the space switch is one-eighth that of the junk highway. For example,
Assuming that the junker highway speed is 32.768 Mbps, the switching speed of the space switch becomes one-eighth, that is, 4.096 Mbps.

For this reason, 32.768M is used for the space switch.
When a control memory that reads data at bps is used, there is a problem that most of the capacity of the memory is wasted. Also, the control data used to control the highway matrix is only a few bits, and the remaining data is wasted. For example, the control memory (data width 12 bits) of a 4096 multiplex time switch is 16 × 1
When controlling 6 highway matrix switches, 1
Since 4 bits of data are required per address, the remaining 8 bits are wasted.

An object of the present invention is to provide a control method of a control memory of a space switch which does not cause the above-mentioned waste.

When a time switch is formed by forming a communication path memory and a control memory for controlling the communication path memory in one integrated circuit, and the data read from the control memory is to be used for controlling the highway matrix, A new output pin is required, which causes a problem that the number of pins of the LSI (integrated circuit) increases.

An object of the present invention is to provide an LSI having a function of a control memory of a space switch without increasing the number of pins of the LSI constituting the time switch.

[0019]

SUMMARY OF THE INVENTION According to the present invention, an object of the present invention is to provide a system in which a plurality of system confounders are provided in order to operate a plurality of common control units and a communication path switch in their own systems. In addition, in order to quickly select a system on the common control device side when the communication channel switch is switched by hardware, a system selection signal is transmitted from the communication channel switch to each common control device, so that For the control device,
This is achieved by making the system selection signal determine which of the communication path switches is the act system and performing system selection.

Further, the object is to insert an arbitrary pattern into a specific time slot in order to confirm the normality of the interface between the common control device and the communication path switch, and to establish a highway for the other device. Checking the frame signal and clock, comparing the expected frame signal created by counting up the clock with the received frame pulse,
This is achieved by causing an obstacle if it is incorrect.

The object is to provide an elastic function,
A multiplexing / demultiplexing function and a function for monitoring the normality of an interface between these devices, for example, a frame synchronization function and a pattern generation check function are configured by one type of integrated circuit, and mode switching is performed. By doing so, it can be applied to the interface unit of the common control unit in the channel switch whose elastic function is the main function, and to the interface of the channel switch in the common control unit whose multiplexing / demultiplexing function is the main function. This is achieved by:

It is another object of the present invention to reduce the multiple connection of the junk highway between the time switch and the space switch, in particular, to eliminate the multiple connection between the time switch card and the space switch card. In addition, this is achieved by connecting the information of the junk highway not in parallel but in serial.

Further, the object of the present invention is to use a time switch control memory as a space switch control memory in order to obviate the need to develop two types of integrated circuits, a time switch and a space switch having a large capacity memory. This is achieved by making the configuration possible.

The object of the present invention is to provide a time switch function and a control memory function by switching modes without using a control memory read-only external pin in an LSI constituting a time switch. This is achieved by allowing the external read function to be set.

Further, the object is to control eight highway selectors in the address direction in order to efficiently use a control memory for controlling switching of a highway matrix in which data is serially transferred, This is achieved by enabling a plurality of highway selectors to be controlled simultaneously in the data direction.

[0026]

[Function] Since the common control unit has a system confounding part,
The act system of the common control device can determine that it is the act system itself. Further, the common control device can send the act-related information to the 0-system and 1-system communication path switches through the system confounding section in the own apparatus. You do not need to be aware of the system.

Although the system selection information is transmitted from the communication path switch to a plurality of common control devices, the common control device performs system switching by taking two-thirds majority decision of the received system selection signal. Also, when a bit error occurs due to noise or the like, no malfunction occurs. Further, when the expected frame signal generated by counting up the clock and the received frame signal do not match three times in a row, a failure is notified as a loss of frame synchronization. Not even.

In the case where a plurality of highway selectors are controlled in the data direction, and there is a parity bit in the control memory (as is the case in most cases), rewriting a part of the data length results in a parity error. However, according to the present invention, when data is written to the control memory, all data is always read out, and parity is rewritten with data other than data to be rewritten and data to be rewritten. Does not occur.

[0029]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a time division communication system according to the present invention.

FIG. 1 is a diagram showing a connection configuration between a time division communication channel device and a common control device, FIG. 2 is a block diagram showing an entire configuration of a time division communication channel system according to an embodiment of the present invention, and FIG. FIG. 1 is a diagram illustrating a configuration of a time-division call channel device according to an embodiment of the present invention;
FIG. 4 is a diagram showing an arrangement of time slots on the junk highway in FIG. 3, FIG. 5 is a diagram for explaining a functional model of the space switch, and FIG. 6 is a diagram for explaining an address / data array of the space switch control memory. . 1 and 2, reference numerals 1 and 2 denote a common control device of a multiplexing unit and a signal processing unit of a 0 system and a 1 system, and 3 and 4 denote a communication line switch forward interface unit of a 0 system and a 1 system. Is 0 and 1
System communication path switches, 7 and 8 are common control devices for the 0 system and 1 system multiplexing unit interface, 9 and 10 are common control devices for the 0 system and 1 system multiplexing unit and signal processing unit, and 11 is forward. Side system selection selector, 12 is a communication path switch forward side interface, 13 is a common control device forward side interface, 14 is a T switch-S switch-T
A switch unit, 15 is a common control device backward interface, 16 speech channel switch backward interface, 17 is a backward system selection selector, 21 is a forward common control device, 22 is a speech channel switch, 2
3 is a backward common control device, 24 is a subscriber circuit,
A single unit such as a trunk, 25 and 26 are a single unit interface common controller for the 0 and 1 systems, and 27 and 28 are 0 units.
A common control device for the multiplexing unit and the signal processing unit for the system and the system
Reference numerals 29 and 30 denote the 0-system and 1-system communication path switch forward-side interface units, 30 denotes the 1-system communication path switch forward-side interface unit, 31 and 32 denote the 0-system and 1-system communication path switches, and 33 and 34 denote the 0-system. And a communication path switch backward side interface unit of the first and third systems, 35 and 36 are common control devices for the multiplexing unit and the signal processing unit of the zero and one systems, and 37 and 38 are single interface units of the zero and one systems. It is a common control device.

The whole time-division communication channel device according to the present invention
As shown in FIG. 2, a duplicated common control device 21 (SPME) on the forward side, a duplicated speech path switch 22 (TDNW), and a common control device 23 (SPME) on the backward side , A subscriber circuit, a trunk, etc., and a simplexing device 24 for interfacing with the outside.

The SPME 21 includes common control units (HWI) 25 and 26 for controlling the single unit 24 and a common control unit (HW) for performing signal processing of the multiplexing and single unit 24.
MPX) 27 and 28 and common control devices (NWINF) 29 and 30 having a forward-side system selection function, an interface function with a communication path switch, and a multiplexing function. The SPME 23 includes common control devices (HWI) 37 and 38 for controlling the simplex device 24, and a common control device (HWMPX) 35 for performing demultiplexing, system selection functions and signal processing of the simplex unit. , 36 and common explanation devices (NWINF) 33, 34 having an interface function with the backward TDNW.

Then, the aforementioned HWIs 25, 26, 37,
38 is mounted on the subscriber circuit unit and the trunk unit. A plurality of NWINFs 29, 30, 33, and 34 are connected to the TDNW 22, and HWIs 25, 26,
7 and 38 are connected to a plurality of HWMPXs 27 and 28 and 35 and 36, and are further connected to multiples.

The TDNW 22 is provided with two sets of communication path switches 31 and 32.

Then, HWMPX27, 28 and NWIN
F29, 30 and NWINF 33, 34 and H
An interlaced portion is provided between each of the WMPXs 35 and 36.

Next, referring to FIG. 1, a description will be given of a time-division communication apparatus according to an embodiment of the present invention.

In the embodiment of the present invention, the forward HW
MPX1,2, forward NWINF3,4, T
NWINF7, 8 by DNW5, 6 and TDNW interface unit (NWINF16) on the backward side
And the system switching selector 1 in the HWMPX on the backward side.
7 and the multiplexing unit and the common control units 9 and 10 of the signal processing unit for selecting the TDNW to be received based on the NWSEL information received from the TDNW. It is configured.

The forward-side HWMPX1,
2, forward side NWINF3, 4, TDNW5, 6,
The NWINFs 7 and 8 and the common control units 9 and 10 of the multiplexing unit and the signal processing unit respectively correspond to the forward-side HWMPXs 27 and 28 and the forward-side NWINF2 in FIG.
9, 30, TDNW31, 32, NWINF33, 36
And HWMPX35, 36.

In the forward-side NWINFs 3 and 4, the forward-side system selection selector 11 inside selects the active standby system by software, and always receives information from the active HWMPX. Also, T
The interface unit 12 with the DNW processes a frame synchronization signal, a clock, and highway information as the interface signal.

In the time slot of the first term of the highway,
As shown in FIG. 1, F, ALM, and F 'are superimposed. Normally, F is “1”, F ′ is “0”, and A
LM is the backward highway (TDDNW → NWI)
NF), a highway error is detected (frame synchronization loss, clock loss, F, F 'pattern NG), and sent to the TDNW as a device alarm.

The interface unit 13 forming the TDNWs 5 and 6 is an interface unit with the NWINF of the SPME in the TDNW, and has a function of synchronizing a frame, cutting off a clock, and checking a highway pattern (F, F ′). The communication path unit 14 includes a time switch-space switch-time switch. Further, the interface unit 15 is an interface unit with NWINF on the backward side, and sends out a frame signal, a clock, and highway information to NWINF.

In the first time slot of the highway,
As shown in FIG. 1, F, F ', ALM (these are the same on the forward side), and NWSEL are superimposed.
NWSEL is information indicating which of the TDNWs is the act system, and when this information is “0”, the TD of the 0 system is
When the NW is an act system and “1”, one TDNW is an act system.

The backward-side TDNW interface section (N) constituting the backward-side NWINFs 7 and 8
A WINF) 16 checks a frame synchronization, a clock cut, and a highway pattern (F, F ′). Further, the TDNW interface unit (NWINF) 16 is responsible for a part of the demultiplexing function in some cases.

The common control unit 9 of the multiplexing unit and the signal processing unit,
The system switching selector 17 in the backward-side HWMPX constituting the system 10 selects the TDNW to be received based on the NWSEL information received from the TDNW. In addition, the received NWSEL signal is protected from the effects of bit errors, noise, and the like because a majority decision of two thirds is taken.

The example shown in FIG. 1 is the SPME on the forward side.
Is active and system 1 of TDNW is active. At this time, if a failure occurs in the forward SPME, the forward SPME
Are switched so that the first system becomes an act. In this case, the system selection selector 11 in the HWMPX of the SPME
Is switched to select the first system.

As described above, the communication path apparatus according to one embodiment of the present invention shown in FIG. 1 has a TDNW of either system 0 or system 1 due to system confounding between HWMPX and NWINF.
, The information of the act SPME can be transferred. Then, it is possible to switch the system only for the SPME without affecting the TDNW side.

In FIG. 1, when a failure occurs in the TDNW,
When switching the TDNW from the 1-system active state to the 0-system active state, the NWSEL signal to be sent to the backward SPME is changed from "1" to "0" by hardware, so that the TD
The NW system is switched.

The SPME takes a two-thirds majority decision of the NWSEL signal, and selects the backward side system selection selector 17.
, And receives information from the 0-system TDNW. As described above, at the same time as the switching of the TDNW system is performed, the SPME system switching is performed by hardware, so that there is little adverse effect at the time of system switching.

Further, between the TWINW interface units 12 and 16 of NWINF and the NWINF interface units 13 and 15 of TDNW, the frame synchronization, clock, The F and F 'patterns of the first time slot are checked, and the system is switched as follows in the failure detection mode.

That is, when a failure is detected in one of the SPME receiving-side systems, the SPME system is first switched because there are a plurality of SPMEs and the effect on other devices is small. When a failure is detected in both systems on the receiving side of the SPME, the TDNW is switched. Similarly, TDN
In the case of a single-system failure of W, the TDNW is switched and a specific SPM
In the event of a TDNW system failure limited to E, SPME switching is performed.

In the embodiment of the present invention shown in FIG. 1, as described above, even if there are a plurality of SPMEs, the system can be switched freely and individually, which is very useful for improving the reliability of the apparatus. effective.

In the embodiment shown in FIG. 1, the multiplexing function is provided in the NWINF 12 on the forward side, and the N
Demultiplexing function in WINF16, SPME in TDNW
Elastic functions for absorbing a phase difference are provided in the interface units 13 and 15, and these are configured using one kind of the same integrated circuit, and the respective functions are realized by mode setting.

That is, when this integrated circuit is used as an elastic function, the input 8 highway and the output 8
When used as a highway elastic store and used as a multiplexing function, input 8 highways and output 4 highways, for example, 16.384 Mbps on the input side
Is used as a multiplexing circuit for multiplexing the eight highways on the output side into four 32.768 Mbps highways. When used as a demultiplexing function, the input four highways and the output eight highways, for example, 32.768 Mbps
It can be used as a demultiplexing circuit for demultiplexing from four highways of s to eight highways of 16.384 Mbps.

Further, the above-mentioned functions are provided by NWINF12,
16 and the TDNWs 13 and 15, a circuit for transmitting and receiving a frame synchronization function and a function of inserting and extracting a pattern of a specific bit are embedded in an integrated circuit for performing these functions, and these are selectively used depending on a mode setting. You can do so.

For example, in the forward interface unit 12 with the TDNW in the NWINF, the integrated circuit is operated in the multiplexing function, frame synchronization, and the bit pattern insertion mode, and the forward interface unit 13 with the NWINF in the TDNW. Then, the integrated circuit can be operated in an elastic function, a frame synchronization check, and a bit pattern check mode. In the backward interface 15 with the NWINF in the TDNW, the integrated circuit operates as a frame synchronization, bit pattern insertion, and NWSEL insertion function. In the backward interface 16 with the TDNW in the NWINF, The integrated circuit can be operated as a demultiplexing function, a frame synchronization check, a bit pattern check, and an NWSEL extraction function.

As described above, in one embodiment of the present invention, 1
By selectively using different types of integrated circuits by mode designation, all the functions described above can be covered, and the cost of the entire device can be reduced.

Next, with reference to FIGS. 3 and 4, an example of a network configuration and an arrangement of time slots on a junk highway will be described. This example shows 16 1
Next time switch (PTSW), 8 space switches (HSW), 16 secondary time switches (STSW)
1 is a configuration example of a network having a TST configuration according to FIG.

FIG. 3 is a configuration diagram when the junctor highway between the time switch, the space switch and the time switch is connected in a serial pattern. FIG. 4 is a diagram showing the junctor highway between the time switch, the space switch and the time switch. FIG. 2 is a configuration diagram in the case of connecting in an 8-bit parallel pattern.

The time switch has a serial / parallel conversion (P / S) at the preceding stage of the 4k multiplex switch and a parallel / serial conversion (P / S) at the subsequent stage.
The space switch is a 16 × 16 matrix switch. The data on each junk highway (JHW) has a transmission rate of 32.768 Mbps, and 4096 bits are multiplexed on one JHW.

In FIG. 3, a primary time switch PTSW
0, this primary time switch PTSW0 is
32.768 Mbps data is input from the eight highways, and after switching this data, 32.76 is sent to the eight junk highways JHW0 to JHW7.
Distribute at a rate of 8 Mbps. This data is passed to the space switches HSW0 to HSW7 via the junk highways JHW0 to JHW7. That is, one time switch is connected to all the space switches by eight JHWs. Therefore, the connection between the time switch PTSW0 and the space switch HSW0 is performed by one JHW.

The pattern shown in FIG. 4 explains the bit arrangement on the JHW shown in FIG. 3 described above.
In the pattern shown in FIG. 4, a time slot TS as a switching unit is composed of 8 bits, and each TS is serially multiplexed on the same JHW. Therefore, 512 TSs are multiplexed on one JHW, and eight JHWs are
In total, 4096 TS is output from one PTSW.

The time switch PTSW0 is 4096 TS
Is input and can be multiplex-converted to an arbitrary TS on an arbitrary output JHW, so that it is not necessary to distribute and connect all the 4096 TSs on the output side to all the space switches. For this reason, in the example of the pattern shown in FIG. 3, the network is configured by connecting the time switch 0 and each space switch by one 512H-multiplexed JHW, and all have one-to-one connection patterns. High-speed bit transmission of 32.768 Mbps.

Next, a functional model of the space switch will be described with reference to FIG. 5, and an address / data array of the space switch control memory will be described with reference to FIG.

The space switch shown in FIG. 5 has a matrix composed of 256 gate elements # 00 to #FF for switching between 16 input junctor highways (JHWI0 to 15) and output junctor highways JHWI0 to JHWI15. A space switch control memory HCM including information group A / B for storing on / off control information of each gate element, and gate control information read from the HCM for 16 gates are accumulated, and the control information is stored in accordance with highway data. And a timing adjusting section for outputting. The HCM uses the speech path switch control memory SCM of the 4096 multiplex time switch, and two types of control information of the information A group and the information B group are allocated to data in the same address. , JHWI0-JHWI
7 and the information B group includes JHWI8 to JHWI1.
5 is performed.

The address / data array of the space switch control memory shown in FIG. 6 shows an image of addresses and data allocation of the space switch control memory HCM and the speech path switch control memory SCM.

In FIG. 6, the pattern A is obtained by replacing the communication path switch control memory SCM with the space switch control memory HCM.
In the example of data allocation when used as
Is an example of data allocation when used as a speech path switch control memory SCM.

S for controlling 4096 multiplex time switches
The CM has a memory capacity of 4096 × 13 bits or more. In the case of a pattern used as an HCM, a total of 13
One bit of parity bit and two types of gate switch control information of group A / group B are stored in the bit. H
Writing to the CM is performed in units of one control information, but since two types of control information are stored in one address, when rewriting the control information, the memory contents are read once and the parity bits are re-attached. I have.

The HCM operates at 32.768 Mbps, and can read 4096 times in one frame period (125 μS). However, 512 TS serial data at 32.768 Mbps is multiplexed on the highway in the space switch, and the 8 bits of the highway data 1TS are simultaneously switched.
The CM control data may be read out 512 times in one frame period.

Therefore, during the control of the serial highway data of 1TS (8 bits), the information is read eight times from the HCM, and the 16 pieces of highway control information of JHWI0 to JHWI15 are sequentially read out. After temporarily storing and reading out the control information for all 16 JHWs, the gate switches of the 16 JHW0 to JHW15 are controlled in accordance with the switching timing of the serial highway data.

[0070]

As described above, according to the present invention, 1
All of the devices except the multiplexing device are duplicated, and the system can be freely switched between the communication path switch and the plurality of common control devices, thereby greatly improving the reliability of the communication path device. Can be. Further, according to the present invention, the system selection of a plurality of common control devices when the communication path switch is switched can be performed by hardware,
Since there is no need to perform communication between the processors, the communication can be performed quickly, and a reduction in service during operation can be prevented.

Further, according to the present invention, the mode of one type of integrated circuit is switched and used so that one type of integrated circuit can be used as a multiplexing function, a demultiplexing function, an elastic function, and a communication path. It can be applied to the frame synchronization function for checking the normality of the interface between the switch and the common control device, the pattern generation check function, the system selection information insertion, and the extraction function. Can be.

Further, according to the present invention, the junk highway between the time switch, the space switch and the time switch can be minimized, so that an increase in the number of patterns between the cards constituting the speech path switch is prevented. Can improve the reliability of operation.
Since there is no mounting bottleneck due to a card external connection bottleneck due to an increase in the number of patterns, size reduction and cost reduction can be achieved.

According to the present invention, one kind of integrated circuit can be used as a time switch or as a control memory of a space switch in a control memory read mode by mode switching. It is not necessary to develop expensive dedicated LSIs for two types of time switch and space switch, only one type has been developed, and in terms of address and data,
Since a plurality of highway matrices can be controlled, the size of the entire device can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a connection configuration between a time-division communication channel device and a common control device.

FIG. 2 is a block diagram showing an entire configuration of a time division communication channel system according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a time-division call channel device according to one embodiment of the present invention.

FIG. 4 is a diagram showing an arrangement of time slots on a junk highway in FIG. 3;

FIG. 5 is a diagram illustrating a functional model of a space switch.

FIG. 6 is a diagram illustrating an address / data array of a space switch control memory.

[Explanation of symbols]

Common control device for multiplexing section and signal processing section of 1, 20 and 1 systems 3, 40 and 1 system communication path switch Forward side interface section 5, 60 and 1 system communication path switch 7, 8 0 system and 1 system multiplexing unit interface common control device 9, 100 system and 1 system multiplexing unit and signal processing unit common control device 11 forward side system selection selector 12 speech path switch forward side interface 13 common Control device forward interface 14 T switch-S switch-T switch unit 15 Common control device backward interface 16 speech channel switch backward interface 17 backward system selection selector 21 forward common control device 22 speech channel switch 23 back Word side common control unit 24 Subscriber circuit, trunk, etc. Duplexer 25, 260 Common control unit interface control unit for system 0 and 1 System 27, 280 Common control unit for multiplexing unit and signal processing unit for system 28 and system 1 Communication between system 29, 300 system and system 1 Route switch forward-side interface unit 30 1-system speech channel switch forward-side interface unit 31, 320 0-system and 1-system speech-path switch 33,340 0-system and 1-system speech-path switch backward-side interface unit 35, 360-system Common control device for multiplexing unit and signal processing unit for system 1 and 37, 380 Common control device for single unit interface for system 300 and system 1

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yozo Oguri 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Information and Communication Division, Hitachi, Ltd. (56) References JP-A-61-194962 (JP, A) JP-A-58-71790 (JP, A) JP-A-61-236296 (JP, A) JP-A-63-9347 (JP, A) JP-A-63-200659 (JP, A) JP-A-52-153607 (JP, A) JP, A) JP-A-62-57396 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04Q 11/04 H04M 3/22 H04Q 3/52 101

Claims (7)

(57) [Claims] 1. A dual common control unit for controlling a single circuit for interfacing with another system,
In the time-division communication channel system constituted by the redundant time-division communication channel switches, all except for the simplex circuit have a double configuration, and the communication in the common control unit is performed.
Sender and interface interfacing with speech switch
A time-division call channel system, characterized in that both sides are provided with a system confounder of the call channel. 2. The time-division communication channel system according to claim 1, wherein a plurality of said common control units are provided, and said common control unit and said communication channel switch operate in their own systems. 3. The system selection of the common control unit when the communication path switch is switched is performed by hardware by transmitting system selection information from the communication path switch to the plurality of common control units. 3. A time-division communication channel system according to claim 2. 4. The system according to claim 1, wherein a fault is detected by performing pattern matching between said common control unit and a communication path switch at all times, and system switching is performed.
Or the time-division communication channel method described in 3. 5. The split channel device when the control memory for controlling the speech path memory and the speech path memory is made of the time switches and space switches in a single integrated circuit, the output of the control memory of the time switch Directly accumulate times
A time-division communication path system , wherein a highway matrix of a space switch is controlled by a control memory of the time switch by outputting to a pin of the path. 6. A plurality of highway matrices are controlled by one control memory.
5. The time-division communication channel method according to 5. 7. The time-division communication channel system according to claim 5, further comprising a time switch that shares an output pin of the read data of the control memory with another output pin.