JPH1153832A - Transmission device, reception device and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a signal from lacking or to prevent signals from being stored in a plurality of storage areas even in the case of a non-standard video signal by detecting that a last signal is read and switching a system to the next storage area at time of selectively reading and transmitting the signals from the plurality of storage areas in the storage means of the digital signal. SOLUTION: A track memory 107 sequentially stores a compression/encoding signal from a compression/expansion circuit 105 for three frames in three banks by sequentially switching them in synchronizing with the vertical synchronizing signal of the input video signal. DIF 111 makes data of the track memory 107 into a packet and transfers it to a reception-side device through a transmission line 20 constituted of an IEEE 394 serial bus cable. The track memory 107 detects final packet data for one frame in data which is read, reads final packet data and switches a read-side bank to the next bank.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission device, a reception device, and a signal processing device, and more particularly, to a digital signal transmission / reception process.

[0002]

2. Description of the Related Art In recent years, with the development of digital technology, a device capable of transmitting a relatively low transmission rate by compressing and encoding various types of digital data having an enormous amount of information to reduce the amount of information has been developed. Various proposals have been made.

[0003] As a device of this type, a format standard for a digital VTR for digitizing a video signal and recording and reproducing the data on a magnetic tape has been determined by the HD Consumer Digital VCR Council recently.

In a VTR based on this standard, an input video signal is compressed and coded by using DCT, quantization, and variable-length coding techniques, and the amount of information is compressed from about 125 Mbps to about 25 Mbps. The video signal thus compressed is subjected to processing for error detection and correction using, for example, a Reed-Solomon product code via a memory, and is recorded on a magnetic tape.

According to the above standard, a video signal can be transmitted to another device at a high speed in the state of a compressed / encoded digital signal using an IEEE 1394 serial bus interface.

[0006]

In a digital VTR as described above, a compressed / encoded digital video signal is recorded / reproduced and transmitted / transmitted in real time.
In general, recording and reproduction processing is performed through a memory capable of storing a plurality of frames of video signals for reception.

That is, for example, when an externally input video signal is compressed and encoded and transmitted via the digital I / F, an area (hereinafter referred to as an area) in which the video signal is written in synchronization with the vertical synchronization signal of the input video signal. (Referred to as a bank) and the read bank is switched at a predetermined predetermined timing, thereby enabling transmission and recording of a video signal in real time.

Therefore, when a standard video signal such as NTSC is handled, the write / read timing is synchronized, and the video signal can be transmitted normally.

However, for example, a non-standard video signal having a frame cycle different from that of a standard video signal, such as a video signal from a home game machine, is input and converted to a digital signal.
When the transmission is performed via / F, the write bank in the memory is switched at an earlier timing than when the standard video signal is transmitted. On the other hand, the switching of the read bank is performed so that the signal is transmitted at a predetermined timing specified by the format. Therefore, when a non-standard signal is transmitted, the video signal that should be transmitted is not transmitted. . As a result, the receiving device receives discontinuous data, which causes an error.

When a video signal transmitted from an external device is received using the digital I / F, the video signal is processed via the memory.
Switching the write bank in TR
Since the synchronization is performed in synchronization with the vertical synchronization timing of R, the video signal of the same frame may be written over two banks, which causes deterioration in image quality.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present invention is to enable accurate transmission of a digital signal even when transmitting the digital signal via a memory.

Another object of the present invention is to enable a non-standard video signal to be transmitted in a good condition even when it is input.

[0014]

In order to solve the above problems and achieve the object, the present invention has a plurality of storage areas,
Storage means for storing digital signals, transmission means for selectively reading and transmitting the digital signals from a plurality of storage areas of the storage means, and transmission from each storage area of the storage means by the transmission means Control means for detecting that the last digital signal has been read and switching the storage area from which the digital signal is to be read.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, a case where the present invention is applied to a digital VTR will be described.

In FIG. 1, reference numeral 10 denotes a digital VTR to which the present invention is applied, and reference numeral 20 denotes a transmission line such as the IEEE 1394 serial bus cable, which is connected to another device having the same I / F. 30 is a video camera, 40
Is a monitor that displays an image related to the video signal output from the VTR 10.

First, a normal recording / reproducing operation will be described. In FIG. 1, when a recording instruction is given by the operation unit 119, a video signal output from an external device such as the video camera 30 is input to the input / output circuit 101. The input / output circuit 101 converts an input video signal into a digital signal and performs a filtering process or the like on the video memory 103.
Output to

The video memory 103 is capable of storing uncompressed video signals for a plurality of frames (two frames in this embodiment), and compresses the stored video signals at a later stage of compression / compression.
The data is read out (shuffled) in an order suitable for the processing of the decompression circuit 105 and output. The compression / expansion circuit 105 compresses and encodes the amount of information of the video signal by using techniques such as DCT, quantization, and variable-length encoding as described above, and stores the information in the track memory so that it is read in the order of the original input video signal. 1
07.

The track memory 107 can store compressed video signals, audio signals, and other additional signals for a plurality of frames (three frames in this embodiment). These three banks are synchronized with the input video signal. The video signals are stored by switching sequentially.

The error correction processing circuit 109 accesses the track memory 109 and performs an error correction coding process on the video signal written in the track memory 107 using the Reed-Solomon product code as described above.

The video signal read from the track memory 107 is output to the recording / reproducing processing circuit 113. The recording / reproducing processing circuit 113 adds an ID, a synchronizing signal, and the like to the error-corrected video signal, performs digital modulation processing, and outputs the result to the recording / reproducing circuit 115. The recording / reproducing circuit 115 records a video signal modulated using a rotary head on a magnetic tape.

Next, at the time of reproduction, the recording / reproducing circuit 1
The video signal reproduced from the recording / reproduction processing circuit 11
3 is output. The recording / reproducing processing circuit 113 demodulates the reproduced video signal and detects the original digital signal. The recording / reproduction processing circuit 113 further includes a synchronization signal, I
The D signal is detected, and the reproduced video signal is written to the track memory 107 based on the ID signal.

An error correction processing circuit 109 accesses the track memory 107, performs error correction decoding processing on the video signal written in the track memory 107, corrects an error in the reproduced video signal, and outputs an uncorrectable signal. Is interpolated by another reproduced video signal.

The video signal subjected to the error correction processing is output to the compression / expansion circuit 105. Compression / expansion circuit 105
Performs a process reverse to that at the time of recording on the reproduced video signal, decodes the reproduced video signal, expands the amount of information, and writes the information in the video memory 103. Video memory 10
Reference numeral 3 reads the video signal in the order of raster scan and outputs the video signal to the input / output circuit 101. The input / output circuit 101 performs pixel interpolation and the like on the video signal read from the video memory 103 to convert the video signal into a signal suitable for display on the monitor 40, converts the signal into an analog signal, and outputs the analog signal to the monitor 40. I do.

Next, the operation of the DIF 111 when transmitting a video signal will be described.

In FIG. 1, reference numeral 111 denotes the above-mentioned IEEE1
A 394 serial bus interface, which transmits a video signal compressed / encoded by the compression / encoding circuit 105 from the track memory 107 as described above, an audio signal output from an audio signal processing circuit (not shown), or a recording / reproduction during transmission. The reproduction signal output from the processing circuit 113 is input.

FIG. 2 shows the state of the data output to the DIF 111 at this time.

The data output to the DIF 111 is, as shown in FIG.
One block is composed of 80 bytes to which D data is added. Of the 3-byte ID data, ID0 indicates a data type (any of header, subcode, video AUX, audio, and video), and ID1 indicates a track of the track on which the data was recorded when the reproduction data was transmitted. No. (1 frame video signal is recorded on 10 tracks in NTSC in the VTR of this embodiment, and 1
These are recorded on two tracks, and here, these 10
ID or ID2), which indicates which of the 12 or 12 tracks the data was recorded on.
Indicates a block number.

In this embodiment, one header block, two subcode blocks, three video AUX blocks, nine audio blocks, and 135 video blocks are formed from one track of data. Normally, at the time of transmission, the six blocks of data are output to the DIF 111 as one packet.

In the DIF 111, header data,
Data having a time axis, such as subcode data, video AUX data, video data, and audio data, is transmitted by isochronous (synchronous) transfer for compensating that communication is completed within a predetermined time (125 μs). Such control data is transmitted by asynchronous transfer in which communication is performed at irregular timings as necessary.

Each packet of transmission data in the isochronous transfer has the configuration shown in FIG.

That is, each packet is composed of 12 + 4 × N bytes of data. In FIG. 3, reference numeral 301 denotes a length field, which defines the byte length of a data field following the header. Reference numeral 302 denotes a channel number field, which gives a logical number to packet data transfer using an 8-bit digital signal. The receiving side refers to this channel number and determines whether the data is required isochronous transfer data. Reference numeral 303 denotes a tcode field, and when this packet is an isochronous transfer, a value indicating that fact is inserted. A sy field 304 is used for exchanging synchronization information between the source and the destination, and is used by application software. A header CRC field 305 is an error detection code for the data in the fields 301 to 304. A data field 306 stores the isochronous data. A data CRC 307 is an error detection code of the packet data.

The DIF 111 packetizes each data as described above, and serially transfers the data to the receiving apparatus via the transmission path 20 which is an IEEE 1394 serial bus cable.

On the other hand, when receiving the data transferred in the isochronous manner, the DIF 111 receives the transfer data from the transmission line 20 and extracts the video data from the received data by using the header.
Write to 7. When the VTR 10 is in the recording state, the video signal received from the track memory 107 is read out, output to the recording / reproduction processing circuit 113, and recorded as described above. If the video signal is in the reproduction state, the compression / expansion circuit 105 decodes and outputs the video signal received as described above.

Next, the characteristic configuration of this embodiment, DI
Control of the track memory 107 at the time of data transmission and reception by F111 will be described.

FIG. 4 is a diagram showing a configuration of the control circuit 117 in FIG.

In the figure, reference numeral 107 denotes a track memory as described above, which has a three-bank configuration. Reference numeral 201 denotes a control circuit 117 and a C for controlling operations of other circuits.
The PU generates a bank switching signal for the memory 107 based on a vertical synchronization signal in an input video signal. That is,
The CPU 201 outputs a switch signal of the write side bank to the switch 209 via the switch 205,
And outputs a switch signal of the read-side bank to the switch 211 via the.

The switch 205 is switched in response to a mode signal indicating a transmission mode or a reception mode supplied from the operation unit 119, and a write-side bank switching signal from the CPU 201 or a packet data end detection circuit 203
The bank switching signal output as described later is selectively supplied to the switch 209.

The switch 209 is switched in response to the write-side bank switching signal supplied from the switch 205, and receives the write data (data from the compression / encoding circuit 105 in the data transmission mode, and D in the reception mode).
The data from the IF 111) is sequentially written to each of the banks 0, 1, and 2.

On the other hand, the switch 211 is switched in response to a mode signal indicating a transmission mode or a reception mode supplied from the operation unit 119, and is read from the read-side bank switching signal from the CPU 201 or the packet data end detection circuit 203 as described later. The output bank switching signal is selectively supplied to the switch 211.

The switch 211 switches in response to the read-side bank switching signal supplied from the switch 207, and sequentially reads data from the banks 0, 1, and 2.

Reference numerals 213 and 215 denote frequency divider circuits, respectively. In this embodiment, a 13.5 MHz clock obtained from a clock generation circuit (not shown) is used as a vertical synchronizing signal VD.
Is divided by 1800 by the frequency dividing circuit 213 using the equation 7.5.
A clock of MHz is generated, and a frequency dividing circuit 215 divides the frequency of the clock by 2 to generate a signal that is inverted every 133.3 μs. The latch 217 controls the system clock (6) supplied from the clock generation circuit.
(7.5 MHz), the output of the frequency divider 215 is latched, and an exclusive OR of this latched output and the output of the frequency divider 215 is obtained by the EXOR circuit 219.
133.3 showing both rising and falling edges (hereinafter referred to as nominal timing) of the output signal from No. 5
A pulse signal 221 for every μs is generated.

The DIF 111 reads out the data for one packet from the memory 107 and transmits it at each nominal timing.

Here, the period of the nominal timing is 13
The reason for the 3.3 μs is based on the standard at the time of transfer of the DIF 111, and it is necessary to transfer 250 packets of data per frame on average by the isochronous transfer.

With such a configuration, consider switching between the write side and the read side bank in synchronization with the vertical synchronizing signal of the input video signal. FIG. 5 is a timing chart in a transmission mode for transmitting a standard video signal in the case where both the write-side and the read-side bank switching are performed in synchronization with the vertical synchronization signal of the input video signal.

In the figure, a is a vertical synchronizing signal of a standard input video signal, and b is a nominal timing signal, which is generated 250 times in one frame period. c is the CPU 20
This is a read-side bank switching signal output from 1 and switches in synchronization with the vertical synchronizing signal of the input video signal. d is the packet data stored in the memory 107, and there are 250 packets of data per frame.

As described above, when a standard video signal is transmitted, 250 packets of data can be transmitted accurately in one frame period.

On the other hand, when transmitting a non-standard video signal from a home game machine or the like, the following is performed.
FIG. 6 is a timing chart in the case where the write-side and read-side banks are switched and transmitted in synchronization with the vertical synchronization signal in the input non-standard video signal.

In the figure, a is the vertical synchronizing signal in the input non-standard video signal, and b is the nominal timing. c is a read-side bank switching signal, which is switched according to a vertical synchronizing signal a in a non-standard video signal. d is packet data.

As is apparent from the figure, when a non-standard video signal is transmitted, if the read side bank is switched based on the vertical synchronization signal in the input video signal as in the transmission of the standard video signal, the frame becomes Is the data transmitted from the bank 1 instead of the data from the bank 0 which should be read during the period e. Therefore, the continuity of the transmitted data is lost, causing an error on the receiving side.

Therefore, in this embodiment, the packet data end detection circuit 203 detects the last packet data of one frame in the data read from the memory 107 at the time of data transmission, and receives the received data at the time of reception. , The last packet data of one frame is detected. By switching between the read side bank and the write side bank according to the detection result, such discontinuity and error of the transmission data are prevented.

As described above, the switches 205 and 207
Are switched in response to a mode signal indicating a transmission mode or a reception mode, respectively, and are connected to the terminal indicated by T in the transmission mode in the transmission mode, and to the terminal indicated by R in the reception mode in the reception mode.

Therefore, in the transmission mode, the write side bank is switched according to the bank switching signal synchronized with the vertical synchronization signal output from the CPU 201, and the read side bank is switched according to the switching signal from the packet end data detection circuit 203. .

Conversely, in the reception mode, the write side bank is switched according to the switching signal from the packet data end detection circuit 203, and the read side bank is switched to the CP.
Switching is performed according to the switching signal from U201.

The packet data end detection circuit 203 includes a circuit 203A on the transmission mode side and a circuit 203 on the reception mode side.
B. FIG. 7 is a diagram showing the configuration of the transmission mode side circuit 203A.

In the figure, reference numeral 401 denotes a symbol counter, which is the number of bytes (0 to 47) in one packet of data read from the memory 107 in accordance with the system clock.
9), and counts that value to the data end detection circuit 40.
5 is output. From the TC of the counter 401, a signal (terminal count signal, hereinafter TCS) which becomes a high level when the counter 401 counts up to 479 is output.

The AND circuit 403 has a counter T
CS and a timing signal indicating the nominal timing are supplied, and the counter 401 is reset by the output of the AND circuit 403.

Reference numeral 402 denotes a packet counter, which is enabled by the TCS of the counter 401 and the number of packets in one frame (0 to 249) according to the system clock.
And outputs the count value to the data end detection circuit 405. Further, the TC of the counter 402 outputs a TCS which becomes a high level when the counter 402 counts up to 249.

The AND circuit 404 has the T
CS, the TCS of the counter 402, and a timing signal indicating the nominal timing are supplied, and the counter 402 is reset by the output of the AND circuit 404.

The data end detection circuit 405 decodes the count values of the counters 401 and 402, and determines that the last data of the last packet in the frame, that is, the packet counter value is 249 and the symbol counter value is 479
Is determined to be the last data of one frame,
Outputs data end signal.

FIG. 8 is a timing chart showing the operation in the transmission mode using such a packet data end detection circuit 203.

In the figure, a is a vertical synchronizing signal in an input video signal, and b is a nominal timing signal. c is the count value of the symbol counter 401, and d is the count value of the packet counter 402. Also, e is a data end detection signal output from the data end detection circuit 405, and as described above, the count value of the counter 401 and the count value of the counter 402 are 47
It is output when it becomes 9, 249. f indicates the read side bank, and the read side bank is switched according to the data end signal.

As described above, in the present embodiment, when transmitting a video signal, the read side bank is not switched according to the vertical synchronization signal in the input video signal, but the last bank of data actually read from the memory 107 is transmitted. And the switching is performed according to the detection result. For example, even when the vertical synchronizing signal in the input video signal changes from T1 to T2 of the input video signal, the read-side bank reads the last data of the frame. Will be switched after waiting for
No discontinuity occurs in transmitted data.

Next, the reception mode will be described. In the reception mode, as described above, the switches 205, 20
7 are respectively connected to the terminals on the R side.

FIG. 9 is a block diagram showing the configuration of the receiving circuit 203B of the packet data detecting circuit 203.

In the figure, reference numeral 501 denotes a symbol counter, which counts the number of bytes (0 to 479) in one packet according to a system clock and outputs the counted value to a data end detection circuit 504 and an ID detection circuit 503. The AND circuit 502 is supplied with a reset signal of the packet period of the received data generated based on the received data by the generating circuit (not shown) and the TCS of the counter 501, and the counter 501 is reset by the output of the AND circuit 502. You.

The ID detection circuit 503 is provided with a counter 5
Using the count value of 01, the position of the ID data is determined from the received data supplied in synchronization with the reset signal, and the track number and block number data are extracted and output to the data end detection circuit 504.

The data end detection circuit 504 is based on the count value of the counter 501, the track number and the block number from the ID detection circuit 503, and has 479 for the count value, 9 for the track number (11 for PAL), and , The block number detects the final 134 of the video data, and outputs a data end signal similar to that shown in FIG. Therefore, in the reception mode, the write side bank is switched according to the data end signal.

The read side bank is switched in accordance with a bank switching signal output from the CPU 201 and synchronized with a vertical synchronizing signal generated inside the VTR 10.

As described above, in the present embodiment, when the video signal is received, the end of the data actually received by the DIF 111 is detected instead of switching the write side bank according to the internal vertical synchronization signal. Since the switching is performed in accordance with the result, for example, even if the timing of the received data changes from T1 of T to T2, the write-side bank switches after waiting for the last data of the frame to be read. There is no need to write the received data of the frame over two banks.

In the above-described embodiment, in the transmission mode, the end of the data read from the memory is detected by the packet data end detection circuit 203 and the read bank is switched. However, in the embodiment described below, This is to prevent the transmission data from being lost in the transmission mode by a different method.

FIG. 10 is a block diagram showing another configuration of the memory control circuit 117 of FIG. In FIG. 10, the same components as those in FIG.

In FIG. 10, reference numeral 223 denotes a frequency division ratio generating circuit, which outputs an H clock, VD, and an input video signal to NT.
An NTSC / PAL signal indicating whether it is SC or PAL is supplied.

FIG. 11 is a block diagram showing a configuration of the frequency division ratio generating circuit 223.

In FIG. 11, reference numeral 601 denotes an H clock (1
This is a 20-bit free-run counter that performs a count operation according to (3.5 NHz), and has a count value for about two frames. Latches 602 and 603 are enabled by the VD signal, and latch the count value of the counter 601 and the value of the latch 602 and output the latched value to the subtractor 604. The subtractor 604 calculates the difference between the outputs of these two latches and outputs the difference to the dividers 605 and 606, respectively. Therefore, the output value of the subtractor 604 indicates the VD cycle of the input video signal.

The dividers 605 and 606 divide the output of the subtractor 604 by 250 and 300, respectively.
07.

The switch 607 is provided with the above-described NTSC / PA
When the L signal is supplied and the input video signal is an NTSC signal, it is connected to the terminal N to select the output of the divider 606, and when the input video signal is PAL, it is connected to the terminal P to connect to the terminal P. Select output.

In this case, no matter what period the VD has, the frequency division ratio for dividing the VD at equal intervals can be obtained. However, in consideration of the indivisible case, 1 is added to the output of the switch 607, and the result is output to the frequency dividing circuit 211 as a final frequency dividing ratio. Therefore, the frequency division ratio obtained from the frequency division ratio generation circuit 223 has a value that changes according to the fluctuation of the cycle of the input VD signal.

The frequency dividing circuit 225 is constituted by a counter capable of presetting a count value.
The count value is preset according to the frequency division ratio supplied from the frequency divider, and the frequency of the H clock is divided.

As a result, the nominal timing signal 221 output from the EXOR circuit 219 reflects a change in the input VD signal, and has a cycle that changes according to the change in VD.

The DIF 111 accesses the memory 107 in synchronization with the nominal timing signal 221.
The packet data of each frame is always transferred within one frame period of the input VD.

Therefore, even if the input VD cycle changes, there is no loss of transfer data.

As described above, in the present embodiment, the period of the vertical synchronizing signal in the input video signal is detected, and the nominal timing is changed according to the fluctuation of the period of the vertical synchronizing signal. It is possible to change and transmit one frame of data without loss.

[0085]

As described above, according to the present invention, the last signal to be transmitted is detected from the signals actually read from each storage area from the storage means and transmitted, and the read area is switched. Therefore, the signal to be transmitted is not lost.

In another invention of the present application, among the received digital signals, the last signal of each group is detected and the write area is switched, so that the signals of the same group are spread over a plurality of storage areas. There is no writing.

In another invention of the present application, the period of the timing signal is changed in accordance with the video signal actually input, and a predetermined amount of signal is transmitted for each period of the timing signal. A predetermined amount of signal can be transmitted every time, and a signal to be transmitted is not lost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram illustrating a state of a signal transmitted by the device of FIG. 1;

FIG. 3 is a diagram showing a format of a signal transmitted by the device of FIG. 1;

FIG. 4 is a diagram showing a configuration of a control circuit in the device of FIG.

FIG. 5 is a timing chart for explaining a transmission operation.

FIG. 6 is a timing chart for explaining a transmission operation.

FIG. 7 is a diagram showing a configuration of a packet data end detection circuit in the circuit of FIG. 2;

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 2;

FIG. 9 is a diagram showing a configuration of a packet data end detection circuit in the circuit of FIG. 2;

FIG. 10 is a diagram showing another configuration of the control circuit in the device of FIG. 1;

11 is a diagram showing a configuration of a frequency division ratio generating circuit in the circuit of FIG.

Claims (22)

[Claims] A storage unit having a plurality of storage areas for storing digital signals; a transmission unit for selectively reading and transmitting the digital signals from the plurality of storage areas of the storage unit; A transmission unit that detects that the last digital signal to be transmitted by the transmission unit has been read from each storage area and switches a storage area from which the digital signal is to be read. 2. The digital signal includes a video signal,
2. The transmission device according to claim 1, wherein each of the plurality of storage areas can store at least one frame of the video signal. 3. The storage device according to claim 2, wherein the control unit switches a storage area in which the input video signal is to be written according to a vertical synchronization signal in the input video signal.
A transmission device according to claim 1. 4. An encoding means for compressing and encoding an information amount of an input video signal, wherein said transmission means transmits a video signal encoded by said encoding means and stored in said storage means. The transmission device according to claim 1, wherein: 5. A reproducing apparatus for reproducing said digital signal from a recording medium, wherein said transmitting means transmits the digital signal reproduced by said reproducing means and stored in said storage means. A transmission device according to claim 1. 6. The transmission device according to claim 1, wherein the digital signal includes a video signal, an audio signal, and an additional signal. 7. The transmission means has a synchronous transfer mode and an asynchronous transfer mode for terminating data transmission within a fixed period, and transmits a digital signal read from the storage means in the synchronous transfer mode. Claim 1
A transmission device according to claim 1. 8. The transmission apparatus according to claim 1, wherein said transmission means includes an IEEE 1394 serial bus interface. 9. A receiving means for receiving a digital signal composed of a plurality of groups, and a storing means having a plurality of storage areas and selectively storing the digital signal received by the receiving means in the plurality of storage areas. And a control unit for detecting a last digital signal of each group received by the receiving unit and switching a storage area in which the digital signal is to be written. 10. The receiving device according to claim 9, further comprising recording means for recording the digital signal read from the storage means on a recording medium. 11. An error correction coding means for adding error correction coding to the digital signal stored in said storage means by adding parity data, and said recording means converts said error corrected coded digital signal to digital data. The receiving device according to claim 10, wherein recording is performed. 12. The receiving apparatus according to claim 9, wherein the digital signal includes an encoded video signal in which an amount of information is compressed and is received in the encoded state. 13. The receiving apparatus according to claim 9, further comprising decoding means for decoding the digital signal stored in said storage means and expanding the information amount. 14. The receiving apparatus according to claim 9, wherein said control means detects a last digital signal of each group by using a digital signal received by said receiving means. 15. A storage unit having a plurality of storage areas for storing digital signals, a transmission unit for selectively reading and transmitting digital signals from the plurality of storage areas of the storage unit, and a plurality of groups. A receiving unit that receives the digital signal and selectively writes the digital signal in a plurality of storage areas of the storage unit; a transmission mode in which the transmission unit transmits the digital signal; and a reception mode in which the reception unit receives the digital signal. Mode switching means for switching between the modes, and in the transmission mode, detecting that the last digital signal to be transmitted by the transmission means has been read from each storage area of the storage means, and In addition to switching the storage area from which data is to be read, in the reception mode, Detecting the last digital signal of each group were, the data processing device and control means for changing a storage area to write the digital signal. 16. A storage means for storing a digital video signal, a generation means for generating a timing signal whose cycle varies in accordance with an input video signal, and a predetermined amount of said digital video signal for each cycle indicated by said timing signal Transmission means for reading and transmitting the data. 17. The generating means includes means for detecting a period of a vertical synchronizing signal of the input video signal, and frequency dividing means for dividing the period of the vertical synchronizing signal to generate the timing signal. The transmission device according to claim 16, wherein: 18. The transmission apparatus according to claim 16, wherein said transmission means accesses said storage means for each cycle of said timing signal. 19. The storage means has a plurality of storage areas, and comprises control means for switching a storage area from which the digital video signal is to be read in accordance with a vertical synchronization signal in the input video signal. The transmission device according to claim 16. 20. The transmission apparatus according to claim 16, wherein said transmission means transmits said digital video signal using a high-speed serial bus communication path. 21. An apparatus for selectively reading and transmitting a video signal from each storage area of a memory having a plurality of storage areas, wherein the video signal is to be written according to a vertical synchronization signal in an input video signal. Reading the video signal from the storage means so that all video signals to be transmitted stored in the respective storage areas can be transmitted regardless of the input timing of the vertical synchronizing signal in the input video signal. A transmission device for controlling operation. 22. A storage unit for storing a digital signal, a transmission unit for reading and transmitting the digital signal from the storage unit, and detecting that a predetermined digital signal has been read from the storage unit by the transmission unit. And a control unit that controls an operation of reading the digital signal from the storage unit according to an output of the detection unit.