JPH114001A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the heat resisting property of an aluminum gate electrode by having a structure in which crystal is grown from a source and drain region, containing high density of a metal element in which the crystallization of silicon is promoted by an active layer, to a channel forming region. SOLUTION: After a pattern, which becomes the base of the gate electrode where a titanium film 102 and an aluminum film 103 are formed, has been formed on a glass substrate 101, a gate insulating film 106 and an amorphous silicon film 107 are formed. Besides, a mask consisting of silicon oxide film is formed, and a state, wherein a nickel element is retained coming in contact with the surface, is obtained. Then, the above-mentioned amorphous silicon film 107 is crystallized by heat treatment. At that time, the growth of crystal makes progress from the region where the nickel element comes in contact, and a crystal grain boundary is formed by the collision of the tip parts of the growth of crystal from the left and the right sides. As a result, a high degree of mobility can be obtained by coinciding the axis in crystal growth direction and the axis in moving direction of the carrier in TFT movement. Also, the irregularity of characteristics of the TFT a number of which are formed on the same substrate, can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a bottom-gate thin film transistor. Further, the present invention relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film transistor (hereinafter referred to as a TF) using a silicon film formed on a glass substrate or a quartz substrate as an active layer.
T) is known.

Although there are several types of thin film transistors, the most practically used at present is a bottom gate type thin film transistor.

In consideration of productivity, it is preferable to develop a bottom-gate type TFT that can share a part of the manufacturing process, the design rule, and the manufacturing apparatus in the future.

[0005] The bottom gate type thin film transistor is composed of an active layer composed of a gate electrode, a gate insulating film, and a silicon film from the substrate side.

An amorphous silicon film is generally used as a silicon film constituting an active layer. However, to obtain higher performance, it is preferable to use a crystalline silicon film.

As a means for obtaining a crystalline silicon film, a technique of crystallizing an amorphous silicon film by irradiating a laser beam is often used.

[0008] A method of heating is also known as a crystallization technique, but is not used for the bottom gate type.

This is because the steps are performed in the order in which heating is performed after the formation of the gate electrode, so that the diffusion of the gate electrode material or the like is concerned.

However, from the viewpoint of the quality of the obtained crystalline silicon film and the stability of the manufacturing process, the method using heating is more preferable than the method using laser light irradiation.

[0011]

SUMMARY OF THE INVENTION As a gate electrode,
It is highly preferred to utilize aluminum with low resistance.

However, when aluminum is used as an electrode material, aluminum diffuses due to the influence of heat applied during crystallization and activation of the active layer, and projections called hillocks and whiskers are formed. There is a problem.

Particularly, in the case of a bottom gate type TFT,
Since the gate electrode is formed first and then the active layer is formed, the influence of heat applied in each step becomes a problem.

An object of the invention disclosed in this specification is to provide a structure in which a crystalline silicon film is used for an active layer in a bottom gate type TFT.

[0015]

Means for Solving the Problems One of the inventions disclosed in this specification is a gate electrode, a gate insulating film formed over the gate electrode, and a crystal formed on the gate insulating film. An active layer made of a conductive silicon film, wherein the active layer has a structure in which a crystal is grown from a source and drain region to a channel formation region, and the source and drain regions are more silicon than the channel formation region. Characterized in that a high concentration of a metal element that promotes crystallization is contained.

In the above structure, it is most preferable to use nickel as a metal element for promoting crystallization of silicon.

Metal elements that promote crystallization of silicon include Fe, Co, Ru, Rh, Pd, Os, Ir, and P.
An element selected from t, Cu, and Au can be used.

Further, instead of the crystalline silicon film, a compound film of silicon and germanium can be used.

According to another aspect of the invention, a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and forming an amorphous silicon film on the gate insulating film A step of forming a mask on the amorphous silicon film above the gate electrode, and a step of introducing a metal element that promotes crystallization of silicon into the amorphous silicon film using the mask, Performing a heat treatment to perform crystal growth from a region where the metal element is introduced to a region below the mask in the amorphous silicon film, and the metal element is introduced using the mask. The method includes a step of doping phosphorus in the region and a step of performing heat treatment to concentrate the metal element in the region where the phosphorus is doped.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG.
A pattern serving as a base of a gate electrode laminated with a titanium film 102 and an aluminum film 103 is formed on the substrate 1. (Fig. 1 (A))

Next, the titanium film 102 is side-etched. (FIG. 1 (B))

This is because the anodic oxide is filled in the region where the side etching has been performed in a later step. That is, the anodic oxidation is performed to the lower part of the edge of the aluminum pattern.

Next, heat treatment is performed to intentionally generate hillocks and whiskers on the surface of the aluminum pattern 103. That is, the projection is formed intentionally by the above growth of aluminum. By doing so, generation of hillocks and whiskers in a later step is suppressed.

The generation of hillocks and whiskers is caused by the non-uniformity of the atomic distribution and the residual stress existing in the aluminum film. Therefore, once hillocks and whiskers are generated, generation of hillocks and whiskers in a subsequent step can be suppressed.

Next, anodic oxidation is performed using the aluminum pattern 103 as an anode to form an anodic oxide film 105. At this time, the anodic oxidation proceeds to the lower part of the peripheral edge portion of the remaining aluminum pattern 100 (the portion side-etched in the step of FIG.

Thereafter, as shown in FIG. 1D, a gate insulating film 106 and an amorphous silicon film 107 are formed.

Further, as shown in FIG. 2B, a mask 110 made of a silicon oxide film is formed, and as shown by 11, a state where the nickel element 111 is held in contact with the surface is obtained.

Then, the amorphous silicon film 107 is crystallized by a heat treatment. At this time, the crystal growth proceeds from the region in contact with the nickel element, and the front ends of the crystal growth from the left and right collide at a portion indicated by 112 in FIG. 3A, and a crystal grain boundary is formed.

This crystal growth is called lateral growth,
The crystal structure in the crystal growth direction is continuous, and the movement of carriers in that direction can be made less susceptible to defects and levels.

Specifically, the axis of the crystal growth direction and the TF
High mobility can be obtained by matching the axis of the moving direction with the carrier during the T operation. For example, an N-channel TFT having a high mobility of 100 cm ² / Vs or more can be easily obtained.

When a large number of TFTs are simultaneously formed on the same substrate, the channel forming region of each TFT may have
Since the crystal grain boundaries are always formed at the portion indicated by 112, it is possible to suppress the occurrence of variations in the characteristics of each TFT.

[0032]

【Example】

[Embodiment 1] FIGS. 1 and 2 show a manufacturing process of this embodiment. First, a gate electrode is formed on a glass substrate 101.

As the substrate, a quartz substrate, a semiconductor substrate having an insulating film formed thereon, or a metal substrate can be used. These substrates are collectively called substrates having an insulating surface.

First, a titanium film was formed on a glass substrate to a thickness of 20 nm by a sputtering method, and an aluminum film containing 0.2% by weight of titanium was further coated with 400 nm.
The film is formed to a thickness of m by sputtering.

Next, the obtained laminated film of the titanium film and the aluminum film is patterned to obtain the pattern shown in FIG. That is, a stacked pattern of the titanium film pattern 102 and the aluminum film pattern 103 is obtained.

In order to obtain this pattern, a dry etching method is used, and a taper etching is performed to obtain a pattern having a tapered shape with inclined side surfaces as shown in the figure.

In this state, heat treatment at 400 ° C. for one hour is performed in an inert atmosphere. This heat treatment is performed to obtain the following effects. (1) Aluminum crystallization by the action of the titanium film. (2) Hillocks and whiskers are intentionally generated on the aluminum surface.

(1) By strengthening the crystal structure,
This is effective for suppressing generation of hillocks and whiskers in a later step. It is also effective for increasing heat resistance.

(2) By generating hillocks and whiskers at this stage, it is effective to suppress generation of hillocks and whiskers in a later step.

One of the factors that cause hillocks and whiskers is the non-uniformity of stress and composition existing in aluminum. As described above, once hillocks and whiskers are generated, the residual stress and whiskers are reduced. This is because the non-uniformity of the composition is reduced.

Next, the titanium film 102 is side-etched using a wet etching method capable of selectively etching the titanium film pattern 102. In this way, the side surface is etched to obtain a titanium film pattern 104 having a reduced area. (FIG. 1 (B))

Next, a pattern 10 made of an aluminum film
An anodic oxide film 105 is formed on the exposed surface of the aluminum film pattern by using an anodic oxidation method using 3 as an anode. (Fig. 1 (C))

At this time, the anodic oxidation proceeds toward the outside and the inside of the aluminum pattern. An anodized film is also formed on the side-etched portion of the titanium film, and is filled with the aluminum oxide film.

Thus, the gate electrode 100 is formed. In this step, the total growth distance of the anodic oxide film is set to 100 nm.

As the gate electrode, materials such as titanium nitride, tantalum nitride, a laminate of tantalum and tantalum nitride, and a laminate of a tungsten silicide layer and an N-type silicon layer can be used.

Once the state shown in FIG. 1C is obtained, FIG.
As shown in (D), a silicon oxide film 10 serving as a gate insulating film
6 is formed. This silicon oxide film 106 is formed by plasma CVD.
The film is formed to a thickness of 500 nm by the method. At this time, it should be noted that a laminated film of the silicon oxide film 106 and the anodic oxide film 105 becomes a gate insulating film.

Next, an amorphous silicon film 107 is formed to a thickness of 50 nm by using a low pressure thermal CVD method. (Fig. 1 (D))

Next, a silicon oxide film 108 is formed to a thickness of 150 nm by a plasma CVD method, and a resist mask 109 is formed. (Fig. 2 (A))

The resist mask 109 is formed by exposing from the back side of the substrate using the gate electrode pattern as a mask. Since this process can be performed in a self-aligned manner,
There is no need to place a new mask.

Next, as shown in FIG. 2B, the silicon oxide film 108 is patterned using the resist mask 109. Thus, a pattern 110 made of a silicon oxide film is obtained.

When the state shown in FIG. 2B is obtained, a nickel acetate solution adjusted to a nickel concentration of 10 ppm by weight is applied. Thus, a state where the nickel element is held in contact with the surface as indicated by 111 is obtained. (Fig. 2 (C))

In this state, the nickel element is not in contact with the surface of the amorphous silicon film 108 in a portion where the mask 110 made of a silicon oxide film is arranged, but is in contact with other regions. Can be (Fig. 2 (C))

As a method for introducing nickel, a CVD method,
Methods such as a sputtering method, an ion implantation method, a gas adsorption method, and a plasma treatment can be used.

As the metal element that promotes crystallization, it is most preferable to use nickel.
o, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au
An element selected from the following can be used.

In this state, a heat treatment is then performed at 550 ° C. for 4 hours in a nitrogen atmosphere. This heat treatment is performed using a heating furnace provided with a resistance heating type heater.

By performing this heat treatment, the amorphous silicon film is crystallized by the action of the nickel element. On this occasion,
With the diffusion of the nickel element, the diffusion of the nickel element occurs in the direction indicated by the arrow in FIG. 3A, and crystallization proceeds accordingly.

Further, crystal growth from both sides collides with the portion denoted by reference numeral 112 to form a crystal grain boundary.

In this way, a state is obtained in which the crystallization is performed while the nickel element is held in contact with the crystallization, and further, the crystal growth proceeds from the area to the area where the nickel element is not in contact.

In such a crystallization method, since the crystal grain boundary is always formed in the middle of the region indicated by 112,
This is effective in suppressing variations in element characteristics when a large number of elements are formed.

Next, as shown in FIG. 3B, doping with phosphorus is performed. This doping is performed under the condition that the region to be doped is a source and a drain region.

Here, a plasma doping method is used as a doping means. As the doping means, an ion implantation method may be used.

In this step, the exposed region of the silicon film is doped with phosphorus. That is, 113 and 1 in FIG.
Fourteen regions are doped with phosphorus.

Next, heat treatment is performed at 550 ° C. for 2 hours in a nitrogen atmosphere. In this step, the nickel element moves from the region 115 to the regions 113 and 114 as indicated by arrows. That is, the nickel element existing in the region 115 is gettered to the regions 113 and 114. (FIG. 3 (C))

This step is preferably performed at a temperature selected from the range of 500 ° C. to 650 ° C. This is because, when the temperature is lower than this temperature range, diffusion of the nickel element becomes slow, and when the temperature is higher than this temperature range, aluminum does not exist.

Phosphorus and nickel are NiP, NiP ₂ , Ni
_It has various bonding states such as ₂ P, and the bonding state is very stable. (The melting point of these combined materials is 900 ° C or more.)

The temperature required for diffusion of phosphorus is 800
It is at least about ° C.

Therefore, in the above-described heat treatment, nickel is actively moved, and phosphorus and nickel are combined, so that a state where the nickel does not move is obtained. (FIG. 3 (C))

Then, since phosphorus and nickel are not decomposed and phosphorus does not move, a state in which nickel is taken in by phosphorus, that is, a state in which nickel is gettered by phosphorus is obtained.

In other words, a state is obtained in which the nickel concentration in the region 115 decreases and the nickel concentration in the regions 113 and 114 increases.

The region 115 where the nickel element is gettered, that is, the region 115 where the nickel element is removed
Will later become the channel region of the TFT.

The regions 113 and 114 where the nickel element is gettered, that is, the region 1 where the nickel element is concentrated
13 and 114 are source and drain regions. Also,
115 becomes a channel formation region later. (FIG. 3 (C))

Next, a metal film (not shown) composed of a laminated film of a titanium film, an aluminum film and a titanium film is formed by a sputtering method. Here, a sputtering method is used as a film formation method, and each film thickness is set to 100 nm for a titanium film and 400 nm for an aluminum film.

By patterning this metal film, a source electrode 115 and a drain electrode 116 are formed. Then, the exposed semiconductor film is patterned by using the patterned metal electrode as a mask.
The state shown in (D) is obtained.

Thus, an N-channel TFT is completed. If a P-channel TFT is to be manufactured,
After doping of the doped phosphorus after the heat treatment of FIG. 3C, boron doping is performed so as to exhibit a P-type.
The regions 113 and 114 may be inverted to P-type.

In this case, after performing gettering, 11
A step of inverting the regions 3 and 114 to P-type is performed.

Before gettering, 113,
A step of inverting the region 114 to P-type may be performed.

According to the basic experiments of the present inventors, even if boron is doped with a higher dose in a region once doped with phosphorus, the effect of gettering is not reduced but a higher effect can be obtained. It turns out that.

[Embodiment 2] In Embodiment 1, FIG.
In the step shown in FIG. 2A, an example in which heat treatment is performed using a heating furnace is described. In this embodiment, this heat treatment is performed by RTA.
This is performed by using a heating means by irradiating strong light called “light”.

The RTA raises the temperature of the irradiated area to a temperature of 600 ° C. to 800 ° C. in a short time by condensing and irradiating infrared light emitted from a lamp with a mirror, and heats the irradiated area. It is a means for performing processing.

Since this heat treatment utilizes the phenomenon that light is absorbed in the irradiated area, the temperature can be raised in a short time, and the heat treatment of the irradiated area can be completed in a short time. it can. Specifically, the crystallization shown in FIG. 3A can be performed by heat treatment for about 1 minute to 10 minutes.

The heat treatment as shown in the first embodiment and the RTA by lamp irradiation as shown in this embodiment may be combined.

[Embodiment 3] This embodiment is an improvement of the fabrication process of Embodiment 1. In this embodiment, FIG.
This is an example in which a photomask is used as a method for forming the resist mask 109 in the manufacturing process shown in FIG.

In the case of this embodiment, there is a disadvantage in the manufacturing process that the number of masks is increased. However, since a photolithography process using a photomask that has been frequently used is used, it is advantageous in terms of process stability. It is.

[Embodiment 4] This embodiment is an example in which the crystallization method is changed in the manufacturing process shown in Embodiment 1.

In the first embodiment, the mask 1 shown in FIG.
In a state in which the element 10 is not disposed, a nickel element is introduced into the entire surface of the amorphous silicon film 107.

In such a case, peculiar crystal growth (lateral growth) as shown in FIG. 3A does not occur. That is, lateral growth does not proceed from a specific area.

In this case, a state where crystal growth progresses from a local portion is obtained in the entire film.

[Embodiment 5] In this embodiment, in order to control the threshold value of the TFT in the structure shown in Embodiment 1, FIG.
When the amorphous silicon film 107 shown in FIG.
This is an example in the case of adding (boron).

In this case, a small amount of diborane (B ₂ H ₆ ) may be added to the source gas when forming the amorphous silicon film 107.

As a doping method, a plasma doping method or an ion implantation method may be used.

[Embodiment 6] In this embodiment, an amorphous silicon film containing germanium (an amorphous silicon film containing silicon as a main component) is used in place of the amorphous silicon film 107 in the manufacturing process shown in the first embodiment. This is an example in the case of using a (silicon film).

The amorphous silicon film mainly containing silicon is made of Si
_X Ge _1-X (0.5 <X <1).

In this embodiment, germanium is contained at 5 atomic%. When germanium is contained in the amorphous silicon film, the threshold of the obtained TFT can be controlled by the content thereof.

As a method for forming an amorphous silicon film containing germanium, a plasma CVD method using silane and germane as a source gas, a low pressure thermal CVD method, or a sputtering method may be used.

[Embodiment 7] This embodiment is an example in which a P-channel TFT and an N-channel TFT are simultaneously manufactured. In the manufacturing process shown in this embodiment, for example, CMO
It can be applied to a manufacturing process of an S circuit.

FIGS. 4 to 9 show the manufacturing process of this embodiment.
First, a gate electrode including a titanium film pattern 402 and an aluminum film pattern 404 is formed on a glass substrate 401 as shown in FIG. At the same time, a gate electrode composed of the titanium film pattern 403 and the aluminum film pattern 405 is formed.

Here, the gate electrode on the left side is a gate electrode of a P-channel TFT. The right gate electrode is an N-channel TFT. That is, a P-channel TFT is manufactured on the left side, and an N-channel TFT is manufactured on the right side.

Thus, the state shown in FIG. 4A is obtained. Next, the titanium film patterns 402 and 403 are side-etched using the aluminum film patterns 404 and 405 as a mask.

In this way, a state in which the titanium film pattern is etched below the peripheral portion of the aluminum film pattern is obtained as exemplified by 406 in FIG. 4B.

Next, aluminum film patterns 404 and 40
By performing anodic oxidation with 5 as the anode, FIG.
The state shown in (C) is obtained. Here, 407 and 408 are anodic oxide films.

As shown in FIG. 4C, the anodic oxide film also advances below the aluminum film pattern. In the figure, the anodic oxidation from the lower portion of the aluminum film in the portion where the titanium film is removed is slightly emphasized.

Next, as shown in FIG.
09 is formed by a plasma CVD method. Further, an amorphous silicon film 410 is formed by a low pressure thermal CVD method.

Next, silicon oxide film patterns 411 and 412 are formed by using an exposure technique from the back side of the glass substrate. Further, a nickel acetate solution is applied to obtain a state in which the nickel element is held in contact with the surface as indicated by 413. (FIG. 5 (B))

Next, the amorphous silicon film is crystallized by performing heat treatment at 550 ° C. for 4 hours in a nitrogen atmosphere.

This crystallization results in the progress of crystal growth as indicated by the arrow in FIG. This heat treatment is preferably performed at a temperature of 500C to 600C.
This is because above this temperature aluminum cannot withstand,
If the temperature is lower than this temperature, the effect of crystallization cannot be obtained.

Next, doping of phosphorus is performed. This step is
This may be performed under conditions for forming the source and drain regions of the N-channel TFT.

In this step, as shown in FIG. 6A, the regions 601, 602 and 603 are doped with phosphorus.

Next, a heat treatment at 600 ° C. for one hour is performed in a nitrogen atmosphere. In this step, 604 and 6
601, 602 doped with phosphorus from the region No. 06,
The movement of the nickel element to the region 603 is performed. (FIG. 6 (B))

That is, the nickel element existing in the regions 604 and 605 is gettered in the regions 601, 602 and 603.

Note that the areas 604 and 605 are later formed by TFTs.
Channel forming region.

Next, as shown in FIG.
1 is arranged. Then, doping of boron is performed. At this time, the TFT on the left side is doped with boron so as to overlap with the region doped with phosphorus. That is, the regions 702 and 703 are doped with boron over phosphorus.

This boron doping is performed under the condition that the influence of the previously doped phosphorus is negated and the conductivity type is inverted to the P type. That is, the process is performed under the condition that the N-type region is inverted to the P-type during the previous phosphorus doping (the step of FIG. 6A).

After the end of the doping, the resist mask 70
Remove one. Then, by irradiating a laser beam, annealing of damage at the time of doping of the doped region and activation of the dopant are performed. This step may be performed by intense light irradiation.

Thus, the P-type regions 702, 703, N
Mold regions 704, 705 are formed.

Here, the P type regions 702 and 703 are formed by doping boron and phosphorus in an overlapping manner. In this region, boron has a role of determining the conductivity type, and phosphorus has a function of gettering nickel.

On the other hand, in the N-type regions 704 and 705,
Phosphorus has both a role of determining the conductivity type and a role of gettering nickel.

In FIG. 7, a P-type region 702 becomes a source region of a P-channel TFT. Reference numeral 703 is a drain region of the P-channel TFT.

Then, the N-type region 704 becomes the drain region of the N-channel TFT. In addition, the N-type region 705
Becomes the source region of the N-channel TFT.

Next, as shown in FIG. 8, a metal film 801 is formed by a sputtering method. This metal film 801 is formed of a laminated film of a titanium film, an aluminum film, and a titanium film.

Next, as shown in FIG. 9, the metal film 801 is patterned to obtain patterns 901, 902, 903, and 904.

Here, reference numeral 901 denotes a source electrode of the P-channel TFT, and reference numeral 902 denotes a drain electrode of the P-channel TFT.

Reference numeral 903 denotes a drain electrode of the N-channel TFT, and reference numeral 904 denotes a source electrode of the N-channel TFT.

Each electrode 901-9 is formed by using the metal film 801.
After the formation of 04, the exposed silicon film (the source and drain regions of each TFT) is etched using those electrodes as a mask. Thus, as shown in FIG. 9, a P-channel TFT (described as Pch TFT) and an N-channel TFT
(Described as Nch TFT) can be simultaneously formed on the same substrate.

[Embodiment 8] This embodiment is an example in which the manufacturing process of the embodiment 7 is improved. In this embodiment, the region to be a P-channel TFT is in a state in which doping of phosphorus for gentering and boron of boron for determining a conductivity type (for determining a channel type) are performed.
The region to be formed is characterized in that a heat treatment for gettering is performed in a state in which doping of phosphorus for determining the conductivity type is performed for gentering.

First, according to the manufacturing process shown in Embodiment 7, FIG.
The state shown in FIG. This state is shown in FIG. At this stage, the regions 601, 602, and 603 other than the region which will be a channel region later are doped with phosphorus.

Next, a resist mask 701 is arranged, and a region to be an N-channel TFT is masked. (FIG. 10
(B))

Then, boron doping is performed. This doping is performed under the condition that the conductivity type of the regions 702 and 703 is inverted from N type to P type. In other words, 7
This is performed under the condition that the influence of phosphorus doped as a dopant in regions 02 and 703 previously as a dopant is canceled and the influence of boron is exerted.

Thus, P-type regions 702 and 703 are obtained. Further, N-type regions 704 and 705 are obtained.

After the completion of the doping, a resist mask 70 is formed.
Remove one. Then, irradiation with laser light is performed to recover damage in the doped region and activate the dopant.

This step may be performed by a method using an infrared lamp (RTA method).

In the present embodiment, at the time when the doping of the dopant for determining the conductivity type of the source and drain regions of the P and N channel type TFT is completed, gettering of nickel used for crystallization is not performed, and N After doping a dopant (boron) that determines the conductivity type of the source and drain regions of the channel type TFT, nickel gettering is performed.

When the state shown in FIG. 10 is obtained, the resist mask 701 is further removed, and after annealing of the region to be doped is completed, heat treatment is performed at 550 ° C. for 1 hour to getter the nickel element. Do.

That is, as shown in FIG. 11, nickel element nickel is gelled from a region 604 to be a channel region later to regions 702 and 703. At the same time, the nickel element is gelled from a region 605, which will later become a channel region, to regions 704 and 705.

Here, the regions 702 and 703 are doped with phosphorus first, and further doped with boron. In this state, the regions 702 and 703 are compared with the regions 704 and 705 doped only with phosphorus. Gettering proceeds with higher efficiency.

According to a basic experiment, gettering does not progress at all in a region in which only boron is doped. However, gettering proceeds in a region doped with phosphorus and boron with higher efficiency than in a region doped only with phosphorus. (This factor is not clear)

Thus, the P-channel type TFT (PTF
A source region 702, a channel formation region 604, and a drain region 703 of T) are obtained. Here, the channel region 604
In this case, nickel is gettered in the source region 702 and the drain region 703, and the nickel concentration is reduced.

Further, a source region 705, a channel formation region 605, and a drain region 704 of an N-channel TFT (NTFT) are obtained. Here, in the channel region 605, nickel is gettered in the source region 705 and the drain region 704, and the nickel concentration is reduced.

After obtaining the state shown in FIG. 11, FIGS.
Through the manufacturing process shown in FIG. 1, a configuration in which a P-channel TFT and an N-channel TFT are formed on one glass substrate is obtained.

When the structure shown in this embodiment is adopted, the nickel element concentration in the channel region sensitive to the operation can be reduced, so that the adverse effect of nickel on the operation of the TFT can be suppressed.

[Embodiment 9] This embodiment is an example in which the manufacturing process shown in Embodiment 1 is improved. Here, gettering of nickel is performed in two stages.

First, according to the manufacturing process shown in FIG.
The state shown in (D) is obtained. That is, the steps up to the step of forming the amorphous silicon film 107 are obtained.

Next, as shown in FIG. 12A, a mask 1201 made of a silicon oxide film is provided. Then, doping with phosphorus is performed, and phosphorus is doped into regions 1202 and 1203 in FIG.

This phosphorus doping does not contribute to the formation of the source / drain, but is performed only for gettering nickel.

Next, heat treatment is performed at 600 ° C. for one hour in a nitrogen atmosphere. In this step, FIG.
As shown in (C), the nickel element existing in the region 1204 is gettered in the regions 1202 and 1203. This step is performed in a state where a mask 1201 made of a silicon oxide film is arranged.

Next, the exposed silicon film is etched using mask 1201 made of a silicon oxide film as a mask. That is, the regions of the gettering sites 1202 and 1203 are etched.

This makes it possible to reduce the nickel element concentration in the region 1204 (this region will later become the active layer of the TFT).

Thereafter, using the area 1204, FIG.
(A) A TFT is manufactured according to the following manufacturing steps.

When the manufacturing process shown in this embodiment is adopted,
The gettering of the nickel element from the region to be the active layer in the step shown in FIG. 12C and the gettering of the nickel element from the channel formation region to the source / drain region in the step shown in FIG. A ring is performed.

By adopting such a process, the influence of the nickel element can be more thoroughly eliminated.

[Embodiment 10] This embodiment is an example in which the structure of the gate electrode is improved in the structure shown in Embodiment 1 (or Embodiment 10).

Here, an example in which silicon is used as a gate electrode of an N-channel TFT will be described.

First, as shown in FIG. 14A, an N-type silicon film is formed on a glass substrate 101 by a low pressure thermal CVD method, and is patterned to form a pattern 1401. . This pattern 1401 becomes a gate electrode.

Then, a silicon oxide film 106 is formed on gate electrode 1401 as a gate insulating film by a plasma CVD method. Further, the amorphous silicon film 107 is subjected to low pressure thermal CVD.
The film is formed by the method.

Further, a silicon oxide film 108 is formed, and a resist mask 109 is formed by exposure from the back side of the substrate. (FIG. 14A)

Next, a mask 110 made of a silicon oxide film is formed using the resist mask 109 to obtain a state shown in FIG.

Next, by removing the resist mask 109 and applying a nickel acetic acid solution, a state in which the nickel element is held in contact with the surface as indicated by 111 is obtained. Thus, the state shown in FIG. 14C is obtained.

Next, by performing a heat treatment, the amorphous silicon film 107 is crystallized as shown in FIG.
Here, the crystallization is performed by heating at 630 ° C. for 4 hours in a nitrogen atmosphere.

The upper limit of the heat treatment in this step is limited by the heat-resistant temperature of the glass substrate since a silicon material having high heat resistance is used for the gate electrode.

For example, when a quartz substrate is used as the substrate, the heating temperature can be further increased.

After the crystallization is completed, as shown in FIG. 15B, phosphorus doping is performed by using a plasma doping method. In this step, the regions 113 and 114 are doped with phosphorus.

Next, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere. In this heat treatment step, the nickel element existing in the region 115 is gettered in the regions 113 and 114. (FIG. 15 (C))

Next, the source electrode 115 and the drain electrode 11
6 is formed. Then, the exposed semiconductor region is etched using this electrode to obtain a state shown in FIG.

As the material for the gate electrode, tantalum, a laminate of tantalum and tantalum nitride, various silicide materials and metal materials can be used.

[Embodiment 11] In this embodiment, an example of a semiconductor device using a TFT as disclosed in another embodiment will be described.

FIG. 13A shows a portable information processing terminal. This information processing terminal includes an active matrix type liquid crystal display or an active matrix type EL display in a main body 2001, and further includes a camera unit 2002 for taking in information from outside.

The camera section 2002 is provided with an image receiving section 2003 and operation switches 2004.

It is considered that the information processing terminal will become thinner and lighter in order to improve its portability.

In such a configuration, it is preferable that the peripheral drive circuit, the arithmetic circuit, and the storage circuit on the substrate on which the active matrix type display 2005 is formed be integrated with TFTs.

FIG. 13B shows a head mounted display. This device includes an active matrix type liquid crystal display and an EL display 2102 in a main body 2101. The main body 2101 can be attached to the head with a band 2103.

FIG. 13C shows a car navigation device. This device includes a liquid crystal display device 2202 and operation switches 2203 in a main body 2201, and has a function of displaying geographic information or the like based on a signal received by an antenna 2204.

FIG. 13D shows a mobile phone. This device has an active matrix type liquid crystal display device 2304, operation switches 2305, an audio input unit 2303, an audio output unit 2302, an antenna 23 in a main body 2301.
06.

Further, recently, a configuration in which the portable information processing terminal shown in (A) and the mobile phone shown in (D) are combined has been commercialized.

FIG. 13E shows a portable video camera. This is because the image receiving unit 240
6, an audio input unit 2403, operation switches 2404, an active matrix liquid crystal display 2402, and a battery 2405.

FIG. 13F shows a projection type liquid crystal display device. In this configuration, a main body 2501 is provided with a light source 2502, an active matrix type liquid crystal display device 2503, and an optical system 2504, and has a function of displaying an image on a screen 2505 provided outside the device.

Here, as the liquid crystal display device, either a transmission type or a reflection type can be used.

In the devices shown in (A) to (E), an active matrix type display using EL elements can be used instead of the liquid crystal display device.

[0177]

By employing the invention disclosed in this specification, the problem in the case where aluminum is used as the gate electrode of the bottom gate type TFT can be solved. Specifically, crystallization by heat treatment can be employed, and a case where heating is performed during a manufacturing process can be dealt with.

[Brief description of the drawings]

FIG. 1 is a diagram showing a process for manufacturing an N-channel TFT.

FIG. 2 is a diagram illustrating a process for manufacturing an N-channel TFT.

FIG. 3 is a diagram illustrating a process for manufacturing an N-channel TFT.

FIG. 4 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 5 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 6 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 7 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 8 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 9 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 10 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 11 shows a P-channel type TFT and an N-channel type TF.
The figure which shows the process of manufacturing simultaneously T.

FIG. 12 illustrates a manufacturing process of an N-channel TFT.

FIG. 13 is a diagram illustrating a configuration of a device using a TFT.

FIG. 14 illustrates a manufacturing process of a TFT.

FIG. 15 illustrates a manufacturing process of a TFT.

[Explanation of symbols]

Reference Signs List 101 glass substrate 102 titanium film pattern 103 aluminum film pattern 104 side-etched titanium film pattern 105 anodic oxide film 100 gate electrode 106 silicon oxide film 107 amorphous silicon film 108 silicon oxide film 109 resist mask 110 mask made of silicon oxide film 111 Nickel element held in contact with the surface 112 A portion where the tip of crystal growth collides 113 A region doped with phosphorus 114 A region doped with phosphorus 115 A region where gettering of phosphorus is performed

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 618B

Claims (8)

[Claims] 1. An active layer comprising: a gate electrode; a gate insulating film formed over the gate electrode; and an active layer made of a crystalline silicon film formed on the gate insulating film. Has a structure in which a crystal is grown from a source and drain region to a channel formation region, and the source and drain regions contain a metal element that promotes crystallization of silicon at a higher concentration than the channel formation region. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein nickel is used as a metal element for promoting crystallization of silicon. 3. A method according to claim 1, wherein Fe, Co, Ru, Rh, Pd, O
A semiconductor device using an element selected from s, Ir, Pt, Cu, and Au. 4. The semiconductor device according to claim 1, wherein a compound film of silicon and germanium is used instead of the crystalline silicon film. 5. A step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, a step of forming an amorphous silicon film on the gate insulating film, Forming a mask on the amorphous silicon film above an electrode, introducing a metal element that promotes crystallization of silicon into the amorphous silicon film using the mask, and performing a heat treatment; Performing crystal growth from a region where the metal element is introduced to a region below the mask in the amorphous silicon film; and doping phosphorus into the region where the metal element is introduced using the mask. And a step of subjecting the metal element to a region where the phosphorus is doped by performing a heat treatment, the method comprising the steps of: 6. The semiconductor device according to claim 5, wherein nickel is used as a metal element for promoting crystallization of silicon. 7. The method according to claim 5, wherein Fe, Co, Ru, Rh, Pd, O
A semiconductor device using an element selected from s, Ir, Pt, Cu, and Au. 8. The semiconductor device according to claim 5, wherein a compound film of silicon and germanium is used instead of the crystalline silicon film.