JPH11346345A - Video input and output device, and video recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video recording and reproducing device that converts data of the moving picture experts group MPEG system from an input terminal in compliance with the IEEE1394 into a pattern of data of the digital video DV system, records the pattern, converts data of the reproduced DV system into data of the MPEG system and outputs it with a simple configuration. SOLUTION: An MPEG packet is received at recording and a DV packet processing circuit 5 receives MPEG required data, gives DV and MPEG identification ID to the data. Converts the data into a data pattern of the DV SDL format and the resulting pattern is fed to a conventional DV recording system 27, in which the data are recorded on a tape T. A DIT packet is inserted to a reproduction data with the SDL format from the tape T and the data are converted into an MPEG packet and fed to an external MPEG terminal from an output terminal. Thus, a conventional DV reproduction system and a conventional recording system are used and recording and reproduction of DV and MPEG data are attained with a simple configuration of addition of a DV packet relating processing circuit and an MPEG packet relating processing circuit at a low manufacture cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a video input / output device and a video recording / reproducing device.

[0002]

2. Description of the Related Art Conventional digital video (DV) includes:
A digital interface conforming to IEEE 1394 is attached, and video is transmitted and received by various digital video systems via the digital interface. The digital interface system has a configuration based on each digital video system.

[0003]

As described above, the conventional digital video digital interface is constituted by a system unique to each digital video system, and therefore, the MPEG (Moving) of a different system is used.
Picture Experts Group) data cannot be received via this digital interface and recorded on a recording medium. In this case, in order to receive and record the data of the MPEG system, two kinds of circuits, a digital video circuit and an MPEG circuit, are required, the hardware part is increased, and the manufacturing cost is reduced. Problems arise.

SUMMARY OF THE INVENTION The present invention has been made in view of the current state of reception of digital video data as described above. A first object of the present invention is to convert MPEG data input from an IEEE1394-compliant input terminal. A video input / output device having a simple configuration for converting a digital video format data pattern and converting the digital video format data to MPEG format data at the time of output, and outputting the data from an IEEE1394 compliant output terminal. Is to provide.

[0005] A second object of the present invention is to provide IEEE1394.
MPEG data input from a compliant input terminal
The data is converted into a digital video data pattern and recorded on a recording medium, and the digital video data reproduced from the recording medium is converted into MPEG data.
An object of the present invention is to provide a video recording / reproducing apparatus having a simple configuration for outputting to an external terminal from an output terminal based on IEEE1394.

[0006]

According to one aspect of the present invention, there is provided a data detecting means for detecting an input of MPEG data from an input terminal conforming to IEEE 1394, and a data detecting means for detecting the data. Means for converting the input data into a digital video data pattern when the input of the MPEG data to the input terminal is detected by the means; and outputting data based on the digital video data pattern. Sometimes, a second conversion means for converting the data into MPEG data,
The MPEG data converted by the second conversion means is
Output means for outputting from an output terminal conforming to IEEE 1394.

In order to achieve the second object, the invention according to claim 2 comprises a data detecting means for detecting an input of MPEG data from an input terminal conforming to IEEE 1394, and the data detecting means comprising: When the input of the MPEG system data to the input terminal is detected, first conversion means for converting the input data into a data pattern of the digital video system, and a digital signal obtained by the conversion by the first conversion means. Recording means for recording a video data pattern on a recording medium, second converting means for converting digital video data reproduced from the recording medium into MPEG data, and second converting means. Output means for outputting the converted MPEG data to an external terminal from an output terminal conforming to IEEE 1394. It is.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a video recording / reproducing apparatus according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a recording system of the present embodiment, FIG. 2 is a block diagram showing a configuration of a reproducing system of the present embodiment, and FIG. 3 is a block diagram showing a configuration of a DV packet processing circuit of FIG. FIG. 4 is a block diagram showing the configuration of the MPEG packetization processing circuit of FIG. 2, FIG. 5 is an explanatory diagram of an SDL block packet of the digital video of the present embodiment, and FIG. 6 is a diagram of the digital video of the present embodiment. FIG. 7 is an explanatory diagram showing a configuration of one sync, and FIG. 7 is an explanatory diagram of pack data of the present embodiment.

A recording system 25 according to the present embodiment has a configuration as shown in FIG. 1. In the recording system 25, a digital signal input from an input terminal 2 of the cable is received inside the cable. A physical layer 3 and a LINK layer 4 that is connected to the physical layer 3 and separates an output signal of the physical layer 3 into a header and data are provided. The circuit 1 is connected to a DV packetization processing circuit 5 to which data is input and which performs DV packetization processing (digital video packetization processing) on the input data. The DV packetization processing circuit 5 and its peripheral circuits are configured as shown in FIG. 3, and a data output terminal of the LINK layer 4 has a switch 2 that is ON-OFF controlled by an output signal of the header detection circuit 1.
1 is connected to a memory 22 in which data from the LINK layer 4 is stored, and an output terminal of the memory 22 is connected to an ID adding circuit 23 for adding an identification ID of MPEG and DV to data required for the packet. The output terminal of the ID addition circuit 23 is a FIFO (First In First Out) that outputs data at the timing of the system.
It is connected to the memory 6.

As shown in FIG. 1, a recording system 27 for recording ordinary digital video on a tape is connected to an output terminal of the FIFO memory 6, and the recording system 27 is connected to the FIFO 6. In addition, the deshuffling process and VAUX (Vid
A deshuffling processing circuit 7 for generating eo auxiliary data is provided. The deshuffling processing circuit 7 is connected to an error correction coding processing circuit 8 for adding an error correction code, and the error correction coding processing circuit 8 is connected to a recording modulation processing circuit 9 for performing data recording modulation. The output data of the recording modulation processing circuit 9 is supplied to and recorded on the tape T via the amplifier 10.

On the other hand, the reproducing system 26 of the present embodiment
The playback system 26 has the following configuration.
A reproduction system 28 for performing normal digital video reproduction from a tape is used as it is. In this reproduction system 28, reproduction data from the tape T is supplied via an amplifier 11 to a demodulation circuit 12 for performing demodulation processing. Have been.
The demodulation circuit 12 is connected to an error correction decoding processing circuit 13 for performing error correction.
3 is connected to a shuffling processing circuit 14 for performing shuffling processing.

An output terminal of the shuffling processing circuit 14 is connected to a FIFO memory 15, to which a DIT packet is supplied from a DIT generating circuit 20 for packetizing data into a standard length. The output terminal of the FIFO memory 15 is connected to an MPEG packetizing circuit 16 for performing MPEG packetizing processing. This MPEG packetization processing circuit 16
And peripheral circuits are configured as shown in FIG.
IEEE 24 is stored in the memory 24 connected to the FIFO memory 15.
A header adding circuit 25 for adding an E1394 header and an MPEG CIP header is connected, and a header adding circuit 2
The LINK layer 17 is connected to the output terminal 5 as shown in FIG. 2, the physical layer 18 is connected to the LINK layer 17, and the physical layer 18 is connected to the output terminal 19 of the cable.

The operation of this embodiment having the above configuration will be described. At the time of the recording operation, the digital signal input from the input terminal 2 of the cable is received by the physical layer 3 and
The header input to the NK layer 4 and separated by the LINK layer 4 is input to the header detection circuit 1 and the data is input to the DV packetization processing circuit 5. The header detection circuit 1 detects the contents of the header, determines whether the received packet is digital video or MPEG, and supplies the determination data to the switch 21 of the DV packetization processing circuit 5. Is done. If the determination data is an MPEG-format packet to be received, the switch 21 is turned ON-O.
By performing the FF operation, a necessary portion of the data of the MPEG format packet is fetched and stored in the memory 22.

In this case, in the packet of the MPEG system,
One packet is not limited to one data, and a data portion excluding a header may be divided and transmitted. Therefore, the memory 22 stores data necessary for a DV packet. Then, data necessary for the packet stored in the memory 22 is input to the ID addition circuit 23, where the ID addition circuit 23 identifies the MPEG and DV.
D is added and the data to which the identification ID is added is FIFO
Input to the memory 6.

[0015] The DV SDL packet is configured as shown in FIG. 5, and in FIG.
In the present embodiment, when data of an MPEG packet is received, this part is filled with data of one MPEG packet in order from the front, and the remaining part is filled with zeros. As shown in FIG. 6, one sink in the DV packet is
The ID part consists of three bytes, one byte of a parameter STA indicating the state of data processing such as whether or not error processing has been completed, a parameter QNO of data division, and 76 bytes of a real data part. In the present embodiment, MPEG data is recorded in the 76-byte portion of the actual data portion, and all four bytes from the head of each sync are filled with zeros. When the MPEG recording rate is lower than the DV recording rate, a dummy packet in which all zeros are filled in the actual data portion is recorded. In this case, the dummy packet is included in the fourth byte from the head of each sync. F is the area of the STA to be recorded, and the fact that the data is dummy data is recorded.

As described above, the output data of the ID addition circuit 23 of the DV packetization processing circuit 5 is stored in the FIFO memory 6, and the data is output from the FIFO memory 6 at the timing of the system. The data is input to the deshuffling processing circuit 7 and is deshuffled. At the same time, VAUX data of system data is created and inserted in the same manner as normal data. In this case, V
An example of the contents of the pack data generated to be inserted into the AUX is as shown in FIG.
ST and REC END are flags that become 1 each for the first frame of recording and the last frame of recording. Then, the output data from the deshuffling processing circuit 7 is input to an error correction coding processing circuit 8 where an error correction code is added, and then the recording modulation processing circuit 9
After the signal is input to a recording head and subjected to a modulation process for recording, the signal is supplied to a recording head via an amplifier 10 and a recording signal is recorded on the tape T.

On the other hand, at the time of a reproducing operation, reproduced data from the tape T is inputted to a demodulation circuit 12 via an amplifier 11, and a demodulation circuit 12 performs a demodulation process of a reproduced signal. The error correction data is input to the decoding processing circuit 13 and error correction is performed. The data after the error correction processing is shuffled by the shuffling processing circuit 14 and then supplied to the FIFO memory 15. By the way, the DIT generation circuit 20 generates a DIT packet of a data section based on the information of RECSTART and REC END recorded in the VAUX at the time of recording, and the DIT packet is supplied from the DIT generation circuit 20 to the FIFO memory 15. You. Therefore, in the FIFO memory 15, D data supplied from the DIT generation circuit 20 is added to the normal data.
An IT packet is inserted, and the data into which the DIT packet is inserted is input to the MPEG packetization processing circuit 16.

This MPEG packetization processing circuit 16
It has a configuration as shown in FIG.
5, the redundant portion for the DV packet is removed and stored in the memory 24. The data is read out from the memory 24 at the output timing conforming to IEEE1394, and is input to the header adding circuit 25. You. In the header adding circuit 25, the 1394 header and the MPEG
And a CIP header for the physical layer 18 via the LINK layer 17.
And output data from the physical layer 18 is connected to an external MPEG terminal by a cable from an output terminal 19 of the cable.

As described above, according to the present embodiment, at the time of recording, a packet received from the input terminal 2 of the cable is M
When the header detection circuit 1 detects that the packet is a PEG packet, the necessary data of MPEG is fetched into the memory 22 by turning on and off the switch 21 of the DV packetization processing circuit 5, and the ID addition circuit 23 In, DV
An identification ID for identifying the data and the MPEG data is added to the data.
Is supplied to a normal DV recording system 27 and is recorded on a tape T in a state where the data pattern is converted into a data pattern of the SDL format of the DV via the.

The normal DV SDL format data reproduced from the tape T by the normal DV reproduction system 28 is obtained by inserting the DIT packet from the DIT generating circuit 20 into the FIFO memory 15. ,
The obtained data is transmitted to the MPEG packetization processing circuit 16.
Then, the packet is converted into an MPEG packet, and is supplied from a cable output terminal 19 to an external MPEG terminal via a LINK layer 17 and a physical layer 18.

Thus, according to the present embodiment,
A normal DV recording system 25 is used for the recording system 25, and a normal DV reproduction system 28 is used for the reproduction system 26. These include a simple circuit portion for performing processing related to DV packetization processing. , A simple circuit portion for performing the MPEG packetization process and related processes, and a simple and low manufacturing cost configuration, so that ordinary DV data and MPE
The recording / reproducing operation can be performed for any of the G data.

[0022]

According to the video input / output device of the first aspect,
An input terminal and an output terminal conforming to IEEE 1394 are provided. When input of MPEG data from the input terminal is detected by the input data detection unit, the input data is converted into digital data by the first conversion unit. MP converted to video data pattern
The data of the EG system is processed as a data pattern of the digital video system, and when outputting data based on the data pattern of the digital video system, the data is converted to the second data pattern.
Is converted into MPEG data by the conversion means, and the converted MPEG data is output from the output terminal by the output means.
IEEE 1394
The interface operation between digital video data and MPEG data can be performed with only a slight change in the interface unit conforming to the standard.

The video recording / reproducing apparatus according to the second aspect is provided with an input terminal and an output terminal conforming to IEEE 1394, and input of MPEG data from the input terminal is performed by input data detection means. When detected, the input data is converted into a digital video data pattern by the first conversion means, and the digital video data pattern obtained by the conversion is recorded on the recording medium by the recording means. The digital video data to be reproduced is converted into MPEG data by the second conversion means, and the MPEG data is output from the output terminal to the external terminal by the output means. The playback unit is used as it is, and a slight Further only allows recording and reproduction of the data of the data and the MPEG system digital video system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a recording system according to an embodiment of a video recording / reproducing apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproduction system according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a DV packetization processing circuit in FIG. 1;

FIG. 4 is a block diagram showing a configuration of an MPEG packetization processing circuit of FIG. 2;

FIG. 5 is an explanatory diagram of an SDL block packet of digital video according to the embodiment;

FIG. 6 is an explanatory diagram showing a configuration of one sync of digital video according to the embodiment.

FIG. 7 is an explanatory diagram of pack data according to the embodiment;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Header detection circuit, 2 ... Input terminal, 3 ... Physical layer, 4 ...
LINK layer, 5 ... DV packetization processing circuit, 7 ... Deshuffling processing circuit, 8 ... Error correction coding processing circuit, 9 ...
Error correction encoding processing circuit, 9 ... recording modulation processing circuit, 12
... demodulation circuit, 13 ... error correction coding processing circuit, 14 ... shuffling processing circuit, 16 ... MPEG packetization processing circuit, 20 ... DIT generation circuit, 21 ... switch, 23 ... I
D addition circuit, 25: header addition circuit.

Claims (2)

[Claims] 1. A data detecting means for detecting an input of MPEG data from an input terminal conforming to IEEE1394, and when the data detecting means detects an input of MPEG data to the input terminal, First conversion means for converting input data into a digital video data pattern; and second conversion means for converting data into MPEG data when outputting data based on the digital video data pattern; MPEG data converted by the second conversion means is
A video input / output device, comprising: output means for outputting from an output terminal conforming to IEEE 1394. 2. A data detecting means for detecting input of MPEG data from an input terminal conforming to IEEE 1394, and when the input of MPEG data to the input terminal is detected by the data detecting means, First conversion means for converting the input data into a digital video data pattern; recording means for recording the digital video data pattern obtained by the conversion by the first conversion means on a recording medium; Second conversion means for converting digital video data reproduced from the medium into MPEG data, and converting the MPEG data converted by the second conversion means from an IEEE1394 compliant output terminal to an external terminal Output means for outputting to a video recording / reproducing apparatus.