JPH11338904A - Method for verifying violation of design rule - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make efficiently detectable violations of design rules in a short time by deleting patterns in two cells which are a prescribed distance or longer apart from the tangent of two adjacent cells and subjecting remaining patterns in two cells to design rule violation detection processing. SOLUTION: Data of patterns 4 to 6 adjacently arranged in all possible positional relations is generated with respect to all combinations of cells 1 to 3 in a given library. All of patterns 4 which are a distance L or longer apart from a tangent 7 of adjacent cells 1 to 3 are removed from the DRC application object. Finally, remaining patterns 5 and 6 are subjected to design rule violation verification using DRC to output all of violation information. The distance L is set in accordance with a design rule. Thus, the number of data of patterns taken as the object of design rule violation verification using DRC is reduced to shorten the DRC execution time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer for arranging a plurality of cells including a certain number of semiconductor elements and determining whether a pattern of the semiconductor elements in the arranged cells does not violate design rules. The present invention relates to a design rule violation verification method used for verification.

[0002]

2. Description of the Related Art In an arrangement design in which necessary cells are extracted from a cell library in which a large number of cells for forming a semiconductor integrated circuit are collected and arranged, the arrangement of semiconductor element patterns in each cell satisfies a design rule. Is not enough,
When cells are actually arranged on a semiconductor chip, it is necessary to prevent design rule violations between patterns of adjacent cells. In other words, the pattern of the cell in the library is arranged such that no matter which two cells in the library are arranged adjacently in any positional relationship, no design rule violation occurs between the patterns of the two cells. There is a need. In order to verify this, for every combination of cells in the library, create pattern data when those cells are placed adjacent to each other in any possible positional relationship. Need to check. A program for verifying design rules for given pattern data is a DRC (Design Rule Checker).
ecker)), which has been widely used for verification of design rule violations.

FIG. 5 is a flowchart showing the procedure of a conventional design rule violation verification method. The procedure of the conventional design rule violation verification method will be described with reference to this flowchart. First, with respect to all combinations of cells in a given library, data of patterns arranged adjacently in all possible positional relations is created (step ST51). Next, the DRC is performed on the thus arranged pattern.
Verification of design rule violations is performed using (Step S)
T52).

FIG. 6 is a top view showing an example of an arrangement of cells to be verified by a conventional design rule violation verification method. In the figure, 61 to 63 are cells, 64 is a pattern of a semiconductor element in the cell 61, and 65 is an example of a design rule violation pattern outputted as a result of design rule violation verification using DRC. That is, in the example of FIG. 6, as a result of executing DRC on the data of the cell arrangement pattern as shown in (1) of FIG. A design rule violation pattern as shown at 65 was found.

[0005]

Since the conventional design rule violation verification method is configured as described above, the variation of the positional relationship between the cell combination and the arrangement is enormous, so that the design rule violation verification using the DRC is performed. However, there is a problem in that the data amount of the target pattern becomes very large, and it takes a very long time to execute the DRC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a design rule violation verification method capable of efficiently detecting a design rule violation pattern in a short time.

[0007]

According to a method of verifying design rule violation according to the present invention, any two cells are arranged adjacent to each other and a first predetermined distance from a tangent of the arranged two adjacent cells is determined. The pattern in the two cells separated from each other as described above is deleted, and the process of detecting a design rule violation is performed on the pattern in the two cells remaining as a result of the pattern deletion.

The design rule violation verifying method according to the present invention removes a pattern located at a position at least a second predetermined distance from a tangent of two adjacent cells, from the detected design rule violation pattern. The method further comprises a step of outputting only a violation pattern other than the above.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a flowchart showing a procedure of a design rule violation verification method according to the first embodiment of the present invention. In the design rule violation verification method according to the first embodiment, first, data of a pattern arranged adjacently to all combinations of cells in a given library in all possible positional relations is created (step ST1 (arrangement). Step)). Next, the distance L from the tangent of the adjacent cell
All patterns located at positions (first predetermined distance) or more apart are deleted from DRC application targets (step ST2).
(Deletion step)). Finally, D for the remaining pattern
Verification of a design rule violation using RC is performed, and all violation information is output (step ST3 (design rule violation detection step)).

Here, the distance L is set according to the design rule. For example, if a design rule is given as a set of minimum allowable values for the spacing or width of a pattern (polygon)
Assuming that the maximum value of the minimum allowable value is X, L is a value larger than X. If a design rule violation occurs between the patterns of both adjacent cells, the pattern related to the violation must be within a distance X from the tangent of the cell (the cell pattern exists only inside the cell boundary). Note that). Therefore, a pattern relating to a rule violation to be detected (a rule violation between cells) is never deleted, so that any rule violation to be detected is always output.

FIG. 2 is a top view showing an example of an arrangement of cells to be verified by the design rule violation verification method according to the first embodiment. The cell arrangement is the same as that of the conventional example shown in FIG. In FIG. 2, reference numerals 1 to 3 denote cells, 4 denotes a pattern of a semiconductor element in cells 1 to 3, and 5 and 6 denote design rule violation patterns output as a result of design rule violation verification using DRC. . Reference numeral 5 denotes a minimum interval rule violation between cells (a rule violation to be detected), and 6 denotes a minimum interval rule violation caused by the deletion of a figure. 7 is the tangent between cells 1 and 3.

In the example of FIG. 2, a cell arrangement pattern as shown in (1) of FIG. 2 exists in the arrangement data. From this data, as shown in (2) of FIG. 7
As a result of deleting a pattern located at a position larger than a predetermined distance L from the target and verifying the remaining pattern using DRC, the design rule violations indicated by reference numerals 5 and 6 in (3) of FIG. Patterns were discovered. Pattern 6
Is false information that does not originally occur.

As described above, according to the first embodiment, since a part of the arranged pattern is deleted, the DRC
Thus, the number of data of the pattern data to be subjected to the design rule violation verification using the method can be reduced, and the effect of shortening the DRC execution time can be obtained.

Embodiment 2 FIG. FIG. 3 is a flowchart showing a procedure of a design rule violation verification method according to the second embodiment of the present invention. In FIG. 3, the same steps as those in the first embodiment shown in FIG. 1 are assigned the same step numbers, and the description thereof is omitted.

In the design rule violation verifying method according to the second embodiment, all the cell combinations are arranged adjacently (step ST1), and the pattern located at a position longer than the distance L from the tangent 7 between the cells is deleted (step ST1). After step ST2),
Of the rule violation patterns detected by executing the DRC, those that are at a position at least a distance S (a second predetermined distance) from the tangent line of the cell are deleted, and only the other violation patterns are output ( Step ST4 (design rule violation detection step, design rule violation pattern output step).

In the second embodiment, the distance L and the distance S are set according to design rules. For example, when the design rule is given as a set of minimum allowable values of the interval and width of a pattern (polygon), if the maximum value of the minimum allowable values is X, the distance S is larger than X, and the distance L is S +
The value is larger than X. If a design rule violation occurs between the patterns of both cells, the pattern involved in the violation must be within a distance X from the tangent of the cell (the cell pattern exists only inside the cell boundary). Note). Therefore, a situation in which the rule violation to be detected is not output due to the deletion of the pattern and the deletion of the violation information does not occur. In addition, the pattern of the arrangement related to a false violation (a violation that would occur if the pattern is not deleted) caused by deleting the pattern should be within the distance X from the deleted pattern. It should be located farther than the distance S. Therefore, the false violation is deleted and not output.

FIG. 4 is a top view showing an example of an arrangement of cells verified by the design rule violation verification method according to the second embodiment. It is assumed that the cell arrangement is the same as that of the conventional example shown in FIG. 6 and the first embodiment shown in FIG. 4, the same elements as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 4, S is cell 1
Represents a predetermined distance from tangent 7 between.

In the second embodiment, the false violation information (pattern 6 in FIG. 2) output in the first embodiment is not output because it is located farther than the distance S.

As described above, according to the second embodiment, similar to the first embodiment, the pattern can be deleted by deleting the pattern.
The effect that the processing time of the RC can be reduced can be obtained, and at the same time, the effect that the user of the program can easily determine whether or not there is a design rule violation that should be detected originally can be obtained.

[0020]

As described above, according to the present invention, a pattern located at a position at least a first predetermined distance from a tangent line of two adjacent cells is deleted to perform a design rule violation detection process. Therefore, there is an effect that a pattern violating a design rule can be efficiently detected in a short time.

According to the present invention, the pattern detected as the design rule violation is removed from the pattern located at a position at least a second predetermined distance from the tangent of the two adjacent cells, and is output. In addition, there is an effect that it is possible to easily determine whether or not there is a rule violation that should be originally detected without outputting false violation information generated by deleting a pattern.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of a design rule violation verification method according to a first embodiment of the present invention.

FIG. 2 is a top view showing an example of an arrangement of cells verified by the design rule violation verification method according to the first embodiment;

FIG. 3 is a flowchart illustrating a procedure of a design rule violation verification method according to a second embodiment of the present invention;

FIG. 4 is a top view showing an example of an arrangement of cells verified by a design rule violation verification method according to a second embodiment;

FIG. 5 is a flowchart showing a procedure of a conventional design rule violation verification method.

FIG. 6 is a top view showing an example of an arrangement of cells verified by a conventional design rule violation verification method.

[Explanation of symbols]

1 to 3 cells, 4 patterns, 5, 6 patterns that violate design rules, 7 tangents, L distance (first predetermined distance), S distance (second predetermined distance), ST1 placement step, ST2 deletion step, ST3 Design rule violation detection step, ST4 Design rule violation detection step, Design rule violation pattern output step.

Claims (2)

[Claims] An arranging step of arbitrarily arranging any two cells adjacent to each other; and the arranging step of arranging the two cells at a position at least a first predetermined distance from a tangent line of the two adjacent cells arranged by the arranging step
A deletion step of deleting a pattern in one cell; and a design rule violation detection step of performing a design rule violation detection process on a pattern in the two cells remaining as a result of the pattern deletion by the deletion step. Design rule violation verification method. 2. The method according to claim 1, wherein the design rule violation detection step detects two adjacent design rule violation patterns.
2. The design rule violation pattern outputting step according to claim 1, further comprising removing a pattern located at a position at least a second predetermined distance from a tangent line of the two cells and outputting only the other violation patterns. Verification method for design rule violation.