JPH11317030A - Information recording and reproducing method, information recording and reproducing circuit and information recording and reproducing device using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of data decoding in a decoding processing in a maximum likelihood sequence detection by applying a processing to be able to detect and correct that specifice coding erroneous phenomena having preliminarily set prescribed coding erroneous patterns are generated till prescribed numbers and recording an error correcting code dividedly or en bloc at a prescribed recording position corresponding to a recording code series block. SOLUTION: Decoded code series 311 decoded in a maximum likelihood sequence decoder 310 are inputted or directly inputted to a first error correcting and coding circuit 304 without logically changing code orders. This processing only continuously applies a fixed processing to respective codes without replacing or exchanging the code orders of the decoded code series 311. Consequently, since the processing is possible to correspond to a code erroneous syndrome one to one, the erroneous syndrome is never dispersed on the code series before and after the processing. This processing can be executed by adopting a constitution in which the first error correcting and coding circuit 304 is connected to the maximum likelihood sequence decoder 310 being a composite means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information recording / reproducing method, an information recording / reproducing circuit, and an information recording / reproducing apparatus using the same for realizing digital information recording / reproducing with high density and high reliability.

[0002]

2. Description of the Related Art In high-density information recording / reproducing systems / devices,
In order to improve the reliability of data reproduction from a low-quality recording / reproduction signal obtained from a recording medium, a maximum likelihood sequence estimation method or maximum likelihood sequence detection (MLSD: Maximum-Likeli
2. Description of the Related Art Data decoding techniques using hood sequence detection) have become widespread, and have been widely used as effective means for error correction decoding methods such as convolutional codes in the communication field.

The maximum likelihood sequence detection is a technique for minimizing an error occurrence probability in a decoded code sequence by estimating a decoded code sequence in a time-series manner using the memory property or correlation of the decoded data. , Playback signal sequence {Y (n)}
(Where n is an integer indicating the discrete signal generation order and time) is given to the decoding input. From all possible recorded information (code) sequences {X (n)}, signal sequence {Y (n)} Is selected (maximum likelihood sequence) having the highest probability (likelihood) of being reproduced, and this is output as a decoded information (code) sequence {Z (n)}. In other words, the maximum likelihood sequence decoder, given the entire sequence of a certain reproduction signal sequence {Y (n)}, under the condition assuming a certain recording information (code) sequence {X (n)}, The recorded information (code) sequence ｛X (n) is set such that the posterior prior probability P [{Y (n)} / {X (n)}] at which the reproduced signal sequence {Y (n)} is received and reproduced is maximized. )｝ To perform the maximum likelihood sequence estimation of the decoded information (code) sequence {Z (n)}. At this time, the recording information (code) sequence {X (n)} is not estimated independently of each other, but is estimated in the context. Such maximum likelihood sequence detection is performed under the condition that all possible recording information (code) sequences {X (n)} are recorded with equal probability, in other words, each recording information (code) sequence {X (n)} } Under the condition that no information on the probability of occurrence of {
Correct decoding probability P [{X (n)} & {Z (n)}] (recorded information (code) sequence
The decoding of the best decoding error probability is provided by maximizing {X (n)} and the decoding information (code) sequence {Z (n)}).

The maximum likelihood sequence detection is performed by a Viterbi algorithm (Viterbi Algo
(rithm), etc., and is efficiently realized. As a paper on maximum likelihood sequence detection and Viterbi algorithm, Day. Forney, “The Viterbi Algorithm”, Procedings of IEE (GDForney, “The Viterbi Algorithm”, Proceedin
gs of the IEEE), vol.61, No.3, March 1973, pp.268
-278 and G. Ungerbock, "Adaptive Maximum Likelihood Receiver for Carrier Modulated Data Transmission System", IEE Transaction
On Communication (G. Ungerbock, "Adaptive Ma
ximum-Likelihood Receiver for Carrer-Modulated Dat
a Transnission Systems ", IEEE Transactions on Comm
unications), vol.COM-22, No.5, May 1974, pp.624-6
38, and these papers show the basic format of a receiving / reproducing apparatus using maximum likelihood sequence detection or a part thereof.
Further, a practical means of realizing the Viterbi algorithm is described in Filing Row, “Implementing the Viterbi Algorithm.
Algorithm ", IEE Signal Processing Magazine (Hui-Ling Lou," Implementing
the Vitrbi Algoithm ", IEEE Signal Processing Magaz
ine), Sept. 1995, pp. 42-52, and G. Fetway's End H. Meir, "High-Speed
Parallel Viterbi Decoding: Algorithm and VSL Architecture, "
EEE Communication Signal Magazine (G. Fettweis and H. Meyr, "High-Speed Parallel Vi
terbi Decoding: Algorithm and VLSI-architecture ",
IEEE Communications Magazine), May 1991, pp.46-55
And so on.

[0005] Such maximum likelihood sequence estimation methods and maximum likelihood sequence detection techniques are rapidly spreading and developing through application to information communication systems and transmission systems, ensuring the reliability of information transmission and maintaining communication quality. Plays a major role in doing so. Further, as disclosed in U.S. Pat. No. 203413, etc., it is widely applied to a high-density information reproducing system,
PRML (Partial-Response Matrix) combining partial response transmission waveform equalization technology and maximum likelihood sequence detection technology
ximum-Likelihood) method is a typical known technology,
Practical application is remarkable.

In such a data decoding technique using the maximum likelihood sequence detection technique, conventionally, a trellis coding / modulation technique or a further extended partial technique has been used in order to further improve noise resistance performance and improve decoding reliability. Active application of response transmission equalization technology has been attempted. As described above, in the maximum likelihood sequence detection, a sequence (maximum likelihood sequence) having the highest probability of being received and reproduced (likelihood) is selected from the context of the reproduction signal sequence, and this is determined as the most likely decoded information (code). It is output as a sequence and is used as a decoding result. For this reason, in the above-mentioned known techniques, various constraint conditions and storage elements are added to a recording code sequence or an information transmission path of a recording / reproducing system by an encoding / modulation technique or an extended partial response, so that the correlation of decoded data can be improved. To increase the Euclidean signal distance (likelihood difference) between reproduced signal sequences for all recorded code sequences, thereby expanding the margin of discrimination of the likelihood difference for noise.

In order to ensure desired decoding reliability in an information recording / reproducing apparatus or an information transmitting apparatus, an error correction coding technique has been actively introduced. High and practical coding and decoding methods have been developed, and this has been introduced into high-density information recording / reproducing systems and high-speed information transmission systems. The reliability of data demodulation has been dramatically improved.

[0008]

Under an information recording / reproducing system in which the recording density is increasing, the quality of the reproduced signal is further deteriorated, and the reliability of the data demodulation is reduced. Therefore, it is required that the conventional data reproducing means using the maximum likelihood sequence detection further improve the noise resistance performance. The application of the trellis coding / modulation technology and the extended partial response transmission equalization technology as described above produces gains due to the expansion of the Euclidean signal distance of the received signal sequence, while various constraints on the transmission code sequence and the transmission signal sequence are applied. The addition of the condition causes an increase in redundancy in the recording information (code) sequence. For this reason, in application to a high-speed / high-density information recording / reproducing system such as a magnetic disk device, the loss of the recording information amount due to the increase in the redundancy of the recording information sequence or the signal transmission path via a narrow-band recording / reproducing system signal transmission path. The reproduced signal is degraded due to a large signal band loss, and is not always an effective method. Further, such a method often requires an oversized and complicated recording code processing circuit and an additional circuit, and a decoder based on maximum likelihood sequence detection requires an exponential function in order to take into account the increased correlation of decoded data. A large circuit size cannot be avoided, and a large amount of hardware resources is required. Also, the maximum likelihood sequence detection technique can provide high reliability by detecting from the context of the reproduced signal sequence, but when a detection error occurs, this causes decoding error propagation due to the sequence error. hand,
Often, burst-like continuous code error propagation occurs. This causes a remarkable loss of the correction capability of the error correction code used together, and also reduces the data demodulation reliability of the entire recording / reproducing system / recording / reproducing apparatus. Also,
Due to this, in order to improve the reliability of data decoding by detecting a maximum likelihood sequence using an error correction code, an extremely strong error correction capability is required. this is,
Encouraging the increase in the complexity and the redundancy of the configuration of the error correction code,
Again, this hinders the realization of an effective and economical means of highly reliable data decoding.

An object of the present invention is to efficiently improve the maximum likelihood decoding error rate (decoding reliability) in data decoding of an information recording / reproducing signal by such a maximum likelihood sequence detection technique,
Another object of the present invention is to provide means for realizing this by using simple and simple means and hardware resources and circuits. In the present invention, by actively and effectively combining the maximum likelihood sequence decoding method and the error correction coding technique, the redundancy of the coding is kept low, and the higher data decoding is achieved while maintaining a simple realization configuration. Provided are an information recording / reproducing method, an information recording / reproducing circuit, and an information recording / reproducing apparatus using the same, which achieve reliability.

[0010]

In order to solve the above-mentioned problems, the present invention actively utilizes the characteristics of the decoded sequence error in the maximum likelihood sequence decoding method, unlike the conventional method. In general, error correction coding can improve the correction capability or simplify the correction process by performing code configuration and decoding after knowing information about a target code error event in advance. . In the present invention, by connecting the error correction encoding / decoding means to the maximum likelihood sequence decoding method, the characteristic of the decoding error event in the maximum likelihood sequence decoding method is utilized, and the error correction encoding with low redundancy is used. And means for achieving highly efficient error correction and high reliability improvement.

The probability of occurrence of a decoding error event in maximum likelihood sequence decoding depends on the likelihood difference between transmission (recording) code sequences corresponding to the Euclidean signal distance between reception (reproduction) signal sequences. A large deviation occurs in the probability of occurrence of the decoding code error pattern of the sequence decoding error. In the present invention, focusing on this,
Since an error event due to a specific decoding code error pattern (code error syndrome) having such a high occurrence frequency dominate the maximum likelihood decoding error probability, a decoding code error pattern having a high occurrence frequency probability among the sequence decoding errors. The present invention provides means for combining an error correction encoding method for performing error correction processing for a limited sequence error having (code error syndrome) with the maximum likelihood sequence decoding. By limiting the decoded code error pattern (code error syndrome) to be corrected in this way, the error correction coding method can be configured with a very simple and low redundancy. In addition, by performing a correction process with priority on a decoding error event having a high occurrence frequency, the error probability in the maximum likelihood decoding can be efficiently improved.

Further, on a decoded code sequence from the maximum likelihood sequence decoding, a sequence decoding error event (burst-like code error event) having the above-described decoding code error pattern (code error syndrome) is generated under random noise conditions. Note that the distribution is random. In other words, it is very rare that sequence-like random error events that govern the decoding error probability are concentrated at short intervals. From this, it can be seen that, within the limited decoding code sequence section (decoding code sequence block), which is significant for improving the maximum likelihood decoding error probability compared to the average occurrence interval of each sequence decoding error event, An error correction encoding method is provided so that the above-described error correction processing is performed only up to the error event. That is, the error correction coding method can be configured to detect and correct only an average random error event according to a specific decoding code error pattern (code error syndrome), which is lower than known techniques. This can be realized with redundancy and a simple configuration. In the present invention, an error code by the error correction coding configured as described above is inserted and added into a data code to be recorded and reproduced, and a decoding code error correction process using the code is effectively performed to improve the maximum likelihood decoding error characteristic. In order to utilize it, by providing an error correction decoder directly connected to the decoding output of the maximum likelihood sequence decoder and implementing it, the most effective maximum likelihood decoding error probability can be obtained with efficient error correction coding redundancy. Have a way to improve.

As described above, in the present invention, the characteristic of the decoded sequence error in the maximum likelihood sequence decoding method is utilized, and a positive combination in which the error correction coding / decoding method and the maximum likelihood sequence decoding are efficiently connected. By means,
An information recording / reproducing method and an information recording / reproducing circuit / information recording / reproducing device realizing method for effectively improving the decoding reliability are provided. Further, the present invention focuses on the fact that a decoding sequence error in the maximum likelihood sequence decoding method as described above occurs depending on a specific recording code sequence / decoding code sequence pattern, or a code for a recording code sequence. The error correction encoding / decoding method is further enhanced by restricting the location of occurrence of the high-frequency decoding code error pattern (code error syndrome) error event on the decoding code sequence by actively using the modulated modulation process. Provide a simple and highly reliable means. Further, by complementarily combining the second error correction coding method and the error correction coding method for the purpose of burst error correction of a random noise factor, the error detection by the error correction coding / decoding method is utilized. By implementing the second error correction encoding / decoding method in which the location of the error code position is limited, the data demodulation reliability of the information recording / reproducing method and the information recording / reproducing circuit / information recording / reproducing apparatus provided by the present invention can be improved. It discloses means for more efficiently and effectively improving the performance.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are closely related to a maximum likelihood sequence decoding / detection method (maximum likelihood sequence estimation method) in the reproduction of digital data and the use of a decoder / decoding device using the same. This principle of maximum likelihood sequence decoding is generally realized widely using a Viterbi algorithm or the like. In order to show an embodiment of the present invention, first, FIG.
An outline of a maximum likelihood sequence decoder based on the Viterbi algorithm will be described with reference to FIGS. Generally, the flow of information processing in an information recording / reproducing system has a similar relationship to that in an information transmission system, and can be described using common processing components and flows.

FIG. 10A shows an outline of a general flow of an information sequence in the information transmission system and the recording / reproducing system. In a transmission or recording process, a transmission code sequence {X (k)} 100 (k is a natural number indicating a time on the sequence), which is transmission or recording information, is obtained after a predetermined constraint condition is added by the encoder 102. , Modulator 103 converts the signal information sequence into an analog or digital signal information sequence that can be transmitted via channel 104,
04 is output. The channel 104 is an information transmission medium including a transmission or recording medium, a transducer, a sensor, and the like. In particular, in an information storage / reproduction device, the modulator 103 transmits a transmission code sequence {X (k)} 1 which is recording information.
An operation of converting and processing 00 into a recording signal sequence and supplying the recording signal sequence to the recording head is performed, and the channel 104 corresponds to a recording and reproducing system including a recording head, an information storage medium, and a reproducing head. Further, the signal in the transmission process is added with additional noise 105, which in the reception or reproduction process makes decoding of the received (decoded input) signal sequence {Y (k)} 107 into the original information uncertain. I do. In the reception or reproduction process, the reception signal processing circuit 106 performs predetermined processing such as signal amplification, filtering, and waveform equalization on the signal output from the channel 104, and then obtains the reception (decoding input).
The decoding from the signal sequence {Y (k)} 107 to the decoded code sequence {Z (k)} 109 is performed via the maximum likelihood sequence decoder 108.
The maximum likelihood sequence decoder 108 estimates the most probable decoded code sequence {Z (k)} 109 corresponding to the transmitted code sequence {X (k)} 100 which is the original transmission or recording information. I do.

The information transmission system 101, which is a pre-processing step from the encoder 102 to the reception signal processing circuit 106 for the maximum likelihood sequence decoder 108, may have various storage elements. For example, the encoder 102 performs decoding error detection / correction using a convolutional code, a trellis code, or the like, or in order to apply some constraint conditions necessary in a transmission process such as a run-length restriction to a transmission code, Redundancy may be intentionally added to the transmission code sequence {X (k)} 100 by a convolution process or a mapping process of input / output codes of the encoder 102 sequentially stored in a finite number of storage elements. In the transmission process from the modulator 103 to the reception signal processing circuit 106, there may be a storage element on the channel due to natural or intentional addition of intersymbol interference or the like. When such a storage element is present in each process of the information transmission system 101, each value of the received signal sequence {Y (k)} 107 becomes the value of the corresponding transmission code sequence {X (k)} 100 Rather than the one-to-one correspondence with
(k)} is determined in correspondence with the state in the storage element depending on the history of 100. The maximum likelihood sequence decoder 108 estimates the transition of the internal state held by the storage element on the information transmission system 101, and stores the memory (redundancy) of the transmission system.
To improve the reliability and quality of the decoding process for noise, and receive and reproduce a more accurate decoded code sequence {Z (k)} 109 for the transmitted code sequence {X (k)} 100. Can be provided by the side.

FIG. 10C shows a received signal sequence {Y (k)} 10 in the transmission channel model shown in FIG.
7 and transmission code sequence {X (k)} 100 and information transmission system 101
It is an example of the Markov state transition diagram model which showed the correspondence relationship with the state in the above storage element. In this state transition diagram example,
The information transmission system 101 has three 1-bit delay storage elements 110a to 110c (D1, D
2, D3) is assumed to be equivalently represented by a model. Then, the value at each time k of the received signal sequence {Y (k)} 107 is
0a to 110c, the history of the code bits at three times immediately before the transmission code sequence {X (k)}, and the addition / subtraction element 111a
To 111c, it is determined by the relationship of the following linear convolution operation.

Y (k) = X (k) + X (k-1) -X (k-2) -X (k-3) The transmission code sequence {X (k)} 100 has a binary code ( X (k) = + 1 or -1) is assumed, and the information transmission system 101 can have a total of eight states depending on the combination of the contents of the 3-bit delay storage element. The information transmission system 101 thus modeled is called a Class 4 Extended Partial Response Class 4 (EPR4) channel, and is often used in an information transmission (recording / reproduction system) channel of a magnetic recording / reproduction system. . This is disclosed in detail in U.S. Patent No. 203413.
Also, for the expression of the above-described convolution operation channel characteristic of the class 4 extended partial response channel, the partial response characteristic polynomial G (D) is often used.
= 1 + D-D2-D3 = (1-D) (1 + D) ² (Dk indicates a k-bit delay operator). In general, magnetic recording / reproducing systems that achieve high-density recording are characterized by a characteristic polynomial G (D) = (1-D) (1 + D) ⁿ (where n is an appropriate natural number) according to various application conditions. Partial response channels are actively applied. Since such a partial response channel allows a DC frequency component and a null frequency characteristic in a transmission required band (1/2 of the maximum transmission / recording frequency), a high-density magnetic recording having a low-frequency cutoff characteristic and a narrow-band frequency characteristic is provided. It is suitable for application to a reproduction system.

In order for the maximum likelihood sequence decoder 108 to perform the maximum likelihood sequence estimation using the storage property (redundancy) of the information transmission system 101, the storage inside the storage element on the information transmission system 101 is required. It is necessary to define and describe the transition of the state. The state transition diagram of FIG. 10C shows that each time one bit of the transmission code sequence {X (k)} is transmitted, each storage element of the class 4 extended partial response channel information transmission system 101 shown in FIG. How the holding state in the state transitions, and what kind of received signal sequence {Y (k)} 107 is received as signal expected value {E (k)}, the transition process in all cases Is expressed. In this figure, eight states Sj (j = 0, 1, 2,..., 7) and 1-bit delay storage elements D1, D2, D3 on the information transmission system 101 (FIG.
a to c), the binary transmission code {X (k)} (X (k) = + 1
Or, the correspondence relationship with the contents of -1) is as shown in the correspondence table in FIG. Arbitrary transmission code sequence {X (k)} 10
When 0 is given, the transmission code sequence and the reception signal expected value sequence are represented by {X (k)} and {E (added to the transition branch arrow sequence) indicated by the unique transition path sequence on this state transition diagram.
(k)}. FIG. 10D shows the temporal transition of the state transition path sequence.
Is a trellis (lattice) diagram obtained by expanding the state transition diagram in the horizontal axis and time axis directions. The transition state corresponding to each time k is denoted by Sj (k) (ie, S0 (k), S1 (k), S2 (k),..., S7 (k)). It shows the state of the code holding in the storage elements D1, D2, D3 determined by the input of the code X (k). At each time k, the state Si
Each branch arrow (branch) indicating a transition from (k-1) to state Sj (k) has a transmission code X (i, j) (in other words, a transition code from state Si to state Sj). , The decoded code when this transition is determined) and when this transition occurs,
The expected value of the received signal E (i, j) output from the transmission channel is X
It is appended in the format (i, j) / E (i, j). (In the time-invariant information transmission system 101, the state transition structure is temporally constant,
It does not change with time k. Therefore, X (i, j) and E (i,
j) is also a constant value that does not change at the time k and is determined depending only on the state Si and the state Sj. Even in time-varying cases, the following discussion can be easily generalized. According to this figure, each time k
, The corresponding relationship between the transmission code {X (k)}, the state transition path and the expected value of the received signal {E (k)} can be clearly expressed. For example, as shown in the example of FIG.
The path sequence 112 represented by five state transition paths (branches) 112a connected in k to (k + 4) is a 5-bit transmission code sequence {+ 1, + 1, -1, + 1, -1}. Information transmission system 101 channel state transition S0 (k-1) → S1 (k) → S3 (k + 1) → S
6 (k + 2) → S5 (k + 3) → S2 (k + 4), and the expected value of the received signal sequence output from the channel at this time is ｛+ 2, + 4,0, -2,0}.

In consideration of the state transition of the information transmission system 101, the maximum likelihood sequence estimation in the maximum likelihood sequence decoder 108 determines the state of the received signal sequence {Y (n)} on which the actually observed noise is superimposed. The amount of error from the received signal expected value {E (n)} in each path on the transition diagram is evaluated, and the received signal sequence {Y (n)}
The transition of the state transition path that minimizes the total error is uniquely determined, and the transmission code sequence for this determined path is determined.
{X (n)} is output as a decoded sequence {Z (n)}. This is nothing but estimation of a signal (code) sequence using a pattern matching method based on the principle of the so-called least square method. The Viterbi algorithm uses a method of sequentially rejecting decoding code sequence candidates that are not suitable for a received signal sequence and performing a pattern matching process on the continuous time series signal by a finite The present invention provides a hardware resource (a storage element for storing time-series signal information) and a means for realizing efficiently in real time within a finite processing delay time. Next, this Viterbi
Means for specifically implementing maximum likelihood sequence decoding (maximum likelihood decoding or Viterbi decoding) by an algorithm will be described. Here, as an example of the target information transmission system 101, the EPR4 channel shown in FIG.
The outline and basic configuration of the Viterbi decoding process will be described with reference to the state transition diagram of the EPR4 transmission line channel based on the binary transmission code sequence in FIG. 10C and the trellis diagram in FIG. In the following specification, the embodiment will be described based on the example of the EPR4 transmission channel using the above-described binary transmission code string. The Viterbi algorithm is described by a state transition model as shown in FIG. It can be applied to any problem that estimates the maximum likelihood event transition that is stochastically most likely for every event, that is, that results in maximum likelihood transition sequence estimation. Also, the description of the following examples
It does not depend on the specific properties or limitations of the EPR4 transmission channel, but also on information transmission channels and models described in various state transition diagrams, having storage elements in various forms described above. Discloses a general embodiment that can be extended and easily applied to target channels and models in a similar manner without any restrictions.

Here, attention is first focused on FIG. 10 (d) which defines the state transition process at one time k on the trellis diagram for the EPR4 channel. Viterbi decoding follows the definition of state transition by this specific trellis diagram, and each time a received (decoded input) signal value Y (k) at time k is input, it corresponds to the state transition path branch (arrow). By evaluating the error with the received signal expected value {E (i, j)}, at each time point, the path branches that transition to each of the states S0 (k) to S7 (k) are narrowed down one by one, Repeat the selection process. Therefore, each state S0 (k-1) to S7 (k-1) selected by repeating the same processing until the previous time (k-1)
Are stored as surviving path sequences P0 (k-1) to P7 (k-1), one for each state. In addition, for each of the surviving path sequences P0 (k-1) to P7 (k-1) reaching each state S0 (k-1) to S7 (k-1), the reception indicated on each path sequence is performed. Cumulative errors (path metrics) M0 (k-1) to M7 (k-1) between the expected signal sequence {E (k)} and the actual received signal sequence {Y (k)} are evaluated. , As a metric (likelihood) indicating the likelihood of each of the surviving path sequences. Each state S0 (k-1) to this time (k-1)
The contents of the surviving path sequences P0 (k-1) to P7 (k-1) and path metrics M0 (k-1) to M7 (k-1) for S7 (k-1) are
By the processing described below at k, new surviving path sequences P0 (k) to P7 (k) and path metrics M0 (k) to M7 (k)
And this is repeated as a recursive process every hour. As shown in FIG. 10E, when focusing on each state on the trellis diagram, the state Sn (k) at time k
As the transition process to (n = 0,1, ～, 7), state Si (k-1) and state
If there is a possibility of transition from any one of Sj (k-1) (i, j = 0, 1, to 7,), the specific processing procedure is summarized as follows.

(1) For the received signal value Y (k) input at time k, the expected value of the received signal corresponding to each transition path from the state Si (k-1) and the state Sj (k-1) Using E (i, n) and E (j, n), square error values (branch metrics) BM (i, n) (k) and BM (j, n) (k ) Is calculated as follows.

Transition branch metric from state Si (k-1) to Sn (k): BM (i, n) (k) = [Y (k) -E (i, n)] ^ ² state Sj (k transition branch from -1) to Sn (k) metric: BM (j, n) ( k) = [Y (k) -E (j, n)] ^ 2 metric by the square error, the received signal sequence {Y It is known that an optimal likelihood metric for maximum likelihood sequence estimation when a noise sequence superimposed on (k)} is independent white Gaussian noise is given. Another error evaluation value such as an absolute value error can be used depending on the decoding implementation conditions.

(2) From each of the states Si (k-1) and Sj (k-1),
Cumulative errors (path metrics) PM (i, n) (k) and PM (j, n) for likelihood comparison for the path sequence transitioning to state Sn (k)
(k) is calculated. Therefore, the surviving paths Pi (k-1) and Pj (k-1) to the states Si (k-1) and Sj (k-1) evaluated by the processing up to the previous time (k-1) For each of the corresponding path sequence accumulated errors (path metrics) Mi (k-1) and Mj (k-1),
State transition branch metric BM calculated in (1)
(i, n) (k) and BM (j, n) (k) are respectively newly added to perform the following addition operation.

Path metric from state Si (k-1) to Sn (k): PM (i, n) (k) = Mi (k-1) + BM (i, n) (k) State Sj (k -1) to the path metric from Sn (k): PM (j, n) (k) = Mj (k-1) + BM (j, n) (k) Further, the path metric PM for these two path transitions
The values of (i, n) (k) and PM (j, n) (k) are compared in magnitude and a likelihood comparison is performed. The path metric, which is the accumulated error of each path sequence, causes the smaller transition path to reach state Sn (k) at time k.
The path sequence is selected as a more reliable and highly likely path sequence, and the other is rejected. Further, the compared path metric PM (i, n) (k)
And PM (j, n) (k), using the path metric value on the selected path side, Mn (k) as a new path metric value of the surviving path sequence that transits to state Sn (k). Update the contents of

The surviving path metric leading to the state Sn (k): Mn (k) = Min [PM (i, n) (k), PM (j, n) (k)] Calculation to Select (3) Update the surviving path sequence history Pn (k) for state Sn (k) at time k. In Pn (k), connection information of (D + 1) transition states on the surviving path that goes back from the current time k to the finite time D earlier is stored in time order. For example, Pn (k) =
Processing up to time k by referring to the stored contents {Sn (k), Si (k-1), Sj (k-2), ~, Sl (k-D + 1), Sm (kD)} The state transition on the surviving path sequence leading to the state Sn (k), selected in, is Sm (kD) → Sl (k−D + 1) → Sj (k−2) → Si (k−1) →
It is shown that they are connected and change in the order of Sn (k). According to (2), whether the surviving transition path to the state Sn (k) at the time k is a transition path from Si (k-1) or a transition path from Sj (k-1) Is selected and confirmed, a new surviving path sequence history Pn (k) to the state Sn (k) determined by the selection processing is the state Si (k-1) up to the previous time (k-1). Of the surviving path sequence histories Pi (k-1) and Pj (k-1) for Sj (k-1), the surviving path sequence history of the selected path side state is updated as follows. .

History of surviving path sequence leading to state Sn (k): Pn (k) = {Sn (k), Pi (k-1)} (when selecting a transition path from Si (k-1)) = { Sn (k), Pj (k-1)} (when a transition path is selected from Sj (k-1))
Select (k-1) or Pj (k-1), and move this temporal storage location to the past one time at a time,
After extracting the ((D + 2) th element) as a result of Viterbi decoding, the result of adding a new transition state Sn (k) to the storage location of the latest time is transcribed as the storage content of Pn (k). Means operation. In the prior art, this is generally configured by a storage circuit such as a shift register that sequentially shifts the storage content at each time (shift register exchange method), and a configuration method using various storage circuits is disclosed. Have been. Further, in many cases, instead of storing the information (state number) of the selected transition state itself, the transmission code for the path branch to the selected transition state is stored as the contents of the path sequence history Pk (n). Is stored. For example, when the transition path from the state Si (k-1) is selected as the surviving path for the state Sn (k) at the time k, the recorded contents in the surviving path history for this state are the states Si (k The value of the transmission code X (i, n) corresponding to the path branch from -1) to Sn (k) can be used. Thereby, when the stored path history information is referred to, the transmission code sequence {X (n)} indicated by the surviving path can be immediately obtained as a decoded code result. Further, in the description of the update processing of the surviving path sequence history information in the above (3), the storage information (path history information for the latest time) in the surviving path sequence history Pn (k) reaching the state Sn (k) is: , And is constant in the state Sn (k) regardless of the state of the path selection from the time k-1. Therefore, in practice, the path information itself does not need to be physically stored, and only the surviving path sequence history information before time k-1 connected to this state Sn (k) is physically stored in the storage circuit. It only has to be recorded. The path history storage information Sn (k) for the time k can be represented by the fact (storage position information) in which this path history information is stored as a surviving path sequence history Pn (k) reaching the state Sn (k), In the processing at the next time k + 1, when referring to the storage contents of the surviving path sequence history Pn (k), the path history storage information for this time k
What is necessary is just to supplement and refer to Sn (k). As described above, even when the value of the transmission code X (i, n) corresponding to the selected path branch is stored as the recorded content in the surviving path history,
This is the same, and each surviving path sequence history Pn
In (k), history information from time k fixed by being a path transition to state Sn (k) to a time before a predetermined time (in the case of EPR4 channel, 3-bit transmission from time k to time k-2) Code history) is the surviving path sequence history
By omitting the information by indicating the storage position information itself that it is stored as Pn (k), and supplementing this information at the time of reference, the hardware amount of the storage device can be saved.

The above-described series of Viterbi decoding processes (1), (2), and (3) are performed every time the received signal value Y (k) at each time is input.
It is processed repeatedly. Specific components for implementing this are shown in FIG. The calculation of the branch metrics BM (i, n) (k) and BM (j, n) (k) in (1) is performed by the square error calculation circuit 201. State Si (k-1) and Sj (k-1)
Path metrics Mi (k-1) and Mj of the surviving path for
(k-1) is stored in the metric storage circuits 202a and 202b, and the path metrics PM (i, n) (k) and PM (j, n) in (2) in the metric accumulation circuit 203.
The calculation of (k) and the comparison operation of these path metric values are performed by the comparator 204. The comparison result is output to the selection signal 205, and the metric selection circuit 206
According to 5, the path metric PM (i, n) (k) or PM (j, n)
(k) is selected and used to update and store the contents of the metric storage circuit 202c that holds the surviving path metric Mn (k) to the state Sn (k). On the other hand, state Si (k-1)
And the surviving path histories Pi (k-1) and Pj (k
-1) is stored in the path history storage circuits 207a and 207b, and the process of updating the content of the surviving path history Pn (k) to the state Sn (k) in (3) is performed by the path designated by the selection signal 205. Either of the contents of the history storage circuit 207a or 207b is selected and referred to by the path history selection circuit 208, and the storage position of this content is shifted by one time, and Pn
(k) is newly updated and stored as the contents of the path history storage circuit 207c. At this time, the path history storage circuit 20
The surviving path history information selected from the storage location at the end of 7a or 207b is the decoding result (decoding code sequence Z (k) 10
9).

In the actual Viterbi decoding, the above processes (1) to (3) for the received signal Y (k) at each time are performed for all states of the trellis diagram for which the maximum likelihood sequence is to be estimated. Each needs to be done independently. Therefore, in the actual configuration of the Viterbi decoder, the state shown in FIG.
Implementing components of the processing for Sn (k) are provided in parallel for the number of states in the same configuration. For example, for the trellis diagram of FIG. 10D, as shown in the configuration of the maximum likelihood decoder based on the Viterbi algorithm of FIG. 11B, eight states S0 (k) to S7 (k) are used. Figure 11 assigned to each
The constituent elements of (a) are provided in parallel with a total of eight systems.
At this time, metric storage circuits 202a to 202h for storing surviving path metrics M0 (k) to M7 (k), and path history storage circuits 207a to 207h for storing surviving path sequence histories P0 (k) to P7 (k). Are the states S0 (k) to S7 (k)
, Respectively, and these reference destinations are connected to a plurality of locations according to the next stage connection state on the trellis diagram of each state. For example, state Si (k) and state Sj
If there is a path connection relationship of the trellis diagram between (k + 1) (i, j = 0, 1, to 7), the reference destination of the metric storage circuit 202 assigned to the state Si (k) Is the other input of the metric accumulator 203 assigned to the state Sj (k) that performs addition with the branch metric BM (i, j) (k). One of the reference destinations of the path history storage circuit 207 assigned to is the input of the path history selection circuit 208 assigned to the state Sj (k). Also, since the value of the expected value E (i, j) of the received signal on the actual trellis diagram is often common to some path branches, a square error calculation circuit that performs an operation on this branch metric is used. 201 is also commonly used, and a configuration input to the corresponding plurality of metric accumulators 203 is often used in practice. As described above, as summarized in FIG. 11B, the Viterbi decoder configuration includes a branch metric operation unit (BM) that performs processing (1) by receiving a received signal Y (k).
U) 200a, a path metric comparison / selection unit (ACS calculation unit) 200 that executes (2) processing using the branch metric output and selects a surviving path to each state.
b. Further, in response to the selection output, the surviving path history by the process (3) is stored and updated, and the result is roughly classified into a path memory unit (PMU) 200c for narrowing down and determining the decoding result. The above is an implementation method and a configuration method of the maximum likelihood sequence decoding process using the Viterbi algorithm.

Next, in order to clarify the principle of the embodiment of the present invention, FIG. 12 shows an example of a state transition on a trellis diagram on the EPR4 channel in FIG. 10 (d). A process from selection of a surviving path to determination of a decoding result in a conventional Viterbi decoding process will be described. By the above-described conventional Viterbi decoding implementation method and configuration method, a state transition path (each time / state) on the trellis diagram using the received (decoded input) signal sequence {Y (k)} 107 at each time. The path branches 112a are always selected one by one. In this way, by repeatedly selecting the surviving path sequence 113, the path sequences surviving at each time are further narrowed down. For example, as shown by the history of the surviving path sequence 113 in FIG. 12, the eight surviving path sequences for each state selected at time k for each state are gradually rejected by the subsequent path selection, and eventually are rejected. At the end of the selection process at time (k + 10), the connected surviving path sequence (thick line arrow sequence) converges to one. At this time, the surviving converged survivors from time (k-1) to (k + 8) The path sequence is determined as the determined maximum likelihood path sequence 114, whereby the decoded code Z (k) at time k is obtained.
Is determined by referring to the transmission code X (i, j) assigned to the only state transition path (path branch) 112b that survives on the determined maximum likelihood path sequence 114. This operation of narrowing down the surviving path sequence (path rejection) is performed by selecting the path history Pj (k-1) or Pj selected in the above-described decoding processing (3).
This is nothing more than an operation of moving the content of j (k-1) to the past one time at a time and transferring it as the new Pk (n) storage content. Then, in FIG. 11B, a path history storage circuit 207a that stores the surviving path sequence histories P0 (k) to P7 (k).
If 207h to 207h have a sufficient storage length, by repeatedly selecting and transferring the path history storage circuit, the storage positions at the end of each storage circuit 207a to 207h (the path branch selection history at the earliest time). The contents of
All the contents converge and coincide with the same storage contents, and any of the contents can be referred to as a decoding result. As mentioned above,
The operation of determining the maximum likelihood path in the maximum likelihood sequence decoding is performed by repeatedly rejecting and selecting a surviving path candidate that reaches each state on the determined maximum likelihood path sequence 114 at each time. The final maximum likelihood path sequence 114 that finally converges and is obtained as a decoding result has a higher likelihood in the state transition path selection at all times on this path sequence, and remains only without being rejected. It is a surviving path sequence.

According to the present invention, in order to efficiently improve the decoding error event in the conventional maximum likelihood sequence decoding process described above, simplify the operation, and provide higher reliability, error detection and correction coding is performed. An object of the present invention is to provide means for realizing an information recording / reproducing method and an information recording / reproducing apparatus by a decoding processing method that effectively utilizes technology. FIG.
The example of the second trellis transition diagram in FIG.
FIG. 4 shows an example of a surviving path sequence 113 in a hexadecimal code transmission sequence EPR4 transmission channel, for explaining the relationship between a decoding error path sequence caused by uncertainty such as noise and a normal path sequence in a maximum likelihood decoding process. belongs to. In this figure, the state transition sequence S6 (k-1) → S5 (k) →
S3 (k + 1) → S6 (k + 2) → S4 (k + 3) → S0 (k + 4) → S0 (k + 5) → S1 (k +
6) → A normal path sequence 115 represented by a path transition of S3 (k + 7)
, The determined maximum likelihood path sequence 114 including the decoding error event (decoding error sequence) is changed to the state transition sequence S6 (k-1) → S5 (k) → S3
(k + 1) → S6 (k + 2) → S5 (k + 3) → S2 (k + 4) → S4 (k + 5) → S1 (k + 6)
→ When determined at the path transition of S3 (k + 7), this decoding error event (decoding error sequence)
This is caused by the occurrence of the error path selection 117 for the two surviving path branch candidates flowing into the state S1 (k + 6) at the time (k + 6). That is, the normal path sequence 11
7 between the two surviving path branch candidates that branch off from state S6 (k + 2) at time (k + 2) and flow into state S1 (k + 6) at time (k + 6) By making an incorrect selection, the partial path sequence S6 (k + 2) → S4 (k + 3) → S0 (k) on the normal path sequence 115 which is one of the surviving path branch candidates
+4) → S0 (k + 5) → S1 (k + 6) (thick dotted arrow path sequence) is the other path sequence S6 (k + 2) → S of the surviving path branch candidate.
5 (k + 3) → S2 (k + 4) → S4 (k + 5) → S1 (k + 6), and a decoding error occurs as a code sequence error. As processing in the decoding circuit, time (k
+6), the surviving path metrics PM (0,1) (k + 6) and PM (4,1) in the above-described decoding process (2) for the state S1 (k + 6).
Judgment of magnitude of (k + 6): M1 (k) = Min [PM (0,1) (k + 6), PM (4,1) (k + 6)] ) (k + 6) instead of PM (4,1)
(k + 6) is selected. As a result, the state transition S0 (k + 5) → S1
Instead of the surviving path sequence on the (k + 6) side, state transition S4 (k + 6
5) → The surviving path sequence on the side of S1 (k + 6) is selected and determined,
In the decoding process (3) for updating and storing the surviving path sequence history, a path history replacement process of P1 (k + 6) = {S1 (k + 6), P4 (k + 5)} is executed, whereby An error occurs. As a result, the time (k + 5) state S0 (k + 5)
The contents of the surviving path sequence history P0 (k + 5) having the normal path sequence 115 are discarded, and the contents of the surviving path sequence history P4 (k + 5) having the error path sequence 116 are selected as the surviving path sequences. Remain in the updated path history storage circuit. In a noise situation, the selection error of the surviving path branch candidate does not occur with a uniform probability frequency in each state on the deterministic maximum likelihood path sequence 114, but the two surviving path sequences flowing into each state. As the cumulative sum of the differences between the expected values of the received signals of the candidates (the distance between signal sequences or the path metric difference) is smaller, the possibility and frequency of an error in the comparison operation processing in the maximum likelihood decoding processing (2) are increased. That is, in the comparison / selection of the path metric likelihood between two surviving path sequences, the smaller the expected value of the discrimination difference (likelihood difference) between the path metrics and the narrower the discrimination margin of the comparison judgment with respect to noise, the smaller the above randomness becomes. A decoding error event due to noise is more likely to occur. FIG.
The expected values of the received signal sequences of the normal path sequence 115 and the error path sequence 116 in (a) are ｛−4, −2, and −4 at a 4-bit time from time (k + 3) to time (k * 6), respectively. 0, + 2｝ and ｛-
Since a discrimination difference of 2,0, -2,0｝ occurs, the cumulative sum of the square errors (distance between signal sequences) is 16. The cumulative sum 16 of the square errors is equal to the minimum cumulative square error (minimum square Euclidean distance, minimum free distance) guaranteed between all the received signal sequences on the binary code transmission sequence EPR4 channel. In addition, the fact that the decoding reliability (decoding error rate) of the transmission channel under noise is mainly determined by an error event between transmission code sequences having such a least square Euclidean distance is determined by the transmission / transmission error. This is a well-known fact in communication theory. In the example of FIG. 13A, due to the error in comparison / selection of the path metric likelihood in the state S1 (k + 6), (k + 3) to (k + 3) in the surviving path history P1 (k + 6) The 4-bit contents up to 6) are replaced with the contents of the error path sequence 116, and an error sequence event occurs.

From the error event generation process described above, the nature of the decoding error event in maximum likelihood sequence decoding can be summarized as follows.

(A) Since a decoding error event in maximum likelihood sequence decoding is generated by replacement of an error path sequence, a sequence-like error event that can simultaneously include a plurality of bits of code errors occurs. Accordingly, in a single decoding error event, a burst-like code error (local error propagation) in which a plurality of code errors partially localize and concentrate on the decoded code sequence.
Frequently occurs. For this reason, the error code in the random decoding error under the noise condition is not a single code error randomly distributed on the decoded code sequence, but a burst error event in which a plurality of error codes are localized (that is, a partial code sequence state). Error events) occur randomly.

(B) A pattern of a code error generated in a sequence or in a burst, that is, an error code pattern sequence (code error syndrome) is a distance between a received signal sequence of an error path sequence corresponding thereto and a normal path sequence. The occurrence probability differs depending on the Euclidean distance). Therefore,
In the maximum likelihood sequence decoding, the frequency of occurrence of an error event is biased toward a specific error code pattern sequence (code error syndrome), and the error event frequently occurs between code sequences having a least square Euclidean distance between received signal sequences. I do.

The present invention provides a method for efficiently improving a code error due to the two basic properties of the decoding error event in the maximum likelihood sequence decoding by using an error code detection and correction technique. Conventionally, in error code detection and correction technology for maximum likelihood sequence decoding, the occurrence of a burst-like error event (error propagation) due to (a) causes a reduction in error code detection and correction capability, and these are completely detected with a predetermined probability. To correct, a complex error code detection and correction coding method having a relatively high correction capability was used. Also,
A bursty long continuous error event is divided into random single error events on multiple code sequences by randomization techniques such as code sequence interleaving, and each is detected and corrected by independent error code detection and correction coding. Thus, practical error detection and correction has been realized by using relatively simple error code detection and correction coding methods in parallel.
In the present invention, the nature of the occurrence of a burst-like decoding error event as shown in (a) is not canceled as in the prior art, but is regarded as extremely high correlation information on the error code occurrence position and is actively utilized. Thus, more efficient decoding error detection and correction than in the past can be realized. In general, error correction coding is
By knowing the information about the target code error event in advance and performing the code configuration and decoding, it is possible to improve the correction capability, reduce the redundancy, or simplify the correction process. In the present invention, by connecting the error correction encoding / decoding means to the maximum likelihood decoding method, the characteristics of the decoding error event in the maximum likelihood decoding method are positively utilized for error correction encoding / decoding, and the low redundancy , The decoding reliability is efficiently improved.

For this reason, attention is paid to each error code pattern sequence (code error syndrome) from among burst-like and sequence-like decoding error events. The error code pattern sequences (code error syndromes) are ordered according to the frequency of occurrence determined depending on the magnitude of the distance between signal sequences, from the one with the highest occurrence frequency, and the error code pattern sequence (code Error syndrome). In this way, focusing only on the error events of the high occurrence frequency error code pattern sequence (code error syndrome), priority is given to the high occurrence frequency error code pattern sequence (code error syndrome) events,
By performing error code detection and correction coding to detect and correct this, the desired decoding reliability can be efficiently improved using simple and low redundancy error code detection and correction coding, or An error code detection / correction coding technique with higher decoding reliability can be realized. As a result, a high-density and high-reliability information recording / reproducing method and information recording / reproducing apparatus can be realized.

As described above, in practicing the present invention,
An error code pattern sequence (code error syndrome) of a specific error event having a high frequency of occurrence in the maximum likelihood sequence decoding is set in advance and limited, and the error events of this error code pattern sequence (code error syndrome) are reduced to a predetermined number. Encoding and decoding of an error code that can be detected and corrected is performed on the transmission code sequence and the decoded code sequence. The error code pattern sequence (code error syndrome) having a high frequency of occurrence is obtained by replacing the contents of the normal path sequence and the error path sequence due to the path selection error in the surviving path history, as described above. Can be easily estimated by utilizing the fact that the path sequence selection error in the above occurs with the occurrence probability depending on the signal sequence distance (Euclidean distance) between the received signal sequence of the normal path sequence and the error path sequence. That is, if the constraint structure added to the transmission code sequence and the target trellis transition diagram of the maximum likelihood sequence decoding process by the modulation process or intentional coding process, the distance structure between the reception signal sequences is defined in advance, In many cases, from the least square Euclidean distance, sequentially focus on a limited signal sequence pair having a large square Euclidean distance, or from the least square Euclidean distance, a limited signal sequence having a small square Euclidean distance equivalent thereto. By paying attention to the pair, it is possible to limit and predict an error code pattern sequence (code error syndrome) frequently occurring due to a selection error between the sequences. Then, by sequentially improving the error events by using an error detection / correction coding technique from the events of the error code pattern sequence (code error syndrome) having a high frequency of occurrence, a suboptimally good decoding error rate (reliability) is improved. Can get better. As shown in the example of FIG. 10 (c), under the fact that maximum likelihood sequence decoding is applied and designed, the target information transmission / recording / reproduction system channel always has a specific Markov state transition. It is uniquely defined by the figure and is modeled. Therefore, as described above, by focusing on the Euclidean distance structure between received signal sequences, it is possible to limit and predict a high-frequency error code pattern sequence (code error syndrome) by a search-and-analytical method. . The estimation of the error code pattern sequence (code error syndrome) based on the squared Euclidean distance between the received signal sequences is most effective when the noise factor on the received signal sequence is regarded as additive white Gaussian noise. In the case of noise factors that follow other characteristics, such as colored noise, the same kind of estimation method is extended to evaluate the stochastic fluctuation of the distance structure between signal sequences on the specified Markov state transition diagram. It is possible to limit and predict an error code pattern sequence (code error syndrome) occurring at a high frequency. This is a method described in a known transmission / communication theory, and is beyond the scope of the present invention, and will not be described here. Further, in actual maximum likelihood sequence decoding, the bias of the frequency of occurrence of error events with respect to a specific error code pattern sequence (code error syndrome) is often extremely remarkable. Is performed on a trial basis by an actual or simulated method, and the decoded code sequence is compared with a regular transmission code sequence, so that a high frequency error code pattern sequence (code error syndrome) can be obtained from the actual statistical frequency. Determining is also effective. At this time, the separation and distinction of individual code error events on the decoded code sequence is based on the fact that the number of normal codes between adjacent error codes is equal to the channel memory length integer n (EPR4
In the case of a channel, the determination is made based on whether or not the number of bits is equal to or more than n = 3), that is, is equal to or more than the number of bits defining the state of the Markov state transition diagram of the target channel. If there are more than two normal codes between the two error codes, the two error codes are due to different path error events; otherwise, the same sequence error (path error event ). By using the actual statistical information of the error code pattern sequence (code error syndrome) obtained in this way, the optimal error code detection and correction means is designed in advance, and the dynamic and variable error code detection and correction means is designed. The decoding reliability can be optimally improved and maintained by changing the structure of, or selecting the optimum one from among a plurality of error code detection and correction means.

An example of a high-frequency error code pattern sequence (code error syndrome) determined for the error code detection and correction means by the above method will be described below. In the surviving path sequence 113 in FIG. 13A, the normal path sequence 115 and the error path sequence 116 are on the path sequence and on the received (decoded input) signal sequence 107, from time (k + 3) to time (k + 6). Take different sequences between the four bit times. As described above, the two sequence pairs are signal sequence pairs having the least square Euclidean distance on the trellis transition diagram, and the error events between the sequences are the most frequent decoding error events, most often This is one of the decoding error code pattern sequences (code error syndromes) that occur. That is, on the transmission code sequence or the decoding code sequence 109, the normal path sequence 115 and the error path sequence 116 have code sequences that are inverted only by one bit at the time (k + 3) and are different from each other. The difference sequence between the code sequences is decoded by the error pattern sequence 11
When an error event, that is, an error code pattern sequence (error syndrome) is described as being defined as 9, it can be expressed as a 1-bit decoding error pattern 121a. here,
In the decoded error pattern sequence 119, 0 indicates no code error, +1 indicates a bit position where the code "1" is erroneously changed to "0", and -1 indicates a bit position where the code "0" is erroneously changed to "1". That is, on the binary code sequence, the non-zero position on the decoded error pattern sequence has the meaning of the error occurrence position, and is a pointer indicating the code position of the inverted bit error. It is also shown that code positions in which the non-zero polarities have the same sign cause code errors in the same direction, and code positions in different codes cause code errors in the opposite directions. In such a representation of the decoded error pattern sequence 119, at the position of the indicated error code, a normal code for the error code, or
The difference between the error codes can be distinguished from each other. In the surviving path sequence 113, at the same time, after branching into two paths indicating different transmission (decoding) codes, the same state is passed through different 3-bit length path sequences indicating the same transmission (decoding) code sequence. Merge with S1 (k + 6). This is the past 3
This is obvious from the definition of the trellis diagram in which the channel state is determined by the bit code history, and this is one form of the path sequence pair having the least square Euclidean distance. As described above, in the EPR4 transmission channel using the binary transmission code, the replacement of the 4-bit error path sequence occurs at a high frequency from any trellis diagram state, and the bit time of the path selection error event occurrence ( In the example of the error path sequence in FIG. 13A, the error path selection detection position 122 at time (k + 6))
The decoding position relatively 3 bits before (FIG. 13)
In the error path sequence example of (a), the error event of the error syndrome in which the normal code at time (k + 3) causes a 1-bit inversion error, that is, the 1-bit decoding error pattern 12
It can be predicted in advance that the error event having 1a is one of the frequently occurring error pattern sequences. In general, in the decoding error pattern, each code at an error bit position can take both plus and minus codes while maintaining the same order of decoding between the codes, so that each code as an error pattern sequence (code error syndrome) Can be considered. In this specification, one of the descriptions will be representative of both.

FIG. 13B shows another example of the relationship between the normal path sequence 115 and the error path sequence 116 in the detection of the maximum likelihood sequence on the EPR4 transmission channel using the same binary transmission code as in FIG. 13A. This is a specific example.
The occurrence of the error path sequence 116 in this specific example is due to the occurrence of the error path selection 117 in the surviving path selection processing for the state S3 (k + 5) at the time (k + 5) on the determined maximum likelihood path sequence 114. It occurs as a 6-bit sequence error from time k to time (k + 5). The normal path sequence 115 and the error path sequence 116 on the received (decoded input) signal sequence 107 have a least square Euclidean distance 16 and, like the error event in FIG. Can be regarded as one. When the relationship between the normal path sequence 115 and the error path sequence 116 is compared on the decoded code sequence 109, the decoded error pattern sequence 119 has the error path selection detection position at the time (k + 5) which is the bit time of the occurrence of the error event. With reference to 122,
Similarly to FIG. 13 (a), a continuous 3-bit code position (time k to (k + 2)
2)) can be regarded as a decoding error event of an error syndrome in which the normal code causes an inversion error, and such a 3-bit decoding error pattern 121b can be predicted in advance as a frequent decoding error event of the channel. .

The decoding error event of the one-bit decoding error pattern 121a shown in FIG. 13A occurs from any state on the target trellis transition diagram and does not depend on the transmission code sequence. This is one of the decoding error pattern sequences (code error syndromes) that have a high probability of occurrence and are determined only by the structure. On the other hand, the binary transmission code E
In the PR4 transmission system channel, there is a signal sequence pair having a least square Euclidean distance depending on a specific transmission code sequence. FIG. 13B shows a 3-bit decoding error pattern 121b as this example. In such a code error pattern, a transmission code sequence of "... 01010 ..." or "... 10101 ..." in which code bits on the transmission code sequence are alternately continuously inverted by 3 bits or more is transmitted through the transmission channel. Is the case. When either one of these two transmission (reception) code sequences is transmitted, in the code string portion where the transmission code bits are alternately inverted, n bits before the last bit position (n is an integer of 2 or more) A decoding error pattern in which all consecutive code bits are inverted may occur at a high frequency. For example, when a transmission code sequence "... 0 01000 000 ..." is transmitted, "010"
The 3-bit code string portion of the above matches the above code pattern,
The respective bits of the code string are inverted. "... 0 101 0
00... Becomes a signal sequence pair having the minimum Euclidean distance.
-1 +1 -1 0 0 0... ”, And an error pattern sequence of a code error syndrome (3
This results in a bit decoding error pattern 121b). Also, when the transmission code sequence “... 0 0101 000...” Is transmitted, the 5-bit code string portion of “01010” matches the above code pattern, and the last 3 bits (n =
2), 4 bits (when n = 3), and 5 bits (when n = 4) are inverted. "... 001 101 0
00 ... "," ... 00 0101 000 ... "," ... 0 101
01 000 ... "becomes three series signal sequence pairs taking the minimum Euclidean distance, both, the highest decoded error code sequence of probability. That is, decoding error pattern sequence (bit error syndrome) is" ... 000 -1 +1-
1 000 ... "," ... 00 +1 -1 +1 -1 000 ... "," ...
0 −1 +1 −1 +1 −1000... ”, And a code error pattern (3 to 5 bit code error pattern sequence) of a code error syndrome that causes a 3 to 5 bit continuous alternating inversion error.
Becomes As described above, when the transmitted transmission code string has a continuous code inversion pattern, an error pattern event in which the subsequence becomes a continuous inversion bit error is also caused by the 1-bit decoding error pattern 121a due to the minimum Euclidean distance.
It can be a decoded code error pattern sequence (code error syndrome) having a high probability of occurrence as well as. Also, conversely,
Assuming a decoded code error pattern sequence (code error syndrome) composed of error code positions of a plurality of bits, the location of an error event having this decoded code error pattern sequence (code error syndrome) is a transmission code sequence or
The reference is limited by referring to the decoded code sequence decoded. That is, in the decoded code error pattern sequence (code error syndrome), the polarity code of the non-zero position indicating the code error position is the direction of the code error in the error event at each code position (whether the code "1" is incorrectly changed to "0"). ,
Since the relative relationship between the code “0” and the error “1” is defined, it is determined whether an error event of the decoded code error pattern sequence (code error syndrome) can occur. Is determined by referring to the transmission code sequence or the decoded code sequence decoded. For example, the above-mentioned error event of the code error syndrome "... 0 -1 +1 -1 0..." That causes a continuous alternate inversion error of 3 bits is caused by the fact that code errors of 3 consecutive bits are always generated in different directions at adjacent bit positions. Since it indicates an error, it is obvious that the error occurs only in the partial code string of "... 010 ..." or "... 101 ..." on the transmission code sequence. On the other hand, even on the decoded code sequence, the code error syndrome "... 0 -1
+ 1-1 0… ”is an error event of“… 010 … ”or“…
101 ... Can also be determined by referring to only the decoded code sequence. Using this fact, a specific decoded code error pattern sequence (code error When encoding for error code detection and correction is performed on a transmission code sequence for an error event of (syndrome), or when error code detection and correction processing using this error code detection and correction code is performed on a decoded code sequence,
By referring to the code sequence pattern of the transmission code sequence or the decoding code sequence to be processed, it is possible to limit the range of the transmission / decoding code sequence to be subjected to the encoding or correction processing. This can be used to simplify coding and correction processing and improve correction efficiency and performance. Further, as described above, when the code error syndrome has an n-bit non-zero code position, the direction of the code error at each code position is defined, and the code position on the transmission code sequence where the error event can occur is defined as Due to the limitation, the probability of occurrence on a random code sequence is reduced to about 1/2 ^(n-1) for a 1-bit code error.
Further, when the transmission code sequence has a predetermined constraint condition by the modulation process, a more accurate occurrence probability is predicted by taking this into account. In consideration of such an appearance frequency probability of a specific transmission code sequence pattern, the error event occurrence probability of each decoded code error pattern sequence (code error syndrome) is more accurately predicted, and the most frequent decoding code error It is possible to set a pattern sequence (code error syndrome).

As described above, the setting of a high-frequency decoding error pattern sequence (code error syndrome) differs depending on the target transmission channel characteristics and the constraint conditions added to the transmission code sequence due to coding / modulation processing. . A binary transmission code sequence E used for the above-described magnetic recording / reproducing system channel or the like.
In general, including the PR4 channel, the partial response characteristic polynomial G (D) = (1-D) (1 + D) F (D) (where F (D) is an arbitrary characteristic polynomial) is often used in many practical applications. It is a form of a transmission channel provided. In the transmission channel of this form, the DC component (continuous sequence of the same code) and the highest recording frequency of the frequency components of the binary transmission code sequence to be transmitted, that is, half the frequency component of the code transmission frequency component (continuous inversion) Code sequence), and has a characteristic on transmission characteristics showing a zero response to the received signal sequence as shown by the example of the EPR4 transmission channel. The most frequent decoding error pattern sequence that defines the least square Euclidean distance is a point of a continuous inversion code error sequence of 1 bit or more, and a portion of the continuous inversion code sequence on the transmission code sequence transmitted through the channel. The common feature is that this continuous inversion code error occurs with the most frequent probability. Therefore, by applying error code detection / correction coding means capable of correcting a continuous inversion code error sequence (adjacent error codes are mutually different codes) up to a predetermined length to the transmission code sequence, the present invention provides Effectively implemented for channels. On the other hand, by restricting the maximum code length of the continuous inversion code sequence on the transmission code sequence to a certain code length or less by adding a constraint condition such as a run-length restriction by coded modulation processing, the most frequent code length exceeding this code length is set. Can be avoided. Therefore, by performing a coding modulation process for limiting the maximum length of the continuous inverted code sequence in advance on the transmission code sequence, the upper limit of the generated code length of the continuous inverted code error sequence is defined, By applying error code detection and correction coding for detecting and correcting a continuous inversion code error sequence having a length equal to or less than the maximum length of the limited continuous inversion code sequence, a high-frequency error event can be further reduced. The detection and correction can be completely and effectively performed, and the configuration of the error code detection and correction code can be simplified. As described above, occurrence of some of the decoded error pattern sequence (code error syndrome) events among a plurality of predicted / limited error events of the high occurrence frequency decoded error pattern sequence (code error syndrome) is determined by coding modulation The processing is used to eliminate or prohibit the appearance of a specific transmission code sequence pattern in which this decoding error pattern sequence (code error syndrome) can occur in the transmission code sequence, thereby avoiding it. The occurrence of a sequence (code error syndrome) event can be avoided by performing error code detection / correction coding on the specific decoded error pattern sequence (code error syndrome) on the transmission code sequence and detecting and correcting this. The present invention can be implemented more effectively by using the coded modulation processing and the error code detection and correction processing complementarily. In this case, as described above, the error event of the decoding error pattern sequence (code error syndrome) having a relatively long code length is avoided by the coded modulation processing, and the error of the decoding error pattern sequence (code error syndrome) having a relatively short code length is avoided. It is appropriate that the event is corrected by error detection and correction coding, and for the coded modulation process, limiting the appearance of a relatively long specific transmission code sequence pattern relaxes code restrictions and constraints. It is desirable in doing. In addition, for error detection and correction encoding, it is desirable to configure so as to detect and correct a relatively short specific decoding error pattern sequence (code error syndrome). This is suitable for simplifying each other's configuration and suppressing an increase in code redundancy for a transmission code sequence due to both.

As a similar technique, the generation of a specific transmission code sequence pattern in which the most frequent decoding error pattern sequence (code error syndrome) can occur by encoding and modulation processing is performed on an actual transmission code sequence. It is also possible to add a constraint condition to allow or exclude periodically or periodically. In this case, error code detection / correction coding for detecting and correcting the decoded error pattern sequence (code error syndrome) is performed only on a code in a time phase on the transmission code sequence in which a specific transmission code sequence pattern is allowed. In the correction process, the error code detection and correction process can be performed only on the decoded code of a specific time phase synchronized with the decoded code sequence. For example, when the detection and correction of the decoding error pattern sequence (code error syndrome) of the 3-bit decoding error pattern 121b shown in FIG. Appearance of a code pattern of " 010 ..." or "... 101 ..." (code pattern start bit) in which a pattern event can occur is allowed only in an n-bit cycle (n is a natural number). In the transmission code sequence, the start of the occurrence of two consecutive code inversions is allowed only in n-bit periods.) Thereby, in the transmission code sequence, three consecutive bits starting from the same bit position in the n-bit period as described above The error code detection / correction code can be configured by narrowing down the target of the error correction position so as to detect and correct only the code error. This can be performed only at a periodic code position synchronized with the bit period.In this way, by allowing the appearance of a specific code pattern that is likely to cause an error periodically in the transmission code sequence, The restriction on the coded modulation processing can be relaxed and the increase in code redundancy due to the modulation processing can be suppressed as compared with the case where the BER is completely restricted and prohibited. Because it is only necessary to apply
This simplifies the error detection and correction code and leads to relatively low redundancy for the transmission code sequence.

In the above description, the transmission code sequence 100
Has been described as being decoded and output as a code sequence equal to the transmission code sequence, although the transmission code sequence output from the maximum likelihood sequence decoder has been described as it is. In, before the input of the transmission channel, or for the decoded sequence in the maximum likelihood sequence decoder or immediately after the output, precoding processing,
Alternatively, various code conversion processing and signal processing operations such as post code processing are often performed. In this case, the error code position of the code error pattern sequence (error syndrome) is determined for the error sequence on the decoded sequence by the same code conversion processing and signal processing operation as for the information code.
The processing code position can be obtained by performing a mapping transformation. For example, for a transmission code sequence on a channel,
When a sequence that has been subjected to post code processing (1 + D * D) (addition of +2 modulo to a binary code) is output as a decoded code sequence, a significant code error pattern for the transmission code sequence Sequence (code error syndrome) "... 0 + 1-1 + 1-1 + 1100
… ”Is subjected to the same post code processing, and“… 0 + 1-10 ”
00-1 + 1... ”And perform error correction coding as a decoded code error pattern sequence (code error syndrome).
Since code reproducibility is guaranteed, one-to-one correspondence between code error pattern sequences (code error syndromes) and code sequence positions before and after conversion is possible. Therefore, it is possible to execute a process equivalent to the above-described embodiment process on the transmission code sequence on the decoded code sequence subjected to various code processes.

In the present invention, in order to easily and more efficiently perform the error code detection and correction processing for the maximum likelihood sequence decoding as in the above-described embodiment, the decoded code sequence is converted into a decoded code sequence block having a predetermined code length. And performs processing for error code detection and correction in each decoded code sequence block. This is based on the nature of the random decoding error event under the noise situation described in (a) above, and each code error event is represented by a sequence (burst).
When viewed as an error event, each error event is considered to occur randomly and randomly on the decoded code sequence. In this way, the present invention focuses on the fact that the probability that random decoding error events caused by noise elements are concentrated at a certain code point is extremely rare, and achieves a practical decoding error probability. As described above, a decoded code sequence block having a predetermined code length is set, and the number of decoding error events that can be detected and corrected within the decoded code sequence block is limited. As a result, the configuration of the error detection and correction code added to the transmission code sequence can be made relatively simple, the code length (redundancy) of the error detection and correction code string can be kept low, and the practical improvement of the decoding error rate can be achieved. Can be fulfilled. In the present invention, a series of decoded code sequences continuously output from the maximum likelihood sequence decoding is subjected to error detection and correction coding in advance so that error detection and correction processing can be performed in units of the decoded code sequence blocks. That is, a transmission code sequence before recording / transmission or a transmission (recording) code sequence supplied to a channel is divided into transmission or transmission (recording) code sequence block units corresponding to the decoded code sequence block. The transmission or transmission (recording) code sequence block is subjected to error correction coding so that error events of the limited specific code error syndrome as described in the above embodiment can be corrected up to a limited predetermined number. Then, a redundant check code sequence for correction processing is generated. Then, this is transmitted / recorded by inserting / adding it to the transmission code sequence in correspondence with the transmission or transmission (recording) code sequence block. For example, if the error probability in the output of maximum likelihood sequence decoding is 1.0E-3, the number of decoding error events occurring in the The number can be approximately one. Therefore, the transmission (recording) code sequence block length is set to 1000 for the corresponding decoded code sequence block.
Bits so that each transmission (recording) code sequence block is subjected to error detection and correction coding capable of detecting a specific error event, and a redundant check code string (error correction code) for error detection and correction to be generated By adding (sequence), it is possible to relieve an error event and improve the decoding error rate. Also, when correcting an error event of a specific code error syndrome that spans a plurality of decoded code sequence blocks,
As a predetermined code error pattern sequence (code error syndrome) set in the error correction coding, a partial sequence of a specified high-frequency code error pattern sequence (code error syndrome) is included and set.

In general, under a decoding system with a certain decoding error rate,
The larger the transmission (recording) code sequence block length,
In order to enhance the detection and correction capability of the error correction code to be added, it is necessary to increase the code length of the redundancy check code sequence (error correction code sequence), and the transmission (recording) code sequence block length and the redundancy check code sequence (error correction code sequence) An optimal length is selected for the configuration and length of the code sequence according to the embodiment. In the present invention, the error detection / correction coding and correction processing configured for a transmission (recording) code sequence block is performed by using a known error detection code / error correction code such as a cyclic redundancy check (CRC). It can be easily configured by technology. Therefore, providing a method for constructing an effective error detection and correction code having low redundancy for a particular code error pattern and the number of corrections is beyond the scope of the present invention and will not be described here. Also,
Transmission (recording) divided into predetermined code lengths as described above
Performing error correction in units of code sequence blocks is more advantageous when performing this error correction processing by soft decision processing. The method of correcting the error event of the specific code error syndrome of the present invention by performing soft decision processing using analog code information to increase the gain of correction coding can be provided by a known technique. The realization scale of the error correction processing circuit generally increases in proportion to the code length power of the correction processing. In response to such an increase in the number of error correction processing circuits (error correction decoders), error correction is performed by limiting the code length of each error detection and correction process to a transmission (recording) code sequence block unit as described above. The required circuit scale of the processing circuit (error correction decoder) can be reduced, and realization with a practical scale can be provided. As described above, in the present invention, the information of the decoding error characteristic of the maximum likelihood sequence decoding is effectively used, and efficient decoding reliability is improved by low redundancy and simple error correction means. For this reason, an error correcting means is connected to the maximum likelihood sequence decoder, and a processing configuration in which both are positively combined is adopted. The present invention relates to the aforementioned (a)
(B) low-redundancy correction processing for correcting a high-frequency code error event having a specific code error syndrome to a limited number of occurrences within a code sequence of a predetermined length, based on the nature of the maximum likelihood sequence decoding error in (b). The present invention has an advantage that the reliability of transmission / recording / reproducing information can be increased by using an error correction detection code having a simple configuration according to an existing technology. The above is the working principle of the present invention.

FIG. 1 is a first basic embodiment showing a flow of processing of an information code sequence in an information recording / reproducing method and a recording / reproducing apparatus according to the present invention. In this embodiment, the information code sequence 300 to be recorded / reproduced is subjected to a code conversion process for adding a predetermined constraint condition such as a run-length limit via an encoding / modulation processing circuit 301 (recording code modulation process). Is done. A first error correction encoding circuit (first error correction encoder circuit) 304 performs a first error correction encoding process on the recording code sequence 302 before recording converted and output by this process. . In the present embodiment, the first error correction coding circuit 304 generates an error check redundant code sequence (first error correction code sequence) for error detection and correction for the input recording code sequence 302. An error correction code string generation circuit 304a and an error correction code string insertion circuit 30 for inserting and adding the generated check redundant code string (first error correction code string) to a predetermined code position on the recording code sequence 302.
4b. As described in the above-mentioned principle of the present invention, a specific high-frequency code error pattern on a decoded code sequence limited by the configuration of the recording / reproducing system channel and the maximum likelihood sequence decoding method (decoder) in the present invention. The event is preset as a predetermined code error pattern (code error syndrome), and the error correction code string generation circuit 30
4a converts the input recording code sequence 302 into recording code sequence blocks 302a and 302b having a predetermined code length.
., And the decoding error event of the set high-frequency code error pattern (code error syndrome) is recorded in each of the recording code sequence blocks 302a, 302b, and 302c. , Error correction coding is performed on the recording code sequence block so that detection and correction (first code error detection and correction processing) is performed up to a predetermined number within the code sequence unit of. The error-correction coding implemented is generally, like cyclic redundancy coding,
In the case of the systematic coding often used for this type of error correction coding, each recording code sequence block 30
2a, 302b, 302c,... Corresponding to the error check redundant code sequence (first error correction code sequence) 303a, 303b, 3
.. Are generated from the error correction code sequence generation circuit 304a. The error correction code sequence insertion circuit 304b converts the input recording code sequence 302 into a recording code sequence block 302.
a, 302b, 302c,..., and in many cases, each recording code sequence block 302a, 302b, 30
2c... At the code position immediately after 2c.
Error check redundant code string (first error correction code string) corresponding to the recording code sequence block generated and output from the buffer unit 04a
.. Are sequentially inserted and output as a channel recording code sequence 305. The error correction code sequence insertion circuit 304b converts the input recording code sequence 302 into recording code sequence blocks 302a and 302a.
.. can be easily configured by a delay storage circuit that delays in units of b, 302c,. When the realized error correction coding is based on systematic coding such as convolutional coding, redundancy for error check is added to each of the recording code sequence blocks 302a, 302b, 302c,. Output from the error correction code sequence generation circuit 304a
These are sequentially output as a channel recording code sequence 305. In this way, a channel recording code sequence 305 obtained by performing error correction coding on the recording code sequence 302 or adding an error check redundant code sequence (first error correction code sequence) to the recording / reproducing system It is provided to channel 306. The configuration of the recording / reproducing system channel 306 is different depending on the information recording / reproducing system to which the present invention is applied.
b, a recording medium 306c, a reproduction head 306d, a reproduction signal processing system 306e, and the like. As an example, the recording signal processing system 306a includes a code processing circuit 307a that performs predetermined code processing such as precoding on the channel recording code sequence 305, and a code signal conversion circuit that converts the channel recording code sequence 305 into a recording signal sequence 308. 307b, a recording signal processing circuit 307c for performing predetermined signal processing such as recording signal correction processing on the recording signal sequence 308, a recording signal amplifier 307d, and the like. These recording signal processing systems 3
The recording signal sequence 306f output via 06a is supplied to the recording head 306b, whereby the channel recording code sequence 305 is recorded on the recording medium 306c.

In the reproducing process, the information of the channel recording code sequence 305 recorded in the recording process as described above is reproduced by using the reproducing head 306d to reproduce the reproduced signal sequence 3 from this output.
06g, and supplied to the reproduction signal processing system 306e to be subjected to predetermined processing. As an example, the reproduced signal processing system 306e is configured to input the reproduced signal sequence 306
reproduction signal amplifier 308a for amplifying g, reproduction signal sequence 3
Variable gain amplifier circuit 30 for compensating signal amplitude fluctuation of 06g
8b, a filter circuit 308c for removing unnecessary (high-frequency) noise on the reproduction signal sequence 306g (high-frequency cutoff), and a sampling circuit (analog for discretizing and quantizing the analog reproduction signal sequence 306g into digital signal values) / Digital converter) 308d, an equalization processing circuit 308e for performing a signal waveform equalization process on the reproduction signal sequence 306g, and the like, and a gain control signal 308g for the variable gain amplification circuit 308b and a sampling circuit 308d. In many cases, a timing reproduction / gain control circuit 308f for reproducing / extracting the sample timing control signal 308h and the like from the information of the reproduction signal sequence 306g is also included. The reproduced signal sequence 306e that has been subjected to the above processing by the reproduced signal processing system 306e is output as a decoded signal sequence 309, and the maximum likelihood sequence decoding circuit 31
Supplied as zero input. The maximum likelihood sequence decoding circuit 310 performs a decoding process using the maximum likelihood sequence estimation method as described above, and outputs a decoded code sequence 311 as a decoding result. At this time, the decoded code sequence 311 may be subjected to predetermined code processing such as post code processing as needed. The output of the maximum likelihood sequence decoding circuit 310 includes a first error detection / correction processing circuit (first error correction / encoding circuit) corresponding to the first error correction encoding circuit (first error correction encoder circuit) 304 in the recording process. Correction decoder circuit) 313 is provided. In the first error detection and correction processing circuit (first error correction decoder circuit) 313, the recording code sequence block 302a, which is a code sequence block unit in the recording process,
The decoded code sequence 31 synchronously corresponding to 302b, 302c,.
1, the decoded code sequence blocks 311a, 311b, 31
1c are subjected to a first code error detection and correction process. That is, in the first error detection and correction processing circuit (first error correction decoder circuit) 313, the error check redundant code sequence (first error correction code sequence) 303a,
03b, 303c,...
Each of the above-described decoding error check redundant code sequences (first error correction code sequences) 312a, 312b, 312c... A code error detection and correction process is performed. In the configuration example of this embodiment, the first error detection / correction processing circuit (first error correction decoder circuit) 313 includes a code error check / correction circuit 313a and an error check redundant code sequence removal circuit 31.
3b. Code error check and correction circuit 313a
.. (Decoded code sequence blocks 311a, 311b, 311c...) And error check redundant code sequences 303a, 303b, 303c. ..), And using the corresponding decoding error check redundant code strings 312a, 312b, 312c... For the respective decoded code sequence blocks 311a, 311b, 311c. An error code check based on a code error detection and correction process is performed. The error check redundant code sequence removal circuit 313b converts the input decoded code sequence 311 into the recording code sequence block 3
(Decoded code sequence blocks 311a, 311b, 311c...) And error check redundant code sequences 303a, 303b, 303c (decode error check redundant code sequences 312a, 312b, 312c. Then, the decoding error check redundant code strings 312a, 312
12b, 312c... Are excluded, and only the decoded code sequence blocks 311a, 311b, 311c.
It is output at a predetermined code reproduction speed as a continuous decoding time series correction decoding code series 314. The error check redundant code sequence removing circuit 313b can be easily constituted by a delay storage circuit for delaying an input code sequence in units of decoded code sequence blocks 311a, 311b, 311c. Further, when the realized error correction coding scheme is based on non-systematic coding, the redundancy for error checking is inherent in each of the decoded code sequence blocks 311a, 311b, 311c. One error detection / correction processing circuit (first error correction decoder circuit) 313 converts the input decoded code sequence 311 into decoded code sequence blocks 311a and 311a.
1b, 311c... Are subjected to a predetermined error correction process for each decoded code sequence block, and the decoded code sequence block after the error correction process is set as a corrected decoded code sequence 314 of a continuous code time sequence. Output at code playback speed.
(The error check redundant code sequence removing circuit 313b has a form inherent in the code error check and correction circuit 313a.)
As in a known example described later, the decoded code sequence block 311
a, 311b, 311c... and decoding error check redundant code string 3
.. May be an information recording / reproducing system which is separately recorded / reproduced, the first error detection / correction processing circuit (first error correction decoder circuit) 31
3 separates the input decoded code sequence 311 into decoded code sequence blocks 311a, 311b, 311c,... And decodes the decoded error check redundant code sequence (first error code) corresponding to each of the simultaneously input decoded code sequence blocks. Correction code sequence) 3
12a, 312b, 312c... Are used for the corresponding decoded code sequence block to perform an error correction process, and the decoded code sequence block after the error correction process is used as a correction code sequence 314 of a continuous code time sequence, and a predetermined code. Output at playback speed. (The function of the error check redundant code sequence removing circuit 313b becomes unnecessary.) Finally, the corrected decoded code sequence output via the first error detection / correction processing circuit (first error correction decoder circuit) 313 314 is input to a demodulation processing circuit 315 (recording code demodulation processing), through which a code conversion processing corresponding to the code conversion processing in the encoding / modulation processing circuit 301 (recording code modulation processing) in the recording process is performed. The decoded code sequence 3 corresponding to the original information code sequence 300
16 is played. The above is the outline of the first basic embodiment of the present invention in FIG. In the practice of the present invention,
Since the first code error check and correction process is based on the premise that the decoding error characteristic of the maximum likelihood sequence decoder 310 is used, generally, as shown in FIG. Output decoded code sequence 311
Is input to the first error correction encoding circuit (first error correction encoder circuit) 304 without logically changing the code order, or is input directly. In the processing such as the above-described post code, only a predetermined processing is sequentially performed on each code without logically changing or changing the code order of the decoded code sequence 311. Therefore,
Before and after the processing, the decoding error syndrome can be one-to-one correspondence, without being spread on the code sequence,
The operation of changing the logical order does not apply. According to the principle of the invention, a first error correction encoding circuit (first error correction encoder circuit) which is a first code error check / correction means.
304 is a maximum likelihood sequence decoder 310 as a decoding means
The structure of the present invention is characterized by the fact that it is connected to the structure. This often results in embodiments where the invention is implemented on an integrated circuit, both of which are mounted on a single integrated circuit.

FIG. 2 is a diagram for explaining the flow of a code sequence in the first basic embodiment of FIG. The information code sequence 300 recorded and reproduced in the present invention is encoded /
After being converted into a recording code sequence 302 by the recording code modulation processing in the modulation processing circuit 301, the first error correction encoding circuit (first error correction encoder circuit) 304
Recording code sequence blocks 302a, 302 having a predetermined code length
., and each of the recording code sequence blocks 302a, 302b, 302c... is subjected to an error check redundant code sequence (first error correction code sequence) 303a, 303.
b, 303c... are generated. The generated error check redundant code sequence (first error correction code sequence) 303a, 303
are recorded together with the recording code sequence blocks 302a, 302b, 302c,... at a predetermined recording position corresponding to the recording code sequence block.
Error check redundant code sequence (first error correction code sequence) 303
a, 303b, 303c... can be recorded and reproduced in a separated form as long as they can be reproduced together while corresponding to the recording code sequence block, but in many cases, Recording and reproduction processing is performed as a collective code sequence. Also in this case, the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c,.
Can be added to a predetermined code position on the recording code sequence 302 which is recorded / reproduced in correspondence with the recording code sequence block, but in most cases, immediately before / after the recording code sequence block. Alternatively, it is inserted / added to a predetermined code position inside. Most commonly, each error check redundant code sequence (first error correction code sequence) 303a, 303
are generated with reference to the recording code sequence block, and are added to the recording code sequence 302 at code positions immediately after the recording code sequence. This is because each of the error check redundant code strings (first error correction code sequences) 303a, 303b,
Even when error correction processing is performed on the decoded code sequence block using 303c..., The processing delay time is reduced, and the correction processing efficiency is the highest. Each error check redundant code sequence (first error correction code sequence) 303a, 303b, 3
.. Are configured as a check redundant code sequence having an extremely low redundancy and an extremely short code length according to the principle of the present invention. Therefore, even if the encoding / modulation processing circuit 301 disperses and adds the recording code sequence 302 after adding a predetermined constraint condition such as a run-length limit to the recording code sequence 302, the constraint condition is largely prevented. It does not become. .. Have a relatively simple and short code length. For example, when constructing the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c. Before and after that,
It is also possible to generate error check redundant code strings (first error correction code sequences) 303a, 303b, 303c... Satisfying a predetermined constraint condition. Generated error check redundant code sequence (first error correction code sequence) 303a, 303
are relatively long, and it is problematic to destroy the above code constraint condition by inserting / adding them, each error check redundant code sequence (first error correction code sequence) Can be avoided by dividing into a plurality of pieces and distributing them at predetermined recording positions / code positions and inserting / adding them. The recording code sequence 302 into which the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c.
Is supplied to the recording / reproducing system channel 306 and is subjected to recording processing. Each recording code sequence block 302a, 3
Are a series of code sequence blocks that are successively decoded by the single maximum likelihood sequence decoder 310 in the reproduction process, as described later. Therefore, in a normal recording / reproducing mode, the channel recording code sequence 305 is recorded / reproduced in this code order,
On the recording medium 306c, this code order and code form are also used.
Recording is performed at physically continuous recording positions. Such a recording code form on the medium indicates an embodiment of the present invention. The decoded code sequence 311 output from the maximum likelihood sequence decoder 310 also has the same code form as the channel recording code sequence 305, and the recording code sequence blocks 302a, 30
2b, decoded code sequence block 31 corresponding to 302c...
1a, 311b, 311c,..., And immediately after the relevant decoded code sequence block, decoded error-checked redundant code sequences (first error-correcting code sequences) 303a, 303b, 303c. Error correction code sequence) 3
12a, 312b, 312c... Are added. In the first error detection / correction processing circuit (first error correction decoder circuit) 313, the decoding error check redundant code sequence (first error correction code sequence) 312a, 312b, 31
., The first error code detection / correction process is performed on the decoded code sequence block, and then only the decoded code sequence blocks 311a, 311b, 311c. Demodulation processing circuit 31
In 5 (recording code demodulation processing), code conversion processing corresponding to the recording code modulation processing is performed on this, and a decoded code sequence 316 corresponding to the original information code sequence 300 is reproduced.

The above-described embodiment of the present invention can take various forms depending on the information recording / reproducing method, the information recording / reproducing apparatus, and the recording / reproducing channel to be processed. Further, as described above, the details of the invention configuration in FIG. 1 are changed by the error code detection / correction coding and correction means used in the first error detection / correction process. The basic feature is that a first error correction coding circuit (first error correction encoder circuit) 304 converts a recording code sequence 302 into a recording code sequence block 30 which is a code sequence unit having a predetermined code length.
Are logically separated into 2a, 302b, 302c,..., Subjected to a first error correction encoding process for each recording code sequence block, and then output.
First error correction processing circuit (first error correction decoder circuit)
Reference numeral 313 denotes a decoded code sequence block 311 a, which is a code sequence unit having a predetermined code length.
., 311c... are logically separated, a first error detection and correction process is performed on each decoded code sequence block, and this is output. First error correction encoding circuit (first error correction encoder circuit) 304
Check redundancy for error detection and correction generated in
That is, in many embodiments, the error check redundant code sequence (first error correction code sequence) 303a, 303b, 303c... Is a recording code sequence 302 (information code sequence) as shown in FIG.
However, these are handled separately from each other by providing a means for managing only the correspondence between them, and different recording media 306c and different recording / reproducing channels 3 are added.
06 may be used for recording and reproduction processing. According to the principle of the present invention, check redundancy for error detection and correction generated in the first error correction coding circuit (first error correction encoder circuit) 304, that is, One error correction code sequence) 303
a, 303b, 303c,... can be made extremely small with respect to the size of the information code to be recorded and reproduced, so that the recording code sequence blocks 302a, 302b, 302c. Correction code sequence) 303
a, 303b, 303c... are often rationalized in consideration of processing efficiency, hardware costs, or recording / reproduction costs. Recording code sequence blocks 302a, 302b,
., And error-check redundant code sequences (first error correction code sequences) 303a, 303b, 303c,... A plurality of recording / reproducing devices or a plurality of recording / reproducing means of the same type (for example, a plurality of magnetic disk devices), or a different type of recording / reproducing device or recording / reproducing means (for example, the former is a magnetic recording means / device and the latter is a semiconductor storage means Various forms can be implemented, such as recording on each device. Further, it is also possible to realize a mode in which the separated and recorded information is simultaneously reproduced by a plurality of transducers (reproducing heads 306d), or reproduced in time by the same transducer (reproducing head 306d). . The most reasonable and economical embodiments are realized by any of the information recording / reproducing methods and information recording / reproducing apparatuses to be used, or combinations of different information recording / reproducing methods and information recording / reproducing apparatuses. . The second basic feature of the configuration of the embodiment is that the decoded code sequence blocks 311a, 311
., 311c... are always sequential code units decoded and output physically continuously from a specific maximum likelihood sequence decoder 310. The decoded code sequence blocks 311a, 311b,. 311c... Is determined in accordance with the unit of 311c... In which the recording code sequence blocks 302a, 302b, 302c.

FIG. 3 shows a second basic embodiment for clarifying the second feature, in which a single recording code sequence 302 is recorded / reproduced by a plurality of recording / reproducing channels 306. 1 shows an embodiment of the present invention. Here, as shown in FIG. 3, a plurality of recording / reproducing system channels are included, including an information recording / reproducing method and an information recording / reproducing apparatus in which a plurality of the above-mentioned target information can be simultaneously separated and recorded / reproduced. 306 is provided, and an embodiment in which these are operated simultaneously for one recording / reproducing processing unit is shown. As described above, the single information code sequence 300 is separated and recorded / reproduced by the plurality of recording / reproducing channels 306 by the multiplexer circuit (code sequence selection circuit) 348a and the demultiplexer circuit (code sequence selection circuit) 348b. In the case of an information recording / reproducing method or an information recording / reproducing apparatus in which each channel output is subjected to decoding processing in parallel or separately by a plurality of maximum likelihood sequence decoders 310, each maximum likelihood sequence decoding Vessel 3
A first error correction encoding circuit (first error correction encoder circuit) 3
The first error detection and correction process by the logical unit 04 is logically performed independently while maintaining the physical code output order of each decoded code sequence 311. This is because, as described above, the principle of the present invention utilizes the nature of the decoded sequence error of the maximum likelihood sequence decoder 310.

For this reason, in many embodiments in such a case, as shown in FIG.
6, a first error detection / correction processing circuit (first error correction decoder circuit) 313 is provided independently for each output of the maximum likelihood sequence decoder 310 connected to. (These sequences may be provided independently of each other from the encoding / modulation processing circuit 301.) The decoding code sequence 311 serially output from each of the maximum likelihood sequence decoders 310 is maintained in a predetermined code order while maintaining its code order. Of the first error detection and correction processing. At this time, the decoded code sequence 311 from the maximum likelihood sequence decoder 310 connected to each recording / reproducing system channel 306 is independently set with decoded code sequence blocks 311a, 311b, 311c... Having a predetermined code length. Then, a predetermined first error detection and correction process is performed on each decoded code sequence block. In the recording process, the information code sequence 30
0 is supplied to a plurality of recording / reproducing channels 306 and is separated into a plurality of streams, and then a first error correction coding circuit (first error correction encoder circuit) 304 provided for each stream is provided. , The decoded code sequence block 311a,
Each of the recording code sequence blocks 302a, 302b, 302c,... Corresponding to 311b, 311c,... Is separated and subjected to a first error correction encoding process, which is supplied to each recording / reproducing system channel 306. To perform the recording process. In this embodiment, a first error correction encoding circuit (first error correction encoder circuit) 304 and a first error detection / correction processing circuit (first error correction decoder circuit) 313 are connected to a recording / reproducing system channel. Although a plurality of independent units are provided for each 306, a single circuit or means can realize an equivalent processing method or configuration. As described above, in the present invention, in order to effectively use the decoding error characteristic of the maximum likelihood sequence decoder 310, the decoded code sequence 311 from the maximum likelihood sequence decoder 310 can be used without changing the code order. The embodiment supplied to the error correction encoding circuit (first error correction encoder circuit) 304 is effective. Therefore, in many embodiments, as in the embodiment of FIG. 1 or FIG. 3, the output of the decoded code sequence 311 from the maximum likelihood sequence decoder 310 is a code-first error correction coding circuit (first error correction coding circuit). (Encoder circuit) 304. In many cases, due to the presence of a code conversion process between the two, a code error pattern (code error syndrome) to be set increases in the first error correction coding process and the first error detection and correction process. Processing becomes impossible, or error encoding / correction processing, a first error correction encoding circuit (first error correction encoder circuit) 304 and a first error detection / correction processing circuit (first error correction Decoder circuit) 313
Is extremely complicated. From this,
As can be seen from the above-described first and second embodiments, in the information recording / reproducing to which the present invention is applied, a predetermined code constraint condition or constraint condition such as a run-length limit is placed on the channel recording code sequence 395. If additional recording code modulation processing and recording code demodulation processing are required, the recording code modulation processing on the information code sequence 300 is performed before the first error correction coding processing is performed, and the decoded code sequence 31
It is an effective embodiment that the recording code demodulation process for No. 1 is added after the first error code detection and correction process is performed. Therefore, in the embodiment of the present invention, the first code error check and correction process is performed by the maximum likelihood sequence decoder 31.
Since it is assumed that a decoding error characteristic of 0 is used, a decoded code sequence 311 decoded and output from the maximum likelihood sequence decoder 310 is generally, as shown in FIG.
The signal is input to the first error correction encoding circuit (first error correction encoder circuit) 304 without logically changing the code order, or is input directly. According to the principle of the invention, a first error correction encoding circuit (first error correction encoder circuit) which is a first code error check / correction means.
304 is a maximum likelihood sequence decoder 310 as a decoding means
Is a structural feature of the present invention, and as described above, in the case of implementing the present invention by an integrated circuit,
Often, this results in an embodiment where both are mounted on a single integrated circuit.

FIG. 4 shows a third basic embodiment of the present invention. In this embodiment, in the recording process, the second error correction encoding circuit (second error correction encoder circuit) 317 for the information code sequence 300 is connected to the first error correction encoding circuit (first error correction code). A second error correction coding process is performed before the device circuit 304. Also,
In the reproduction process, a second error detection / correction processing circuit (the second error detection / correction circuit) is used to apply the second error code detection / correction processing corresponding to the second error correction encoding processing to the reproduction code sequence 316 before output. Error correction decoder circuit) 318 to a first error correction encoding circuit (first error correction encoder circuit) 313.
Later. The second error correction encoding process and the second error code detection / correction process are the same as those in the above-described embodiments, except that the first error code detection / correction process (specific error code event of a predetermined predetermined code error syndrome is performed). , A decoding error event that cannot be detected and corrected in a process of detecting and correcting up to a predetermined number of occurrences, a decoding error event that has been erroneously corrected, or a random noise factor that can occur in the actual recording / reproducing process. Is provided for the purpose of relieving an unpredictable decoding error event and obtaining a desired recording / reproducing reliability.

According to the principle of implementation of the present invention, the probability of occurrence of an error code event of a code error syndrome that is not to be corrected in the first error code detection and correction process, and the predetermined number (errors) in a single decoded code sequence block Since the probability of occurrence of an error code event exceeding the detection error correction capability becomes a relatively low occurrence frequency, in the present invention, a decoding error event that cannot be corrected by the first error code detection and correction process, or
Attention is paid to the fact that the probability that the decoding error event subjected to the erroneous correction process occurs continuously or frequently in a plurality of decoded code sequence blocks is extremely small. Therefore, in the present embodiment, in the recording process, for example, the information code sequence 300 which is continuously and collectively recorded / reproduced in one operation unit of the recording / reproducing process such as a sector unit in a disk device or a block unit in a tape device. Code sequence unit (recording frame) or recording code sequence 30
2, a plurality of collective recording code sequence blocks 302a,
The code sequence units on the information code sequence 300 corresponding to 02b, 302c... Are the processing units (information code frames 319a, 319b, 319c...) In the second error detection and correction coding and the second error code detection and correction processing. I do. In the recording process, the second error correction encoding circuit (second error correction encoder circuit) 317
Each of the information code frames 319a, 319b, 31
9c is subjected to a second error correction encoding process, or an error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c. In the reproduction process, the second error detection / correction processing circuit (second error correction decoder circuit) 318 outputs the reproduced code sequence 316
Above, the information code frames 319a, 319b, 319
The reproduced code frames 325a, 325b corresponding to c ...
325c... As a processing unit, and an error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c.
.. 326a, 326b, 326c,... 326a, 326b, 326c,.
Is used for the reproduction code frame 325,
After performing the second error code detection / correction processing, this is output as a final reproduced code sequence (1) 316a.

As described above, the second error correction coding process and the second error code detection / correction process correct a code event that is out of the target or cannot be corrected in the first error code detection / correction process. For the purpose, such a code error event includes many burst-like code error events due to a decoding error propagation phenomenon in the maximum likelihood sequence decoder 310.
In addition, occurrence of error code events exceeding a predetermined number (correction capability of the first error code detection and correction process) is treated as a set of a plurality of error events, and error correction is performed by the first error code detection and correction process. The resulting error event will also be a relatively long code error event. Furthermore, decoding error events due to factors other than the random noise factors that occur practically in the recording / reproducing apparatus (defects on the recording medium or partial failure of the reproduction signal sequence) have a relatively low probability of occurrence, and are not predictable during high-density recording. It is necessary to assume a difficult and extremely long code length bursty code error event. From such a point, the second error correction coding process and the second error code detection and correction process have various code errors compared to the first error correction coding process and the first error code detection and correction process. It is necessary to apply a relatively powerful error correction coding and correction method, such as Reed-Solomon code, to correct a long code error event that takes a syndrome. In the prior art, such a powerful error correction coding and correction method generally requires a code configuration having a complicated and high check redundancy, and an error check formed and added to the information code sequence 300 by coding. The redundancy required for the redundant code sequence (second error correction code sequence) 320a, 320b, 320c, etc. is large. In the present invention, the second error correction encoding process and the second error code detection and correction process are performed based on the nature of the probability of occurrence of a code error event to be corrected in the second error correction encoding process as described above. , A relatively long code string unit (information code frames 319a, 319b, 319c,...) On the information code sequence 300 as compared with the first error correction coding processing and the first error code detection and correction processing.
And reproduced code frames 325a, 325b, 325c
... can be applied to As a result, it is possible to avoid a decrease in recording / reproducing efficiency due to an increase in the redundancy of the check code and a complicated error correction encoding and correction process. In the present invention, random short code errors occurring at a high frequency are first error correction coding and error detection correction of relatively low redundancy, which are dispersion-coded on the recording code sequence 302 in recording code sequence block units. It is corrected by processing. In addition, a long code error that occurs in a continuous burst of relatively low frequency is strong (high redundancy) by the second error correction coding and error detection / correction processing using the long information code frame 319 as a unit of correction processing. Correction processing is performed using the error correction code. As described above, the second error correction coding and the first error code detection and correction processing and the second error correction coding and the second error code detection and correction processing In the code detection and correction process, it is possible to avoid the burden on the correction process and the loss of correction capability for random decoding errors that occur widely in a distributed manner, and to correct and correct long burst decoding error events with emphasis on the correction target. The optimal configuration of the processing is also easy. As a result, in the present invention, it is possible to effectively and efficiently improve the error correction efficiency and the decoding reliability in the entire recording / reproducing process, and without using the first error code detection / correction process as in the related art. In the case where the same decoding reliability is to be ensured only by the second error code detection and correction processing, the required error check redundancy is kept low, and the means for efficient error detection and correction in information recording and reproduction is improved. Can be realized. The configuration method of the error correction code and the second error code detection and correction processing in the second error correction coding processing can be realized by a known technique, and thus will not be described in detail here. The correction processing capability and error correction code configuration required for the second error correction encoding process and the second error code detection / correction process, the code length of the information code frames 319a, 319b, 319c. Appropriate settings can be made according to the recording / reproducing system channel or apparatus to be the object of the invention and the desired information recording / reproducing reliability. As can be seen from the present embodiment, in the information recording / reproducing to which the present invention is applied, a recording code modulation process and a recording code for adding a predetermined code constraint condition such as a run-length limit or the like on the channel recording code sequence 305. When demodulation processing is required, the error check redundant code string in the second error correction coding is relatively long, so that the code constraint condition or the constraint After performing the error correction encoding process, the recording code modulation process is performed,
An embodiment in which after performing the recording code demodulation processing on the decoded code sequence 311, a second error code detection and correction processing is performed;
That is, the second error correction coding circuit (second error correction encoder circuit) 317 precedes the coding / modulation processing circuit 301, and the second error code detection / correction processing circuit (second error correction coding circuit). A configuration in which a correction decoder circuit 318 is provided after the demodulation processing circuit 315 is often taken as a simple practical embodiment.

FIG. 5 is a diagram for explaining the flow of a code sequence in the third basic embodiment of FIG. The information code sequence 300 to be recorded and reproduced in the present invention is first input to a second error correction coding circuit (second error correction encoder circuit) 317 provided in front thereof, and a predetermined information code frame 319 is processed. As a unit, the second error correction encoding processing as described above is performed. When the second error correction coding is the systematic error correction coding by Reed-Solomon coding or the like, each of the information code frames 31
9a, 319b, 319c... Include an error check redundant code sequence (second error correction code sequence) 32
. 0a, 320b, 320c... Are respectively generated, and the corresponding information code frame 3 on the information code sequence (1) 300a is
Recording and reproduction are performed together at a predetermined recording position corresponding to 19. Error check redundant code sequence (first error correction code sequence) 303a, 3a in the first error correction coding
03b, 303c,..., The error-check redundant code sequence (second error-correcting code sequence) 320a, 320b,
20c... May be recorded and reproduced as they are separated as long as they can be recorded and reproduced together with the information code frame 319. The present invention is applicable to the case where the two are recorded and reproduced at different recording positions, recording media, recording devices and recording means, or are recorded and reproduced by different recording and reproduction channels. It is possible,
In many cases, both are recorded and reproduced as a collective code sequence as shown in FIG. Also in this case, the error check redundant code sequence (second error correction code sequence) 320a, 320b, 3
20c... Can be added to a predetermined code position in the information code sequence if it can be recorded and reproduced in correspondence with the information code frame 319, but in most cases, immediately before or immediately after the information code frame 319 or It is inserted and added to a predetermined code position inside. Most commonly, each error check redundant code sequence (second error correction code sequence) 320a,
20b, 320c... Correspond to the information code frame 319.
, The information code sequence (1) 3
On 00a, each is inserted and added to the code position immediately after the information code frame 319. In the reproduction process, the second error code detection and correction process is performed on the information code frame 319 using the respective error check redundant code sequences (second error correction code sequences) 320a, 320b, 320c,. Also in this case, the processing delay is reduced, and the correction processing efficiency is the highest. However, some code constraint condition has already been added to the information code sequence 300 input to the second error correction coding circuit (second error correction encoder circuit) 317, and the error check redundant code sequence (Second error correction code sequence) When it is a problem that the insertion and addition of 320a, 320b, 320c,.
Each error check redundant code sequence (second error correction code sequence)
320a, 320b, 320c,... Is divided into a plurality of parts, which are dispersed and inserted / added to predetermined recording positions / code positions in the information code frame 319, thereby avoiding this. In many cases, as in the embodiment of FIG.
Information code sequence (1) 300a output from second error correction encoding circuit (second error correction encoder circuit) 317
Above, the information code frames 319a, 319b, 31
Error check redundant code strings (second error correction code sequences) 320a, 320b, 32 at predetermined code positions corresponding to 9c.
After adding / adding 0c...
01 is performed. As shown in FIG.
When the encoding / modulation processing circuit 301 is provided and the code conversion processing is performed, each information code frame 319a, 319b, 3
19c are code-converted on the recording code sequence 302 corresponding to the recording code frames 321a, 321b, 321c. Further, the error check redundant code sequence (second error correction code sequence) 320a, 320b, 320c.
Error check redundant code conversion sequence (second error correction code sequence) 3
22a, 322b, 322c,... (If the encoding / modulation processing circuit 301 is not provided,
.., Recording code frames 321a, 321b, 321c..., Error check redundant code sequences 320a, 320b, 320c... And error check redundant code conversion sequences 322a, 322b, 322c.
Matches. 1) The first error correction encoding circuit (first error correction encoder circuit) 304 is, like the embodiment of FIGS.
1b, 321c... Are divided into recording code sequence blocks,
A first error correction encoding process is performed on each of them.
In the present embodiment, the first error correction encoding process is not performed on the error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c,.
As another embodiment, this error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c
, The first error correction coding process and the subsequent first error code detection and correction process may be performed. In this case, each recording code frame (information sequence section) 300
a, 300b, 300c... and the corresponding error check redundant code conversion sequence (second error correction code sequence) 320a, 320b,
.. 320c are regarded as one concatenated sequence, and recording code sequence blocks 302a, 302b, 302
After setting c ..., the first error correction encoding process and the first error code detection / correction process may be performed on each of the separated recording code sequence blocks, or as shown in FIG. Recording code frame (information sequence part) 300a, 3
.. Are divided into recording code sequence blocks 302a, 302b, 302c... Of a predetermined length, and a first error correction coding process and a first error code detection / correction process are performed on each of them. The error check redundant code conversion sequence (second error correction code sequence) 320a, 32
. 0b, 320c... Independently and, in some cases, may be separated into blocks of a predetermined code length and subjected to the same first error correction coding processing and first error code detection and correction processing. Good.

As described above, the error check redundant code sequence (first error correction code sequence) 303a, 303b, 30
3c... And an error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c. You. In a normal recording / reproducing mode, the channel recording code sequence 305 is
Recording and reproduction processing is performed in this code order, and the recording medium 306 c
Also above, in this code order and code form, they are recorded at physically continuous recording positions. Such a recording code form on the medium indicates an embodiment of the present invention. The decoded code sequence 311 output from the maximum likelihood sequence decoder 310 is also:
Taking the same code form as the channel recording code sequence 305,
In addition to the code form of the decoded code sequence 311 in the embodiment of FIG. 2, the recording code frames 321a, 321b, 321
Each of the decoded code frames 323a, 323 corresponding to c.
3b, 323c,...
Immediately after 23, decoded error check redundant code conversion sequences (second error correction code sequences) 324a, 324b, 324c corresponding to error check redundant code conversion sequences (second error correction code sequences) 322a, 322b, 322c. .. Are added. In the first error detection / correction processing circuit (first error correction decoder circuit) 313, in each decoded code frame 323a, 323b, 323c..., A decoded error check redundant code sequence (first error correction code sequence) 314
a, 314b, 314c,..., a first error code detection and correction process is performed on the decoded code sequence block.
After that, the decoding error check redundant code sequence (first error correction code sequence) 312a, 312b, 312c. On the other hand, the demodulation processing circuit 315 (recording code demodulation processing) performs code conversion processing corresponding to the recording code modulation processing. The decoded code frames 323a, 323b on the corrected decoded code sequence 314,
323c are reproduction code frames 325a, 325c,
25b, 325c..., And a decoding error check redundant code conversion sequence (second error correction code sequence) 324
a, 324b, 324c... are decoding error check redundant code sequences (second error correction code sequences) 326a, 326, respectively.
, 326c... are converted into a reproduced code sequence (1).
316a is obtained. In the second error detection / correction processing circuit (second error correction decoder circuit) 318, each of the reproduced code frames 325a,
325b, 325c,..., The corresponding decoding error check redundant code sequence (second error correction code sequence) 326a, 326
, 326c... are subjected to the first error code detection and correction processing, and then the normal reproduced code frames 325a, 325c
b, 325c,... are obtained and reproduced and output as a reproduction code sequence 316. In the above description of the embodiment, when the second error correction coding means uses non-organized error correction coding such as convolutional coding, an error check redundant code string (second Error correction code sequence) 320
a, 320b, 320c,... are not treated separately as described above, and each information code frame 319a, 31c
9b, 319c... Are inserted and added. Therefore, the error check redundant code conversion sequence (second error correction code sequence) 322a, 322b, 322c.
Decoding error check redundant code sequence (second error correction code sequence) 324a, 324b, 324c... And decoding error check redundant code sequence (second error correction code sequence) 326a, 3
26b, 326c... Are not subjected to the recording / reproducing processing in distinction, and the second error detection / correction processing circuit (second error correction decoder circuit) 318 applies each reproduced code frame 325a, 325b, 325c. Using the inherent error detection redundancy, a second error code detection and correction process is performed on each reproduced code frame, and the result is output as a reproduced code sequence 316.

In general, in many information recording / reproducing methods and recording / reproducing apparatuses, the unit of the second error correction encoding process and the second error code detection / correction process is, for example, from the convenience in controlling the recording / reproducing process. The code sequence unit (recording frame) on the information code sequence 300 that is continuously recorded / reproduced in one operation unit of recording / reproducing processing, such as a sector unit in a disk device, a block unit in a tape device, etc. The information code frame 319 is reasonable.

FIG. 6A shows the recording code form of the recording frame, that is, the information code sequence 30 in this embodiment.
0 and the code form of the channel recording code sequence 305 continuously recorded on the recording medium 306c. On the information code sequence 300, a recording frame (information coding unit) 326
Has a preamble 326a and a postamble 326b added as necessary. In particular, the preamble 326a includes the recording frame (information coding section) 349.
Indicating the recording position of the signal, information for performing signal gain control and signal timing detection, and a recording signal processing system 306a.
Learning information for adjusting the reproduction signal processing system 306e;
Then, synchronization information indicating the start of the recording frame (information encoding section) 349 is included. In the present embodiment, the recording frame (information coding section) 326 corresponds to each of the information coding frames 319a, 319b, 319c... In the embodiment of FIG. 5, but in other embodiments, the preamble 326a
In some cases, all or part of the postamble 326b may be included in the information code frame 319 and processed. In the present embodiment, on the channel recording code sequence 305, the recording code frame 321 which is the information after the recording code modulation processing of the recording frame (information coding unit) 326 is a recording code sequence block 302a, 302b having a predetermined code length. 302
c. Then, as shown in the embodiment of FIGS. 2 and 5, an error check redundant code sequence (first error correction code sequence) 303 for each recording code sequence block
a, 303b, 303c,... are divided or collectively inserted / added to corresponding predetermined code positions of the recording code sequence block, and are recorded on the recording medium 306c. In the present embodiment, each error check redundant code sequence (first error correction code sequence) is collectively inserted and added to the code position immediately after the recording code sequence block, and the recording medium 30
6c.

As shown in the embodiment of FIG. 5, the recording frame (information encoding section) 326 is subjected to the second error correction encoding process and the recording code modulation process to perform an error check redundant code conversion sequence (second When the error correction code sequence 322 is configured, the information is divided or collectively inserted / added to a predetermined code position corresponding to the recording code frame 321 as the information, and is recorded on the recording medium 306c. In this embodiment, each error check redundant code conversion sequence (second error correction code sequence) 322 is collectively inserted and added to a code position immediately after the recording code frame 321 and the recording medium 306 c Recorded above. As described above in the embodiment of FIG. 5, in another embodiment, the first error correction coding is also performed on this error check redundant code conversion sequence (second error correction code sequence) 322. , An error check redundant code sequence (first error correction code sequence) 303 may be added,
In some cases, this error check redundant code conversion sequence (second error correction code sequence) 322 is included in the recording code frame 321 and is subjected to the first error correction coding. Also, as described above, when using an unorganized error coding method,
Error check redundant code sequence (first error correction code sequence) 303
a, 303b, 303c... are included in the recording code sequence blocks 302a, 302b, 302c..., or the error check redundant code conversion sequence (second error correction code sequence) 322 is a recording code frame 321. It becomes the form included in. In this embodiment, the recording frame 349 is continuously recorded on the recording medium 306c by the recording code form of the channel recording code sequence 305 as described above.

As shown in the embodiments of FIGS. 4 and 5, in the present invention, a relatively long code length is used for the second error correction encoding process and the second error code detection and correction process. It is often required to detect and correct code error events, such as Reed-Solomon error correction coding.
Error correction coding using a continuous code sequence (information symbol) having a predetermined code length as a unit of correction processing is used. Therefore, the information code frame 319 to be processed by the second error correction coding process has such an information symbol 327.
Often, it is treated as a sequence of (for example, bytes). In the second error correction encoding process and the second error code detection and correction process, in order to easily detect and correct a code error event having a longer code length, the second error correction encoding process is performed. The information code frame 319 to be processed is divided into n (n is a natural number) independent information symbol sequences by interleave processing in units of information symbols, and the second error correction is performed on each information symbol sequence. It is practical to perform an encoding process. FIG. 6B shows such an interleaving process (n
= 4) shows the recording code form of the information code frame 319 to be performed. In the second error correction encoding process, the information code frame 3 regarded as a sequence of the information symbol 327
19, an (n-1) -th information symbol 327 is regarded as a series, and an error check redundant code sequence (second error correction code sequence) 320 is formed for each sequence.
As a result, while applying the error correction encoding of the same correction capability as the second error correction encoding process to the n information symbols 327 independently and in parallel, the second error code detection and correction process is performed. The maximum information symbol length of the burst code error correction process can be made n times. In the present embodiment, each information symbol 327 in the information code frame 319 is interleaved every four information symbols 327 indicated by the same hatching.
Are considered as one continuous series. Then, in the second error correction encoding process, each of the four sequences A, B, C, and D of the information symbol 327 is subjected to an error check redundant code sequence A, B, C, D (second error correction Code sequence) 328a,
328b, 328c, and 328d are configured and added to the information code frame 319 on the information code sequence (1) 300a in the same interleave format in units of information symbols 327. In FIG. 6B, each error check redundant code sequence A, B, C, D (second error correction code sequence) 3
The information symbols 327 constituting 28a, 328b, 328c, and 328d are hatched in the same manner as the information symbols 327 of the series in the information code frame 319. By such an interleave process, a code error event that occurs consecutively in four information symbols 327 on the information code sequence (1) 300a is logically divided into four single information symbols 327 and the correction process is performed. Even if the second error correction coding process having the same correction capability is used, a burst code error event having a quadruple information symbol length can be corrected by correcting four sequences independently and in parallel. .

FIG. 6C shows the recording code form of the information code frame 319 subjected to such interleaving processing (n = 4), that is, the channel recording code sequence 305.
1 shows a code form in which A predetermined recording code modulation process is performed on the information code sequence (1) 300 having the code form shown in FIG. 6B, and then a first error correction coding process is performed. Is obtained. In this embodiment, the recording code sequence block 302
The code length of a, 302b,... desirably corresponds to a code string unit of a continuous natural number of information symbols 327 constituting the information code frame 319 before the recording code modulation processing. As described above, the code unit (recording code sequence block 302) of the coding / correction process in the first error correction coding process and the first error code detection / correction process on the recording code sequence 302 is , A code sequence unit composed of a natural number of code units (information symbols 327) of the coding / correction process in the second error correction coding process and the second error code detection / correction process. Is preferable for performing error correction coding in conjunction with both. For example, if the first error code detection / correction process detects an error in the recording code sequence block 302a, 302b, 302c,... But cannot correct the error, the recording code sequence block 302a, 302b, 302c,. On the information code sequence 300 and the information code sequence (1) corresponding to.
In the second error code detection and correction process, the information symbol 327 and the code on the information symbol 327 and the code are indicated in the second error code detection and correction process. realizable. This effectively improves the error correction capability in the second error code detection and correction process. At this time, the fact that the code lengths of the recording code sequence blocks 302a, 302b, 302c,... Correspond to consecutive natural number code units of the information symbol 327 on the information code sequence 300 indicates that the information may contain an error. This is more preferable in indicating the symbol 327.

Further, on the recording code sequence 302, the code unit (recording code sequence block 302) of the encoding / correcting process in the first error correction encoding process and the first error code detection / correction process is performed by the recording code modulation process. Alternatively, it may be configured to correspond to a code unit corresponding to a natural number multiple of the code processing unit of the code conversion process in the recording code demodulation process. This is a more preferable configuration of the present invention for avoiding enlargement.

FIG. 7 shows an embodiment in which erasure error correction is performed in the second error code detection and correction processing.
In the first error detection / correction processing circuit (first error correction decoder circuit) 313, an error block flag 328 is set for the decoded code sequence blocks 311a, 311b, 311c,. publish. The error pointer generation circuit 329 receives this error block flag 328 and takes into account the code processing unit of the recording code demodulation processing in the demodulation processing circuit 315, and decodes the error decoding code sequence block 311 indicated by the error block flag 328.
For the code or the information symbol 327 corresponding to a, 311b, or 311c, the information symbol 327 or the code output from the demodulation processing circuit 315 is synchronized with the information symbol 327 or the information symbol 327 to generate an error event. An erroneous symbol / error code erasure pointer 330 indicating that the pointer may be included is issued. The second error detection / correction processing circuit (second error correction decoder circuit) 318 performs erasure error correction on the information symbol 327 or code indicated by the error symbol / error code erasure pointer 330. This effectively improves the error correction capability in the second error code detection and correction process.

As described in the previous embodiments, the information recording / reproducing method and the recording / reproducing apparatus using the error correction coding provided by the present invention utilize the characteristics of the decoding error by the maximum likelihood sequence decoder 310. , By providing error correction coding and error code detection and correction processing specialized for a decoding error pattern sequence (code error syndrome) of a specific high-frequency error event,
Improve decoding reliability. The decoded error pattern sequence (code error syndrome) takes a different form depending on the transfer characteristics of the target recording / reproducing channel 306 and the constraint conditions added to the channel recording code sequence 305 due to encoding / modulation processing. Will be. As described in the principle of the present invention, many high-density magnetic recording / reproducing channels include the class 4 extended partial response (EPR4) channel of the binary transmission code sequence shown in FIG. Partial response characteristic polynomial G (D) = (1
Binary code recording partial response channels represented by -D) (1 + D) F (D), where D is a one-bit delay operator and F (D) is an arbitrary characteristic polynomial, are often applied. .
When recording / reproducing by assigning a binary information code to a binary signal level on a recording signal sequence, such a partial response channel generally has a transmission frequency characteristic as shown in FIG. , DC frequency component and maximum recording frequency (recording / reproducing code transmission required band, transmission Nyquist frequency, recording / reproducing code transmission frequency 1
/ T), which allows transmission characteristics suitable for high-density magnetic recording / reproducing channels that require low-frequency cutoff characteristics and narrow-band transmission frequency characteristics. ing. In this kind of partial response channel, a class 4 type channel configuration represented by a characteristic polynomial G (D) = (1-D) (1 + D) ⁿ (natural number n) is actively applied to a magnetic disk device or the like. When n = 1, the PR4 channel is used, and when n = 2, the extended PR4 (EP4
The R4) channel, where n = 3, is called an extended EPR4 channel, and matches very well with a high-density magnetic recording / reproducing channel whose band is limited. In a recording / reproducing channel in which information is recorded at a high frequency or a high recording density,
Applying a class 4 type partial response channel channel characteristic in which the high-frequency degradation of the signal transmission frequency characteristic is extremely large, and as shown in FIG. By choosing to
It is possible to realize a recording / reproducing channel which is less affected by high-frequency degradation.

Such a partial response channel is the recording / reproducing channel 3 in the embodiment of FIG.
05, mainly for the reproduction signal processing system 306e (high-frequency cutoff)
This is realized by adjusting the filter circuit 308a and the equalization processing circuit 308e. Then, the recording / reproducing channel 30 realizing this kind of partial response channel characteristic
In No. 6, the recording signal sequence A331a having only a DC frequency component (corresponding to a non-inverted continuous code sequence having the same level code value) and the maximum recording frequency (from the null frequency characteristic on the transmission frequency characteristic shown in FIG. (Transmission Nyquist frequency, 1/2 of recording / reproducing code transmission frequency 1 / T), ie, a recording signal sequence B331b (corresponding to a continuous inversion code sequence of binary level code values) whose signal level is continuously inverted at the recording / reproducing operation frequency of the channel. Is applied as a recording signal sequence 306f and recorded / reproduced, a zero-value continuous signal sequence appears in any case in the reproduction signal sequence (decoded signal sequence 311) at the output of the recording / reproduction system channel 306. It has the feature of.

When the decoded signal sequence 311 output from such a recording / reproducing system channel 306 is decoded by using the maximum likelihood sequence decoder 310, a representative example of the class 4 extended partial response (EPR4) channel is described above. As shown, the reproduced signal sequence (decoded signal sequence 311) is generated due to the common channel state transition structure.
The distance between signals (square Euclidean distance) becomes small,
A high-frequency decoding error pattern sequence (code error syndrome) concentrates on a sequence of consecutive inversion code errors of a binary level code value having a code length of 1 bit or more. That is, according to the above-described notation of the decoding error pattern sequence (code error syndrome), an n-bit continuous inverted code error pattern sequence (n-bit continuous inverted code error syndrome) 332 having an n-bit (n is a natural number) continuous error code is used. Is
"... 0 0 +1 -1 +1 ... 0 0 ..." (underlined portions indicate n-bit continuous inversion code positions of +1 -1 +1 ...). FIG.
(B) shows an example of a code error event (in the case of n = 4) according to an n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332, which is composed of two channel recording codes. Sequence A332a and channel recording code sequence B332b (two channel recording signal patterns A333a and recording signal pattern B333 applied as recording signal sequence 306f when recording these)
This is a code error event that occurs mutually between b). (On the decoded code sequence 311, the channel recording signal pattern A 33
3a is erroneously decoded as the channel recording signal sequence B332b or the channel recording code sequence A332a is decoded as the channel recording code sequence B332b. In the recording / reproducing system channel 306, the frequency of occurrence of each code error event with respect to the code length n of the continuous error changes under the influence of the correlation characteristics and statistical characteristics such as noise which may cause a decoding error. A code error event of an n-bit continuous inversion code error pattern sequence 332 (n-bit continuous inversion code error syndrome) 332 having a relatively short code length n, for example, "... 0 + 10 ...", up to about 3 bits in code length. … 0 +1 -1 0… ”,“… 0 +
1 -1 +1 0...) Becomes dominant in the probability of occurrence.

Therefore, the recording / reproducing channel 30
6, an error event of a continuous inversion code sequence having a predetermined code length of n bits (n = 1, 2, 3 bits in the above example) (a binary code decoding error according to the n-bit continuous inversion code error pattern sequence 332). Event), the first error correction encoding process / error code detection / correction process
First error correction encoding circuit (first error correction encoder) 3
04 and the first error code detection / correction processing circuit (first error correction decoder) 313, correction is performed from a decoding error event having a high occurrence probability, and effective improvement in decoding reliability can be achieved.

As described above, in this embodiment, in the first error correction coding circuit (first error correction encoder) 304, the error check redundant code sequence (first Error correction code sequence) 303 is a decoding error event (n) of a binary level code value continuous inversion code sequence having a predetermined code length of n bits (n = 1, 2, 3 bits in the above example).
The binary code decoding error event according to the bit continuous inversion code error pattern sequence 332) is
02a, 302b, 302c... Are corrected to a predetermined number i or less (i is a natural number, in many cases, a plurality of code lengths n are set and one of each error event is one) or less. The first error code detection / correction processing circuit (first error correction decoder) 313 outputs a decoded code sequence 311
, Using the above-mentioned error check redundant code sequence (first error correction code sequence) 303, and using the above-mentioned binary level having a code length of n bits or less (n = 1, 2, 3 bits in the above example) or less. The decoding error event of the code value continuous inverted code sequence (binary code decoding error event according to the n-bit continuous inverted code error pattern sequence 332) is transmitted to each of the recording code sequence blocks 302a,
02b, 302c... Are detected and corrected to the predetermined number i or less (one of one of the error events having the set plural code lengths n). Further, the code length of each of the recording code sequence blocks 302a, 302b, 302c,... Sets a code length at which a desired improvement in the decoding reliability is obtained from the actual decoding reliability of the maximum likelihood sequence decoder 310. For example, from the decoding error probability of the maximum likelihood sequence decoder 310, the average number of occurrences of the decoding error event is determined by the respective recording code sequence blocks 302a and 302.
b, 302c... (decoded code sequence blocks 311a, 31
1b, 311c...), The codes of the recording code sequence blocks 302a, 302b, 302c. If the length is set, decoding reliability can be improved. When correcting the decoding error event of the binary level code value continuous inversion code sequence over a plurality of recording code sequence blocks 302a, 302b, 302c. As a predetermined code error pattern sequence (code error syndrome) set in one error correction encoding, it is necessary to set the code error pattern sequence (code error syndrome) including a partial sequence thereof. In the present embodiment, a subsequence of a predetermined inverted code error pattern sequence (continuous code error syndrome) of a predetermined code length n = 1, 2, 3 bits is also included in this.

In the present embodiment, the decoded code sequence 311 output from the maximum likelihood sequence decoder 310, like the channel recording code sequence A 332a and the channel recording code sequence B 332b shown in FIG. Signal sequence 30
6f is a code form in which a binary code is assigned to each of two recording signal levels (binary level code or NRZ
A recording code expression), and based on this code form, an n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is defined as a high-frequency code error pattern. This n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 is different when the code representation form of the decoded code sequence 311 is different (for example, the presence or absence of level inversion on the recording signal sequence 306f is changed to a binary code). In the case where some precoder processing is performed on the decoded code sequence 311 as described above, the decoded code sequence 31
On the other hand, in some cases, it is expressed as a different code pattern, but in any case, the code error pattern sequence (code error syndrome) expression is obtained by performing inverse conversion of the code expression and code processing on the decoded code sequence 311 in principle. FIG.
By converting to a representation of a binary level code value sequence error event on the recording signal sequence 306f as in (b), the n-bit continuous inverted code error pattern sequence (n-bit continuous inverted code error syndrome) of the present embodiment 332 can be checked. In the first error correction encoding process and the first error code detection / correction process described in the present invention, a set code error pattern sequence (code error syndrome) is represented by a code expression for such a decoded code sequence 311. The first error correction encoding process and the first error code detection / correction process are represented by a binary level code value sequence on the recording signal sequence 306f. And error correction coding and detection and correction processing for an error event equivalent to the above-described code error.

Next, an embodiment using the recording code modulation processing / recording code demodulation processing will be described. As apparent from FIG. 8B, the code error event of the n-bit continuous inverted code error pattern sequence (n-bit continuous inverted code error syndrome) 332 is a signal having a continuous recording / reproducing code period T on the recording signal sequence 306f. It can occur only in the sequence portion where the level inversion occurs (n-1) times or more. For example, the recording signal sequence 306
If the continuous signal level inversion of f is limited to a maximum of two times, as shown in FIG. 8 (b), n = 4-bit length or an n-bit continuous inversion code error pattern sequence 332 having a code length n longer than this. Error events cannot occur. From this,
By the recording code modulation processing in the encoding / modulation processing circuit 301, the recording signal sequence 306f is converted into the recording signal sequence 302 such that the maximum number of such continuous signal level inversions is limited to a predetermined number k (k is a natural number). By adding the code constraint condition, the maximum code sequence length n of the code error event of the n-bit consecutive inverted code error pattern sequence 332 (the n-bit continuous inverted code error syndrome) 332 having a high frequency of occurrence is calculated by (k +
1) It can be limited to: In this case, in the first error correction encoding circuit (first error correction encoder) 304, an error check redundant code sequence (first error correction code sequence) 303 configured for the recording code sequence 302 is (K +
1) From the limited code lengths of bits or less, select all or some of them as the predetermined code length n bits depending on the frequency of occurrence, and continuously invert the binary level code value of the predetermined code length n bits The decoding error event of the code sequence (binary code decoding error event according to the n-bit continuous inverted code error pattern sequence 332) is transmitted to each recording code sequence block 302.
a, 302b, 302c,... are corrected to a predetermined number i or less (i is a natural number, in most cases, one of each error event). Further, the first error code detection / correction processing circuit (first error correction decoder) 313 uses the above-described error check redundant code sequence (first error correction code sequence) 303 for the decoded code sequence 311. , The predetermined code length n bits (in the above example, a 3-bit code length)
The following binary level code value decoding error event of the continuous inverted code sequence (a binary code decoding error event according to the n-bit continuous inverted code error pattern sequence 332) is performed in each of the recording code sequence blocks 302a, 302b, 302c,. A process for detecting and correcting the number to a predetermined number i or less (one of each error event is the same as above) is performed. Recording signal sequence 306f
Is limited to 2, the n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 with a high occurrence frequency
Is limited to a length of 3 bits or less at most, so that the first error correction coding / error detection / correction for all or a part of the data may be performed. Such an embodiment is effective for simplifying the encoding and correction processing.

As is apparent from FIG. 8B, under the code constraint condition that the maximum number k of continuous recording signal level inversions is limited to 3, the channel recording code sequence A332a
If a decoding error occurs in the channel recording code sequence B332b from, the recording signal pattern B333b clearly goes against this, and this decoding error can be avoided. If this code constraint condition is considered for the decoded code sequence 311, the maximum code sequence length n of the continuous inverted code error pattern sequence to be generated can be limited to k = 3 or less. In the maximum likelihood sequence estimation processing in the maximum likelihood sequence decoder 310, a code constraint on the maximum number k of successive recording signal level inversions added in the recording code modulation is considered, and a decoding code sequence 311 that is inappropriate for the maximum likelihood is determined. It can be easily excluded from the sequence estimation candidates and output. At this time, the maximum code sequence length n of the n-bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome) 332 having a high occurrence frequency can be limited to k or less, and the first error correction coding / Error events that can be subjected to error detection and correction can be further limited.

As another embodiment using the recording code modulation processing / recording code demodulation processing, there is a method of applying a code constraint condition to the recording code sequence 302 in a time-varying or periodic manner. This is a method of providing a constraint condition only for the pattern of the recording code sequence 302 starting from a certain code time on the recording code sequence 302, or relaxing the constraint condition. For example, a 4-bit continuous inversion code error When the pattern sequence is to be eliminated by the recording code modulation process and the first error detection and correction process, only the maximum number k of continuous recording signal level inversions starting from a code time taking a certain period on the recording code sequence 302 is set to 4 Maximum number k of continuous recording signal level inversions that are allowed and start from other code times
Is limited to 3. As described above, when the decoded code sequence that does not satisfy the constraint conditions is to be eliminated from the candidates by the maximum likelihood sequence decoder 310, the decoded code sequence 311 also performs The occurrence of a code error of a 4-bit continuous inversion code error pattern sequence is allowed only at a limited number of four consecutive code points corresponding to the code time of the cycle of the above, and at four consecutive code points corresponding to other code times, Its occurrence is limited.
Accordingly, the first error correction for correcting the error of the 4-bit continuous inversion code error pattern sequence is performed only at the periodically limited code points where the 4-bit continuous inversion code error pattern sequence can occur. Encoding and error code correction processing is performed. In this way, by relaxing the constraint condition in a time-varying and periodic manner, the burden of adding code redundancy in the recording code modulation process can be reduced, and this can be compensated for by the first error correction coding / error code correction process. Thus, the overall decoding reliability of the recording / reproducing system is increased.

Further, as is apparent from FIG.
The decoding error event of the binary level code value continuous inversion code sequence (the n-bit continuous inversion code error pattern sequence 33
2 is a recording code sequence 30).
2 and the decoded code sequence 311, it is apparent that the error occurs only at the code position where the continuous recording signal level inversion occurs. Therefore, the recording code sequence 302 and the decoded code sequence 311 are referred to and Can be limited to a position where a decoding error event of the continuous inverted code sequence can occur. FIG.
(A) shows a configuration for performing this. In a recording process, a location of a specific code sequence pattern where a predetermined code error syndrome can occur is checked with reference to the recording code sequence 302. Pattern matching circuit 334, a code sequence pattern pointer 335 for indicating the code position of the collated code sequence pattern, and a first error correction code for the code error syndrome in response to the information of the code sequence pattern pointer 335. A coding pointer 337 for designating a code position to be converted and a coding pointer generating circuit 336 for generating the coding pointer 337 are provided. First error correction encoding circuit (first error correction encoder circuit) 30
4, the encoding pointer 337 on the recording code sequence 302
Performs the first error correction coding on the code error syndrome for the code position indicated by. In the reproduction process, similarly, a code sequence pattern matching circuit 334 for matching a specific code sequence pattern where a predetermined code error syndrome can occur with reference to the decoded code sequence 311, A code sequence pattern pointer 335 that indicates the code position of the pattern, a correction pointer 339 that receives the information of the code sequence pattern pointer 335, and indicates the target code position of the first error code detection and correction process for the code error syndrome, A generated correction pointer generation circuit 338 is provided. First error code detection and correction circuit (first error correction decoder circuit) 3
13, the correction pointer 339 on the decoded code sequence 311
Performs a first error code detection and correction process on the code error syndrome for the code position indicated by.
The above embodiments of the present invention may be those that only implement the means of the recording process for the first error correction coding, or those that implement only the means of the reproduction process for the first error code detection and correction processing. These can simplify the configuration of the first error correction coding or the first error code detection and correction processing or improve the error correction accuracy.

Further, the recording / reproducing channel 30 of the signal transfer characteristic having the characteristics described above with reference to FIG.
6, that is, in a recording / reproducing system channel generally represented by the above-described transmission polynomial G (D), as shown in FIG. 8C, a single isolated signal level inversion 340 of the recording signal sequence 306f is performed. It is more preferable that the response signal waveform at the output of the reproduction signal processing system 306e is intentionally imparted with phase distortion and tilted back and forth in time to become an asymmetric shape response signal 341. Usually, a widely used characteristic polynomial G (D)
= (1-D) (1 + D) ⁿ Each of the class 4 type partial response channels represented by ⁿ (natural number n) has a symmetric response signal shape. Thus, the code length of the n-bit continuous inverted code error pattern sequence 332 (the n-bit continuous inverted code error syndrome) 332 occurring at a high frequency can be stochastically and relatively shortened. This is because the combination of code sequences in which the Euclidean distance between the reproduced signal sequences is small is stochastically reduced due to the asymmetry, and this fact indicates that the first error correction coding error in the implementation of the present invention. This is more preferable in improving the correction effect and simplifying the realization. Such an asymmetric response signal waveform is supplied to the recording / reproduction system channel 305 mainly by the (high-frequency cutoff) filter circuit 308a and the equalization processing circuit 30 of the reproduction signal processing system 306e.
8e, which can be realized by making the response signal waveform at the output of the reproduction signal processing system 306e for the inversion of the isolated recording signal level close to the minimum phase transition waveform characteristic of the response signal waveform in the reproduction signal sequence 306g. And FIG.
As shown by the asymmetrical shape response signal channel characteristic 342 in FIG. 7A, the target recording / reproducing channel 3 is compared with the class 4 type partial response channel described above.
This can be achieved while achieving better matching with the transmission frequency characteristic of the signal line 06. In a high-density magnetic recording / reproducing apparatus, a fourth-order transfer polynomial of a partial response channel suitable for realizing this is G (D) = (1-D)
(1 + D) (5 + 4D + 2), which have the same number of channel memories as the extended EPR4 channel, and are decoded by the maximum likelihood sequence decoder 310 of the same scale.

Further, in the recording / reproducing apparatus and the recording / reproducing system, the decoding error characteristic of the maximum likelihood sequence decoder 310 depends on the recording / reproducing apparatus / condition and the use environment condition and various disturbance factors. Or, it often changes over time. Also, in an actual recording / reproducing apparatus or system, an unexpected unique decoding error event may often occur due to a nonlinear physical phenomenon or the like. In a recording / reproducing apparatus or a recording / reproducing system in which the decoding error characteristic may vary, a predetermined decoding code error pattern (code error syndrome) set in the first error correction coding / error code detection / correction processing is previously determined. It is not preferable to use a fixed one. A plurality of predetermined decoding code error patterns (code error syndromes) to be set are facilitated, statistical information of decoding error characteristics in an actual recording / reproducing apparatus or recording / reproducing system is collected, and this is appropriately selected. It is desirable to use.

FIG. 9B shows an embodiment in this case and a fifth basic embodiment of the present invention. In this embodiment, a code error syndrome detection circuit 343 for detecting a code error and a decoded code error pattern (code error syndrome) on the decoded code sequence 311 output from the actual maximum likelihood sequence decoder 310 is provided. The decoding code error syndrome detection circuit 343 collates the known channel recording code sequence 305 with the decoding code sequence 311 output by recording and reproducing the recording code sequence 30 by the target recording / reproducing channel 306, A decoding error is detected, and a decoding code error pattern (code error syndrome) is determined. The method of discriminating the event of each decoded code error pattern (code error syndrome) is as described above, and the pattern of the determined code error syndrome is output and instructed by the syndrome output signal 344. The code error syndrome totalization circuit 345 counts the frequency of occurrence of the code error syndrome indicated by the syndrome output signal 344, and, via the selection signal 346 and the selection circuit 347, responds to the first error corresponding to the code error syndrome having a high frequency of occurrence. An error correction encoding circuit (first error correction encoder circuit) 304 and a first error detection / correction processing circuit (first error correction decoder circuit) 313 are selected from a plurality of pieces, and are selected as actual information. Used in recording / playback processing. The change of the code error syndrome in the encoding / correction processing is performed by selecting a circuit means corresponding to the plurality of code error syndrome processing candidates set in advance as shown in FIG. Or a first error correction encoding circuit (first error correction encoder circuit) 30 corresponding to the code error syndrome processing selected by the code error syndrome totalization circuit 345.
4 and the encoding / correction processing configuration in the first error detection / correction processing circuit (first error correction decoder circuit) 313 may be logically or programmatically changed. By providing the above means, the known channel recording code sequence 302 is used as a test code sequence at the time of production of a recording / reproducing apparatus or a recording / reproducing system, or before an information recording / reproducing operation is started or during an idle period during the operation. Giving,
By performing the above-described optimization operation, the first error correction encoding / error code detection / correction processing can be more effectively performed in an actual recording / reproducing apparatus.

As described above, any of the embodiments of the present invention can be easily configured using the existing digital circuit technology, and this can be mounted on a single integrated circuit or divided into a plurality of integrated circuit groups. A high-speed, small-sized and low-power information recording / reproducing circuit can be provided. An information recording / reproducing circuit realized in a form mounted on such an integrated circuit can be easily mounted on a small-sized portable recording / reproducing apparatus which requires higher density recording, and has high reliability in data demodulation. Can be provided. Further, in the embodiment of the present invention, the information recording and reproducing method and the recording and reproducing circuit and device,
The recording process (recording circuit, recording device), the reproducing process (reproducing circuit, reproducing device), and the recording medium are described in an integrated form, but this is not a configuration requirement for implementing the present invention.
Each of them may be configured independently, and it is sufficient if they can be integrated in function as described in the present embodiment. Each of the recording process (recording circuit, recording device), the reproducing process (reproducing circuit, reproducing device), and the recording medium in which the present invention is implemented includes a first error correction encoding process (encoding circuit, code). Means, a first error code detection and correction process (correction circuit, correction means), a first error correction code sequence, and the like are separately included. The implementation of the present invention is clear, and the functions of the present invention realized when the components are integrated are also clear.
In particular, when the present invention is mounted on a semiconductor integrated circuit, there are various realization modes in which the configuration requirements of the present invention are separately mounted on a plurality of integrated circuit groups because of the convenience of integration with other realized functions. Can be taken. The scope of the invention includes the described features of the invention and separately configured recording processes (recording circuits, recording devices), reproducing processes (reproducing circuits, reproducing devices),
It includes a recording medium or any other separated configuration.

[0078]

As described above, it is possible to improve the decoding reliability of the decoding process based on the maximum likelihood sequence detection by using simple circuit resources and an error correction code having a low redundancy.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first basic embodiment of the present invention.

FIG. 2 is a diagram for explaining a flow of a code sequence in the first basic embodiment.

FIG. 3 is a diagram showing a second basic embodiment of the present invention.

FIG. 4 is a diagram showing a third basic embodiment of the present invention.

FIG. 5 is a diagram for explaining a flow of a code sequence in the third basic embodiment.

FIG. 6A is a diagram for explaining a recording code form of a recording frame according to the present invention.

FIG. 6b is a diagram illustrating an example for describing a recording code form of an information code frame according to the present invention by n-interleaving processing.

FIG. 6c is a diagram showing another example for describing the recording code form of the information code frame in the present invention by the n interleaving process.

FIG. 7 is a diagram showing a basic embodiment of the present invention using erasure error correction processing.

FIG. 8A is a view showing a channel response frequency characteristic of a partial response recording / reproducing system.

FIG. 8b is a diagram showing an n-bit continuous inversion code error event in a binary partial response recording / reproduction channel.

FIG. 8C is a diagram showing a waveform of a reproduction response signal with respect to inversion of an isolated recording signal level.

FIG. 9a shows a fourth basic embodiment of the present invention.

FIG. 9b shows a fifth basic embodiment of the present invention.

FIG. 10a is a diagram showing a flow of an information sequence in an information transmission system or a recording / reproducing system.

FIG. 10b shows an EPR4 partial response runway channel model.

FIG. 10c is a state transition diagram (binary code transmission sequence EPR4 transmission channel).

FIG. 10D shows a trellis transition at time k (2
Hex code transmission sequence EPR4 transmission path channel).

FIG. 10E is a diagram showing a path transition to each state at time k (binary code transmission sequence EPR4 transmission channel).

FIG. 10f is a diagram showing an example of a state transition path from time k to k + 4 (binary code transmission sequence EPR4 transmission channel)
It is.

FIG. 11A is a diagram for describing specific components that implement a Viterbi decoding process.

FIG. 11B is a diagram showing a configuration of a maximum likelihood decoder (maximum likelihood sequence decoder, Viterbi decoder) based on the Viterbi algorithm.

FIG. 12 is a trellis diagram (binary code transmission sequence E
PR4 transmission channel).

FIG. 13A is a first trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.

FIG. 13B is a second trellis diagram (binary code transmission sequence EPR4 transmission channel) for explaining the relationship between the normal path sequence and the error path sequence in the maximum likelihood decoding process.

[Explanation of symbols]

100: transmission code sequence, 101: information transmission system, 102:
Encoder 103, modulator 104, channel 105
Additional noise, 106: received signal processing circuit, 107: received (decoded input) signal sequence, 108: maximum likelihood sequence decoder, 109: decoded code sequence, 110a, 110b, 11
0c... 1-bit delay storage element, 111a, 111b, 1
11c: addition / subtraction operation element, 112: path sequence, 112a,
112b state transition path (path branch), 113 survival path sequence, 114 determined maximum likelihood path sequence, 115
Normal path sequence, 116: error path sequence, 117: error path selection, 119: decoded error pattern sequence, 121a: 1
Bit decoding error pattern, 121b ... 3-bit code error pattern, 122 ... error path selection detection position, 200a ...
Branch metric operation unit, 200b ... ACS operation unit,
200c: path memory unit, 201: square error calculation circuit,
202a to 202h: metric storage circuit, 203: metric accumulation circuit, 204: comparator, 205: selection signal, 206: metric selection circuit, 207a to 207
h: path history storage circuit, 208, 208a to 208h ...
Path history selection circuit, 300 ... information code sequence, 300a ...
Information code sequence (1), 301... Coding / modulation processing circuit,
. 302 recording code sequence, 302a, 302b, 302c...
Recording code sequence block, 303... Error check redundant code sequence (first error correction code sequence), 303a, 303b, 3
03c: error check redundant code sequence (first error correction code sequence), 304: first error correction coding circuit (first error correction encoder circuit), 304a: error correction code sequence generation circuit, 304b: error Correction code string insertion circuit 305: channel recording code sequence 306: recording / reproducing system channel 306a
... Recording signal processing system, 306b ... Recording head, 306c ...
Recording medium, 306d playback head, 306e playback signal processing system, 306f recording signal sequence, 306g playback signal sequence, 307a code processing circuit, 307b code signal conversion circuit, 307c recording signal processing circuit, 307d recording Signal amplifier, 308a reproduced signal amplifier, 308b ... variable gain amplifier circuit, 308c ... (high-frequency cutoff) filter circuit,
308d: sampling circuit (analog / digital converter), 308e: equalization processing circuit, 308f: timing reproduction / gain control circuit, 308g: gain control signal, 308
h: sample timing control signal, 309: decoded signal sequence, 310: maximum likelihood sequence decoder, 311: decoded code sequence, 311a, 311b, 311c: decoded code sequence block, 312, 312a, 312b, 312c: decoding error check redundancy Code sequence (first error correction code sequence), 31
3 ... first error detection and correction processing circuit (first error correction decoder circuit), 313a ... code error check and correction circuit, 313b
... Error check redundant code sequence removing circuit, 314 ... correction decoding code sequence, 315 ... demodulation processing circuit, 316 ... reproduction code sequence, 316a ... reproduction code sequence (1), 317 ... second error correction encoding circuit (second Error correction encoder circuit), 31
8 ... second error detection / correction processing circuit (second error correction decoder circuit), 319, 319a, 319b, 319c ... information code frame, 320, 320a, 320b, 320
c: error check redundant code sequence (second error correction code sequence),
328a: error check redundant code sequence A (second error correction code sequence), 328b ... error check redundant code sequence B (second error correction code sequence), 328c: error check redundant code sequence C (second error correction) Code sequence), 328d ... error check redundant code sequence D (second error correction code sequence), 321, 321a,
321b, 321c ... recording code frames 322, 322
a, 322b, 322c ... error check redundant code conversion sequence (second error correction code sequence), 328a ... error check redundant code conversion sequence A (second error correction code sequence), 328b ... error check redundant code conversion sequence B (Second error correction code sequence), 3
28c: error check redundant code conversion sequence C (second error correction code sequence), 328d: error check redundant code conversion sequence D (second error correction code sequence), 323, 323a, 323b,
323c: decoded code frame, 324, 324a, 32
4b, 324c... Decoding error check redundant code conversion sequence (second error correction code sequence), 325, 325a, 325b, 3
25c ... reproduced code frame, 326, 326a, 326
b, 326c: decoding error check redundant code sequence (second error correction code sequence), 327: information symbol, 328: error block flag, 329: error pointer generation circuit, 330
... Error symbol / error code erasure pointer, 331a ... Recording signal sequence A, 331b ... Recording signal sequence B, 332 ... n
Bit continuous inversion code error pattern sequence (n-bit continuous inversion code error syndrome), 332a ... channel recording code sequence A, 332b ... channel recording code sequence B, 333
a: recording signal pattern A, 333b: recording signal pattern B, 334: code sequence pattern collation circuit, 335: code sequence pattern pointer, 336: encoding pointer generation circuit, 337: encoding pointer, 338 ... correction pointer generation circuit, 339: Correction pointer, 340: Isolated signal level inversion, 341: Asymmetric shape response signal, 342: Asymmetric shape response signal channel characteristics, 343: Code error syndrome detection circuit, 344: Syndrome output signal, 345
... Code error syndrome summation circuit, 346 ... Selection signal,
347: selection circuit, 348a: multiplexer circuit (code sequence selection circuit), 348b: demultiplexer circuit (code sequence selection circuit), 349: recording frame (information coding section), 349a: preamble, 349b: postamble.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03M 13/12 H03M 13/12

Claims (81)

[Claims] An information code sequence is recorded on a recording medium, and a reproduction signal sequence from the recording medium is subjected to a maximum likelihood sequence estimation method (a maximum likelihood sequence decoding / detection method, a maximum likelihood decoding method, a Viterbi decoding method). In the information recording / reproducing method for decoding / reproducing the information code sequence, (1) the information code sequence having a predetermined code length which is continuously decoded by the maximum likelihood sequence estimation method is included in the recorded information code sequence. The first error correction coding is performed in units of sequences (recording code sequence blocks), or a first error correction code sequence corresponding to each of the recording code sequence blocks is configured, and The error correction coding and the configuration of the first error correction code sequence are performed by a predetermined code set in advance in the recording code sequence block and the error correction code sequence decoded by the maximum likelihood sequence estimation method. Error (2) first code error detection and correction (first code error detection and correction processing) to detect occurrence of a specific number of code error events having a predetermined number (code error syndrome) up to a predetermined number. The error correction code sequence is divided or collectively recorded at a predetermined recording position corresponding to the recording code sequence block on the recording medium or a recording medium different from the recording medium, and is decoded and decoded together with the information code sequence. The first error correction code sequence to be reproduced, or the first error correction code sequence is divided or collectively inserted / added at a predetermined code position immediately before, immediately after, or inside the recording code sequence block on the recording medium. (3) The information code sequence decoded from the recording medium by the maximum likelihood sequence estimation method is processed by the recording code sequence block. An information recording / reproducing method, wherein a first error correction coding or a first code error detection / correction process using the first error correction code sequence decoded together is performed as a unit. . 2. In the code position of each error code indicated by the code error pattern (code error syndrome), a normal information code for the error code or a difference between the error codes can be distinguished from each other. The information recording / reproducing method according to claim 1, wherein: 3. The information code sequence decoded by the maximum likelihood sequence estimation method is subjected to a first code error detection and correction process without logically changing the code order on the information code sequence. 2. The information recording / reproducing method according to claim 1, wherein: 4. The information code sequence to be recorded, before the first error correction coding and the first error correction code sequence in the above (1), is configured by a first recording code modulation process by a predetermined recording code modulation process. A code sequence conversion process is performed, and the information code sequence decoded from the recording medium by the maximum likelihood sequence estimation method is subjected to the first error code detection and correction process in (3) above. 2. The information recording / reproducing method according to claim 1, wherein a second code sequence conversion process is performed by a predetermined recording code demodulation process corresponding to the recording code modulation process. (4) The information code sequence to be recorded is recorded by the information recording / reproducing method before the first error correction coding and the first error correction code sequence in (1). A continuous processing unit (recording frame) of the information code sequence in the reproduction process or a code sequence unit corresponding to a plurality of the recording code sequence blocks as a unit (information code frame) of the second code error detection and correction process; A second error correction encoding is performed, or a second error correction code sequence corresponding to each of the information code frames is formed, and (5)
The second error correction code sequence is divided or collectively recorded at a predetermined recording position corresponding to the information code frame on the recording medium or a recording medium different from the recording medium, and the information code sequence Or the second error-correcting code sequence, before the configuration of the first error-correcting coding and the first error-correcting code sequence in the above (1), In addition, divided or collectively inserted / added and recorded at a predetermined code position immediately before / after or inside the information code frame, and decoded / reproduced together with the information code sequence, (6)
The information code sequence decoded from the recording medium by the maximum likelihood sequence estimation method is subjected to the first code error detection and correction processing in the above (3), and then the information code frame is processed in units of: 2. The information according to claim 1, wherein a second code error detection / correction process using the second error correction coding or the second error correction code sequence decoded together is performed. Recording and playback method. 6. The information code sequence to be recorded includes the second error correction code and the second error correction code sequence in (4) or the second error correction code in (5). After the insertion / addition of the correction code sequence, the first code sequence conversion process is performed, and the information code sequence decoded from the recording medium by the maximum likelihood sequence estimation method includes the second code sequence in (6). 6. The information recording / reproducing method according to claim 5, wherein a second code sequence conversion process is performed before the error code detection / correction process is performed. 7. The recording code sequence block is obtained by dividing the recording frame, and each first error correction code sequence corresponds to the recording code sequence block on the information code sequence. The recording medium is characterized by being divided or collectively inserted / added to a predetermined code position or a corresponding code position immediately before, immediately after, or inside the recording code sequence block, and recorded on the recording medium. 1. The information recording / reproducing method according to 1. 8. The information recording / reproducing method according to claim 5, wherein the recording code sequence block is obtained by dividing the recording frame, and each first error correction code sequence is On the code sequence, the recording medium is divided or collectively inserted / added at a predetermined code position corresponding to the recording code sequence block, or at a corresponding code position immediately before, immediately after, or inside the recording code sequence block, and And a second error correction code sequence is recorded on the information code sequence at a predetermined code position corresponding to the recording frame, or at a corresponding code position immediately before, immediately after, or inside the recording frame. , Split or insert all at once
6. The information recording / reproducing method according to claim 5, wherein the information is added and recorded on the recording medium. 9. The information code frame is regarded as an information symbol sequence having a continuous code sequence (information symbol) having a predetermined code length as a unit, and the second error correction coding and the second error correction coding in (6) are performed. The structure of the error correction code sequence of is independent of n independent information symbol sequences (n is a natural number) obtained by dividing the information code frame by interleaving using the information symbol as a division processing unit. ,
And the second code error detection and correction processing in the above (4) uses the information symbol as an error detection and correction processing unit. The information recording / reproducing method according to claim 5, wherein the information recording / reproducing method is performed independently. 10. The information recording / reproducing method according to claim 9, wherein said recording code sequence block is composed of a natural number of said information symbols physically and continuously recorded on said recording medium. 11. The recording code sequence block according to claim 4, wherein the recording code sequence block is composed of a first code sequence conversion process or a natural number of code sequences serving as a minimum processing unit in the first code sequence conversion process. Also, in the information recording / reproducing method described in 5, the information recording / reproducing method. 12. The information recording / reproducing method according to claim 5, wherein a code error is detected in the first code error detection and correction processing of (3), and the code error correction is determined to be impossible. 6. The information recording / reproducing method according to claim 5, wherein the code or information symbol belonging to the block is subjected to an erasure code error correction process by the second code error detection and correction process in (6). 13. The information recording / reproducing method according to claim 1, wherein the first error correction coding and the first error correction code sequence in the above (1) are configured as follows: Referring to the information code in the recording code sequence block, a code position in the recording code sequence block corresponding to a predetermined information code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) is referred to. Or the first code error detection and correction processing in the above (3) is performed on the information code sequence decoded by the maximum likelihood sequence estimation method. A predetermined code error pattern (code error syndrome) set with reference to the decoded code in the sequence block
2. The information recording / reproducing method according to claim 1, wherein the method is applied only to the decoded code in the recording code sequence block at a code position that matches a predetermined decoded code sequence pattern corresponding to the information. . 14. The information code sequence recorded in the first code sequence conversion process by the recording code modulation process includes a predetermined code error pattern (code error syndrome) set only at a predetermined information code position. ) Is added, and the first error correction encoding and the configuration of the first error correction code sequence in the above (1) are recorded. In the recording code sequence block on the information code sequence,
The information code at the predetermined information code position is applied so that a specific code error event having the predetermined code error pattern (code error syndrome) can be detected and corrected. The first error code detection / correction processing is performed by using the first error correction coding or the first error correction code sequence, and applying the first error correction code sequence to the information code sequence decoded by the maximum likelihood sequence estimation method. In the recorded code sequence block, only the decoded code corresponding to the predetermined information code position is subjected to a specific code error event detection and correction process having the predetermined code error pattern (code error syndrome). 6. The information recording / reproducing method according to claim 4, wherein the information recording / reproducing method is performed. 15. The information recording / reproducing method according to claim 4, wherein the information code sequence recorded in the first code sequence conversion process by the recording code modulation process includes a predetermined information code position only. A code constraint condition allowing the appearance of a predetermined information code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) is added, and the first error correction coding and the first The configuration of one error correction code sequence is such that a predetermined code error pattern (code error) is applied only to the information code at the predetermined information code position in the recording code sequence block on the information code sequence to be recorded. The first error code detection and correction process in the above (3) is performed so that a specific code error event having a syndrome can be detected and corrected. The first error correction coding, or, using the first error correction code sequence, for the decoded code in the recording code sequence block on the information code sequence decoded by the maximum likelihood sequence estimation method That is, detection and correction processing of a specific code error event having a predetermined code error pattern (code error syndrome) is performed only on a decoded code corresponding to the predetermined information code position. The information recording / reproducing method according to claim 4 or 5, wherein: 16. The first error correction coding and the configuration of the first error correction code sequence in the above (1), or a predetermined error detection and correction process in the above (3). The code error pattern (code error syndrome) is obtained by recording and reproducing a predetermined information code sequence on the recording medium, decoding the information code sequence decoded from the recording medium by the maximum likelihood sequence estimation method, It is estimated by collating with the information code sequence, and among the estimated code error patterns (code error syndromes),
2. The information recording / reproducing method according to claim 1, wherein a predetermined number is selected from those having a predetermined frequency or higher or those having a maximum frequency and set. 17. A method for recording and reproducing a binary information code sequence on a recording medium using a recording signal sequence having a binary signal level, wherein (7) the recording signal sequence having only a DC frequency component. When a binary information code sequence (non-inverted continuous code sequence of the same level code value) is recorded / reproduced, and a binary information code sequence (binary level In the case of recording / reproducing a continuous inverted code sequence of code values, a signal transfer characteristic information recording / reproducing system which outputs a zero-value continuous signal sequence as a reproduced signal sequence input to the maximum likelihood sequence estimation method in each case. (8) For the binary information code sequence to be recorded, the first error correction coding and the configuration of the first error correction code sequence in (1) are decoded by the maximum likelihood sequence estimation method. Was done On a binary information code sequence, a code error event corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length is detected and corrected up to a predetermined number in the recording code sequence block. The first code error detection / correction processing is performed, or the first information in the above (3) is applied to the binary information code sequence decoded by the maximum likelihood sequence estimation method. The code error detection and correction processing is to detect and correct a predetermined number of code error events corresponding to continuous code errors of a binary level code value continuous inverted code sequence having a predetermined continuous code length. The information recording / reproducing method according to claim 1. 18. A method for recording and reproducing a binary information code sequence on a recording medium using a recording signal sequence having a binary signal level, wherein (9) the recording signal sequence having only a DC frequency component. When a binary information code sequence (non-inverted continuous code sequence of the same level code value) is recorded / reproduced, and a binary information code sequence (binary level In the case of recording / reproducing a continuous inverted code sequence of code values, a signal transfer characteristic information recording / reproducing system which outputs a zero-value continuous signal sequence as a reproduced signal sequence input to the maximum likelihood sequence estimation method in each case. (10) The recording code modulation process in the first code sequence conversion process is performed such that the maximum number of continuous signal level inversions on the recording signal sequence is limited to a predetermined number k (k is a natural number). And (11) adding the first error correction coding and the first error correction code sequence in (1) to the binary information code sequence to be recorded. The configuration is such that, on the binary information code sequence decoded by the maximum likelihood sequence estimation method, a binary level code value continuous inversion having a predetermined continuous code length of (k + 1) or less in the recording code sequence block. A code error event corresponding to a continuous code error of a code sequence is performed so as to enable a first code error detection and correction process for detecting and correcting a predetermined number of code error events, or the maximum likelihood sequence estimation method. The first code error detection and correction process in the above (3) is performed on the binary information code sequence decoded by (1), and the binary level code value continuous inversion code sequence having a predetermined continuous code length of (k + 1) or less. For consecutive code errors The code error events, and detects correction to a predetermined number,
The information recording / reproducing method according to claim 4 or 5, wherein: 19. The configuration of the first error correction coding and the first error correction code sequence in the above (8) to (11) is the same as that of the recording code sequence block on the recorded binary information code sequence. Is applied only to an information code at a code position that matches a binary level code value continuous inverted code sequence having a predetermined continuous code length, or (8) to (8). The first code error detection and correction process in 11) refers to a decoded code in the recording code sequence block on the binary information code sequence decoded by the maximum likelihood sequence estimation method, and has a predetermined continuous code length. 19. The information recording / reproducing method according to claim 17, wherein the method is applied only to a decoded code at a code position coinciding with a binary level code value continuous inverted code sequence. 20. The binary information code sequence recorded in the first code sequence conversion process by the recording code modulation process includes a binary level having a predetermined continuous code length only at a predetermined information code position. A code constraint condition allowing a code value continuous inversion code sequence is added, and the configuration of the first error correction coding and the first error correction code sequence in the above (11) is based on the binary information to be recorded. A code error event corresponding to a continuous code error of a binary level code value continuous inversion code sequence having a predetermined continuous code length with respect to an information code at a predetermined information code position in a corresponding recording code sequence block on a code sequence. And the first error code detection and correction processing in the above (11) is performed by the first error correction coding or the first error correction code sequence. Using In the corresponding recording code sequence block on the binary information code sequence decoded by the maximum likelihood sequence estimation method, only the decoded code corresponding to the predetermined information code position has a predetermined continuous code length. 19. The information recording / reproducing method according to claim 18, wherein a code error event corresponding to a continuous code error of the value-level code value continuous inversion code sequence is detected and corrected. 21. The binary information code sequence recorded in the first code sequence conversion process by the recording code modulation process includes:
At only a predetermined information code position, a code constraint condition allowing a binary level code value continuous inversion code sequence having a predetermined continuous code length is added, and the first error correction coding and the first error correction coding in (11) are performed. The configuration of one error correction code sequence has a predetermined continuous code length for only the information code at the predetermined information code position in the recording code sequence block on the binary information code sequence to be recorded. The code error event corresponding to the continuous code error of the value level code value continuous inversion code sequence is performed so that it can be detected and corrected, and the first error code detection and correction processing in the above (11) is One error correction encoding, or, using the first error correction code sequence, a predetermined recording code sequence block on the binary information code sequence decoded by the maximum likelihood sequence estimation method, The And performing a detection and correction of a code error event corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length only for a decoded code corresponding to a broadcast code position. The information recording / reproducing method according to claim 18, wherein 22. A reproduction signal sequence input to the maximum likelihood sequence estimation method from the recording / reproduction system when recording / reproducing the binary information code sequence with the recording signal sequence having only a single isolated signal level inversion. 19. The information recording / reproducing method according to claim 17, wherein the information recording / reproducing system having a signal transmission characteristic in which the response signal waveform has an asymmetric shape is used. 23. Recording means for recording an information code sequence on a recording medium, and a maximum likelihood sequence estimation unit (maximum likelihood sequence decoding / detection device, maximum likelihood decoder, Viterbi decoding) And (12) the information code sequence to be recorded is continuously decoded by the maximum likelihood sequence estimator. First error correction coding is performed in units of the information code sequence (recording code sequence block) having a predetermined code length, or a first error correction code sequence corresponding to each of the recording code sequence blocks is formed. First error correction encoding means is provided, and the configuration of the first error correction encoding and the first error correction code sequence by the first error correction encoding means is decoded by the maximum likelihood sequence estimator. The recorded code sequence In the lock and the error correction code sequence, detection and correction of occurrence of a predetermined number of specific code error events having a predetermined code error pattern (code error syndrome) set in advance (first code error detection Correction processing)
(13) The first error correction code sequence is divided or collectively recorded at a predetermined recording position corresponding to the recording code sequence block on the recording medium or a recording medium different from the recording medium, and It is decoded and reproduced together with the code sequence, or the first error correction code sequence is
On the recording medium, divided or collectively inserted / added and recorded at a predetermined code position immediately before, immediately after, or inside the recording code sequence block, and is decoded / reproduced together with the information code sequence, 14) The information code sequence decoded by the maximum likelihood sequence estimator from the recording medium is subjected to a first error correction encoding or a corresponding error code decoded together with the recording code sequence block as a processing unit. An information recording / reproducing apparatus, comprising: first error correction decoding means for performing a first code error detection / correction process using a first error correction code sequence. 24. At the code position of each error code indicated by the code error pattern (code error syndrome), it is determined that a normal information code for the error code or a difference between the error codes can be distinguished from each other. The information recording / reproducing apparatus according to claim 23, characterized in that: 25. The information code sequence decoded by the maximum likelihood sequence estimator is supplied to first error correction decoding means without logically changing the code order on the information code sequence, 24. The information recording / reproducing apparatus according to claim 23, wherein the information code sequence decoded and output from the maximum likelihood sequence estimator is directly input to first error correction decoding means. 26. The information code sequence to be recorded, before the first error correction coding and the construction of the first error correction code sequence in (12), is performed by a first recording code modulation process by a predetermined recording code modulation process. Code modulation processing means for performing code sequence conversion processing is provided before the first error correction coding means, and the information code sequence decoded from the recording medium by the maximum likelihood sequence estimator. After performing the first error code detection and correction processing in (14), a code demodulation for performing a second code sequence conversion processing by a predetermined recording code demodulation processing corresponding to the recording code modulation processing The information recording / reproducing apparatus according to claim 23, wherein the processing means is provided after the first error correction decoding means. (15) The information code sequence to be recorded is recorded by the information recording / reproducing apparatus before the first error correction coding and the first error correction code sequence in (12). A continuous processing unit (recording frame) of the information code sequence in the reproduction processing operation or a code sequence unit corresponding to a plurality of the recording code sequence blocks as a unit (information code frame) of the second code error detection and correction process. Performing the second error correction encoding, or forming a second error correction code sequence corresponding to each of the information code frames, the second error correction encoding means, the first error correction encoding means (16) The second error correction code sequence is divided or divided into predetermined recording positions corresponding to the information code frame on the recording medium or a recording medium different from the recording medium. And the information is recorded and reproduced together with the information code sequence. Alternatively, the second error correction code sequence is the first error correction code and the first error correction code in (12) above. Prior to the formation of a sequence, the information code sequence is divided or collectively inserted / added and recorded at a predetermined code position immediately before, immediately after, or inside the information code frame, and decoded / reproduced together with the information code sequence. (17) From the recording medium,
The information code sequence decoded by the maximum likelihood sequence estimator is subjected to the first code error detection and correction processing in (14), and then the second error correction code is set to the information code frame as a processing unit. , Or a second error correction decoding means for performing a second code error detection and correction processing using the second error correction code sequence to be decoded together, The information recording / reproducing apparatus according to claim 23, wherein the information recording / reproducing apparatus is provided. 28. The information code sequence to be recorded, after the second error correction coding and the construction of the second error correction code sequence in (15), or the second error correction code in (16). After the insertion / addition of the correction code sequence, a code modulation processing means for performing a first code sequence conversion process is provided after the second error correction coding means, and the code modulation processing means is provided from the recording medium. Code demodulation processing means for performing a second code sequence conversion process on the information code sequence decoded by the likelihood sequence estimator before performing the second error code detection and correction process in (17). 28. The information recording / reproducing apparatus according to claim 27, wherein the information recording / reproducing apparatus is provided before the second error correction decoding means. 29. The recording code sequence block is obtained by dividing the recording frame, and each first error correction code sequence corresponds to the recording code sequence block on the information code sequence. At a predetermined code position, or at a corresponding code position immediately before, immediately after, or inside the corresponding recording code sequence block, divided or collectively inserted / added,
24. A recording medium recorded on the recording medium.
An information recording / reproducing apparatus as described in the above. 30. The recording code sequence block is obtained by dividing the recording frame, and each first error correction code sequence corresponds to the recording code sequence block on the information code sequence. At a predetermined code position, or at a corresponding code position immediately before, immediately after, or inside the corresponding recording code sequence block, divided or collectively inserted / added, recorded on the recording medium, and The error correction code sequence is divided or collectively inserted / added at a predetermined code position corresponding to the recording frame on the information code sequence, or a corresponding code position immediately before, immediately after, or inside the recording frame. 28. The information recording / reproducing apparatus according to claim 27, wherein the information is recorded on the recording medium. 31. The information code frame is regarded as an information symbol sequence having a continuous code sequence (information symbol) having a predetermined code length as a unit. A second error correction encoding is independently performed on n independent information symbol sequences (n is a natural number) obtained by dividing the information code frame by interleaving processing in which a symbol is a division processing unit.
Alternatively, the second error correction code sequence constitutes a second error correction code sequence, and the second error correction decoding means in the above (17) independently generates n independent information symbol sequences by:
28. The information recording / reproducing apparatus according to claim 27, wherein a second code error detection / correction process is performed using the information symbol as an error detection / correction processing unit. 32. The information code frame is regarded as an information symbol sequence in units of a continuous code sequence (information symbol) having a predetermined code length, and the second error correction coding and the second error correction coding in (15) are performed. Before the configuration of the correction code sequence and before the second code error detection and correction process in the above (17), the information code frame is used as a division processing unit, and the information code frame is divided into n independent information symbol sequences (n is Interleave processing means for dividing the sequence into (natural numbers), and in (15), independently subjecting the n independent information symbol sequences to the second error correction coding;
Alternatively, a second error correction encoding means constituting a second error correction code sequence is provided, and in the above (17), the information symbol is independently assigned to the n independent information symbol sequences. 28. The information recording / reproducing apparatus according to claim 27, further comprising: second error correction decoding means for performing a second code error detection / correction process in which is a unit of error detection / correction processing. 33. The recording code sequence block according to claim 31, wherein said recording code sequence block is composed of a natural number of said information symbols physically and continuously recorded on said recording medium.
2. The information recording / reproducing apparatus according to item 2. 34. The recording code sequence block according to claim 26, comprising a first code sequence conversion process or a natural number of code sequences serving as a minimum processing unit in the first code sequence conversion process. Or the information recording / reproducing apparatus according to 27. 35. An error correction method for a code or information symbol belonging to a recording code sequence block in which a code error is detected and code error correction is determined to be impossible in the first code error detection and correction processing of (14). Means for transmitting flag information, error correction decoding means for performing erasure code error correction processing on the code or information symbol indicated by the error correction flag in the second code error detection and correction processing of (17), or 28. The information recording / reproducing apparatus according to claim 27, further comprising: second error correction decoding means. 36. The structure of the first error correction coding and the first error correction code sequence in (12) includes an information code in the recording code sequence block on the information code sequence to be recorded. An information code in the recording code sequence block that matches a predetermined information code sequence pattern corresponding to a set predetermined code error pattern (code error syndrome) using the referred information code; And code matching means for checking the code position of
The first error correction encoding means performs the first error correction encoding on only the information code specified by the information of the code position from the code collation means in the recording code sequence block, or , Or a first error correction code sequence, or the first code error detection and correction processing in (14) above includes, on the information code sequence decoded by the maximum likelihood sequence estimator, Means for referring to the decoded code in the recording code sequence block, and using the referenced decoded code, matching a predetermined decoded code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome). Code collating means for inspecting the code position of the decoded code in the recording code sequence block, and the first error correction decoding means comprises: Only for decoding the code indicated by the information of said code the position of al, the information recording and reproducing apparatus according to claim 23, wherein this is to subject the first code error detection and correction process. 37. The code modulation processing means performs a first code sequence conversion process by a predetermined recording code modulation process on the information code sequence to be recorded, and outputs a predetermined information code sequence on the information code sequence. Only at the position, the appearance of a predetermined information code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) is allowed, and a code constraint condition is added. The one error correction encoding means converts a predetermined code error pattern (code error syndrome) for an information code at a predetermined information code position in the recording code sequence block on the information code sequence to be recorded. Applying the first error correction encoding so that it can detect and correct a specific code error event having, or to apply the configuration of the first error correction code sequence,
Further, the first error correction decoding means in the above (14) uses the above first error correction code or the first error correction code sequence to decode the first error correction code by the maximum likelihood sequence estimator. A specific code error event having a predetermined code error pattern (code error syndrome) is detected and corrected only for a decoded code corresponding to a predetermined information code position in the recording code sequence block on the information code sequence. 28. The information recording / reproducing apparatus according to claim 26, wherein the first code error detection and correction processing is performed. 38. The code modulation processing means performs a first code sequence conversion process by a predetermined recording code modulation process on the information code sequence to be recorded, and outputs a predetermined information code sequence on the information code sequence. Only at the position, the appearance of a predetermined information code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) is allowed, and a code constraint condition is added. The one error correction encoding unit is configured to perform a predetermined code error pattern (code error syndrome) on only the information code at the predetermined information code position in the recording code sequence block on the information code sequence to be recorded. The first error correction coding is performed so as to detect and correct the specific code error event having the following, or the first error correction code sequence is configured, and the above ( The first error correction decoding means in 4) uses the first error correction coding or the first error correction code sequence to decode the information code sequence decoded by the maximum likelihood sequence estimator. A first method of detecting and correcting a specific code error event having a predetermined code error pattern (code error syndrome) for only the decoded code corresponding to the predetermined information code position in the recording code sequence block above. 28. The information recording / reproducing apparatus according to claim 26, wherein the code error detection and correction processing is performed. 39. The information recording / reproducing apparatus according to claim 23, wherein the first error correction encoding means in (12) or the first error correction decoding means in (14) is:
Code sequence matching means for comparing the information code sequence decoded by the maximum likelihood sequence estimator with the information code sequence before recording, checking a normal code position and an error code position, and outputting an error code position sequence; 24. The information recording / reproducing apparatus according to claim 23, further comprising: a code error pattern detection unit configured to detect a code error pattern (code error syndrome) from the error code position sequence. 40. The first error correction encoding means in the above (12) or the first error correction decoding means in the above (14), wherein: 40. The information recording / reproducing apparatus according to claim 39, further comprising frequency recording means for recording the frequency of occurrence of the code error syndrome and the code error pattern (code error syndrome). 41. The first error correction encoding means in (12) or the first error correction decoding means in (14) converts the information code sequence decoded by the maximum likelihood sequence estimator into Code sequence checking means for checking the normal code position and error code position by comparing with the information code sequence before recording and outputting an error code position sequence, and a predetermined code error pattern (code error syndrome) from the error code position sequence 24. The information recording / reproducing apparatus according to claim 23, further comprising: a code error pattern detecting unit that detects the error. 42. The first error correction encoding means in the above (12) or the first error correction decoding means in the above (14), wherein the first error correction encoding means detects the predetermined error code detected by the error code pattern detecting means. 42. The information recording / reproducing apparatus according to claim 41, further comprising a frequency recording unit that records a frequency of occurrence of a pattern (code error syndrome). 43. The code error pattern detecting means detects a partial sequence of the error code position sequence separated by a normal code position having a predetermined continuous length or more as a code error pattern (code error syndrome). 40. The information recording / reproducing apparatus according to claim 39, wherein: 44. The structure of the first error correction coding and the first error correction code sequence in the above (12), or
In the first code error detection and correction processing in the above (14),
In a predetermined code error pattern (code error syndrome) set in advance, a predetermined information code sequence is recorded and reproduced on the recording medium before the start of the information recording / reproducing operation or during a predetermined period during the operation. The code error pattern (code error syndrome) in which the occurrence frequency is recorded by the frequency recording means
40. The information recording / reproducing apparatus according to claim 39, wherein a predetermined number is selected from those having a predetermined frequency or higher or those having the maximum frequency, and the selected number is set. 45. An apparatus for recording and reproducing a binary information code sequence on a recording medium using a recording signal sequence having a binary signal level, wherein (18) the recording signal sequence having only a DC frequency component. When a binary information code sequence (non-inverted continuous code sequence of the same level code value) is recorded / reproduced, and a binary information code sequence (binary level When recording / reproducing a continuous inverted code sequence of code values), an information recording / reproducing system of a signal transmission characteristic for outputting a zero-value continuous signal sequence as each reproduced signal sequence inputted to the maximum likelihood sequence estimator is provided. , (19) for the recorded binary information code sequence, the first error correction coding means in the above (12) performs the coding on the binary information code sequence decoded by the maximum likelihood sequence estimator. Record mark It is possible to perform a first code error detection and correction process of detecting and correcting a predetermined number of code error events corresponding to continuous code errors of a binary level code value continuous inverted code sequence having a predetermined continuous code length in a sequence block. Apply the first error correction coding so that, or constitute the first error correction code sequence, or
With respect to the binary information code sequence decoded by the maximum likelihood sequence estimator, the first error correction decoding means in the above (14) performs a continuous conversion of a binary level code value continuous inversion code sequence having a predetermined continuous code length. 24. The information recording / reproducing apparatus according to claim 23, wherein a first code error detection and correction process for detecting and correcting a code error event corresponding to a code error to a predetermined number is performed. 46. An apparatus for recording and reproducing a binary information code sequence on a recording medium using a recording signal sequence having a binary signal level, wherein (20) the recording signal sequence having only a DC frequency component When a binary information code sequence (non-inverted continuous code sequence of the same level code value) is recorded / reproduced, and a binary information code sequence (binary level When recording / reproducing a continuous inverted code sequence of code values), an information recording / reproducing system of a signal transmission characteristic for outputting a zero-value continuous signal sequence as each reproduced signal sequence inputted to the maximum likelihood sequence estimator is provided. (21) The code modulation processing means performs a first code sequence conversion process by a predetermined recording code modulation process on the binary information code sequence to be recorded, and outputs a continuous signal on the recording signal sequence. Lebe A code constraint condition is added to limit the maximum number of inversions to a predetermined number k (k is a natural number). (22) The binary information code sequence to be recorded is The one error correction coding unit performs (k +) on the binary information code sequence decoded by the maximum likelihood sequence estimator in the recording code sequence block.
1) A first code error detection and correction process for detecting and correcting a predetermined number of code error events corresponding to continuous code errors of a binary level code value continuous inverted code sequence having the following predetermined continuous code length becomes possible. Applying the first error correction coding as described above, or constituting the first error correction code sequence, or, for the binary information code sequence decoded by the maximum likelihood sequence estimator, The first error correction decoding means in (14) outputs a predetermined number of code error events corresponding to continuous code errors of a binary level code value continuous inverted code sequence having a predetermined continuous code length of (k + 1) or less. 28. The information recording / reproducing apparatus according to claim 26, wherein a first code error detection / correction process for detecting and correcting the error is performed. 47. The configuration of the first error correction coding and the first error correction code sequence in the above (19) to (22) includes the recording code sequence block on the recorded binary information code sequence. Means for referring to the information code in the information code, and using the referenced information code, determine the code position of the information code in the recording code sequence block that matches the binary level code value continuous inverted code sequence having a predetermined continuous code length. Code checking means for checking, and the first error correction coding means,
In the recording code sequence block, only the information code indicated by the information of the code position from the code collating means is subjected to the first error correction coding, or the first error correction code sequence is Or the first code error detection and correction processing in (19) to (22) above includes the recording code sequence on the binary information code sequence decoded by the maximum likelihood sequence estimator. Means for referring to the decoded code in the block, and a code of the decoded code in the recording code sequence block corresponding to a binary level code value continuous inverted code sequence having a predetermined continuous code length using the referenced decoded code. Code matching means for checking the position, and
The first error correction decoding means performs a first code error detection and correction process only on the decoded code specified by the code position information from the code collating means in the recording code sequence block. 47. The information recording / reproducing apparatus according to claim 45, wherein: 48. The code modulation processing means performs a first code sequence conversion process by a predetermined recording code modulation process on the recorded binary information code sequence, and A code constraint condition for permitting the appearance of a binary level code value continuous inverted code sequence having a predetermined continuous code length is added only at a predetermined information code position, and the first error correction in (22) is performed. The encoding means includes a binary level code value continuous inversion code having a predetermined continuous code length for an information code at a predetermined information code position in the recording code sequence block on the binary information code sequence to be recorded. The first error correction coding is performed so that a code error event corresponding to a continuous code error of the sequence can be detected and corrected, or the configuration of the first error correction code sequence is performed. Smell The first error correction decoding means uses the first error correction coding or the first error correction code sequence to perform decoding on the binary information code sequence decoded by the maximum likelihood sequence estimator. A code error event corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length for only the decoded code corresponding to the predetermined information code position in the recording code sequence block of FIG. 47. The information recording / reproducing apparatus according to claim 46, wherein a first code error detection and correction process for detecting and correcting the error is performed. 49. The code modulation processing means performs a first code sequence conversion process by a predetermined recording code modulation process on the recorded binary information code sequence, and A code constraint condition for permitting the appearance of a binary level code value continuous inverted code sequence having a predetermined continuous code length is added only at a predetermined information code position, and the first error correction in (22) is performed. The encoding means includes a binary level code value sequence having a predetermined continuous code length for only the information code at the predetermined information code position in the recording code sequence block on the binary information code sequence to be recorded. The first error correction coding is performed so that a code error event corresponding to a continuous code error of an inverted code sequence can be detected and corrected, or the first error correction code sequence is configured,
In addition, the first error correction decoding means in (22) uses the first error correction coding or the first error correction code sequence and decodes the first error correction code by the maximum likelihood sequence estimator. A continuous code of a binary level code value continuous inverted code sequence having a predetermined continuous code length for only a decoded code corresponding to the predetermined information code position in the recording code sequence block on the binary information code sequence. 47. The information recording / reproducing apparatus according to claim 46, wherein a first code error detection and correction process for detecting and correcting a code error event corresponding to an error is performed. 50. A reproduction signal sequence input from said recording / reproduction system to said maximum likelihood sequence estimator when said binary information code sequence is recorded / reproduced by said recording signal sequence having only a single isolated signal level inversion. 47. The information recording / reproducing apparatus according to claim 45, further comprising an information recording / reproducing system having a signal transmission characteristic in which the response signal waveform has an asymmetric shape. 51. A circuit means (recording processing circuit) for converting and outputting an input information code sequence to a recording signal sequence or a control signal sequence for generating the recording signal sequence, An information recording / reproducing circuit having circuit means (reproduction processing circuit) for decoding and reproducing the information code sequence using a likelihood sequence estimation circuit (a maximum likelihood sequence detection circuit, a maximum likelihood decoding circuit, and a Viterbi decoding circuit). And (23)
The information code sequence before being converted and output from the recording processing circuit includes, as a unit, the information code sequence (recording code sequence block) having a predetermined code length which is continuously decoded by the maximum likelihood sequence estimation circuit. A first error correction encoder circuit for performing a first error correction encoding or constituting a first error correction code sequence corresponding to each of the recording code sequence blocks, and The configuration of the first error correction encoding and the first error correction code sequence by the correction encoder circuit is, in the recording code sequence block and the error correction code sequence decoded by the maximum likelihood sequence estimation circuit, It is possible to detect and correct the occurrence of a predetermined number of specific code error events having a predetermined code error pattern (code error syndrome) set in advance (first code error detection and correction processing). It is intended to be applied cormorants, (24)
Circuit means for converting and outputting the first error correction code sequence to a recording signal sequence or a control signal sequence for generating the recording signal sequence; or A first code sequence processing circuit that divides or collectively inserts / adds a predetermined code position immediately before, immediately after, or inside the recording code sequence block on the information code sequence before being converted and output from the circuit. The code sequence output and generated from the code sequence processing circuit is supplied to the recording processing circuit, and is converted and output into a recording signal sequence or a control signal sequence for generating the recording signal sequence, and (2)
5) The information code sequence decoded and output from the maximum likelihood sequence estimation circuit includes the recording code sequence block as a processing unit,
A first error correction decoder circuit for performing a first code error detection and correction process using the first error correction code sequence or the first error correction code sequence to be decoded together; An information recording / reproducing circuit characterized by the above-mentioned. 52. At the code position of each error code indicated by the code error pattern (code error syndrome), it is determined that the normal information code for the error code or the difference between the error codes can be distinguished from each other. 52. The information recording / reproducing circuit according to claim 51, wherein: 53. The information code sequence decoded and output from the maximum likelihood sequence estimation circuit is supplied to a first error correction decoder circuit without logically changing the code order on the information code sequence. 52. The information recording / reproducing circuit according to claim 51, wherein the information code sequence outputted from the maximum likelihood sequence estimating circuit is directly input to a first error correction decoder circuit. 54. The information code sequence before being converted and output from the recording processing circuit includes a predetermined error correction code and a predetermined error correction code sequence in (23). A code modulation processing circuit for performing a first code sequence conversion process by a recording code modulation process is provided in front of the first error correction encoder circuit, and is decoded and output from the maximum likelihood sequence estimation circuit. The information code sequence includes (2)
After the first error code detection and correction processing in 5) is performed, a code demodulation processing circuit for performing a second code sequence conversion processing by a predetermined recording code demodulation processing corresponding to the recording code modulation processing includes 52. The information recording / reproducing circuit according to claim 51, wherein the information recording / reproducing circuit is provided after the one error correction decoder circuit. 55. The information recording / reproducing circuit according to claim 51, wherein (26) the information code sequence before being converted and outputted from the recording processing circuit is provided with the first error correction coding in (23). Before the configuration of the first error correction code sequence, it corresponds to a continuous processing unit (recording frame) of the information code sequence in the recording / reproduction processing operation of the information recording / reproducing apparatus, or a plurality of the recording code sequence blocks. The code sequence unit is the unit of the second code error detection and correction processing (information code frame)
As a second error correction encoding circuit, or a second error correction encoder circuit constituting a second error correction code sequence corresponding to each of the information code frames, the first error correction encoder And (27) circuit means for converting and outputting the second error correction code sequence to a recording signal sequence or a control signal sequence for generating the recording signal sequence. Before the second error correction code sequence and the configuration of the first error correction code sequence and the first error correction code sequence in the above (23), the second error correction code sequence is output from the information code sequence before being converted and output from the recording processing circuit. A second code sequence processing circuit that divides or collectively inserts / adds the code sequence at a predetermined code position immediately before, immediately after, or inside the information code frame, and a code sequence output and generated from the code sequence processing circuit. Is the first sign After being supplied to the sequence processing circuit, it is supplied to the recording processing circuit and converted and output into a recording signal sequence or a control signal sequence for generating the recording signal sequence. The decoded and output information code sequence is subjected to the first code error detection and correction processing in (25), and then the information code frame is processed in units of second error correction coding or both. A second error correction decoder circuit for performing a second code error detection and correction process using the second error correction code sequence to be decoded is provided after the first error correction decoder circuit. And an information recording / reproducing circuit. 56. The information code sequence before being converted and output from the recording processing circuit includes the second error correction coding and the second error correction code sequence in (26),
Alternatively, after the insertion / addition of the second error correction code sequence in the above (27), the code modulation processing circuit for performing the first code sequence conversion processing is provided by the second error correction encoder circuit or the second error correction encoder circuit. The second error code detection and correction process in (28) is performed on the information code sequence that is provided after the code sequence processing circuit and is decoded and output from the maximum likelihood sequence estimation circuit. 56. The information recording / reproducing circuit according to claim 55, wherein a code demodulation processing circuit for performing the second code sequence conversion processing is provided before the second error correction decoder circuit. 57. The recording code sequence block is obtained by dividing the recording frame, and converts each first error correction code sequence into an information code before being converted and output from the recording processing circuit. On the sequence, a predetermined code position corresponding to the recording code sequence block concerned, or a corresponding code position immediately before, immediately after, or inside the recording code sequence block, a first code to be divided or collectively inserted / added. The information recording / reproducing circuit according to claim 51, further comprising a code sequence processing circuit. 58. The recording code sequence block is obtained by dividing the recording frame, and converts each first error correction code sequence into the information code before being converted and output from the recording processing circuit. On the sequence, a predetermined code position corresponding to the recording code sequence block concerned, or a corresponding code position immediately before, immediately after, or inside the recording code sequence block, a first code to be divided or collectively inserted / added. A code sequence processing circuit, and a second error correction code sequence,
On the information code sequence before being converted and output from the recording processing circuit, a predetermined code position corresponding to the recording frame, or a corresponding code position immediately before, immediately after, or inside the recording frame, is divided or divided. 56. The information recording / reproducing circuit according to claim 55, further comprising a first code sequence processing circuit for inserting / adding all at once. 59. The information code frame is regarded as an information symbol sequence having a continuous code sequence (information symbol) having a predetermined code length as a unit. A second error correction coding is independently performed on n independent information symbol sequences (n is a natural number) obtained by dividing the information code frame by interleaving processing in which a symbol is a division processing unit.
Alternatively, a second error correction code sequence constitutes a second error correction code sequence, and the second error correction decoder circuit in the above (28) independently converts the information symbol 56. The information recording / reproducing circuit according to claim 55, wherein a second code error detection / correction process is performed using the error detection / correction processing unit as a unit. The information code frame is regarded as an information symbol sequence in units of a continuous code sequence (information symbol) having a predetermined code length, and the second error correction coding and the second error coding in (26) are performed. Before the configuration of the correction code sequence and before the second code error detection and correction processing in (28), the information code frame is used as a division processing unit and the information code frame is divided into n independent information symbol sequences (n is An interleave processing circuit for dividing into a (natural number) is provided in front of the second error correction encoder circuit and the second error correction decoder circuit, and in the above (26),
A second error correction encoder circuit for independently performing a second error correction encoding on the n independent information symbol sequences, or constituting a second error correction code sequence,
In the above (28), the second error correction decoding for independently performing a second code error detection and correction process using the information symbol as an error detection and correction processing unit for the n independent information symbol sequences 56. The information recording / reproducing circuit according to claim 55, further comprising a device circuit. 61. An information recording / reproducing circuit according to claim 59, wherein said recording code sequence block comprises a natural number of said information symbols continuously converted and output from said recording processing circuit. . 62. The recording code sequence block according to claim 54, comprising a first code sequence conversion process or a natural number of code sequences serving as a minimum processing unit in the first code sequence conversion process. Or an information recording / reproducing circuit according to 55. 63. In the first code error detection / correction processing of (25), a code error is detected, and an error correction is performed on a code or information symbol belonging to a recording code sequence block for which code error correction is determined to be impossible. A flag generation circuit for transmitting flag information; and in the second code error detection and correction processing of (28), a code or information symbol indicated by the error correction flag output from the flag generation circuit is subjected to an erasure code error. 56. The information recording / reproducing circuit according to claim 55, further comprising an error correction decoding circuit for performing a correction process, or a second error correction decoding circuit. 64. The structure of the first error correction coding and the first error correction code sequence in (23) includes an information code in the recording code sequence block on the information code sequence to be recorded. A reference circuit, and an information code in the recording code sequence block that matches the predetermined information code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) using the referenced information code. And a code matching circuit for checking the code position of
The first error correction encoder circuit performs the first error correction encoding only on the information code specified by the information on the code position from the code matching circuit in the recording code sequence block, Alternatively, it constitutes a first error correction code sequence, or the first code error detection and correction processing in the above (25) includes, on the information code sequence decoded by the maximum likelihood sequence estimation circuit, A circuit that refers to the decoded code in the recording code sequence block, and matches the predetermined decoded code sequence pattern corresponding to the set predetermined code error pattern (code error syndrome) using the referenced decoded code. A code matching circuit for checking the code position of the decoded code in the recording code sequence block.
The first error correction decoder circuit performs a first code error detection and correction process on only the decoded code specified by the code position information from the code matching circuit in the recording code sequence block. The information recording / reproducing circuit according to claim 51, wherein the information recording / reproducing circuit is applied. 65. The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the information code sequence before being converted and output from the recording processing circuit, On a code sequence, only at a predetermined information code position, a predetermined information code sequence pattern corresponding to a set predetermined code error pattern (code error syndrome) is allowed to appear and a code constraint condition is added, Further, the first error correction encoder circuit in the above (23) is adapted to provide information of a predetermined information code position in the recording code sequence block on the information code sequence before being converted and output from the recording processing circuit. Performing a first error correction coding on the code so that a specific code error event having a predetermined code error pattern (code error syndrome) can be detected and corrected;
Alternatively, a first error correction code sequence is configured, and the first error correction decoder circuit in (25) performs the first error correction coding or the first error correction coding. Using the error correction code sequence of the above, in the recording code sequence block on the information code sequence decoded and output from the maximum likelihood sequence estimation circuit, only for the decoded code corresponding to the predetermined information code position, 56. The information recording apparatus according to claim 54, wherein a first code error detection and correction process for detecting and correcting a specific code error event having a predetermined code error pattern (code error syndrome) is performed. Regeneration circuit. 66. The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the information code sequence before being converted and output from the recording processing circuit, On a code sequence, only at a predetermined information code position, a predetermined information code sequence pattern corresponding to a set predetermined code error pattern (code error syndrome) is allowed to appear and a code constraint condition is added, Further, the first error correction encoder circuit in the above (23) is adapted to provide information of a predetermined information code position in the recording code sequence block on the information code sequence before being converted and output from the recording processing circuit. A first error correction coding is applied to only the code so that a specific code error event having a predetermined code error pattern (code error syndrome) can be detected and corrected, or The first error correction decoder circuit in (25) performs the first error correction coding or the first error correction code sequence. , A predetermined code error for only the decoded code corresponding to the predetermined information code position in the recording code sequence block on the information code sequence decoded and output from the maximum likelihood sequence estimation circuit. 56. The information recording / reproducing circuit according to claim 54, wherein a first code error detection and correction process for detecting and correcting a specific code error event having a pattern (code error syndrome) is performed. 67. The first error correction encoder circuit according to (23) or the first error correction decoder circuit according to (25), wherein the information code decoded and output from the maximum likelihood sequence estimation circuit is provided. A code sequence matching circuit for comparing a sequence with the information code sequence before being converted and output from the recording processing circuit, checking a normal code position and an error code position, and outputting an error code position sequence; 52. The information recording / reproducing circuit according to claim 51, further comprising: a code error pattern detection circuit for detecting a code error pattern (code error syndrome) from the data. 68. The first error correction encoder circuit according to (23) or the first error correction decoder circuit according to (25), wherein the code error pattern detected by the code error pattern detection circuit is 68. The information recording / reproducing circuit according to claim 67, further comprising a frequency recording circuit for recording a frequency of occurrence of the (code error syndrome) and the code error pattern (code error syndrome). 69. The first error correction encoding circuit in (23) or the first error correction decoding circuit in (25) converts the information code sequence decoded by the maximum likelihood sequence estimation circuit into A code sequence matching circuit that checks the information code sequence before being converted and output from the recording processing circuit, checks a normal code position and an error code position, and outputs an error code position sequence; 52. The information recording / reproducing circuit according to claim 51, further comprising: a code error pattern detection circuit for detecting a code error pattern (code error syndrome). 70. The first error correction encoder circuit according to the above (23) or the first error correction decoder circuit according to the above (25), wherein the first error correction encoder circuit detects the predetermined code detected from the code error pattern detection circuit. 70. The information recording / reproducing circuit according to claim 69, further comprising a frequency recording circuit for recording an occurrence frequency of an error pattern (code error syndrome). 71. The code error pattern detection circuit detects a partial sequence of the error code position sequence separated by a normal code position having a predetermined continuous length or more as a code error pattern (code error syndrome). The information recording / reproducing circuit according to claim 67, characterized in that: 72. The structure of the first error correction coding and the first error correction code sequence in the above (23), or
In the first code error detection and correction process in (25), a predetermined code error pattern (code error syndrome) set in advance includes the code error pattern (code error) in which the occurrence frequency is recorded by the frequency recording circuit. 68. The information recording / reproducing circuit according to claim 67, wherein a predetermined number is selected from those having a predetermined frequency or higher or those having a maximum frequency among the syndromes. 73. A recording processing circuit for converting and outputting a recording signal sequence having a binary signal level or a control signal for generating the recording signal sequence, wherein the recording processing circuit and the reproduction processing circuit perform binary conversion. A circuit for recording / reproducing an information code sequence, wherein (29) when recording / reproducing a binary information code sequence (a non-inverted continuous code sequence having the same level code value) with the recording signal sequence having only a DC frequency component,
And when a binary information code sequence (continuous inverted code sequence of binary level code values) is recorded / reproduced by the recording signal sequence in which the continuous signal level is inverted at the recording / reproducing operation frequency,
(30) the recording processing circuit and the reproduction processing circuit each having a signal transmission characteristic in which a reproduction signal sequence input to the maximum likelihood sequence estimation circuit in each case is a zero-value continuous signal sequence;
With respect to the binary information code sequence before being converted and output from the recording processing circuit, the first error correction encoder circuit in the above (23) decodes the binary information code sequence output from the maximum likelihood sequence estimation circuit.
On the binary information code sequence, within the recording code sequence block, a code error event corresponding to a continuous code error of a binary level code value continuous inversion code sequence having a predetermined continuous code length,
The first error correction encoding is performed so as to enable the first code error detection and correction processing for detecting and correcting up to a predetermined number, or a first error correction code sequence is configured, or For the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit, the first error correction decoder circuit in the above (25) performs a binary level code value continuous inversion code sequence having a predetermined continuous code length. 52. The information recording / reproducing circuit according to claim 51, wherein a first code error detection and correction process for detecting and correcting a predetermined number of code error events corresponding to continuous code errors is performed. 74. A recording processing circuit for converting and outputting a recording signal sequence having a binary signal level or a control signal for generating the recording signal sequence, wherein the recording processing circuit and the reproduction processing circuit perform binary conversion. A circuit for recording / reproducing an information code sequence, wherein (31) when recording / reproducing a binary information code sequence (a non-inverted continuous code sequence having the same level code value) with the recording signal sequence having only a DC frequency component
And when a binary information code sequence (continuous inverted code sequence of binary level code values) is recorded / reproduced by the recording signal sequence in which the continuous signal level is inverted at the recording / reproducing operation frequency,
(32) the recording processing circuit and the reproduction processing circuit having a signal transmission characteristic in which a reproduced signal sequence input to the maximum likelihood sequence estimation circuit in each case is a zero-value continuous signal sequence;
The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the binary information code sequence before being converted and output from the recording processing circuit, and A code constraint condition is added so as to limit the maximum number of inversions of the above continuous signal level to a predetermined number k (k is a natural number). (23) for the binary information code sequence
The first error-correcting encoder circuit in (2), on the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit, in the recording code sequence block, has a predetermined continuous code length of (k + 1) or less. A first error correction code so as to enable a first code error detection and correction process for detecting and correcting a predetermined number of code error events corresponding to continuous code errors of a binary level code value continuous inversion code sequence having Or to constitute a first error correction code sequence, or
For the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit, the first error correction decoder circuit in the above (14) performs a binary coding having a predetermined continuous code length of (k + 1) or less. 55. A first code error detection / correction process for detecting and correcting a predetermined number of code error events corresponding to continuous code errors of a level code value continuous inverted code sequence. Information recording and reproduction circuit. 75. The configuration of the first error correction coding and the first error correction code sequence in (29) to (31) includes the binary information code before conversion and output from the recording processing circuit. A circuit that refers to the information code in the recording code sequence block on the sequence, and the recording code that matches the binary level code value continuous inversion code sequence having a predetermined continuous code length using the referenced information code. A code matching circuit for checking the code position of the information code in the sequence block, and the first error correction encoder circuit detects the code position of the code position from the code matching circuit in the recording code sequence block. The first error correction coding is performed only on the information code indicated by the information, or a first error correction code sequence is formed, or the above (29) to (31)
In the first code error detection and correction processing in the above, on the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit,
A circuit that refers to the decoded code in the recording code sequence block; and a circuit in the recording code sequence block that matches the binary level code value continuous inverted code sequence having a predetermined continuous code length using the referenced decoding code. And a first error correction decoder circuit, in the recording code sequence block, instructed by information on the code position from the code verification circuit. 75. The information recording / reproducing circuit according to claim 73, wherein the first code error detection and correction processing is performed only on the decoded code. 76. The code modulation processing circuit, for the binary information code sequence before being converted and output from the recording processing circuit,
A first code sequence conversion process is performed by a predetermined recording code modulation process, and a binary level code value continuous inversion code sequence having a predetermined continuous code length is provided only at a predetermined information code position on the binary information code sequence. The first error correction encoder circuit in the above (31) is for adding a code constraint condition allowing the appearance, and the first error correction encoder circuit in the above (31) performs a conversion on the binary information code sequence before being converted and output from the recording processing circuit. In the recording code sequence block, a code error event corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length can be detected and corrected for an information code at a predetermined information code position. To perform the first error correction coding, or to perform the configuration of the first error correction code sequence, and,
The first error correction decoder circuit in (31) uses the first error correction coding or the first error correction code sequence to decode and output from the maximum likelihood sequence estimation circuit. In the corresponding recording code sequence block on the binary information code sequence, only a decoded code corresponding to the predetermined information code position is a continuous binary code value continuous inversion code sequence having a predetermined continuous code length. 75. The information recording / reproducing circuit according to claim 74, wherein a first code error detection and correction process for detecting and correcting a code error event corresponding to a code error is performed. 77. The code modulation processing circuit performs a first code sequence conversion process by a predetermined recording code modulation process on the binary information code sequence before being converted and output from the recording processing circuit. A code constraint condition for allowing the appearance of a binary level code value continuous inverted code sequence having a predetermined continuous code length only at a predetermined information code position on the binary information code sequence; The first error correction encoder circuit in (31) is an information code at a predetermined information code position in the recording code sequence block on the binary information code sequence before being converted and output from the recording processing circuit. Only the first error correction coding is performed so that a code error event corresponding to a continuous code error of a binary level code value continuous inverted code sequence having a predetermined continuous code length can be detected and corrected. Mistake of The first error correction decoder circuit in (31) uses the first error correction coding or the first error correction code sequence. In the recording code sequence block on the binary information code sequence decoded and output from the maximum likelihood sequence estimation circuit, only the decoded code corresponding to the predetermined information code position has a predetermined continuous code length. 75. The information recording / reproducing method according to claim 74, wherein a first code error detection and correction process for detecting and correcting a code error event corresponding to a continuous code error of a binary level code value continuous inversion code sequence is performed. circuit. 78. A reproduction signal sequence inputted from said recording / reproduction system to said maximum likelihood sequence estimation circuit when recording / reproducing said binary information code sequence by said recording signal sequence having only a single isolated signal level inversion. 74. The information recording / reproducing circuit according to claim 73, further comprising the recording processing circuit and the reproduction processing circuit having a signal transmission characteristic in which the response signal waveform has an asymmetric shape. 79. An information recording / reproducing apparatus equipped with the information recording / reproducing circuit according to claim 51. 80. An integrated circuit on which the information recording / reproducing circuit according to claim 51 is mounted. 81. An information recording / reproducing apparatus equipped with the information recording / reproducing circuit according to claim 78.