JPH11289165A - Multilayer wiring board and method for manufacturing the same - Google Patents

Multilayer wiring board and method for manufacturing the same

Info

Publication number
JPH11289165A
JPH11289165A JP9142898A JP9142898A JPH11289165A JP H11289165 A JPH11289165 A JP H11289165A JP 9142898 A JP9142898 A JP 9142898A JP 9142898 A JP9142898 A JP 9142898A JP H11289165 A JPH11289165 A JP H11289165A
Authority
JP
Japan
Prior art keywords
wiring board
core
layer
wiring
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9142898A
Other languages
Japanese (ja)
Inventor
Yoshizumi Sato
由純 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9142898A priority Critical patent/JPH11289165A/en
Publication of JPH11289165A publication Critical patent/JPH11289165A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring board wherein, comprising via connection of high reliability, high-density mounting and high density-wiring are allowed, and for simplifying the process. SOLUTION: A bump is provide at a first conductor layer, and a conductor layer 1b is laminated/allocated on a bump formation surface through an insulator layer 3. This is pressurized so that the tip end part of the bump is press- fitted/inserted into the insulator layer 3 for connection to the conductor layer 1b, thus forming a double-sided conductor layer core laminating plate. The double surface conductor layer of a core laminating body is patterned for wiring to form a core wiring board, and insulator layers 5a and 5b are formed on at least one main surface, forming connection via to the wiring pattern of the core wiring board. On the insulator layers 5a and 5b surfaces comprising it, conductive plating layers 6a and 6b are formed, which are patterned for wiring.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は多層配線基板および
その製造方法に係り、さらに詳しくは実装や配線パター
ンの高密度化が可能な多層配線基板、および多層配線板
を容易に製造できる方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method of manufacturing the same, and more particularly to a multilayer wiring board capable of mounting and increasing the density of wiring patterns, and a method of easily manufacturing a multilayer wiring board.

【0002】[0002]

【従来の技術】配線回路の高密度化やコンパクト化、も
しくは高機能化などの点から、多層配線型の配線基板が
広く実用に供されている。そして、この種の多層配線基
板は、一般的に、絶縁体層の両面に銅箔を張り合わせて
成る積層板を素材として製造されている。
2. Description of the Related Art A multilayer wiring type wiring board has been widely put into practical use from the viewpoints of increasing the density, reducing the size, and increasing the functionality of a wiring circuit. In general, this type of multilayer wiring board is manufactured using a laminate made by laminating copper foil on both sides of an insulator layer as a raw material.

【0003】すなわち、前記銅箔張り積層板の所定箇所
(所定位置)に、たとえばNCドリリングマシンを用い
て、一つづつシリーズに貫通孔を穿設し、この穿設孔の
内壁面をメッキなどで導電性化して、両面の銅箔間を電
気的に接続する。その後、前記両面の銅箔を、たとえば
フォトエッチング処理し、配線パターニングして両面型
の配線基板を得ている。
That is, through holes are drilled one by one at predetermined positions (predetermined positions) of the copper foil-clad laminate using, for example, an NC drilling machine, and the inner wall surfaces of the drilled holes are plated or the like. And electrically connect the copper foils on both sides. Thereafter, the copper foil on both sides is subjected to, for example, photoetching treatment and wiring patterning to obtain a double-sided wiring board.

【0004】また、多層型の配線基板の場合は、 (a)前
記両面型の配線基板間にガラス・樹脂系プリプレグ層を
介在させ、あるいは (b)両面型の配線基板をコア配線基
板とし、コア配線基板面にガラス・樹脂系プリプレグ層
を介して銅箔を積層し、これを積層一体化することによ
って製造される。
In the case of a multilayer wiring board, (a) a glass-resin prepreg layer is interposed between the double-sided wiring boards, or (b) a double-sided wiring board is used as a core wiring board, It is manufactured by laminating a copper foil on the surface of a core wiring substrate via a glass / resin prepreg layer and laminating and integrating the copper foil.

【0005】ここで、 (b)の銅箔を積層する製造方法
は、いわゆるビルドアップ方式ともいわれ、具体的に
は、次ぎのように行われている。先ず、スルホール接続
型のコア配線基板を用意し、コア配線基板の主面に絶縁
性樹脂の塗布、あるいは絶縁性樹脂フィルムを積層・一
体化して絶縁体層を形成する。
[0005] Here, the manufacturing method of (b) laminating copper foil is also called a so-called build-up method, and specifically, it is performed as follows. First, a through hole connection type core wiring board is prepared, and an insulating resin is applied to the main surface of the core wiring board, or an insulating resin film is laminated and integrated to form an insulator layer.

【0006】その後、コア配線基板の配線パターンに対
する接続のため、前記形成した絶縁体層にビアを形設し
てから、形設したビア内壁面を含む絶縁体層面に、たと
えばCuメッキによって導電性膜を被覆形成する。次い
で、前記形成した導電性膜に対して、たとえばフォトエ
ング処理を施し、コア配線基板の配線パターンにビア接
続する配線パターニングを行う。この絶縁体層の形成、
ビア形設(穿孔)、導電体層の被覆および配線パターニ
ングの繰り返しによって、所要の多層配線基板を製造す
る。
After that, for connection to the wiring pattern of the core wiring board, a via is formed in the formed insulator layer, and then a conductive layer is formed on the surface of the insulator layer including the formed via inner wall surface by, for example, Cu plating. The film is coated. Next, the formed conductive film is subjected to, for example, a photo aging process, and wiring patterning for via connection to the wiring pattern of the core wiring substrate is performed. Formation of this insulator layer,
A required multilayer wiring board is manufactured by repeating via formation (perforation), covering of a conductor layer, and wiring patterning.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前記ビ
ルドアップ方式による多層配線基板の製造、製品として
の多層配線基板には、次ぎのような不都合が認められ
る。すなわち、スルホール内壁面を導電体化して電気的
な接続を行った配線基板をコアとし、このコア配線基板
面に絶縁体層を形成するため、前記スルホール接続部
(孔・空洞)がそのままの状態で残存したり、あるいは
絶縁樹脂層の流入・陥没などによって凹面化する。
However, the following inconveniences are recognized in the manufacture of a multilayer wiring board by the build-up method and the multilayer wiring board as a product. In other words, the wiring board in which the inner wall surface of the through hole is made conductive and electrically connected is used as a core, and an insulator layer is formed on the surface of the core wiring board, so that the through hole connection portion (hole / cavity) is left as it is. Or a concave surface due to inflow or depression of the insulating resin layer.

【0008】したがって、コア配線基板面上に、絶縁体
層を介して配線パターンを積層するに当たっては、コ
ア配線基板のスルホール接続部を充填した絶縁樹脂の露
出部分を研磨・除去するか、あるいはスルホール接続
部を形成している孔を絶縁樹脂などで充填し、コア配線
基板面と同一面化する工程を要する。つまり、ビルドア
ップ方式は、工程の簡略化や低コスト化など期待されな
がら、実際には、工程の煩雑化やコストアップなどを招
来する傾向がある。
Therefore, when laminating a wiring pattern on the surface of the core wiring substrate via an insulating layer, the exposed portion of the insulating resin filling the through-hole connection portion of the core wiring substrate is polished and removed, or the through-hole is removed. A step of filling the hole forming the connection portion with an insulating resin or the like and making it flush with the surface of the core wiring board is required. In other words, the build-up method is expected to simplify the process and reduce the cost, but actually tends to complicate the process and increase the cost.

【0009】本発明は、上記事情に対処してなされたも
ので、信頼性の高いビア接続を有するだけでなく、高密
度実装や高密度配線化が可能な多層配線基板、およびプ
ロセスの簡略化を容易に図れる多層配線基板の製造方法
の提供を目的とする。
The present invention has been made in view of the above circumstances, and not only has a highly reliable via connection, but also has a multilayer wiring board capable of high-density mounting and high-density wiring, and a simplified process. It is an object of the present invention to provide a method of manufacturing a multilayer wiring board which can easily achieve the above.

【0010】[0010]

【課題を解決するための手段】請求項1の発明は、層間
絶縁体層を圧入・貫挿した導電性バンプでスルホール接
続されたコア配線基板と、前記コア配線基板の少なくと
も一主面に絶縁体層を介して積層形成され、かつコア配
線基板の配線パターンにビア接続する配線パターンとを
有する多層配線基板であって、前記積層形成された配線
パターンが複数層であることを特徴とする多層配線基板
である。
According to a first aspect of the present invention, there is provided a core wiring board which is connected through holes by conductive bumps into which an interlayer insulating layer is press-fitted and inserted, and at least one principal surface of the core wiring board is insulated. A multi-layer wiring board having a wiring pattern laminated and formed via a body layer and via-connected to a wiring pattern of a core wiring board, wherein the multi-layered wiring pattern has a plurality of layers. It is a wiring board.

【0011】請求項2の発明は、第1の導電体層の所定
位置に、第1の導電性バンプを設ける工程と、前記第1
の導電性バンプ形成面に第1の絶縁体層を介して第2の
導電体層を積層・配置する工程と、前記積層体を加圧し
て第1の導電性バンプの先端部を、第1の絶縁体層を圧
入・貫挿させて対向する第2の導電体層に接続して両面
導体層張りコア積層板を形成する工程と、前記コア積層
板の両面導電体層をそれぞれ配線パターニングし、コア
配線基板を形成する工程と、前記コア配線基板の少なく
とも一主面に絶縁体層を形成し、コア配線基板の配線パ
ターンに対する接続用のビアを形設する工程と、前記ビ
アを形設部を含む絶縁体層面に導電性メッキ層を形成す
る工程と、前記形成した導電性メッキ層を配線パターニ
ングする工程とを有することを特徴とする多層配線基板
の製造方法である。
According to a second aspect of the present invention, a step of providing a first conductive bump at a predetermined position on a first conductive layer;
Laminating and arranging a second conductive layer on the conductive bump forming surface via a first insulator layer, and pressing the laminated body so that the tip end of the first conductive bump is in contact with the first conductive bump. Forming a double-sided conductor-layered core laminate by press-fitting and inserting the above-mentioned insulator layer to the opposing second conductor layer; and wiring-patterning the double-sided conductor layers of the core laminate, respectively. Forming a core wiring board, forming an insulating layer on at least one main surface of the core wiring board, forming a via for connection to a wiring pattern of the core wiring board, forming the via A step of forming a conductive plating layer on an insulator layer surface including a portion, and a step of wiring-patterning the formed conductive plating layer.

【0012】請求項1および2の発明において、コア配
線基板の絶縁体および積層する配線パターンとの層間絶
縁体を成す樹脂としては、たとえばエポキシ樹脂、フェ
ノール樹脂、ポリイミド樹脂、ポリカーボネート樹脂、
ホットメルト接着剤、ポリビニルブチラール樹脂、ニト
リルラバー、フェノキシ樹脂、酢酸ビニル樹脂、ポリア
ミド樹脂、ポリアミドイミド樹脂、液晶ポリマー、ポリ
エーテルエーテルケトン樹脂、ポリエーテルイミド樹脂
などの1種もしくは2種以上の混合系樹脂溶液、また
は、前記樹脂とガラスクルスヤやマット、合成繊維や布
などとを組み合わせたシート状(もしくはフィルム状)
のものが挙げられる。そして、これら樹脂系シートは、
たとえば厚さ50〜 150μm 、好ましくは80〜 120μm 程
度である。
In the first and second aspects of the present invention, the resin forming the insulator of the core wiring board and the interlayer insulator with the wiring pattern to be laminated is, for example, an epoxy resin, a phenol resin, a polyimide resin, a polycarbonate resin,
Hot melt adhesive, polyvinyl butyral resin, nitrile rubber, phenoxy resin, vinyl acetate resin, polyamide resin, polyamide imide resin, liquid crystal polymer, polyetheretherketone resin, polyetherimide resin, etc. Resin solution, or sheet (or film) in which the resin is combined with glass crusader, mat, synthetic fiber, cloth, etc.
One. And these resin-based sheets
For example, the thickness is about 50 to 150 μm, preferably about 80 to 120 μm.

【0013】請求項1および2の発明において、コア配
線基板の配線パターンは、たとえば厚さ10〜20μm 程度
の銅箔、アルミ箔、ニッケル箔、金箔、銀箔などの導電
体層を素材として、これをパターニングしたもので、経
済性および加工性の点などから銅箔が適する。
In the first and second aspects of the present invention, the wiring pattern of the core wiring board is made of a conductive layer such as a copper foil, an aluminum foil, a nickel foil, a gold foil or a silver foil having a thickness of about 10 to 20 μm. And copper foil is suitable from the viewpoint of economy and workability.

【0014】また、前記コア配線基板の構成において、
層間絶縁体に圧入され、その先端部が対向する配線パタ
ーンの被接続面に対接し、電気的な接続部を形成する導
電性バンプは、たとえばAg粉末などの導電性粉末および
エポキシ樹脂などのバインダー成分で調製された導電性
組成物である。そして、導電性バンプは、前記導電性組
成物をスクリーン印刷などし、ほぼ一定高さ・形状の突
起を形成し、これを乾燥・硬化させることなどによって
作製される。
In the configuration of the core wiring board,
The conductive bumps, which are press-fitted into the interlayer insulator and whose leading ends contact the surfaces to be connected of the wiring pattern facing each other and form electrical connection parts, are made of, for example, conductive powder such as Ag powder and binder such as epoxy resin. It is a conductive composition prepared with the components. The conductive bumps are produced by screen printing or the like of the conductive composition to form projections having a substantially constant height and shape, and drying and curing the projections.

【0015】請求項1および2の発明において、コア配
線基板や積層した配線パターンに対する層間絶縁体は、
上記樹脂溶液の塗布・乾燥、上記樹脂系シートの熱圧着
などによって形成される。ここで、層間絶縁体の厚さ
は、絶縁性樹脂の種類や配線の容量などにもよるが、一
般的には30〜 120μm 程度である。また、積層される配
線パターン間を電気的にビア接続するため、層間絶縁体
の所定位置に孔を穿設するが、この穿孔加工は、たとえ
ばレーザー加工などで行われる。
In the first and second aspects of the present invention, the interlayer insulator for the core wiring board and the laminated wiring pattern is:
It is formed by application and drying of the resin solution, thermocompression bonding of the resin sheet, and the like. Here, the thickness of the interlayer insulator depends on the kind of the insulating resin, the capacity of the wiring, and the like, but is generally about 30 to 120 μm. In order to electrically connect vias between the wiring patterns to be laminated, a hole is formed at a predetermined position of the interlayer insulator. The hole is formed by, for example, laser processing.

【0016】請求項1および2の発明において、コア配
線基板面上に積層する配線パターンは、たとえば厚さ10
〜20μm 程度の導電性メッキ層であり、たとえば銅メッ
キ層、アルミニウムメッキ層、ニッケルメッキ層、金メ
ッキ層などを配線パターニングしたものである。ここ
で、メッキ層は、たとえば化学メッキおよび電気メッキ
の併用で形成することもできるし、また、異種の金属層
を積層する構成であってもよい。さらに、これら導電体
層のパターニングは、一般的には、いわゆるフォトエッ
チング処理であるが、レーザー照射による方式であって
もよい。
According to the first and second aspects of the present invention, the wiring pattern laminated on the core wiring board surface has a thickness of, for example, 10%.
A conductive plating layer having a thickness of about 20 μm, for example, a wiring pattern of a copper plating layer, an aluminum plating layer, a nickel plating layer, a gold plating layer, or the like. Here, the plating layer may be formed by, for example, a combination of chemical plating and electroplating, or may have a configuration in which different types of metal layers are stacked. Further, the patterning of these conductor layers is generally a so-called photo-etching process, but may be a method by laser irradiation.

【0017】請求項1および2の発明では、コア配線基
板として、スルホール接続部が充填的に形成されたもの
を使用するので、コア配線基板面に積層配線するために
絶縁体層を積層・被覆する際において、他の処理を別途
施さずとも、部分的な凹面化や厚さの変化など招来する
恐れも解消される。つまり、信頼性の高い絶縁性および
配線パターンが容易に確保されるとともに、導電性バン
プの微細化が可能なこと、貫挿による充填型のスルホー
ル接続と相俟って、高密度配線もしくは高密度実装型の
多層配線基板が提供される。
According to the first and second aspects of the present invention, since the core wiring substrate having the through hole connection portion formed in a filling manner is used, the insulating layer is laminated and coated for the laminated wiring on the surface of the core wiring substrate. In this case, even if other processing is not separately performed, there is no possibility of causing a partial concave surface or a change in thickness. In other words, highly reliable insulating properties and wiring patterns can be easily secured, and the conductive bumps can be miniaturized. A mounting type multilayer wiring board is provided.

【0018】[0018]

【発明の実施の形態】以下、図1 (a)〜 (c)および図2
(a)〜 (e)を参照して実施例を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, FIGS. 1A to 1C and FIG.
Embodiments will be described with reference to (a) to (e).

【0019】図1 (a)〜 (c)は、この実施例において使
用するコア配線基板の製造例の実施態様を、工程順に模
式的に示す断面図である。
FIGS. 1A to 1C are cross-sectional views schematically showing an embodiment of a manufacturing example of a core wiring board used in this embodiment in the order of steps.

【0020】先ず、厚さ18μm の銅箔1aを用意し、この
銅箔1aの一主面の所定位置に、エポキシ樹脂系銀ペース
トを印刷・乾燥固化して底面径 250μm 、高さ 150μm
程度の円錐状導電性バンプ2′を形成する。その後、図
1 (a)に示すごとく、前記円錐状導電性バンプ2′形成
面側に、厚さ60〜 120μm 程度のガラス・エポキシ樹脂
プリプレグ3を介して厚さ18μm の銅箔1bを積層する。
次いで、この積層体を熱加圧して一体化し、両面銅箔1
a,1b張りコア積層板4′を作製する。この熱加圧工程
において、円錐状導電性バンプ2′の先端部は、ガラス
・エポキシ樹脂プリプレグ3を圧入・貫挿し、図1(b)
に示すように、対向する銅箔1b面に対接し、電気的な接
続部2を形成した両面銅箔張りのコア積層板4′が製造
される。
First, a copper foil 1a having a thickness of 18 μm is prepared, and an epoxy resin-based silver paste is printed and dried and solidified at a predetermined position on one main surface of the copper foil 1a to obtain a bottom diameter of 250 μm and a height of 150 μm.
An approximately conical conductive bump 2 'is formed. Thereafter, as shown in FIG. 1A, an 18 μm thick copper foil 1 b is laminated on the conical conductive bump 2 ′ forming surface via a glass epoxy resin prepreg 3 having a thickness of about 60 to 120 μm. .
Next, the laminate was integrated by applying heat and pressure, and the double-sided copper foil 1
a, 1b upholstered core laminate 4 'is produced. In this heat-pressing step, the tip of the conical conductive bump 2 ′ is press-fitted and inserted with a glass-epoxy resin prepreg 3, as shown in FIG.
As shown in FIG. 7, a double-sided copper-clad core laminate 4 ′ in which an electrical connection portion 2 is formed in contact with the opposed copper foil 1 b surface is manufactured.

【0021】次に、前記コア積層板4′の銅箔1a,1b面
に、エッチングレジスト(商品名,UVエッチングレジス
トAS-400 太陽インキKK製)をパターン状にスクリーン
印刷法によって印刷し、露光・現像してエッチングレジ
スト層を設ける。その後、塩化第2銅浴を用いて、露出
している銅箔1a,1bを選択的にエッチング除去してか
ら、前記エッチングレジスト層を除去し、図1 (c)に示
すように、両面に所要の配線パターン1a′,1b′を有す
るコア配線基板4を作製する。
Next, an etching resist (trade name, UV etching resist AS-400 made by Taiyo Ink KK) is printed on the copper foil 1a, 1b surface of the core laminate 4 'in a pattern by a screen printing method. Develop and provide an etching resist layer. Thereafter, the exposed copper foils 1a and 1b are selectively removed by etching using a cupric chloride bath, and then the etching resist layer is removed. As shown in FIG. A core wiring board 4 having required wiring patterns 1a 'and 1b' is manufactured.

【0022】図2 (a)〜 (e)は、前記コア配線基板4面
に、ビルドアップ方式によるビア接続で、配線パターン
層を積層配置する多層配線基板の製造例の実施態様を、
工程順に模式的に示す断面図である。
FIGS. 2A to 2E show an embodiment of a manufacturing example of a multilayer wiring board in which wiring pattern layers are stacked and arranged on the surface of the core wiring board 4 by via connection using a build-up method.
It is sectional drawing which shows typically in a process order.

【0023】先ず、図2 (a)に示すごとく、コア配線基
板4の配線パターン1a′,1b′形成面に、それぞれ厚さ
50〜 100μm 程度のエポキシ樹脂フイルムを積層し、こ
れを熱圧着して絶縁体層5a,5bを一体的に形成する。な
お、この絶縁体層5a,5bは、樹脂溶液を塗布し、乾燥・
硬化して厚さがほぼ一様な膜として形成する方式を採っ
てもよい。
First, as shown in FIG. 2A, the thickness of each of the wiring patterns 1a 'and 1b'
An epoxy resin film having a thickness of about 50 to 100 μm is laminated, and this is thermocompression-bonded to integrally form the insulator layers 5a and 5b. The insulating layers 5a and 5b are coated with a resin solution, dried and dried.
A method in which the film is cured to form a film having a substantially uniform thickness may be employed.

【0024】次に、前記コア配線基板板4の配線パター
ン1a′,1b′に対するビア接続に対応する絶縁体層5a,
5bの領域に、レーザー加工を施して、図2 (b)に示すご
とく、ビア接続部5a′,5b′をそれぞれ開口する。その
後、化学銅メッキ液中に漬け、図2 (c)に示すように、
ビア接続部5a′,5b′(開口部)を含む絶縁体層5a,5b
面に銅メッキ層を形成してから、さらに電気銅メッキ液
中に漬けて、銅メッキ層上に電気銅メッキ層を成長・肉
盛りして、厚さ 5〜15μm 程度の銅メッキ層6a,6bをそ
れぞれ形成した。
Next, the insulator layers 5a, 5b corresponding to the via connections to the wiring patterns 1a ', 1b' of the core wiring board 4 will be described.
Laser processing is performed on the region 5b to open via connection portions 5a 'and 5b' as shown in FIG. 2B. Then, dipped in a chemical copper plating solution, as shown in FIG.
Insulator layers 5a, 5b including via connection parts 5a ', 5b' (openings)
After forming a copper plating layer on the surface, immerse it further in an electrolytic copper plating solution, grow and build up an electrolytic copper plating layer on the copper plating layer, and form a copper plating layer 6a, about 5 to 15 μm thick. 6b were each formed.

【0025】次いで、前記形成した銅メッキ層6a,6b上
に、エッチングレジスト(商品名,UVエッチングレジス
トAS-400 太陽インキKK製)をパターン状にスクリーン
印刷法によって印刷し、露光・現像してエッチングレジ
スト層を設ける。その後、塩化第2銅浴を用いて、露出
している銅メッキ層6a,6bを選択的にエッチング除去し
てから、前記エッチングレジスト層を除去し、図2 (d)
に示すように、両面に所要の配線パターン6a′,6b′を
有する多層配線基板7を作製する。
Next, an etching resist (trade name, UV etching resist AS-400 manufactured by Taiyo Ink KK) is printed in a pattern on the copper plating layers 6a and 6b formed by the screen printing method, and is exposed and developed. An etching resist layer is provided. Thereafter, the exposed copper plating layers 6a and 6b are selectively removed by etching using a cupric chloride bath, and then the etching resist layer is removed.
As shown in (1), a multilayer wiring board 7 having required wiring patterns 6a 'and 6b' on both sides is manufactured.

【0026】さらに、多層の配線パターンを積層配置す
るためには、図2 (e)に示すごとく、前記多層配線基板
7の配線パターン6a′,6b′形成面に、それぞれ厚さ50
〜 100μm 程度のエポキシ樹脂フイルムを積層し、これ
を熱圧着して絶縁体層8a,8bを一体的に形成する。その
後、この絶縁体層8a,8bに対するビア接続部の形設、銅
メッキ層の形成、銅メッキ層のパターニングを上記に準
じて行うことにより、目的とする多層配線基板を製造で
きる。
Further, in order to arrange a multilayer wiring pattern in a stacked manner, as shown in FIG. 2E, the multilayer wiring board 7 has a thickness of 50 μm on the surface on which the wiring patterns 6a ′ and 6b ′ are formed.
An epoxy resin film having a thickness of about 100 μm is laminated, and this is thermocompression-bonded to integrally form insulator layers 8a and 8b. Thereafter, by forming a via connection portion with respect to the insulator layers 8a and 8b, forming a copper plating layer, and patterning the copper plating layer according to the above, a target multilayer wiring board can be manufactured.

【0027】上記ビルドアップ方式で構成したスルホー
ル接続2およびビア接続6a′,6b′を有する多層配線基
板を厚さ方向に切断し、各配線パターン1a′,1b′,6
a′,6b′間の接続状態、それら接続部2,6a′,6b′
の位置ズレ・変形状態をそれぞれ観察したところ、良好
な接続状態や位置決めが確保されており、また、各接続
部の抵抗は平均 2 mΩであった。
The multilayer wiring board having the through-hole connection 2 and the via connection 6a ', 6b' constructed by the above-mentioned build-up method is cut in the thickness direction, and each wiring pattern 1a ', 1b', 6 is cut.
connection state between a 'and 6b', connection portions 2, 6a 'and 6b'
Observation of the positional deviation and deformation state of each indicated that a good connection state and positioning were secured, and the resistance of each connection part was 2 mΩ on average.

【0028】さらに、配線パターン1a′,1b′,6a′,
6b′間の接続部2,6a′,6b′の信頼性を評価するた
め、ホットオイルテストで( 260℃のオイル中に10秒浸
漬,20℃のオイル中に20秒浸漬のサイクルを 1サイクル
として)、 100回行っても不良発生は認められなかっ
た。
Further, the wiring patterns 1a ', 1b', 6a ',
In order to evaluate the reliability of the joints 2, 6a ', 6b' between 6b ', one cycle of a hot oil test (one cycle of immersion in oil at 260 ° C for 10 seconds, immersion in oil at 20 ° C for 20 seconds) As a result, no defect was observed even after 100 times.

【0029】本発明は上記実施例に限定されるものでな
く、本発明の趣旨を逸脱しない範囲で、いろいろの変形
を採ることができる。たとえば導電性バンプを形成する
導電性組成物として、銅粉入りペースト(商品名,DDペ
ースト タツタ電線KK製)などを、また、層間絶縁体と
して、ポリイミド樹脂系ボンディングフィルムなどを使
用することができる。
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, a paste containing copper powder (trade name, manufactured by DD Paste Tatsuta Electric Cable KK) or the like can be used as a conductive composition for forming a conductive bump, and a polyimide resin-based bonding film or the like can be used as an interlayer insulator. .

【0030】[0030]

【発明の効果】請求項1および2の発明によれば、コア
配線基板面に積層配線するために絶縁体層を積層・被覆
する際において、他の処理を別途施さずとも、部分的な
凹面化や厚さの変化など招来する恐れも解消される。つ
まり、全体的に緻密で、信頼性の高い絶縁性および配線
パターンが容易に確保されるとともに、導電性バンプの
微細化が可能なこと、貫挿による充填型のスルホール接
続と相俟って、高密度配線もしくは高密度実装型の多層
配線基板が提供される。また、コア配線基板に対する平
坦面化の処理などが省略されるため、製造工程も簡略と
なり、生産性や歩留まりの向上を図ることもできる。
According to the first and second aspects of the present invention, when laminating and covering an insulator layer for laminating wiring on the surface of a core wiring substrate, a partial concave surface can be obtained without performing another processing separately. The possibility of inconvenience such as change of thickness and change in thickness is also eliminated. In other words, the dense and reliable insulating properties and wiring patterns are easily secured as a whole, and the miniaturization of the conductive bumps is possible. A high-density wiring or a high-density mounting type multilayer wiring board is provided. In addition, since the process of flattening the core wiring substrate and the like are omitted, the manufacturing process is simplified, and productivity and yield can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a), (b), (c)は実施例に係る多層配線板に
使用されるコア配線基板の製造例を工程順に模式的に示
す断面図。
FIGS. 1A, 1B, and 1C are cross-sectional views schematically illustrating a manufacturing example of a core wiring board used for a multilayer wiring board according to an embodiment in the order of steps.

【図2】(a), (b), (c), (d), (e)は実施例に係る
多層配線板の製造例を工程順に模式的に示す断面図。
FIGS. 2 (a), (b), (c), (d), and (e) are cross-sectional views schematically showing an example of manufacturing a multilayer wiring board according to an example in the order of steps.

【符号の説明】[Explanation of symbols]

1a,1b……銅箔 1a′,1b′,6a′,6b′……配線パターン 2……コア配線基板のスルホール接続 2′……導電性バンプ 3,5a,5b,8a,8b……絶縁体層 4……コア配線基板 5a′,5b′……ビア接続開口部 6a,6b……銅メッキ層 7……多層配線基板 1a, 1b: Copper foil 1a ', 1b', 6a ', 6b': Wiring pattern 2: Through hole connection of core wiring board 2 ': Conductive bump 3, 5a, 5b, 8a, 8b: Insulation Body layer 4 Core wiring board 5a ', 5b' Via connection opening 6a, 6b Copper plating layer 7 Multilayer wiring board

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 層間絶縁体層を圧入・貫挿した導電性バ
ンプでスルホール接続されたコア配線基板と、 前記コア配線基板の少なくとも一主面に絶縁体層を介し
て積層形成され、かつコア配線基板の配線パターンにビ
ア接続する配線パターンとを有する多層配線基板であっ
て、 前記積層形成された配線パターンが複数層であることを
特徴とする多層配線基板。
1. A core wiring board connected through holes by conductive bumps into which an interlayer insulating layer is press-fitted and inserted, and a core laminated and formed on at least one principal surface of the core wiring board via an insulating layer. What is claimed is: 1. A multilayer wiring board, comprising: a wiring pattern connected to a wiring pattern of the wiring board via-connected to the wiring pattern, wherein the multilayered wiring pattern has a plurality of layers.
【請求項2】 第1の導電体層の所定位置に、第1の導
電性バンプを設ける工程と、 前記第1の導電性バンプ形成面に第1の絶縁体層を介し
て第2の導電体層を積層・配置する工程と、 前記積層体を加圧して第1の導電性バンプの先端部を、
第1の絶縁体層を圧入・貫挿させて対向する第2の導電
体層に接続して両面導体層張りコア積層板を形成する工
程と、 前記コア積層板の両面導電体層をそれぞれ配線パターニ
ングし、コア配線基板を形成する工程と、 前記コア配線基板の少なくとも一主面に絶縁体層を形成
し、コア配線基板の配線パターンに対する接続用のビア
を形設する工程と、 前記ビアを形設部を含む絶縁体層面に導電性メッキ層を
形成する工程と、 前記形成した導電性メッキ層を配線パターニングする工
程とを有することを特徴とする多層配線基板の製造方
法。
A step of providing a first conductive bump at a predetermined position of the first conductive layer; and a step of forming a second conductive bump on the first conductive bump forming surface via a first insulator layer. Stacking and arranging a body layer, and pressing the stack to form a tip of the first conductive bump,
A step of press-fitting and inserting the first insulator layer to connect to the opposing second conductor layer to form a double-sided conductor layer-clad core laminate; wiring the double-sided conductor layers of the core laminate respectively Patterning to form a core wiring board; forming an insulating layer on at least one main surface of the core wiring board; forming a via for connection to a wiring pattern of the core wiring board; A method for manufacturing a multilayer wiring board, comprising: a step of forming a conductive plating layer on a surface of an insulator layer including a shaping portion; and a step of wiring-patterning the formed conductive plating layer.
JP9142898A 1998-04-03 1998-04-03 Multilayer wiring board and method for manufacturing the same Pending JPH11289165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9142898A JPH11289165A (en) 1998-04-03 1998-04-03 Multilayer wiring board and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9142898A JPH11289165A (en) 1998-04-03 1998-04-03 Multilayer wiring board and method for manufacturing the same

Publications (1)

Publication Number Publication Date
JPH11289165A true JPH11289165A (en) 1999-10-19

Family

ID=14026115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9142898A Pending JPH11289165A (en) 1998-04-03 1998-04-03 Multilayer wiring board and method for manufacturing the same

Country Status (1)

Country Link
JP (1) JPH11289165A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001045478A1 (en) * 1999-12-14 2001-06-21 Matsushita Electric Industrial Co. Ltd. Multilayered printed wiring board and production method therefor
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
JP2005045191A (en) * 2003-07-04 2005-02-17 North:Kk Manufacturing method for wiring circuit board and for multi-layer wiring board
JP2007049194A (en) * 2006-10-23 2007-02-22 Dainippon Printing Co Ltd Printed-circuit board, and manufacturing method thereof
JP2011071533A (en) * 2008-04-03 2011-04-07 Samsung Electro-Mechanics Co Ltd Method of manufacturing multilayer printed circuit board

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001045478A1 (en) * 1999-12-14 2001-06-21 Matsushita Electric Industrial Co. Ltd. Multilayered printed wiring board and production method therefor
US6630630B1 (en) * 1999-12-14 2003-10-07 Matsushita Electric Industrial Co., Ltd. Multilayer printed wiring board and its manufacturing method
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
JP2005045191A (en) * 2003-07-04 2005-02-17 North:Kk Manufacturing method for wiring circuit board and for multi-layer wiring board
JP2007049194A (en) * 2006-10-23 2007-02-22 Dainippon Printing Co Ltd Printed-circuit board, and manufacturing method thereof
JP4485505B2 (en) * 2006-10-23 2010-06-23 大日本印刷株式会社 Printed circuit board and method for manufacturing printed circuit board
JP2011071533A (en) * 2008-04-03 2011-04-07 Samsung Electro-Mechanics Co Ltd Method of manufacturing multilayer printed circuit board
JP2013030807A (en) * 2008-04-03 2013-02-07 Samsung Electro-Mechanics Co Ltd Method of manufacturing multilayered printed circuit board

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