JPH1127137A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the stability and high speed property of a level conversion operation for a signal output to the outside when the amplitude of an internal signal is small to an external signal. SOLUTION: This circuit consists of a 1st circuit 11 which makes 1st power supply voltage VDL operating power supply and outputs a 1st signal S1, a level conversion circuit 13 which makes 2nd power supply voltage VDH that has a higher level than the voltage VDL operating power supply and converts the amplitude of the signal S1 into an amplitude corresponding to the voltage VDH and an output circuit 14 which makes the voltage VDH operating power supply and performs an external output operation in accordance with a logical value of a 2nd signal outputted by the circuit 13. In such cases, a booster circuit 12 which makes the voltage VDL operating power supply, boosts a high level of the 1st signal and supplies it to the circuit 13 is provided, and drain current of differential input MOS transistors M3 and M4 of the circuit 13 is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which the operating power of an internal circuit is made lower with respect to the level of an interface signal with the outside, in other words, the amplitude of an internal signal is smaller than that of an external signal. The present invention relates to a technology effective when applied to the realization of stability and high-speed operation of an external output operation of a CMOS (complementary MOS) integrated circuit using two power supplies.

[0002]

2. Description of the Related Art When elements are miniaturized in order to increase the degree of integration and operation speed of a semiconductor integrated circuit, the power supply voltage is reduced. At this time, the power supply specification of the system using the semiconductor integrated circuit is not always reduced. In that case, regarding the external interface specification, a signal amplitude such as 5 V before the voltage is reduced may be required.

In this case, when outputting the low voltage signal amplitude in the internal circuit of the semiconductor integrated circuit to the outside, the signal amplitude must be converted to a signal amplitude before the low voltage such as 5V.

For example, a CMOS static latch can be used as a circuit for performing such amplitude conversion.
That is, a series circuit of a pair of p-channel MOS transistors and an n-channel MOS transistor is provided in parallel, and the gate of one p-channel MOS transistor is cross-coupled to the drain of the other p-channel MOS transistor. An n-channel MOS transistor is configured as a pair of differential input MOS transistors.

Examples of documents describing level conversion using a static latch include "Ultra LSI Memory" (published by Baifukan Co., Ltd. in April 1994) and "A Hi
gh-Speed Low-Power 0.3μm CMOS Gate Array with VT
Scheme (CICC 1996) ".

[0006]

However, in the level conversion using the static latch, a differential input MO is used.
The present inventor has clarified that since the gate voltage of the S-transistor is low, high-speed operation cannot be expected and there is a risk of malfunction due to process variation. For example, consider the circuit of FIG. The static latch is composed of p-channel MOS transistors M1 and M2 and n-channel MOS transistors M3 and M4.
The CMOS inverter including the OS transistor M5 and the n-channel MOS transistor M6 uses a relatively high power supply voltage VDH such as 5V as an operation power supply. Differential input MOS transistors M3, M of static latch
The inverters 1 and 2 that supply signals to the inverter 4 use a relatively low power supply voltage VDL such as 3.3 V as an operation power supply. A logic signal to be output from the inside of the semiconductor integrated circuit to the outside is supplied to the input of the inverter 1. The operating power supply of the internal circuit is VDL, and the maximum signal amplitude of the logic signal has a potential difference from the ground potential GND to the power supply voltage VDL.

The level conversion operation by the static latch shown in FIG. 6 is based on the premise that the latch state can be inverted by the current flowing through the MOS transistor M3 or M4.
For example, when the level of the node N1 is at the level of the power supply voltage VDH and the gate voltage of the MOS transistor M4 is at the high level of the power supply voltage VDL, MO
A through current flows through the S transistors M2 and M4. At this time, if the level of the node N1 is not sufficiently lowered, the MOS transistor M1 is not turned on, and no feedback is applied to the static latch. Therefore, return to MO
To turn on the S transistor M1, when the transistors M2 and M4 are turned on at the same time,
The ON resistance of the S transistor M4 is the MOS transistor M
2 must be smaller than the on-resistance. In other words, the MOS transistor M4 must have a larger transconductance than the MOS transistor M2.

However, while the gate voltage of the MOS transistor M4 is at most the level of the power supply voltage VDL, the amplitude of the gate input signal of the MOS transistor M2 has an amplitude corresponding to the high level of the power supply voltage VDH. In terms of supply capability, the MOS transistor M4 is disadvantageous in terms of the gate input voltage as compared with the MOS transistor M2.

Therefore, the transistor size (channel width) of the MOS transistor M2 must be reduced to reduce its current supply capability. Then, the present inventor has clarified that the transient response time of the static latch becomes longer and the determination of the output operation is delayed.

Thus, the MOS transistors M2 and M4
Since the relationship between the current supply capability and the current supply capability is important in operation, the size of both transistors M2 and M4 is barely required to satisfy both requirements of the inversion operation of the static latch and the shortening of the transient response period of the static latch. Is determined, the p-channel MOS transistor and n
The present inventor has clarified that the static latch itself may not operate if the drain current of both MOS transistors M2 and M4 fluctuates from a predetermined value due to a variation in the manufacturing process with the channel type MOS transistor. Was done. This relationship is the same for the MOS transistors M1 and M3.

An object of the present invention is to provide a semiconductor integrated circuit in which the operating power of an internal circuit is reduced with respect to the level of an external interface signal, in other words, the amplitude of an internal signal is reduced with respect to the amplitude of an external signal. In semiconductor integrated circuits,
An object of the present invention is to provide a semiconductor integrated circuit capable of realizing stability and high speed of a level conversion operation for outputting a signal to the outside.

Another object of the present invention is to provide a level conversion circuit for converting an internal signal having a small signal amplitude into the amplitude of an external output signal having a large signal amplitude by employing a static latch due to manufacturing variations in transistor characteristics. It is an object of the present invention to provide a semiconductor integrated circuit which does not easily cause a malfunction and can reduce a transient response time of an inversion latch operation of a static latch.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a first circuit (11) operated using a first power supply voltage (VDL) as an operation power supply, and a second power supply voltage (VD) having a higher level than the first power supply voltage.
H) as an operating power supply, and a first output from the first circuit.
A level conversion circuit (13) for converting the signal amplitude of the signal (S1) into a signal amplitude corresponding to the second power supply voltage, and a second output from the level conversion circuit using the second power supply voltage as an operation power supply. And an output circuit (14) that performs an external output operation in accordance with the logical value of the signal (S2), wherein the first power supply voltage is used as an operation power supply and the first signal is at a high level. And a booster circuit (12) for boosting and supplying the boosted level to the level conversion circuit. Since the high level supplied to the level conversion circuit (13) operated by the second power supply voltage has a level boosted from the first power supply voltage, the transistors (M3, M4) receiving that level at the control terminal ), The current supply capability or the transconductance is increased, which increases the speed and stability of the transient response operation of the level conversion circuit.

More specifically, the level conversion circuit has a static latch configuration including a pair of differential input transistors (M3, M4) to which complementary signals (out, -out) are supplied, and has a storage node (N1). ) To output the second signal (S2). The booster circuit increases a booster capacitance (C1, C2) in response to a change from a low level to a high level for each of the complementary signals (in, -in) of the first signal.
Boosting section (1) boosting a high-level voltage level through
20, 121), and outputs (out, -o) of each booster.
ut) is a complementary signal to the level conversion circuit. Thereby, the pair of differential input transistors (M3, M4)
The high level of the complementary signal supplied to the gates of the differential input transistors (M3, M4) has a higher level than the first power supply voltage (VDL), so that the current supply capability or the mutual conductance of the differential input transistors (M3, M4) is increased. Thus, the speed and stability of the transient response operation of the level conversion circuit can be increased.

The level conversion circuit can be constituted by a CMOS static latch circuit, and the output circuit is a CMOS inverter which inputs a signal output from one storage node of the CMOS static latch circuit as a second signal. It can be configured by a circuit.

In order to enable the output circuit to be controlled to a high output impedance state, the output circuit has first and second output transistors (M5, M6) connected in series, and the series connection point is used as an output terminal. , The booster circuit (12A, 1A) for each control terminal of the first and second output transistors.
2B) and the level conversion circuits (13A, 13B)), and further supplied to the first and second transistors via a path for supplying the first signal to both of the booster circuits. Gate means (3A, 3B) for selectively forcing the second signal to a level for controlling the output circuit to a high output impedance state may be provided.

[0019]

FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit technology. The semiconductor integrated circuit 10 shown in FIG. 1 has a relatively low level power supply voltage (first power supply voltage) VDL such as 3.3V.
And a relatively high power supply voltage such as 5 V (second
Is the operating power supply. GND is 0V
The ground voltage is as follows. For example, the power supply voltage VDL is generated by stepping down the power supply voltage VDH by an internal step-down circuit. Alternatively, power supply voltages VDL and VD can be supplied from dedicated external power supply terminals, respectively.
You may receive H.

In the semiconductor integrated circuit 10 shown in FIG. 1, circuits denoted by reference numerals 11, 1, and 2 respectively include a power supply voltage VD
This circuit uses L as the operating power supply. When the semiconductor integrated circuit 10 is a logic LSI (Large Scale Integrated Circuit), the internal circuit 11 performs an appropriate logic operation. In FIG. 1, one signal S1 is typically output from the internal circuit 11. The signal S1 is a logic signal that the internal circuit 11 intends to output to the outside. The amplitude of the logic signal S1 is in the range from the ground voltage GND to the power supply voltage VDL. For example, the low level is the level of the ground voltage GND, and the high level is the level of the power supply voltage VDL. Inverters 1 and 2
Converts the signal S1 into complementary signals in and -in. The amplitudes of the complementary signals in and -in are the same as the signal S1.

The booster circuit 12 supplies the complementary signals in, -in
Is a booster circuit that boosts the high level of the signal by using a capacitive element. The booster circuit 12 uses the power supply voltage VDL as an operation power supply, and outputs complementary signals out and -out whose high level has been boosted.
Is output.

The level conversion circuit 13 has a CMOS static latch form, and has a pair of n-channel type differential inputs M.
The signal ou is applied to the gates of the OSD transistors M3 and M4.
In response to t and -out, the output signal amplitude is converted into a signal S2 having a signal amplitude corresponding to the power supply voltage VDH. Differential input MOS
In the p-channel MOS transistors M1 and M2 forming a load with respect to the transistors M3 and M4, the gate of one p-channel MOS transistor is cross-coupled to the drain of the other p-channel MOS transistor.

The output circuit 14 uses a power supply voltage VDH as an operation power supply, and is configured as a CMOS inverter circuit including a p-channel MOS transistor M5 and an n-channel MOS transistor M6. MOS transistor M
5, the gate of M6 is supplied with the signal S2,
The common drain of transistors M5 and M6 is output pad 1
5 The output pad 15 is, for example, a bonding pad.

FIG. 2 shows an example of the booster circuit 12. In FIG. 2, a p-channel MOS transistor M
The boosting unit 120, which includes the transistors M7, M9, and M11, the n-channel MOS transistors M8, M10, and M12, and the capacitor C1, generates a signal out from the signal in. P-channel type MOS transistors M17, M19, M21 and n-channel type MOS transistors M18, M20, M22, which are constructed in substantially the same manner.
And the booster 121 configured by the capacitive element C2,
A signal -out is generated from the signal -in.

In the booster 120, the MOS transistor M8 forms a pull-up MOS transistor diode-connected to the node N3, the transistor M7 charges the node N3 according to the low level of the signal in, and the transistor M10 charges the node N3. Discharging the node N2 in response to the operation (the signal -in is at a high level);
The capacitor C1 is charged to the power supply voltage VDL. During this charging operation, the MOS transistor M11 is turned off, and M
The OS transistor M12 is turned on, and the output signal o
ut is at a low level.

When the logical values of the input signals in and -in are inverted (in = high level, -in = low level), the MO
The charging operation by S transistor M7 is stopped, MOS transistor M9 is turned on (M10 is turned off), and node N2 is charged. Thereby, the level of node N3 coupled via capacitive element C1 is raised from the level of power supply voltage VDL. At this time, MO
Since the S transistor M12 is turned off and the MOS transistor M11 is turned on, the output signal out is set to a level boosted from the power supply voltage VDL.

Thereafter, when the logic values of the input signals in and -in are again inverted (in = low level, -in = high level), the node N2 is set to the low level, and the level of the node N3 is correspondingly changed. Reduced by capacitive coupling.
At this time, in order to prevent the level of the node N3 from being excessively lowered, the pull-up MOS transistor M8 having a relatively small conductance is used to control the node N3.
Is previously charged to a level lower than the power supply voltage VDL by the threshold voltage of the MOS transistor M8 to secure a level required for the next boosting operation.

The booster 121 operates in a complementary manner to the booster 120, and its basic operation and operation are the same as those described above.

FIG. 3 shows an example of the waveform of the output signal out which is boosted with respect to the input signal in. As shown in the figure, the high levels of the signals out and -out input to the differential input MOS transistors M3 and M4 of the level conversion circuit 13 are boosted to the low level power supply voltage VDL or higher, so that the MOS transistor M3 , M4 can be increased. When the MOS transistor M4 is turned on in a state where the level of the node N1 in FIG. 1 is at the level of the power supply voltage VDH, the signal level of the MOS transistor M4 is raised to a level higher than the power supply voltage VDL level. out is supplied to the gate electrode. The drain current flowing through the MOS transistor M4 is made larger than when the high level of the power supply voltage level VDL is supplied to the gate electrode of the MOS transistor M4. As a result, the level of the node N1 rapidly decreases, and the MOS transistor M1 is turned on, so that M
The transient response operation time until the OS transistor M2 is turned off is shortened. Therefore, the operation until the signal S2 is inverted according to the change of the signal S1 is speeded up, and the speed of the output operation can be increased.

As described above, since the current flowing through the MOS transistor M4 can be increased, the transistor size (channel width) of the MOS transistor M2 is reduced and the drain current of the MOS transistor M4 is reduced as discussed previously by the present inventors. Need not be dealt with.
For this reason, the output operation can be settled earlier. Moreover, it is not necessary to determine the size ratio of the two transistors M2 and M4 at the last minute in order to satisfy both requirements of the inversion operation of the level conversion circuit and the reduction of the transient response period of the level conversion circuit. There is some variation in the manufacturing process between the channel type MOS transistor and the n-channel type MOS transistor.
Even if the drain currents of the S transistors M2 and M4 vary from a predetermined value, it is possible to prevent the level conversion circuit 13 from being unable to perform a latch operation.

FIG. 4 shows an example in which the output circuit 14 can be controlled to have a high output impedance. 12A,
Reference numeral 12B is the same booster circuit as the booster circuit 12 in FIG. 1
3A and 13B are the same circuits as the level conversion circuit 13 in FIG. MOS transistor M constituting output circuit 14
5 and M6, each has a booster circuit 12A, 12B and a level conversion circuit 13A, 13B. The output signal S2A of the level conversion circuit 13A is supplied to the gate of the MOS transistor M5, and the output signal S2B of the level conversion circuit 13B is
It is supplied to the gate of the S transistor M6. Inverters 2A and 2B are the same as inverter 2 in FIG. The input terminal of the inverter 2A is coupled to the output terminal of a two-input NOR gate 3A, and the input terminal of the inverter 2B is coupled to the output terminal of a two-input NAND gate 3B. The gate 3
The signal S1 is supplied to one input terminal of A and 3B. An output enable signal OE is supplied to the other input terminal of the NOR gate 3A, and a signal obtained by inverting the output enable signal OE by the inverter 4 is supplied to the other input terminal of the NAND gate 3B.

The output enable signal OE instructs an output operation according to a low level. In this state, the NAND gate 3A and the NOR gate 3B perform the same inversion operation as the inverter. Therefore, if the signal S1 is at a low level, the signals S2A and S2B are both at a high level, and the output circuit outputs a low level. When the signal S1 is at a high level, the operation is reversed. The output enable signal OE indicates a high output impedance state when it is at a high level. In this state, inA = high level, -i
nA is fixed to a low level, and thereby the signal S2A
Is fixed at a high level, and the MOS transistor M5 is turned off. Similarly, when a high output impedance state is indicated by the high level of the output enable signal OE, inB is fixed at a low level and -inB is fixed at a high level, whereby the signal S2B is fixed at a low level, and the MOS transistor M6 is turned on. It is turned off.
Therefore, the output circuit 14 can select an output operable state or a high output impedance state. Even in such a configuration, similarly to FIG. 1, the semiconductor integrated circuit in which the operation power of the internal circuit is lowered with respect to the level of the interface signal with the outside, in other words, the amplitude of the internal signal with respect to the amplitude of the external signal In a semiconductor integrated circuit having reduced size, the stability and high speed of the level conversion operation for outputting a signal to the outside can be realized.

FIG. 5 shows another example of the level conversion circuit. The level conversion circuit 13A shown in the figure is different from the level conversion circuit 13 in FIG.
This is one in which transistors M31 and M32 are further arranged. The signal out is connected to the gate of the MOS transistor M31.
Is supplied to the gate of the MOS transistor M32, and the signal -out is supplied to the gate of the MOS transistor M32. In this circuit, MOS
In the pair of transistors M3 and M31 and the pair of MOS transistors M4 and M32, since the respective p-channel MOS transistors and n-channel MOSD transistors switch complementarily, the signal S2 is changed from high level to low level. The MOS transistor M3 without waiting for the ON state of the MOS transistor M1.
2 is turned off, the change of the signal S2 from the high level to the low level is further accelerated. Similarly, when the signal S2 changes from the low level to the high level, the MOS transistor M32 is about to be turned on without waiting for the off state of the MOS transistor M1, so that the signal S2 changes from the low level to the high level. The change is even faster.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, other circuit configurations can be adopted for the booster circuit and the level conversion circuit. In the above description, the gate input signals of both differential input transistors M3 and M4 of the level conversion circuit are configured to be able to boost. However, when the level conversion circuit is used for single-ended output, one of the output side differentials is used. Dynamic input MOS transistor M4
May be boosted only. Even if only one side of the output side is boosted, the normal operation as a static latch is guaranteed and the area occupied by the chip by the booster circuit can be reduced.

The semiconductor integrated circuit according to the present invention has an ASIC
(Application Specific Integrated Circuit), custom LSI, semi-custom LSI, etc.
In terms of functions such as a memory LSI and a logic LSI, the present invention can be applied to various semiconductor integrated circuits.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit in which the operating power of the internal circuit is made lower than the level of the interface signal with the outside, in other words, in a semiconductor integrated circuit in which the amplitude of the internal signal is made smaller than the amplitude of the external signal. Thus, the stability and high speed of the level conversion operation for outputting the signal to the outside can be realized.

Further, when a static latch is employed as a level conversion circuit for converting an internal signal having a small signal amplitude into the amplitude of an external output signal having a large signal amplitude, a malfunction is unlikely to occur due to manufacturing variations in transistor characteristics. The transient response time of the inverting latch operation in the static latch can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit showing an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of a booster circuit.

FIG. 3 is an output signal ou boosted with respect to an input signal in;
FIG. 9 is a waveform chart showing an example of a waveform at t.

FIG. 4 is a block diagram illustrating an example of a configuration in which an output circuit is capable of high output impedance control.

FIG. 5 is a circuit diagram showing another example of the level conversion circuit.

FIG. 6 is an explanatory diagram of a level conversion circuit and an output circuit studied by the present inventors.

[Explanation of symbols]

 1, 2 Inverter 3A NOR gate circuit 3B NAND gate circuit 10 Semiconductor integrated circuit 11 Internal circuit 12, 12A, 12B Boost circuit 120, 121 Boost unit 1313A, 13B Level conversion circuit 14 Output circuit M1, M2 Load MOS transistor M3, M4 Differential input MOS transistor S1 Output signal of internal circuit in, -in Input signal of boost circuit out, -out Output signal of boost circuit S2 Output signal of level conversion circuit C1, C2 Capacitance element VDL First power supply voltage VDH Second power supply voltage

Claims (4)

[Claims] 1. A first circuit which operates using a first power supply voltage as an operation power supply, and an output from the first circuit which uses a second power supply voltage higher in level than the first power supply voltage as an operation power supply A level conversion circuit for converting the signal amplitude of the first signal to be converted into a signal amplitude corresponding to the second power supply voltage, and a second signal output from the level conversion circuit using the second power supply voltage as an operation power supply And an output circuit that performs an external output operation in accordance with the logical value of (i), wherein the first power supply voltage is used as an operation power supply, and a high level of the first signal is boosted and supplied to the level conversion circuit. A semiconductor integrated circuit comprising a booster circuit. 2. The level conversion circuit has a static latch configuration including a pair of differential input transistors to which a complementary signal is supplied, and outputs the second signal from a storage node thereof. For each of the complementary signals of the first signal,
A booster that boosts a high-level voltage level via a booster capacitor according to a change from a low level to a high level;
2. The semiconductor integrated circuit according to claim 1, wherein an output of each booster is a complementary signal to said level conversion circuit. 3. The level conversion circuit is a CMOS static latch circuit, and the output circuit is a CMOS inverter circuit that inputs a signal output from one storage node of the CMOS static latch circuit as a second signal. 3. The semiconductor integrated circuit according to claim 2, wherein: 4. The output circuit has first and second output transistors connected in series, and a series connection point is used as an output terminal. Each of the control terminals of the first and second output transistors is connected to the booster circuit. And a second signal individually supplied to the first and second transistors in a path for supplying the first signal to both of the booster circuits. 3. The semiconductor integrated circuit according to claim 2, further comprising gate means for selectively forcing a level to control the output circuit to a high output impedance state.