JPH06291638A - Semiconductor unit - Google Patents

Abstract

PURPOSE:To prevent a leak current from flowing through a parasitic diode at the time of the high impedance of an input/output buffer circuit when performing bus connection at a certain voltage higher than that of 7 an own power source. CONSTITUTION:This device is provided with an N channel MOS transistor 114 to connect a source/drain current path between output terminals 110 and 111 of an output buffer 101 composed of a P channel MOS transistor 112 and an N channel MOS transistor 113. The gate of the transistor 114 is controlled by an enable signal for controlling it to the high impedance state of an output buffer 101, and the leak current is prevented caused by the parasitic diode from flowing from an input/output terminal 111 to a power source VDD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a CMOS type input / output buffer protection circuit against an external signal.

[0002]

2. Description of the Related Art The power supply voltage of an LSI used in recent electronic devices such as personal computers is
To reduce the power consumption of electronic devices, lower voltage has been achieved, and the 5V power supply voltage is rapidly becoming 3.3V.

However, not all the LSIs on the printed circuit boards of the above electronic devices have been converted to 3.3V, and therefore 3.3V is used for an ASIC (application specific integrated circuit) for glue logic or bus interface. System and 5
A device that handles both V-system signals is required.

Even in the CMOS type gate array which is a standard ASIC product, the power supply voltage thereof is becoming lower, and products capable of handling both 3.3V and 5V signals are being put on the market. .

LS of this CMOS type gate array
The semiconductor device I is generally composed of a plurality of P channel MOSs.
Cell having a plurality of P-channel MOS transistors and N-channel MOS transistors as basic elements and a plurality of external cells having a plurality of P-channel MOS transistors and N-channel MOS transistors It has a configuration as. The above-mentioned external cell has a function of level conversion between the input / output signal level (generally TTL level) to this LSI and the CMOS level signal of the internal cell in order to interface this LSI with another LSI.

Referring to FIG. 5, which shows a circuit diagram of an output external cell of a conventional CMOS type LSI semiconductor device, a conventional output external cell 500 is a P channel having a source connected to a power supply VDD and a drain connected to an output terminal 510. Type MOS
Transistor 512 and N-channel MOS transistor 5 whose source is grounded and whose drain is connected to output terminal 510
13 has an output buffer 501 and an output terminal 511 connected to the output terminal 510 and outputting an output signal to the outside.

Further, this conventional output external cell 500
Is a 2-input NAND circuit 518 for receiving a data input signal D1 at its input end 504 and an enable signal EN at its input end 505 and a data input signal D.
1 and a 2-input NOR circuit 507 which receives an inverted signal of the enable signal EN inverted by the inverter circuit 520, and outputs the output of the 2-input NAND circuit 518 via the output terminal 506 to the P-channel MOS transistor 512.
Of the 2-input NOR circuit 519 connected to the gate of the N-channel MOS transistor 5 via the output terminal 507.
P-channel type MOS transistor 512 and N-channel type MOS transistor 5 connected to the gate of No. 13 by the data input signal D1 and the enable signal EN.
Output buffer control circuit 50 for controlling ON / OFF of 13
Have two.

Next, the operation of the conventional output external cell 500 will be described.

When a potential of about 5.0 V is applied to the power supply VDD and the enable signal EN is at a high level (hereinafter referred to as "H"), the "H" signal is input to one input of the 2-input NAND circuit 518. Is input to one input of the 2-input NOR circuit 519, and a low level signal (hereinafter referred to as “L”) of the inverted signal of the enable signal EN is input.

The 2-input NAND circuit 518 and the 2-input NOR circuit 519 output the inverted signal of the data input signal D1 from their respective circuits 518 and 519, and when the data input signal D1 is "H", the 2-input NAND circuit. 5
The respective outputs of the 18- and 2-input NOR circuits 519 are "L", and when the data input signal D1 is "L", the respective outputs described above are "H".

Therefore, in the external cell 500, when the data input signal D1 is "H", the P-channel MOS transistor 512 is turned on and the N-channel MOS transistor 513 is turned off to output a "H" signal. On the other hand, when the data input signal D1 is "L", the P channel type MOS
The transistor 512 is turned off and the N-channel type MOS transistor 513 is turned on to output an “L” signal.

When the enable signal EN is "L", one input of the 2-input NAND circuit 518 is "L".
Signal is input and the “H” signal is input to one input of the 2-input NOR circuit 519.

The outputs of the 2-input NAND circuit 518 and the 2-input NOR circuit 519 are determined by the enable signal EN, and do not depend on the data input signal D1. The 2-input NAND circuit 518 inputs the "H" signal to the 2-input. NO
The R circuit 519 outputs an “L” signal.

Therefore, this CMOS output buffer 5
01 is a P-channel MOS transistor 512 and N
Both of the channel type MOS transistors 513 are turned off to be in a high impedance state.

As described above, the conventional output external cell 500 functions as a 3-state output circuit.

Next, a prior art CMOS type LSI
6, which shows an input external cell of the semiconductor device of FIG.
This input external cell 600 has a P-channel type MOS transistor 612 whose source is connected to the power supply VDD and whose gate is connected to the input end 606, and an N-channel type MOS transistor 613 whose source is grounded and whose gate is connected to the input end 606. The drains of the transistor 612 and the transistor 613 are connected to each other, and a signal is supplied to the internal cell via the output terminal 610.

The CMOS input buffer 601 has a P-channel and N-channel MOS transistor 612.
And a diode 613 for receiving an input signal, an electrostatic protection diode element 6 for preventing destruction by static electricity.
04 and 605, the diode 604 has its anode connected to the input end 606 and its cathode connected to the power supply VDD, the diode 605 has its input grounded and its cathode connected to the input end 606;
And an input terminal 611.

Next, the operation of the conventional input external cell 600 will be described.

When a potential of about 5.0 V is applied to the power supply VDD and an input signal of "H" of TTL level is supplied to the input terminal 611, the P-channel MOS transistor 612 is turned off and the N-channel MOS transistor is turned on. 613
This input buffer 601 outputs a CMOS level "L" to output 6
Supply to the internal cell via 10.

On the other hand, when an "L" level input signal at the TTL level is supplied to the input terminal 611, the P-channel type MOS transistor 612 turns on and the N-channel type MOS transistor is turned on.
The transistor 613 is turned off, the CMOS level of “H” is output, and this output signal is supplied to the internal cell via the output terminal 610.

Further, in order to save power, the power supply voltage supplied to the LSI has been lowered, and the power supply voltage of 5V is 3.3V.
The conventional CMOS type gate array LSI
The power supply voltage VDD of the semiconductor device is supplied at 3.3V.

At this time, the conventional CMOS type LS is used.
The power supply VDD of the output external cell 500 of I also functions as an output circuit in the 3-state state by being supplied by being lowered from 5.0V to 3.3V, and the input external cell 600 similarly changes its power supply VDD from 5.0V to 3V. It operates by converting the TTL input signal to a CMOS level signal supplied by being lowered to 0.3V.

[0023]

However, when the enable signal EN of the output external cell 500 described above is "L", the output external cell 500 is in a high impedance state. At this time, the potential 3.
When a bus VDDEX having a potential higher than 3V (for example, a signal of 5V) is connected to the terminal 521, the terminal 521 is passed through the parasitic diode 515 between the drain region of the P-channel type MOS transistor 512 and the N well or the N type substrate.
There is a problem that a leak current flows from the power supply VDD to the power supply VDD via the output terminal 511 and the output terminal 510.

In addition, the above-mentioned input external cell 600 is the other L
When receiving an "H" signal of about 5V of the SI output signal, there is also a problem that a leak current flows from the terminal 621 to the power supply VDD through the input terminal 611 through the electrostatic protection diode element 604.

Therefore, an object of the present invention is to provide a CMOS type LS having an output external cell capable of preventing generation of a leak current even if a bus having a potential higher than the potential of a power supply is connected.
It is an object of the present invention to provide a semiconductor device of CMOS type having a semiconductor device of I and an input external cell capable of preventing generation of a leak current even when receiving an input level higher than the potential of a power supply.

[0026]

The semiconductor device of the present invention comprises:
The first and second power supply terminals, the plurality of output terminals, the plurality of output buffers for supplying the output signals to the output terminals, and the output state of the output buffer by receiving at least one control signal. In a semiconductor device having an output buffer control circuit for controlling, a MOS transistor connecting a source / drain path between the output terminal and an output end of the output buffer, and receiving the control signal and outputting its output to the MOS transistor. Supply to the gate and the MO
A protection transistor control circuit for controlling ON / OFF of the S transistor is provided.

Further, another semiconductor device of the present invention is a plurality of first and second power supply terminals and a plurality of externally supplied input signals or externally supplied output signals and outputting the output signals to the outside. A semiconductor device having a plurality of input / output terminals, a plurality of input buffers for receiving the output signals, and an output buffer control circuit for receiving at least one control signal and controlling an output state of the output buffers. A first MOS transistor connecting a source / drain path between the input / output terminal and the output terminal of the output buffer;
To the gate of the MOS transistor of the first M
A protection transistor control circuit for controlling on / off of an OS transistor, and a second MOS transistor for connecting a source / drain passage between the input / output terminal and an input end of the input buffer and supplying a power supply potential to its gate. And a configuration having.

Still another semiconductor device of the present invention is
In a semiconductor device having first and second power supply terminals, a plurality of input terminals receiving an input signal from the outside, and a plurality of input buffers receiving the input signal via the input terminals, A semiconductor device comprising a source / drain passage connected between a terminal and an input end of the input buffer, and a MOS transistor for supplying a power supply potential to a gate thereof.

Further, the semiconductor device of the present invention comprises the MOS
The transistor may be a depletion type N-channel MOS transistor.

Further, in the semiconductor device of the present invention, the output buffer includes a P-channel type MOS transistor having a source connected to the first power supply terminal and an N-channel type MOS transistor having a source connected to the second terminal. The drains of the P-channel type MOS transistor and the N-channel type MOS transistor may be connected to the output terminal of the output buffer.

Still further, in the semiconductor device of the present invention, the output buffer control circuit has a first input end to which a data input signal is supplied and a second input end to which an enable signal is supplied and the first and the first and second input ends. A NAND circuit for connecting its input to the second input terminal and connecting its output to the gate of the P-channel type MOS transistor; and a first input terminal for connecting one end of the input to the second input terminal for an inverter circuit A NOR circuit that connects the other end of the input to the gate of the N-channel type MOS transistor through the output buffer and outputs the data input signal from the output buffer at a high level of the enable signal. The output buffer may be in a high impedance state when the enable signal is at a low level.

Further, in the configuration of the semiconductor device of the present invention, the control signal of the protection transistor control circuit is the enable signal, and when the enable signal is at a high level, the MOS transistor is turned on and the enable signal is at a low level. Sometimes the MOS transistor can be turned off.

Further, in the semiconductor device of the present invention, the protection transistor control circuit has a drain connected to the first power supply terminal and a gate connected to the first N-channel MOS transistor for receiving the enable signal. A second N-channel MOS transistor connected to the first power supply terminal via a load and receiving a reference potential at its gate, and a constant current is applied to the sources of the first and second N-channel MOS transistors. It may be configured such that the output signal from the source of the second N-channel MOS transistor is supplied to the gate of the MOS protection transistor by connecting to the second power supply terminal via a source.

Further, in the semiconductor device of the present invention, the protection transistor control circuit connects the sources and drains of the first P-channel MOS transistor and the first N-channel MOS transistor, respectively. The enable signal is supplied to the gate of the first P-channel MOS transistor and the inverted signal of the enable signal is supplied to the gate of the first N-channel MOS transistor and supplied to its input terminal. A first transfer gate circuit for outputting the low potential of the MOS transistor from its output terminal to turn off the MOS transistor,
The sources and drains of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other, and the inverted signal of the enable signal is supplied to the gate of the second P-channel MOS transistor. For supplying the second N-channel type M
A second transfer gate circuit for supplying the enable signal to the gate of the OS transistor and outputting a desired high potential supplied to the input terminal from the output terminal to turn on the MOS transistor is provided. You can also

[0035]

Next, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, in the output external cell 100 of the semiconductor device of the first embodiment, the source is a power supply VDD.
P-channel MO with drain connected to output 110
An S-channel transistor 112 and an N-channel type M whose source is connected to the ground potential GND and whose drain is connected to the output terminal 110.
It has a CMOS output buffer 101 composed of an OS transistor 113. Further, the output external cell 100 of the semiconductor device according to the first embodiment has the data input signal D1.
To the input terminal 104 and the enable signal EN to the input terminal 5
2 inputs N to receive these signals at 05
An AND circuit 118 and a 2-input NOR circuit 119 which inputs the inverted signal of the enable signal EN via the data input signal D1 and the inverter circuit 120, and the output of the 2-input NAND circuit 118 is output via the output terminal 106 to the P channel. Connected to the gate of the MOS transistor 112,
The output of the 2-input NOR circuit is connected to the gate of the N-channel type MOS transistor 113 via the output terminal 107,
It has a control circuit 102 for controlling on / off of the transistor 113 and the transistor 112 by the data input signal D1 and the enable signal EN.

Furthermore, the output external cell 100 of the semiconductor device of the first embodiment is an N-channel MOS which receives the enable signal EN at the terminal 108, inputs the signal to the gate, and connects the drain to the power supply VDD. A transistor 115, an N-channel MOS transistor 116 having a gate to which a reference potential VREF is input and a drain connected to a power supply VDD via a resistive load 122, and the transistor 11
A constant current source 1 is provided between the sources 5 and 116.
Connected to the ground potential GND via 17, and the resistance load 122
To the drain of the transistor 116 and output terminal 1
09 protection transistor control circuit 103 configured to be connected to
Have.

Further, in the output external cell 100 of the semiconductor device of the first embodiment, the source / drain current path is connected to the output terminal 110 and the output terminal 111 and the gate thereof is connected to the output terminal 109 to turn on / off. This is a configuration having a depletion type N-channel MOS transistor 114 that is turned off. This transistor 114 has its threshold voltage V
Set T to about VT = 0 volts. Also, the reference potential VR
EF is VDD / 2 which is the logic threshold value of the enable signal EN.
Set to a degree.

Next, the operation of the semiconductor device of the first embodiment of the present invention will be described.

First, a case where a potential of about 3.3V is applied to the power supply VDD and the enable signal EN is "H" will be described.

The "H" signal is input to one input of the 2-input NAND circuit 118, and the "L" signal which is the inverted signal of the enable signal EN is input to one input of the 2-input NOR circuit 119.

That is, both the 2-input NAND circuit 118 and the 2-input NOR circuit 119 output the inverted signal of the data input signal D1 by the respective circuits 118 and 119,
When the data input signal D1 is "H", the outputs of the 2-input NAND circuit 118 and the 2-input NOR circuit 119 are "L", and when the data input signal D1 is "L", the above output is "H". Becomes

Therefore, the data input signal D1 is "H".
When, the transistor 112 turns on and the transistor 11
3 turns off and outputs a signal of "H" to the terminal 110. On the other hand, when the data input signal D1 is "L", the transistor 112 is turned off and the transistor 113 is turned on to "L".
Signal is output to the terminal 110.

At the same time, the enable signal EN is also input to the input terminal 108 of the protection transistor control circuit 103. Since the reference potential VREF is set to the potential (1/2 of VDD) which is the logical threshold value of the enable signal EN, the transistor 115 is turned on and the transistor 116 is turned off when the enable signal EN is “H”. . Therefore, the high level of the power supply potential VDD is output to the output terminal 109. The output signal is input to the gate of the N-channel MOS transistor 114, the transistor 114 is turned on, and the data signal D1 output to the output terminal 110 of the output buffer 101 is output to the outside via the output terminal 111. .

That is, this protection MOS transistor 1
This output external cell 100 has the same function as the conventional output external cell 500 to which 14 is not connected.

Next, the case where the enable signal EN is "L" will be described.

At this time, the "L" signal is input to one input of the 2-input NAND circuit 118, and the "H" signal is input to one input of the 2-input NOR circuit 119. That is, each of the outputs of the 2-input NAND circuit 118 and the 2-input NOR circuit 119 is determined by the enable signal EN and does not depend on the data input signal D1.
The circuit 118 outputs a "H" signal and the 2-input NOR circuit 119 outputs a "L" signal.

Therefore, this CMOS output buffer 1
01 turns off both the transistor 112 and the transistor 113 to enter a high impedance state.

At the same time, the enable signal EN is also input to the input terminal 108 of the protection transistor control circuit 103. The reference potential VREF is 1 / of the power supply potential VDD
Since the value is set to 2, the transistor 115 is turned off and the transistor 116 is turned on. Therefore, the constant current I1 of the constant current source 117 flows from the power supply voltage VDD to the resistance load 122 at the output end 109, and the resistance value R of the resistance load 122 is R.
Then, the dropped voltage VR becomes VR = R × I1 (1), and the power supply voltage VDD drops to the potential VDD−R × I1 (2), and the “L” signal is output.

This output signal is an N channel type MOS.
Since the transistor 114 is turned off by being input to the gate of the transistor 114, the output current from the output terminal 111 does not flow and the leak current can be prevented.

Next, a semiconductor device according to the second embodiment of the present invention will be described.

Referring to FIG. 2 which is a circuit diagram of a semiconductor device according to the second embodiment of the present invention, the output external cell 200 of the semiconductor device according to the second embodiment includes a protection transistor control circuit 103 and a protection transistor control circuit 103. Except for replacing the circuit 203 with the circuit 203, the same configuration as that of the first embodiment is used, and the same components are designated by the same reference numerals.

That is, the protection transistor control circuit 203 of the semiconductor device of the second embodiment has a terminal 201 for inputting the ground potential GND, a terminal 209 for inputting the power supply potential VDD, and a terminal 20 for receiving the enable signal EN.
8 and a P-channel type MOS whose gate is connected to this terminal
A transistor 206 and an N-channel type MOS transistor 207, an inverter 204 connecting its input to a terminal 208 and outputting an inverted signal, and this inverter 204
Channel MOS transistor 205 and P channel MOS transistor 21 for connecting the output of the
0 and connect the sources and drains of transistors 205 and 206 to each other,
The transfer gate circuit is configured by connecting the sources and drains of 07 and 210 to each other to form a terminal 20.
1, the sources of the transistors 205 and 206 are connected, the terminals 209 are connected to the sources of the transistors 207 and 210, and the transistors 205, 206, 207 are connected.
And the drains of 210 and 210 are connected to the terminal 202 for output.

Next, the operation of the semiconductor device of this embodiment will be described.

Since the operations of the output buffer control circuit 102 and the output buffer circuit 101 are the same as those of the first embodiment, detailed description will be omitted.

Next, the operation of the protection transistor control circuit 203 will be described.

The enable signal EN is input to the input terminal 208 of the protection transistor control circuit 203. First, the case where the enable signal EN is "H" will be described.

This signal is a P-channel type MOS transistor 206 and an N-channel type MOS transistor 207.
, The transistor 206 is turned off and the transistor 207 is turned on.

At the same time, since the enable signal EN is inverted by the inverter 204 and input to the transistors 205 and 210, the transistor 205 is turned off and the transistor 210 is turned on. That is, the transfer gate circuit formed of the transistors 207 and 210 is turned on, and the high level potential which is lowered from the power supply potential VDD by the threshold value VT of the transistor is output through the terminal 202.

Therefore, the enable signal EN is "H".
At this time, the transistor 114 is turned on, and the output buffer 101 outputs the signal output to the output terminal 110 to the output terminal 110.

Next, the case where the enable signal EN is "L" will be described. At this time, the operation is opposite to the case where the enable signal is "H", the transfer gate circuit constituted by the transistors 205 and 206 is turned on, and the ground potential GND is generated.
The low-level potential is output via the terminal 202.
That is, the "L" signal is supplied to the gate of the protection MOS transistor 114.

At this time, the output terminal 11 of the output buffer 101
Even if 0 is in the high impedance state, the transistor 114 is completely off. Therefore, VDD higher than the power supply voltage VDD is applied to the terminal 121 of the other LSI.
Even if EX is connected to the bus, the leak current from the output terminal 111 can be prevented from flowing.

Next, a semiconductor device according to the third embodiment of the present invention will be described.

Referring to FIG. 3, the input external cell 300 of the semiconductor device of this embodiment has a P-channel type MOS transistor 312 whose source is connected to the power supply VDD and whose gate is connected to the input terminal 306, and whose source is grounded and whose gate is input. Edge 306
And an N-channel type MOS transistor 313 connected to each other, and the drains of the transistor 312 and the transistor 313 are connected to each other to supply a signal to the internal cell via the output terminal 310. Further, the input external cell 300 has diodes 304 and 305 for preventing gate breakdown of the transistors 312 and 313 due to static electricity, and the diode 304 has its anode connected to the input terminal 306 and its cathode connected to the power supply VDD, and the diode 305 has its anode connected. It has an input buffer 301 with a configuration in which it is grounded and its cathode is connected to an input end 306. Further, the input end 306
A protection MOS transistor 314, which is a depletion type N-channel type MOS transistor, is connected between the source / drain current path between the output terminal 311 and the output terminal 311, and supplies the power supply VDD to the gate. The threshold voltage VT of this transistor 314 is set to approximately 0 volt.

Next, the operation of the third embodiment of the present invention will be described. The operation of the input buffer 301 is the same as the operation of the input buffer 601 of the conventional semiconductor device, and thus detailed description thereof will be omitted.

When the power supply potential VDDEX higher than the power supply voltage VDD is input to the input terminal 311, that is, the power supply voltage VDD is 3.3 V and the high level of the output of another LSI is 5.0 V. In that case, since the gate potential of the transistor 314 is always the power supply potential VDD, a potential that is lowered from VDD by the threshold value VT of the transistor 314 is output to the source of the transistor 314. Since the threshold value VT is now set to VT≈0 volt, the power supply potential V is applied to the input terminal 306.
DD is output. That is, the normal high level is input to the input buffer 301, and the leak current due to the forward current of the diode 304 can be prevented.

Next, a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. This embodiment constitutes a bidirectional buffer circuit 400 having an input / output terminal 411. The bidirectional buffer circuit 400 has an output external cell 200 of the semiconductor device of the second embodiment and an input external cell 300 of the semiconductor device of the third embodiment, and has an input / output terminal 41.
1 is connected in common, the constituent elements are the same as the respective constituent elements of the second and third embodiments, and the same reference numerals are given to the same constituent elements, which are shown in the drawings. Omitted explanations are omitted.

In the operation of this embodiment, the bidirectional buffer circuit 400 is normally in the output mode and the input mode depending on whether the enable signal EN is "H" or the enable signal is "L". It is similar to the bidirectional buffer circuit.

That is, when the enable signal EN is "H", the bidirectional buffer circuit 400 is in the output mode, and the operation of the fourth embodiment at this time is the same as the operation of the second embodiment.

When the enable signal EN is "L", the output end 110 of the output buffer 101 is in the high impedance state, and the bidirectional buffer circuit 400 is in the input mode. At this time, 400 of the semiconductor device of the fourth embodiment
Is performed by the input external cell 30 of the semiconductor device of the third embodiment.
The operation of 0 is exactly the same.

Therefore, detailed description of the operation of the semiconductor device of the fourth embodiment will be omitted, but other LS
A leak current from the high potential power supply VDDEX due to the I bus connection can be prevented.

[0072]

As described above, the semiconductor device of the present invention has the leak current protection MOS transistor between the input / output terminal and the input / output terminal of the external cell, and controls the gate voltage thereof by the enable signal EN. Power source VD
Even if the bus connection is at a potential higher than D, there is an effect that a leak current does not occur.

In the case of an electronic equipment structure in which 3.3 V and 5 V power supplies are mixed, a CMOS type semiconductor device which can easily perform an input / output operation can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional semiconductor device.

FIG. 6 is a circuit diagram of another conventional semiconductor device.

[Description of Reference Signs] 100, 200, 500 Output External Cell 101, 201, 501 Output Buffer Circuit 102, 202, 502 Output Buffer Control Circuit 103, 203 Protection Transistor Control Circuit 104, 105, 106, 107, 108, 109, 1
10, 201, 202, 208, 209, 306, 31
0,504,505,506,507,510,60
6,610 terminal 111,311,511,611 input / output terminal 112,113,114,115,116,205,2
06,207,210,214,312,313,31
4 MOS transistor 117 Constant current source 118,518 NAND circuit 119,519 NOR circuit 120,204,520 Inverter 300,600 Input external cell 400 Bidirectional buffer circuit D1 Data input signal EN Enable signal I1 Constant current VDD, VDDEX Power supply voltage VREF Reference voltage VT threshold

Claims (10)

[Claims] 1. A first and a second power supply terminal, a plurality of output terminals, a plurality of output buffers for supplying the output signals to the output terminals, and at least one control signal for receiving the output. A semiconductor device having an output buffer control circuit for controlling an output state of a buffer, comprising: a MOS transistor connecting a source / drain path between the output terminal and an output end of the output buffer; To the gate of the MOS transistor to control ON / OFF of the MOS transistor, and a protection transistor control circuit. 2. A first power supply terminal and a second power supply terminal, and a plurality of input / output terminals for receiving an input signal from the outside or receiving an output signal and outputting the output signal to the outside.
A semiconductor device comprising: a plurality of input buffers that receive the input / output signals from the output signals; and an output buffer control circuit that receives at least one control signal and controls an output state of the output buffers. And a first MOS transistor connecting a source / drain path between the output buffer and the output end of the output buffer, and receiving the control signal and outputting the output thereof to the first MOS transistor.
A source / drain path is connected between the input / output terminal and the input end of the input buffer, and a gate is provided between the input / output terminal and the input terminal of the input buffer. And a second MOS transistor for supplying a power supply potential to the semiconductor device. 3. A semiconductor having first and second power supply terminals, a plurality of input terminals for receiving input signals from the outside, and a plurality of input buffers for receiving the input signals via the input terminals. The semiconductor device according to claim 1, further comprising a MOS transistor that connects a source / drain passage between the input terminal and an input end of the input buffer and supplies a power supply potential to a gate thereof. 4. The semiconductor device according to claim 1, wherein the MOS transistor is a depletion type N-channel type MOS transistor. 5. A first electrostatic protection diode connecting an anode to the input terminal and a cathode to the first power supply terminal, and a second electrostatic protection diode connecting an anode to the second power supply terminal and a cathode to the input terminal. The semiconductor device according to claim 2, further comprising an electrostatic protection diode. 6. The P-channel MOS transistor, wherein the output buffer comprises a P-channel MOS transistor having a source connected to the first power supply terminal and an N-channel MOS transistor having a source connected to the second power supply terminal.
6. The semiconductor device according to claim 1, wherein the drain of the transistor and the drain of the N-channel type MOS transistor are connected to the output terminal of the output buffer. 7. The output buffer control circuit has a first input terminal to which a data input signal is supplied, a second input terminal to which an enable signal is supplied, and its inputs to the first and second input terminals. Connect and connect the output to the P-channel MOS
A NAND circuit connected to the gate of a transistor and one end of its input is connected to the first input end, and the other end of its input is connected to the second input end through an inverter circuit, and its output is the N-channel type. A NOR circuit connected to the gate of a MOS transistor, wherein the data input signal is output from the output buffer when the enable signal is at a high level, and the output buffer is in a high impedance state when the enable signal is at a low level. The semiconductor device according to claim 1, 2, 4, 5, or 6. 8. The control signal of the protection transistor control circuit is the enable signal, wherein the MOS transistor is turned on when the enable signal is at a high level, and the MOS transistor is turned off when the enable signal is at a low level. Claims 1, 2,
The semiconductor device according to 4, 5, 6 or 7. 9. The protection transistor control circuit includes a first N-channel MOS transistor having a drain connected to the first power supply terminal and a gate receiving the enable signal, and a drain connected to the first N-channel MOS transistor via a load. Second N-channel MO connected to power supply terminal and receiving reference potential at gate
An S-transistor, the sources of the first and second N-channel MOS transistors are connected to the second power supply terminal via a constant current source, and the drain of the second N-channel MOS transistor is connected to the second power supply terminal. 9. The semiconductor device according to claim 1, wherein the output signal is supplied to the gate of the MOS protection transistor. 10. The protection transistor control circuit connects sources and drains of a first P-channel MOS transistor and a first N-channel MOS transistor, respectively, and connects the first P-channel MOS transistor and the first P-channel MOS transistor to each other.
The enable signal is supplied to the gate of the channel type MOS transistor and the inverted signal of the enable signal is supplied to the gate of the first N-channel type MOS transistor, and a desired low potential supplied to the input terminal thereof is supplied. The first transfer gate circuit which outputs from the output terminal and turns off the MOS transistor is connected to the respective sources and the respective drains of the second P-channel type MOS transistor and the second N-channel type MOS transistor. , The inversion signal of the enable signal is supplied to the gate of the second P-channel MOS transistor, and the enable signal is supplied to the gate of the second N-channel MOS transistor and is supplied to its input terminal. Output the desired high potential from its output end to turn on the MOS transistor Claim, characterized in that a second transfer gate circuits 1,2,4,5,6,7
Or the semiconductor device according to 8.