JPH11259540A - Wiring design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the wiring design manhour by stacking up the single via holes to define these-connected via holes as a new via hole and accordingly connecting together all inter layers of the wiring design by a single via hole placing job. SOLUTION: The names of layers to be connected to each other are inputted to select the via holes which are necessary to connect together plural specific interlayers. Then the lands which connect together the via holes are generated and stacked up in a designated form, and these stacked lands are stored as a new piece of via hole data. A computer 140 of this wiring design device consists primarily of a via hole library part 130, a stack via hole generation part 110 and a wiring part 120. The part 110 generates the stack via hole data based on the connecting layer data 114 given from a via hole arrangement part 122 and the data 112 in a single via hole data storing part 131. These stack via hole data are stored in a stack via hole data storing part 132.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a wiring design apparatus suitable for wiring design of a multilayer printed circuit board using non-penetrating via holes and a build-up substrate having no penetrating via holes.

[0002]

2. Description of the Related Art In recent years, printed wiring boards have been required to have a higher density of wiring in accordance with miniaturization and higher performance of products. As a countermeasure for this, there is a multilayer printed circuit board. At this time, the via hole necessary for connecting the wiring between layers is a through via hole.In the case of a through hole, when the thickness is increased due to the multilayering of the substrate, it is necessary to increase the hole diameter and land diameter so that plating can be performed to the inside. In addition, the wiring accommodation ratio with respect to the increase in the number of layers decreases. Further, when components are mounted on both sides of the printed circuit board, the lands are exposed on both outer layers, which hinders high-density component arrangement. For this reason, for example, JP-A-6-2
A non-penetrating via hole such as a brand via hole, a buried via hole, or a build-up via hole in a build-up printed circuit board has been devised as disclosed in Japanese Patent Application Publication No. 07118, “Method of Manufacturing Printed Circuit Board”.

However, when wiring is designed using these non-penetrating via holes, most of them connect only between specific wiring layers. Therefore, when connecting wirings over multiple layers, a plurality of non-penetrating via holes are required. Need to be placed.

[0004]

When arranging via holes, each via hole is arranged at a minimum allowable interval so that the via hole and the via hole do not obstruct other wiring. A line connecting the hall is arranged. During wiring design, this work has to be performed every time a layer is crossed, so that it takes a lot of man-hours.

[0005]

Means for Solving the Problems By inputting a layer name for connection between layers, a plurality of via holes for connecting specific layers required for the connection are selected, and the via holes are connected to each other. Is generated, stacked in a specified format, and stored as a new piece of via hole data. This via hole is named as a stack via hole.
This can be performed by a single via-hole arrangement operation, and the number of via-hole arrangement steps can be reduced.

[0006]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a CAD system as one embodiment of the present invention.

The illustrated CAD system includes an input device 100,
It comprises a computer 140 and an output device 150.

[0009] The input device 100 transmits a designer's instruction to the computer 140.

The input device 150 displays output information of the computer 140.

The computer 140 is roughly divided into a via hole library unit 130, a stack via hole generation unit 110, and a wiring unit 120.

By the way, the stacked via hole described here is data defined as one via hole by stacking via holes connecting specific layers as shown in FIG.

The stack via hole generation unit 110 and the stack via hole data storage unit 132 are new functions according to the present invention.

The via hole library section 130 will be described below.
, Stack via hole generation unit 110, wiring unit 12
The function of 0 will be described.

First, the via hole library 130 has a single via hole data storage unit 131 and a stacked via hole data storage unit 132.

The single via hole data storage 13
1 stores data of a single via hole, that is, data such as a layer name to be connected, a land diameter, and a hole diameter.

By the way, the single via hole described here is a basic via hole for connecting a wiring between specific layers on a printed circuit board. For example, a build-up via hole 400 shown in FIG. It is a hall.

On the other hand, the stack via hole data storage 1
Reference numeral 32 stores data of a stack via hole.

The stack via hole generation unit 110 connects the connection layer data 114 from the via hole arrangement unit 122.
And the data 11 in the single via hole data storage unit 131
The stack via hole data 113 is generated based on the data 2 and stored in the stack via hole data storage unit 132.

By the way, the connection layer described here means a wiring layer before switching and a wiring layer after switching, which are input when arranging via holes for switching wiring layers in wiring. For example, the connection layer when arranging the via hole 400 in FIG. 4 changes from the A layer to the B layer. Wiring section 1
At 20, a line arrangement and a via hole arrangement are performed by a line arrangement unit 121 and a via hole arrangement unit 122 provided inside.

At the time of connection layer input at the time of via hole arrangement, if connection is possible with a single via hole, the data 111 is taken out from the single via hole data storage unit 131. If connection is impossible, data is already stored. If the stack via hole can be connected, the data 115 is extracted from the stack via hole data storage unit 132. If the stack 115 cannot be used and a new stack via hole needs to be generated, the stack via hole generation unit 11
0, the connection layer data 114 is sent, and the stack via hole generation unit 110 receiving the data 114 creates data 113,
The data is stored in the stack via hole data storage unit 132, and then the stored data 115 of the stacked via hole is taken out and the via holes are arranged.

Next, the process of generating a stack via hole in the stack via hole generation unit 110 will be described in detail with reference to FIGS.

For the sake of explanation, the build-up printed circuit board shown in FIG. 4 is used as a subject.

As a precondition at this time, it is assumed that the data of via holes 400 and 401 are stored in the single via hole data storage unit 131.

The contents of these data are shown in FIGS. 7a and 7b.

Where 700 is the name of the via hole, 70
1 is a layer in which a land exists, 702 is a land use code, 703 is a land shape, 704 is a land size,
705 is the shape of the drill, 706 is the size of the drill, 70
7 indicates the end of the data. The usage codes of the lands are: 1 is a land of a pad for a signal layer; and 2 is a land of a clearance for a power supply and a ground layer.

The stack via hole data generated by the stack via hole generation process described below is indicated by 7c in FIG.

Next, the operation will be described with reference to the flow chart of FIG.

First, a connection layer is input at a connection layer input 200 shown in FIG.

This input is performed when a user arranges a via hole using the via hole wiring section 122 of the wiring section 120. In order to simplify the explanation, it is assumed that a new stack via hole needs to be generated in order to cross the connection layer input here. In other words, this means that the connection layer data 114 shown in FIG. 1 has been sent from the via hole arrangement unit 122 to the stack via hole generation unit 110. The connection layers input here are from the build-up A layer 410 to the core C layer 412 of the build-up printed circuit board in FIG.

Next, in process 201, via holes required for connection are selected.

This processing will be described with reference to the flowchart of FIG.

First, a start layer and an end layer are inputted at an input 300.
Of the layers and the C layer, the A layer close to the component surface is defined as a start layer, and the end layer is defined as a C layer. In the next process 301, the start layer A is set as the search layer.

Next, at 302, a search for via holes is performed. When a land close to the component surface is located in the A layer, which is a search layer, the via hole is stored in the single via hole data storage unit 13.
Search from 1. As a result, via hole 400 is selected.

Next, in step 303, the number of lands near the solder surface of the via hole 400 selected in step 302 is checked and set as a search layer.

As a result, the layer B is set as a search layer.

In the next process 304, it is checked whether or not the search layer set in 303 is equal to the end layer.
Return to 2 and search for via holes again.

Since the current search layer is the layer B and the end layer is the layer C, the process returns to the step 302 again.

In the process 302, a search for a via hole is performed this time in the search layer B, and as a result, a via hole 401 is selected this time.

In the process 303, the search layer is set to the C layer,
In the process 304, since both the search layer and the end layer are the C layer, the process ends.

As a result, via holes 400 and 401 required for connection between the layer A and the layer C are selected. These 400 and 401 are stored in 710 of 7c in FIG.

In the next process 202, the via hole selected in the process 201 is arranged.

At the time of arrangement, the type of stacking via holes is selected from the stack type shown in FIG. 6, and this selection is determined in advance or can be selected at the time of via hole arrangement.

The arrangement of the via holes in the stacking format shown in FIG. 6 will be described in detail. 6a arranges via holes while moving in the X direction alternately in the plus and minus directions as it proceeds in the Z direction, and 6a follows in the Z direction as plus in the X direction, plus in the Y direction, minus in the X direction, and Y. The via holes are arranged while repeating the four movements of minus in the direction, and the via holes 6c are arranged while constantly moving in the plus direction in the X direction as they proceed in the Z direction.

Here, the Z direction is the direction of the thickness of the substrate, and the X direction and the Y direction are the directions of the substrate surface. The movement amounts in the plus direction and the minus direction are the same as the minimum allowable distance 420 between via holes. The values in the X and Y directions are stored in 711 of 7c in FIG.

In the next process 203, a stack via hole land is generated.

FIG. 6 shows the stack via hole land.
As shown by reference numeral 600, this is a land at the junction when the via holes are stacked.

In FIG. 600, two lands and their connections are shown for easy understanding of the stacked state, but are defined as one land on the data of the stack via hole land.

In this process, first, a layer in which both 400 and 401 selected in the process 201 exist is checked. As a result, the layer B is selected. Here, a stacked via hole land in the B layer is generated from the lands 400 and 401 in the B layer and the minimum allowable interval 420 between via holes. Note that the minimum allowable interval between via holes described herein is the closest manufacturing distance at which via holes can be stacked.

FIG. 5 shows the stack via hole land generated by this processing.

The shape of 500 is such that 400 and 401 are arranged at the minimum allowable interval between via holes, and the center of each land is set to the smaller land diameter, that is, 40 mm.
It has the same shape as that connected by a line having the same width as the land diameter of 0.

As described above, the manufacture of the land on the data is not defined by two lands and lines of 400 and 401, but is defined as one land.

Reference numeral 501 denotes a shape which is bordered by a line having a width of the clearance value between the solid copper foil of the power supply or ground layer and the power supply or ground layer, that is, the negative at the time of Gerber data output. Used for layers. The stack viahole land name generated by this process 203 is stored in 714 of 7c in FIG.

By the processes 200 to 203 described above, the data 7c of the stacked via hole can be generated from the single via hole data 7a and 7b of FIG.

Then, as described in the description of FIG. 1, by storing the stack via hole data 7c in the stack via hole data storage section 132, it becomes possible to use the data as one via hole data.

[0056]

As described above, according to the present invention, a single via hole is stacked, and a connected via hole is formed as one new via hole, so that connection between all layers is one in terms of wiring design. Since the number of via hole arrangement operations becomes possible, wiring man-hours can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a wiring design apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing when a stack via hole is generated.

FIG. 3 is a flowchart illustrating a process when selecting a via hole required for connection.

FIG. 4 is an example of a build-up printed circuit board.

FIG. 5 is an example of a stack via hole land.

FIG. 6 is an example of a stacked via hole.

FIG. 7 is an example of various via hole data.

[Explanation of symbols]

111: Data of a single via hole sent to the via hole arrangement unit; 112: Data of a single via hole sent to the stack via hole generation unit; 113: Data of a stack via hole sent to the stack via hole data storage unit; Connection layer data, 115: Stack via hole data sent to via hole arrangement unit, 400: Build-up via hole, 401: Non-penetrating via hole, 420: Minimum allowable distance between via hole and via hole, 500: Positive Stack via hole lands for layers, 501: stack via hole lands for negative layers, 600: junctions when via holes are stacked, 7a: data for via holes 400, 7b: data for via holes 401, 7c ... Viaho Data of the stack via holes generated based on the Le 400 and 401.

Claims (1)

[Claims] In a wiring design apparatus having a function of storing data of via holes and a function of arranging via holes, a function of inputting a layer name when connecting between layers and a function of inputting only one kind of via holes are required. A function to select multiple via holes required to connect layers that cannot be connected, a function to generate lands connecting the selected via holes, a function to stack the selected via holes in a specified format, and a selection A wiring design device having a function of storing data as a single via hole by stacking lands connecting via holes and via holes in a specified format.