JPH11250677A - Semiconductor non-volatile storage and it information erasure method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce total time required for switching a voltage and to reduce time for an entire erasure mode by allowing an electron emission operation to include the application operation of a plurality of pulses, allowing a plurality of pulses to include pulses with different widths, and preventing the width of a preceding pulse from becoming larger than the width of succeeding pulses. SOLUTION: When erasure time is divided for performing erasure, the pulse width of erasure is not made constant and one erasure pulse width is extended, thus reducing the number of erasures to be repeatedly made, thus reducing the switching count of voltage or the like to be applied to the gate, drain, and source of a memory cell being made when switching from erasure to verification and from verification to erasure and hence reducing time required for switching the voltage. In this case, however, the pulse width of erasure is set so that the threshold voltage of a memory cell cannot become a negative voltage with one erasure by considering the characteristic fluctuation of temperature and rewriting characteristics or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a technology effective when used in a flash memory and a microcomputer system using the same.

[0002]

2. Description of the Related Art A flash memory is an EPROM (Era).
sable Programmable Read O
nly Memory), and has an EEPRO with the same memory cell area as EPROM.
M (Electrically Erasable an
d Programmable Read OnlyM
(e.g., memory).

In general, the threshold voltage of a flash memory after erasing can be a negative voltage, unlike the threshold voltage in a thermal equilibrium state when erasing with an ultraviolet ray as in EPROM. As described above, when the threshold voltage of the memory cell decreases to a negative voltage, there is an adverse effect on reading and the like. That is, if the threshold voltage of the memory cell is reduced to a negative voltage, a current (non-selective leak current) flows through the data line even if the word line voltage, that is, the control gate voltage is 0V. This causes a delay in the read time and, consequently, an erroneous read.

The threshold voltage of each memory cell in the memory array after erasing the flash memory has a certain distribution (variation) in the array. The magnitude of the variation in the threshold voltage is about 1 V to 3 V.
Therefore, it is necessary to precisely control the threshold voltages of all the memory cells in the memory array after erasing so that the threshold voltages do not become negative. For this, the erasing time is divided into several times, and after each erasing, reading (verify) is performed to confirm whether the erasing is sufficient, and if not enough, the operation of erasing again is repeated. There is a need.

FIG. 2 is a flowchart of the erase mode in Japanese Patent Laid-Open No. 2-289997, and a series of operations in the erase mode will be described. When you enter erase mode,
Prior to the actual erasure, a prewrite operation as shown by a dotted line in FIG. 2 is executed. The pre-write operation is an operation for writing to all memory cells in order to prevent the threshold voltage of unwritten memory cells from becoming negative due to erasing. When the prewrite operation is completed, address setting is performed in preparation for verification. Thereafter, an erase pulse is generated to perform the erase. When erasure is completed, verification is performed to confirm whether erasure is sufficient. If the erasure is insufficient, the erasure is performed again. In this repeated erasure, when each erasure is completed, verification is performed from the address determined to be insufficient in the previous erasure. As described above, when it is determined that all memory cells have been erased by repeating erasing and verifying, the erasing mode in which erasing and verifying after prewriting are repeated is ended. In the above-described prior art erase mode, the pulse width of the erase performed repeatedly is constant.

[0006]

In the above-mentioned prior art, since the pulse width of the erase performed repeatedly as described above is constant, the erase pulse generation from the step 6 indicated by the thick arrow in FIG. , And the number of repetitions from the verification in step 7 to the generation of the erase pulse in step 6 increases. When switching from the generation of the erase pulse in step 6 to the verification in step 7 and from the verification in step 7 to the generation of the erase pulse in step 6, switching of the voltage applied to the gate, drain and source of the memory cell is performed. Therefore, a voltage switching time is required. Therefore, if the number of repetitions of the portion indicated by the thick arrow in FIG. 2 increases as in the related art, the number of switching of the voltage and the like applied to the memory cell also increases. As a result, the total time required for switching the voltage or the like applied to the memory cell becomes longer, and the time from the start of the erase mode to the end of the erase mode in FIG. 2 becomes longer.

Accordingly, an object of the present invention is to reduce the number of repetitions of erasing and verifying in a semiconductor non-volatile memory device and reduce the number of repetitions of erasing and verifying, and perform switching from erase to verify and from verify to erase. An object of the present invention is to reduce the number of times of switching the voltage or the like applied to the source, thereby shortening the total time required for switching the voltage and shortening the time of the entire erase mode.

[0008]

The above object is achieved by making the pulse width of repeated erasure not constant.

That is, in a flash memory, the threshold voltage of a memory cell decreases as erasure proceeds. The relationship between the change in the threshold voltage of the memory cell and the erase time is as follows:
While the change in the threshold voltage of the memory cell is represented by a real axis, the erase time is represented by a logarithmic axis. Therefore, there is no particular limitation on the method of not making the pulse width of the repeated erasure constant, but at least one of the repeated erasures requires a long erasure pulse width that does not make the threshold voltage of the memory cell negative. The method of erasing and the method of increasing the pulse width of erasing as the number of erasing increases are superior.

FIG. 1A shows the relationship between the number of erasures and the erasure pulse width when the first erasure pulse is lengthened and the second and subsequent erasure pulse widths are fixed. FIG. 1- (2) shows the relationship between the number of erasures and the erasing pulse width when is increased as the number of erasures increases. FIG. 1- (3) shows the relationship between the number of erases and the erase pulse width in the conventional method in which the erase pulse width is fixed.

As described above, according to the present invention, when erasing is performed by dividing the erasing time, the pulse width of erasing is not fixed, and the erasing pulse width shown in FIG.
As shown in (1) and FIG. 1- (2), by increasing the pulse width of one erasure, the number of erasures to be repeated is reduced. As a result, the number of times of switching the voltage, etc. applied to the gate, drain, and source of the memory cell at the time of switching from erase to verify and from verify to erase is reduced, and the total time required for switching this voltage is shortened. This is to shorten the time of the entire erase mode.

However, when increasing the erase pulse width,
It is necessary to set the erasing pulse width so that the threshold voltage of the memory cell does not become a negative voltage in one erasing in consideration of the characteristic fluctuation such as the temperature characteristic and the rewriting characteristic.

In contrast to the prior art in which the pulse width of the erasure repeatedly performed in the erasing mode is fixed as described above, the present invention does not make the pulse width of the erasure performed repeatedly constant but performs one of the erasures. By increasing the pulse width, the number of repeated erasures can be reduced.

That is, when the erase pulse width is increased, the erasure at that time is performed deeply, and the rate at which the erasure of the memory cell is determined to be insufficient by the verification after the erasure is reduced. Therefore, the number of repetitions of erasing and verifying is reduced by the increase in the erasing pulse width.

As a result, the number of times of switching the voltage, etc. applied to the gate, drain and source of the memory cell at the time of switching from erase to verify and from verify to erase is reduced, and the total time required for this voltage switch is reduced. And the time of the entire erase mode is shortened.

[0016]

FIG. 3 is a circuit diagram of a semiconductor nonvolatile memory device.

(1) Element Structure of Semiconductor Nonvolatile Memory Device Each circuit element shown in FIG.
MOS (complementary MOS) integrated circuit manufacturing technology
It is formed on a semiconductor substrate such as a piece of single crystal silicon.

Although not particularly limited, the integrated circuit is a single crystal p
It is formed on a semiconductor substrate made of mold silicon. An n-channel MOSFET is formed of polysilicon formed on a semiconductor substrate between a source region and a drain region and between the source region and the drain region with a thin gate insulating film formed between the source region and the drain region formed on the surface of the semiconductor substrate. It is composed of a gate electrode. The p-channel MOSFET is formed in an n-type well region formed on the surface of the semiconductor substrate.
This allows the semiconductor substrate to have a plurality of n formed thereon.
A common substrate gate of the channel MOSFET is formed, and the ground potential of the circuit is supplied. The common substrate gate of the p-channel MOSFET, that is, the n-type well region is connected to the power supply voltage Vcc. Or, if it is a high voltage circuit,
This n-type well region is supplied with an externally applied high voltage Vp.
p, or connected to the on-chip internally generated high voltage or the like. Alternatively, the integrated circuit may be formed over a semiconductor substrate made of single-crystal n-type silicon. In this case, n channel M
The OSFET is formed in a p-type well region.

(2) Circuit Configuration and Address Circuit System of Semiconductor Nonvolatile Memory Device Although not particularly limited, in the semiconductor nonvolatile memory device of this embodiment, row and column address signals A supplied from external terminals are provided.
Address buffers XADB and YADB that receive X and AY
Are supplied to the row and column address decoders XDCR and YDCR. Although not particularly limited, the row and column address buffers XADB and YADB are activated by a selection signal ce inside the device, take in address signals AX and AY from external terminals, and have the same phase as the address signals supplied from the external terminals. A complementary address signal composed of the internal address signal and the address signal having the opposite phase is formed.

The row address decoder XDCR forms a select signal of the word line WL of the memory array in accordance with the complementary address signal of the address buffer XADB, and the column address decoder YDCR generates the memory array in accordance with the complementary address signal of the address buffer YADB. Of the data line DL is formed.

Although there is no particular limitation, the selection of memory cells is carried out in units of 8 bits or 16 bits, so that eight or sixteen memory cells are selected by a row address decoder XDCR and a column address decoder YDCR in order to perform writing and reading. You. The number of memory cells in one data block is m in the word line direction (row direction) and n in the data line direction (column direction). In other words, the memory array is divided into 8 or 16 data blocks of m × n memory cell groups.

(3) Non-Volatile Memory Array System The non-volatile memory array includes a memory cell MOSFET M1 to M9 having a control gate and a floating gate, and a word line W.
L, a data line DL, and a common source line CS.

The memory cell is not particularly limited.
A known memory cell having a configuration similar to that of a PROM memory cell and having a control gate and a floating gate, or a known memory cell having a control gate, a floating gate, and a select gate. However, the point that the erasing is performed electrically utilizing the tunnel phenomenon between the floating gate and the source coupled to the source line is a conventional EPROM using ultraviolet rays.
Is different from the erasing method.

(4) Erase Circuit System The common source line CS is connected to the ground potential V of the circuit at the time of writing, reading and verifying by the erasing circuit ERC.
In contrast to ss, the voltage is switched to the high voltage Vpp during erasing. In the memory array shown in the figure, the control gates of the memory cells arranged in the same row, for example, M1, M4, M7 are connected to the word line WL1, and the drains of the memory cells arranged in the same column, for example, M1 to M3 are connected to the data line DL.
1 connected.

(5) Common Data Line, Write Circuit, Read Circuit A plurality of data lines DL1 to DLm
A common data line CD via column select switch MOSFETs Q1 to Q3 receiving a select signal formed by DCR.
Connected to. A write data input buffer DIB is connected to the common data line CD via a MOSFET Q5 which is turned on at the time of writing. This write data input buffer DIB receives a write signal input from an external terminal I / O. The common data line C
D is a sense amplifier S via a switch MOSFET Q4 which is turned on at the time of reading upon receiving a read control signal se.
A, and a read data output buffer DO
It is connected to an external terminal I / O via B.

(6) Timing Control Circuit Although the timing control circuit CONT is not particularly limited, a chip enable signal, an output enable signal, a write enable signal supplied to the external terminals / CE, / OE, / WE, / EE, respectively. In response to the erase enable signal and the write / erase high voltage Vpp, it generates timing signals such as internal control signals ce, se, we, and er, and selectively supplies read signals to an address decoder and the like. A power supply voltage Vcc, a high voltage Vpp for writing and erasing, a voltage Vcv for verifying, and the like are generated.

(7) Write Operation During writing, the internal signals ce and we are set to high level. The source potential of the common source line CS is
It is set to the circuit ground potential Vss by RC.

Row and column address decoder circuits XDCR, Y
The high voltage Vpp is supplied to the DCR and data input circuit DIB as its operating voltage. The voltage of the word line WL on which writing is performed becomes the high voltage Vpp.
The data line DL to which the memory cell into which electrons are to be injected is connected to the floating gate is connected to the high voltage Vpp as described above.

Thus, writing is performed on the memory cell. In the written ("0" state) memory cell, electrons are accumulated in its floating gate.

(8) Erasing Operation At the time of erasing, the internal signals ce and er are set to a high level.
A high voltage Vpp for erasing is supplied to the common source line CS by the erasing circuit ERC. At this time, a high electric field is applied from the control gate to the source, and electrons accumulated in the floating gate of the memory cell are drawn out to the source line side by the tunnel phenomenon ("1" state), thereby performing erasing.

The external terminals I / O and / CE, / O
Each operation may be designated by supplying a control signal instructing operations such as writing and erasing from E and / WE. The high voltage Vpp is not supplied from outside, but is
It may be a potential obtained by boosting cc.

(9) Read operation During normal read, the internal signals se and ce are set to high level. The potential of the common source line CS is
It is set to the circuit ground potential Vss by RC.

Row and column address decoder circuits XDCR, Y
The power supply voltage Vcc is supplied as an operation voltage to the DCR, the sense amplifier SA, and the data input circuit DIB.

The voltage of the word line WL connected to the memory cell from which reading is performed becomes the power supply voltage Vcc. A low voltage of about 1 V is supplied from the sense amplifier SA to the data line DL so that weak writing is unlikely to occur.

The memory cell written to the “0” state is
Since electrons are accumulated in the floating gate, the threshold voltage increases, and no drain current flows even when the word line WL is selected at the time of reading. On the other hand, the threshold voltage of the memory cell in the “1” state where electrons are not injected is low, and a current flows when the word line WL is selected. This current is received by the sense amplifier SA and output to the external terminal I / O through the data output circuit DOB. Thus, normal reading of the memory array is performed.

(10) Verification Operation after Erasing In a flash memory, it is necessary to precisely control the threshold voltage of a memory cell so as not to be a negative voltage in order to prevent erroneous reading. For this reason, a pre-write operation is performed prior to the actual erasure, and then the erasing time is divided into several times.After the erasing, verification is performed to confirm whether the erasing is sufficient. If not, it is necessary to repeat the operation of erasing again.

The erasing mode performs such an algorithm as a series of operations. An algorithm in which the above-described algorithm of the erase mode can be controlled inside the semiconductor nonvolatile memory device is called an automatic erase mode.

At the time of verification in the erase mode, the source potential of the common source line CS is set to the circuit ground potential Vss by the erase circuit ERC. On the other hand, a voltage Vcv lower than the power supply voltage Vcc is supplied to the row and column address decoder circuits XDCR and YDCR, the sense amplifier SA, and the data input circuit DIB as their operation voltages.

That is, at the time of verification, in order to determine whether or not the selected memory cell is in an erased state (a state where the threshold voltage is low), the power supply voltage is almost equal to the lower limit power supply voltage Vccmin at which a read operation can be performed on the flash memory. Reading is performed with voltages that are equal.

(11) Erasing Mode Japanese Patent Application Laid-Open No. 2-289997 describes an example of an automatic erasing mode in which the algorithm of the erasing mode can be controlled inside the semiconductor nonvolatile memory device. On the other hand, in the erase mode of the embodiment of the present invention,
The difference from the erasing mode in Japanese Patent Application Laid-Open No. 2-289997 is that the pulse width of erasing is not fixed. Accordingly, the main circuit is disclosed in Japanese Patent Laid-Open No. 28999/1990.
7, a circuit for setting an erase pulse width, that is, an erase pulse end signal PE
A description will be given with reference to FIGS. 4 to 7 mainly of a binary counter circuit BCS3 for generating an error detection signal and a binary counter circuit BCS4 for generating an abnormality detection signal FAIL.

(12) Erase Pulse Generating Circuit and Erase Operation The binary counter circuit BCS3 shown in FIGS. 4 and 6 is a circuit necessary for setting the erase pulse width. The binary counter circuit BCS4 shown in FIGS. 4 and 6 is a circuit necessary for counting the number of times the erase pulse has been generated.

In the automatic erasing mode, when pre-writing is completed for all the addresses of the memory array, the automatic erasing mode setting signal AE rises and enters an erasing period. Also, with the rise of the automatic erase mode setting signal AE,
The automatic erasing mode setting delay signal AED rises with a certain delay. In response to the rise of the signal AED, the erase start signal ST rises for a certain period, and the flip-flop circuit FF3 is set. After a time set by the delay circuit D5, the erase pulse / EP falls.
The low level of the erase pulse / EP causes the erase circuit E
High voltage Vpp is applied to the source of the memory cell via RC. The oscillation circuit O2 and the binary counter circuit BCS3
After the time determined by the erasing pulse / EP being set to the low level has elapsed, the erasing pulse end signal PE is changed from the low level to the high level, and the flip-flop circuit FF3 is reset. Since the erase pulse / EP rises in response to this, the erase circuit ERC
As a result, the source potential of the memory cell is switched from the high voltage Vpp to the circuit ground potential Vss.

After the delay time set by the delay circuit D7, the erase verify signal EV rises and shifts to verify. The frequency-divided signal OS2 of the verifying reference pulse is a high-level signal in the first half of the cycle and a low-level signal in the second half of the cycle. During the low-level period, the output signals S0 to S7 (in the case of 8-bit output) from the sense amplifier are high. When the signals S0 to S7 of all bits output from the sense amplifier are at the low level, in other words, when the threshold voltage of each memory cell is low, the flip-flop circuit FF
3 is not set, an internal address signal indicating the next address is formed in response to the address increment signal EAI at the time of verification, and the determination is performed again during the low level period of the signal OS2. If the output signal S of the sense amplifier is
If a signal of one or more bits among 0 to S7 is at a high level, that is, if there is a memory cell determined that erasure is insufficient even with one bit, the flip-flop circuit FF3
Is set and a low-level erase pulse / EP is generated again. Erasure is performed again by this low-level erase pulse / EP, and then verify is performed again. At this time, the operation of the delay circuit D8 prevents the last pulse of the signal OS2 from appearing in the address increment signal EAI, indicating that the last pulse remains at the address determined to be insufficiently erased. In other words, the verification after the erasure is performed again is executed from the address determined to be insufficient in the erasure by the previous verification.

When the memory cells corresponding to all the addresses are verified by repeating the above operation, the automatic erase mode setting signal AE falls and the erase mode end signal E
R is set to high level for a certain period, and the erase mode ends. Further, with the fall of the automatic erase mode setting signal AE, the automatic erase mode setting delay signal AED falls with a certain delay.

Although not particularly limited, FIG. 4 shows a circuit diagram for increasing the pulse width of the first erase and making the pulse width of the second and subsequent erases a constant pulse width. FIG. The timing of various waveforms is shown. In FIG. 5, while the erase pulse / EP falls, an erase pulse is applied to the source line to perform erasure. When the erase pulse / EP rises and the erase verify signal EV rises with a certain delay, verification is performed. The timing at which the erase pulse / EP falls is determined by output signals S0 to S7 from the sense amplifier. That is, if there is a memory cell that has been verified and erasure is insufficient, one of the signals S0 to S7 rises and the erase pulse / EP falls. Also, the erase pulse / E
The timing at which P rises is determined by the erase pulse end signal PE. That is, the d signal and the binary counter B. C
The output signal PEA of the two-input NOR circuit which receives the output signal A of the second input circuit or the / a signal and the binary counter B. When one of the output signals PEC of the two-input NOR circuit to which the output signal C of C is input rises, the erase pulse end signal PE
Rises and the erase pulse / EP rises. The above-mentioned d signal is maintained at a high level until the erase pulse / EP first rises, and is at a low level after the erase pulse / EP rises until the erase mode end signal ER rises and the erase mode ends. As described above, when the erase mode is first entered, the d signal is at the high level, so that even if A falls, the PEA signal does not rise. Therefore, the erase pulse end signal PE does not rise until the PEC signal rises, so that an erase pulse / EP having a long pulse width can be obtained. Therefore, the pulse width of the first erasure can be increased by the circuit shown in FIG. 4, and the pulse width of the second and subsequent erasures can be made constant. Further, the binary counter B.1 in the binary counter BCS3. Change the number of stages of C, output PEA signal 2
An input NOR circuit and a two-input N output PEC signal
The OR circuit is connected to a binary counter B. The erasing pulse width can be arbitrarily set depending on whether the pulse is taken out from the output of C.

Although not particularly limited, FIG. 6 shows a circuit diagram for increasing the pulse width of repeated erasing as the number of times of erasing increases, and FIG. 7 shows timings of main waveforms at that time. It is shown. As described above, the timing at which the erase pulse / EP falls is determined by the output signals S0 to S7 of the sense amplifier. The timing at which the erase pulse / EP rises is determined by the erase pulse end signal PE. The circuit shown in FIG. 6 is designed such that the PEA signal rises at the first erasing by using the / x signal and the abnormality detection signal FAIL from / a, and the PEB signal rises at the second erasing. As the number of erasures increases, the pulse width of the erasure performed repeatedly becomes longer. In the circuit shown in FIG. 6, the binary counter B.1 in the binary counter circuit BCS3 is used. By changing the number of stages of C, it is possible to arbitrarily determine how long the erase pulse width is to be, that is, how many times the erase is to be repeated.

As described in Japanese Patent Laid-Open No. 2-289997, the binary counter circuit BCS4 counts the number of generations of the erase pulse / EP, and even if the erase pulse / EP is counted a certain number of times, the erase mode is not changed. If the process is not completed, that is, if erasing cannot be performed even if the erasing pulse / EP is applied a certain number of times, the abnormality detection signal FAIL is raised. As a result, the erase mode end signal ER rises to forcibly end the erase mode.

[0048]

The effects obtained by the invention disclosed in the present application will be briefly described as follows.

That is, in the erasing mode of the semiconductor nonvolatile memory device, the number of erasing and verifying repetitions is reduced by making the pulse width of erasing that is repeatedly performed not constant, and when switching from erasing to verifying and from verifying to erasing is performed. The number of times of switching of the voltage, etc. applied to the gate, drain and source of the memory cell is reduced. As a result, the total time required for the above-described voltage switching can be reduced, and the time for the entire erase mode can be shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart of an erase mode according to an embodiment of the present invention.

FIG. 2 is a flowchart of a conventional erase mode.

FIG. 3 is a circuit diagram of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of an erase pulse generating circuit according to an embodiment of the present invention.

FIG. 5 is a waveform timing chart of the erase pulse generation circuit according to the embodiment of the present invention.

FIG. 6 is a circuit diagram of generation of an erase pulse according to another embodiment of the present invention.

FIG. 7 is a waveform timing chart of an erase pulse generating circuit according to another embodiment of the present invention.

[Explanation of symbols]

LOGC: erase control circuit, ERC: erase circuit, SA: sense amplifier, XDCR: row address decoder, YDCR
... column address decoder, XADB ... row address buffer, YADB ... column address buffer, DOB ... output buffer, DIB ... input buffer, CONT ... timing control circuit, M1 to M9 ... memory cells, Q1 to Q5 ... MOS
FET, WL1 to WLn ... word line, DL1 to DLm ...
Data line, CS: common source line, CD: common data line,
ce: Internal control signal, se: Read control signal, we ...
Write control signal, er: Erase control signal, Vss: Ground voltage, Vcc: Power supply voltage, Vpp: High voltage, Vcv: Verify voltage, AX: Row address signal, AY: Column address signal, / CE: External terminal (chip Enable signal), / OE: external terminal (output enable signal), / WE: external terminal (write enable signal), / OE
EE: external terminal (erase enable signal), I / O:
External input / output terminals, PP: prewrite pulse, ES: signal indicating erase mode, DC: decoder control signal, EV: erase verify signal, AED: automatic erase mode setting delay signal, VE: sense amplifier activation signal at verify, D5
~ D8: delay circuit, O2: oscillation circuit, BCS3, BCS
4: binary counter circuit, / EP: erase pulse, AE: automatic erase mode setting signal, ST: erase start signal, OS2:
Divided signal of verify reference pulse, S0 to S7: output signal of sense amplifier, EV: erase verify signal, EA
I: Address increment signal during verification, PE:
Erase pulse end signal, FAIL ... abnormality detection signal, ER ...
Erase mode end signal.

Continued on the front page (72) Inventor Hitoshi Kume 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (9)

[Claims] An erase mode for erasing information by storing a plurality of memory cells each having a floating gate, storing information according to an amount of electrons of the floating gate, and erasing the information by emitting electrons of the floating gate. Including an electron injection operation of injecting electrons into the memory cell and an electron emission operation of emitting electrons from the memory cell, wherein the electron emission operation includes an operation of applying a plurality of pulses,
The semiconductor nonvolatile memory device according to claim 1, wherein the plurality of pulses include pulses of different widths, and a width of a preceding pulse is set so as not to be larger than a width of a subsequent pulse. 2. The semiconductor nonvolatile memory device according to claim 1, wherein a verify operation for checking a charge accumulation state of the floating gate is performed during the application of the plurality of pulses. 3. The nonvolatile semiconductor memory according to claim 2, wherein said verify operation is performed by applying a verify voltage to a memory cell after application of each of said plurality of pulses. apparatus. 4. The semiconductor nonvolatile memory device according to claim 1, wherein a width of said plurality of pulses is sequentially increased. 5. The method according to claim 1, wherein the width of each of the plurality of pulses is set so that the threshold voltage of the memory cell does not become negative in one pulse. The semiconductor nonvolatile memory device according to any one of the above. 6. In a semiconductor nonvolatile memory device having a memory cell having a floating gate and storing information in accordance with a charge amount of the floating gate, an erasing operation for erasing information is performed by tunneling from the floating gate. A charge discharging operation for discharging charges using a phenomenon, and a charge injection operation for charging charges to the floating gate. In the charge discharging operation, an erase pulse for giving a voltage necessary for the charge discharge is applied to each memory cell. When an erase operation to be applied and a verify operation for reading and verifying whether or not the memory cell is in a desired state by applying a voltage to the memory cell thereafter to determine whether the memory cell is in a desired state are defined as one cycle, the erase / verify cycle is repeated. The width of the erase pulse in the preceding cycle is set so as not to be larger than the width of the erase pulse in the subsequent cycle. Somatic non-volatile storage. 7. An information erasing method for a semiconductor nonvolatile memory device having a memory cell provided with a floating gate and erasing information by emitting electrons from the floating gate. The electron emission operation for lowering the threshold value of the memory cell and the electron injection operation for raising the threshold value of the memory cell are performed together. The first operation to be applied to the cell and the second operation to read and verify the information by applying a voltage to the memory cell to determine whether or not the memory cell has reached a desired state are defined as one cycle. When repeating, the semiconductor nonvolatile memory is controlled so that the width of the erase pulse in the last cycle is larger than the width of the erase pulse in the previous cycle. Information erasing method of the device. 8. The semiconductor non-volatile memory device according to claim 7, wherein the threshold value of the memory cell after erasing information by the electron emission operation and the electron injection operation is controlled so as not to become negative. Information erasing method. 9. The memory cell has a drain region and a source region. By supplying the erase pulse to the source region, electrons accumulated in the floating gate are emitted to the source region by a tunnel phenomenon. 9. The method according to claim 7, wherein information is erased.