JPH11232243A - Communication control equipment, its method and communication control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute data transfer between plural serial ports without requiring the involvement of a microprocessor to be used for load control in a device by providing the device with a data transfer means from a 1st data storage area to a 2nd data storage area and executing data communication between 1st and 2nd equipments without requiring 1st and 2nd equipment control means. SOLUTION: When data from an equipment connected to a channel(CH) 1 are received by a CH1 shared receiving area in a shared data block area 924 in the case of transmitting data from the equipment connected to the CH1 to an equipment connected to CHs 2, 3 without passing a host, data are automatically transferred to a CH2/CH3 shared transmitting area. It is also available to transfer data from the 1st equipment connected to the CH1 to the 2nd equipment connected to the CH2 and from the 2nd equipment to a 3rd equipment cascade-connected to the 2nd equipment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device, a method, and a communication control system for exchanging data between a plurality of devices by communication.

[0002]

2. Description of the Related Art Conventionally, as a system for exchanging data between a plurality of apparatuses by communication, a copying system including, for example, a copying apparatus and an additional apparatus is known. In this case, the additional device is a recirculating document feeder (RDF) or a sorter.

Each of the copying apparatus and the additional apparatus has a device control unit for performing control unique to the copying apparatus and the additional apparatus.
The device control units between the devices are connected by serial communication or the like.

The copying system performs system control while transmitting and receiving control data such as an operation start command and an operation completion notice via a serial control IC connected to a serial port of a microprocessor or a data bus. Also,
In order to reduce the load of serial data transmission / reception processing in the microprocessor, a built-in communication control C
There is also known a copying system in which a chip called a communication control controller for controlling a plurality of serial controllers with a PU is introduced.

In such a copying system, the copying apparatus and each additional apparatus are connected point-to-point in order to increase the transmission and reception efficiency.

[0006] Some communication control devices include a microprocessor used for load control of the device in order to maintain smooth data transfer between devices connected in cascade and real-time communication. Some have a bridge function that allows data transfer without involvement.

[0007]

However, in the former communication control device, since each device is communicably connected in a point-to-point format, data transmission / reception with a device connected to a specific serial port is performed. However, in order to transfer the data to a device connected to another serial port, a microprocessor in the copying apparatus must be involved to transfer data between the serial ports. When controlling the load in a device such as a motor, there is a possibility that load control in the device such as a motor may be affected.

On the other hand, since data is transmitted and received equivalently between each device, in the case of a device which takes a bus format instead of a serial format, data of all devices connected to the bus is transmitted and received. The throughput of the transfer was reduced, and it was not suitable for a device such as a copying machine in which real-time property was emphasized.

In the latter communication control device having a bridge function for enabling data transfer between cascade-connected devices, the communication paths between the devices are cascade-connected to those directly connected. Since the data is shared with the device, data transmitted to each device using the bridge function is transferred to a device that does not need the data. As a result, a communication path may be used, which may hinder transmission and reception of directly connected data.

Therefore, the present invention can perform data transfer between a plurality of serial ports without involvement of a microprocessor used for load control in the apparatus, and has a function of suppressing the use of a bridge function. Accordingly, it is an object of the present invention to provide a communication control device, a communication control system, and a communication control system capable of avoiding a problem in transmission / reception of directly connected data.

[0011]

In order to achieve the above object, a communication control apparatus according to a first aspect of the present invention comprises: a data control unit for controlling a first device; In a communication control device for communicating data accessed by a second device control means for controlling two devices with the first device via a first communication port, the communication control device transmits data received from the first communication port. Means for receiving data stored in the first data storage area, means for transferring data stored in the first data storage area to the second data storage area, and means for transferring data transferred to the second data storage area. A data transmitting means for transmitting to a third device cascaded to the first device via a second communication port; Setting means for setting data transfer to the second data storage area to be prohibited or permitted, and between the first device and the third device without the first and second device control means interposed therebetween. It is characterized by performing data communication.

According to a second aspect of the present invention, in addition to the first and second data storage areas used for communication with the cascade-connected third device in the communication control apparatus according to the first aspect, It has a third data storage area used only for communication of data accessed by the second device control means.

According to a third aspect of the present invention, there is provided a communication control apparatus according to the second aspect, further comprising an access information storage unit for storing the access by the second device control unit.

According to a fourth aspect of the present invention, there is provided a communication control apparatus including a synchronization procedure storing means for storing a synchronization procedure for performing communication in the communication control apparatus according to the first aspect.

According to a fifth aspect of the present invention, in the communication control apparatus according to the second aspect, the first and second data storage areas are selectively used with respect to the third data storage area. Features.

According to a sixth aspect of the present invention, in the communication control apparatus according to the first aspect, the communication control apparatus is mounted on an image forming system for forming an image on a sheet, and the first device controls the image forming system. Wherein the second and third devices are sorters for sorting the discharged sheets.

According to a seventh aspect of the present invention, there is provided a communication control method for communicating data accessed by first device control means for controlling a first device and data accessed by second device control means for controlling a second device. Is performed between the first device and the first device via the first communication port, the data received from the first communication port is stored in the first data storage area, and the data is stored in the first data storage area The transferred data is transferred to the second data storage area, and the data transferred to the second data storage area is transmitted to a third device cascaded to the first device via a second communication port. In this case, the data transfer from the first data storage area to the second data storage area is set to be prohibited or permitted, and when the data transfer is set to be permitted, the first and second device control are performed. Without an intervening stage, the first
Data communication is performed between a device and the third device.

In the communication control system according to the present invention, the first device communicates data accessed by the first device control means for controlling the first device with the second device via the first communication port. A communication comprising: a control device; and a second communication control device for communicating data accessed by a second device control means for controlling the second device with the first device via the first communication port. In the control system, the second communication control device includes: a data receiving unit configured to store data received from the first communication port in a first data storage area; and a second data control unit configured to transfer data stored in the first data storage area to a second data storage area. Data transfer means for transferring the data to the storage area; and transmitting the data transferred to the second data storage area to a third device cascaded to the first device via a second communication port. Data transmission means, and setting means for setting data transfer from the first data storage area to the second data storage area to be prohibited or permitted by the data transfer means, wherein the first and second device control means are provided. Data communication is performed between the first device and the third device without intervening.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the communication control device, method and communication control system of the present invention will be described. The communication control device according to the present embodiment is applied to a copying machine.

FIG. 1 is a diagram showing the internal configuration of the copying apparatus according to the embodiment. In the figure, 100 is a copying apparatus main body, 300 is a circulating original feeding apparatus (hereinafter, referred to as RDF) for automatically feeding an original, and 400 and 500 are sorting apparatuses for storing recorded paper in a plurality of bins. Less than,
(Referred to as a sorter). RDF300 and sorter 4
Reference numerals 00 and 500 can be freely combined with the copying apparatus main body 100 and used. Copying apparatus body 100, RDF3
00 and sorter 400 are disclosed in
Since it is well known in Japanese Patent Publication No. 50 and the like, a detailed description thereof will be omitted.

FIG. 2 is a diagram showing the configuration of a system centered on a communication control device. The communication control device (IPC) connected to the master host CPU is provided with three serial ports, and each serial port is connected to the IPC connected to the slave host CPU. In this embodiment, the master device 1 corresponds to the control device 800 in the copying apparatus main body 100, and the slave devices 2 to 5 are the RDF 300, the sorters 400 and 5, respectively.
Equivalent to 00. In FIG. 2, I on the master side of device 1
IPC on the slave side of device 4 and device 5 to PC
Are cascaded.

[Control Device 800] FIG.
FIG. 3 is a block diagram showing a configuration of a control device 800 in 00. The control device 800 is connected to the RDF 300 and the sorter 400 via a communication control device (IPC) 812. Further, the sorter 400 has an IPC4
51 are cascaded. In the figure,
Reference numeral 801 denotes a central processing unit (CPU) for performing arithmetic control. Reference numeral 803 denotes a read-only memory (ROM) in which a control program is stored in advance.
Each component device connected via the bus is controlled in accordance with the control program stored in the device 03.

Reference numeral 805 denotes a random access memory (RAM) as a main storage device used for storing input data, a working storage area, and the like. An output interface (I / O) 807 outputs a control signal of the CPU 801 to an output load 813 such as a motor. Reference numeral 809 denotes an input interface for inputting a signal from an input load 814 such as a sensor and transmitting the signal to the CPU 801. Reference numeral 811 denotes an interface for controlling input / output of a key 815 of a control panel (not shown) and a display 816.

Reference numeral 812 denotes a communication control device (communication dedicated IC, I
PC). FIG. 4 is a block diagram showing the configuration of the communication-only IC (IPC) 812. In addition, IPC351, 45
1, 551 is the same as the configuration of FIG. The communication IC 812 includes a dual port RAM 920, a UART section 930 capable of communicating with a plurality of partners, a control section 910, and the like. The communication dedicated IC 812 includes:
When the CPU 801 changes the data in the dual port RAM 920, the control unit 910 sets the dual port R
A function of transmitting the change data of the AM 920 via the UART unit 930 and a function of setting the data received via the UART unit 930 in the dual port RAM 920 after processing such as an error check in the control unit 910 are provided. I have. The IPC 551 cascaded to the IPC 451 can communicate with the IPC 812 bidirectionally using two channels of the UART section of the IPC 451 and a shared data area of a dual port RAM described later.

Further, the RDF 300 and the sorter 400 are communication dedicated ICs 3 having the same function as the communication dedicated IC 812.
51 and 451, respectively. In the dual-port RAM 920 of the communication-dedicated IC 812, the latest condition data such as the operation status sent from the sorter 400 and the RDF 300 is stored. The CPU 801 accesses the dual-port RAM 920 so that the sorter 40
0, it is possible to grasp the control state of the RDF 300. The dual port RAM 920 has an IPC45
The condition data sent from the sorter 500 via the first sorter 500 is also stored.
00 control state can be grasped.

When the CPU 801 sets data for controlling the sorter 400 and the RDF 300 in the dual port RAM 920, the control data is stored in the UART section 9
30 and the sorter 400 and RD via the TX line
The data is transmitted to the communication-specific ICs 451 and 351 of the F300. CPU 4 with a built-in control program
50 and 350 access the control data of the dual port RAM of the communication-dedicated ICs 451 and 351 and start the above-described control operation according to the control data. Similarly, the CPU 80
1 sets data for controlling the sorter 500 in the dual port RAM 920, and the control data is UART.
Transmitted to the IPC 451 via the unit 930 and the TX line, and further cascaded to the IPC 451.
It is transmitted to C551. The CPU 550 of the sorter 500 accesses the control data of the dual port RAM of the IPC 551 and starts the control operation according to the control data.

[Communication Dedicated IC (IPC) 812] A communication dedicated IC (hereinafter referred to as IPC: Intelligent Pr)
otocol Controller) 812
CPU, ROM, RAM, as shown in FIG.
This is a high-performance communication control IC having a function of integrating a 3ch asynchronous serial interface and a BUS interface on one chip, automatically transmitting data on the RAM, and expanding received data on the RAM.

The IPC 812 includes a control unit 910 for internal control and a dual port RAM 92 as described above.
0, a UART section 930 for executing actual communication control, and a BUS interface section 940 for connecting to the outside (host). Note that the IPCs 351, 451, and 551 have the same configuration as described above.

[Control Unit 910] The control unit 910 is a single-chip CPU 911 having a built-in ROM and RAM for executing internal control, a timer 912 for controlling timing, and a port 91 for external memory.
3 is comprised.

[Dual-port RAM 920] The dual-port RAM 920 includes data block areas 921, 9
24, an access flag area 922, and a communication register area 923.

The data block area includes a non-shared data block area 921 and a shared data block area 924. The data block area is divided into 32-byte RAM areas for storing Tx data and Rx data of each channel, which will be described later. You. For each block, simultaneous access (read / read) from external (host) side and internal (local) side
Write) is possible, but if the same memory cell (same byte) is accessed, the read content is undefined if one is a write operation.

FIG. 5 is a diagram showing a configuration of a data block used in each channel. The assignment when the data block used in each channel is in the 3-channel mode and in the 1-channel mode is as shown in the figure. In the shared area, data transfer between data blocks is performed.

For example, a case where data is transmitted from a device connected to channel 1 to a device connected to channels 2 and 3 without going through a host will be described. FIG. 29 is a flowchart showing a shared data transmission processing procedure for transmitting data to a device without going through a host. When data from the device connected to channel 1 is received in the CH1 shared reception area (block 9 shown in FIG. 7 in this embodiment) (step S61), the designated parameters RM6 and RM
When 7 is set to the value 1 (see FIG. 12C, steps S61A and S61B), CH2 and CH3 are automatically set.
The data is transferred to the shared transmission area (blocks 11 and 15 in the present embodiment) (steps S62, S62).
63 and S65, S66).

Thereafter, the block semaphore flag BS1
1, BS15 is set to "1" (step S64,
S67), the transmission processing of the devices connected to channel 2 and channel 3 to the shared reception area is automatically performed.

Here, if there is another device connected to the other party, this process is repeated on the open side. In the present embodiment, only data transmission from channel 1 to channel 2 and channel 3 has been described, but the same applies to the case where data is transmitted and received between other channels without the intervention of a host. Similarly, it is also possible to transfer data from the first device connected to channel 1 to the second device connected to channel 2, and from the second device to a third device cascade-connected.

On the other hand, if the designated parameters RM6 and RM7 are set to 0 in steps S61A and S61B (see FIG. 12 (c)), the data transfer (acceptance) to the shared area is prohibited. No delivery is made to the block. That is, in this case, channel 2,
The data transmission to channel 3 is not performed, and the process ends.

The access flag area 922 is made up of access flags prepared one bit at a time corresponding to each memory address of the data block, and the lowest address of the data block sequentially corresponds to the lowest bit of the access flag. Bits are assigned to upper bits.

Each access flag is set to "0" when the corresponding memory address is read, and is set to "1" when the corresponding memory address is written. The access flag is read in 8-bit units, but since this area is read-only, even if this space is accessed, the contents of the access flag do not change. FIG. 6 shows an access flag area.

Communication register area 923
Is composed of an IPC mode setting register / IPC error register and an IPC synchronization register. The IPC mode setting register / IPC error register shares the same address for 4 bytes on the system bus. (UART mode setting / UA
RT baud rate setting / operation mode setting)
The latter is read-only and is used for determining an error (error channel error type) occurring in the IPC. FIG. 7 is a diagram showing the memory mapping of the entire dual port RAM 920.

The IPC synchronization register is a register for handshaking between the host CPU and the local CPU.
Block semaphore flag 18 bits (BS0 to BS1
7) and 1 bit of ready flag (IPC_RDY). FIG. 8 shows the configuration of the IPC synchronization register. BS0 to BS17 are related to the transmission / reception operations of each UART unit, and BS0, 2, 4, 6, 7, and
8, 10, 11, 12, 14, 15, 16 are each UART
This is a semaphore flag for controlling the transmission of the UART. When the semaphore flag is set to "1", transmission of each UART is started. BS
Reference numerals 1, 3, 5, 9, 13, and 17 denote semaphore flags for controlling reception of each UART section, and are set to "1" by the local CPU each time reception is completed in each UART section.

[UART part 930] The UART part has three channels of UARTs, and all functions are equivalent. Further, since the three-channel UART has a built-in baud rate generator, it can be operated completely independently. Each channel has three external terminals TxD (transmission output), RxD (reception input), control output, internal registers TxB (transmission buffer register), RxB (reception buffer register), and STA.
TUS (status register), MODE (mode register), CONTROL (control register), BAUDR
It has an ATE (baud rate generator) and a CLK terminal (baud rate external clock input) shared by three channels.

The control outputs are INTR, RxRDY, and LINEERR in order from channel 1. When a UART error occurs, the INTR outputs an interrupt request. At this time, by reading the error register, the channel in which the error has occurred and the content thereof can be known.

FIG. 9 is a timing chart showing the relationship between RxRDY and the block semaphore. As shown in the drawing, RxRDY outputs "L" at the same time when the reception of the packet is completed and the BS of the reception data block is set. When all the BSs of the reception blocks of all channels become "0", RxRDY returns to "H".

LINEERR is a communication line error output. When a line error (parity or framing) occurs in one of channels 1, 2, and 3, a pulse of about 6 us is output.

[BUS Interface 940] The BUS interface connecting the host and the IPC is composed of (1) eight lines of address, (2) eight lines of data, and (3) control CS, WR, and RD, each one line.

[System Software] The system software of the IPC will be described. This software is for internal control of the IPC and packet communication by the UART, information exchange with the host CPU, and synchronization. The IPC performs error recovery and initialization in communication with another IPC via the UART, stores only correct data in the dual port RAM,
Has the function of passing to

[Power-On Reset] After the power is turned on, various ports, timers, registers, etc. are initialized, and after the mode setting from the host computer is completed, the UART is started to start communication processing.

[Mode Setting] There are the following three types of mode designation.

(1) UART mode designation The data length, parity, and stop bits are determined by setting parameters in IPCM (IPC mode setting register) 1, 2, and 3. FIG. 10 is a diagram showing the relationship between parameters and modes.

(2) UART baud rate designation Similarly, the baud rate is determined by setting parameters for IPCMs 1, 2, and 3. FIG. 11 shows the system clock = 9.
It is a figure which shows the relationship between a parameter and baud rate in 216Mz.

(3) IPC operation mode designation When the IPC operation mode command is set in the IPCM (IPC mode setting register), the operation mode is set by the parameters set in IPCM1, and the entire data block is set to "00H". clear. FIG. 12 is a diagram showing values of designated parameters.

When RM0 = 1 and RM1 = 0, the operation mode is one-channel operation. RM0 = 1, RM1 =
When it is 1, the operation mode is a three-channel operation mode. In the transfer mode, RM5 = 0, RM6 = 0, R
When M7 = 0, transfer to channel 1, channel 2, and channel 3 is prohibited, and RM5 = 1,
When RM6 = 1 and RM7 = 1, the transfer to channel 1, channel 2, and channel 3 is permitted.

When one-channel operation is designated by setting RM0 = 1 and RM1 = 0, data blocks 0, 1 and 2 are set to Tx
And 3, 4, and 5 are used for Rx. When the operation mode is designated, the BS flag of the Tx data block corresponding to the operation mode is set. Reset when the initial communication is completed after the mode is specified.

[Communication] IPC packet communication will be described. FIG. 13 shows the structure of a packet. The packet includes a header H, an address A, a data Dn, and a checksum CK. FIG. 14 shows the header H
FIG. 3 is a diagram showing the configuration of FIG. The header portion H indicates the type of the packet by the upper four bits (B7 to B4 in the figure), and includes the last packet PE, retransmission request code PR, initial communication request code PS, continuation packet P, idle packet Pi, and cancel code Pc. Have seeds. FIG. 15 is a diagram showing types of packets.

Lower 4 bits (B3 to B0 in FIG. 13)
Indicates the data length, and the data length is 0 to 16 bytes.
The address part A indicates the address of the data part (D0) transmitted following the address data. Data part Dn is maximum 1
It can include 6 bytes of data. The checksum part CK is added to the end of the packet, and the contents thereof are obtained by adding the data from the header part to the last data (ignoring the carry) and inverting the result of the addition.

[Packet Content] Each packet will be described. FIG. 16 is a diagram showing the relationship between packet types and control codes. First, the continuation packet P indicates that there is a packet to be transmitted after this packet. The packet length is 4 to 19 bytes. The last packet PE indicates that there is no data packet after this packet, and the packet length is 4 to 19 bytes. The idle packet Pi includes only the memory checksum D0 of the transmission address and is composed of 4 bytes. Retransmission request code P
R is a packet retransmission request and is composed of one byte.

The initial communication request code PS is a transfer request for all data and is composed of one byte. The cancel code PC is a response to PR and indicates cancellation of a packet being transmitted or transmitted, and is composed of one byte.

[Communication Interval] FIG. 17 is a diagram showing intervals during communication. Data interval TD
int is from 100 us to 330 us, and the interval TPint between packets is 700 us (96 kbps).
Hour) or 2000 us (less than 48 kbps).

[Communication Timing] Initial communication (when power is turned on) FIG. 18 is a timing chart showing the initial communication. When the own station IPC starts up at the timing shown in FIG.
Start transmitting Ps at intervals of Txint. When the partner station IPC rises at the timing shown in the figure, Ps is received and Ps is transmitted, so that normal communication is established (TXint = 4 ms in the figure).

2. Normal Communication FIG. 19 is a timing chart showing normal communication. In normal communication, communication control is performed independently for 3 channels. When there is no event (transmission request from the host or reception from the partner station), Pi transmission / reception is performed at intervals of Txint, and when an event occurs (a: transmission request from host, b in the figure) : Reception from the partner station), transmission or reception of P or PE is performed as described above. (In the figure, Txint = 4 ms, Rxint = 12 ms).

[Communication Error Occurrence and Recovery] The IPC has a function of performing an automatic recovery process when a reception data error occurs for each channel. Among the types of errors, there are parity errors, checksum errors, and framing errors as the ones caused by the line. In addition, there are data loss due to excessive communication, reset of the partner IPC, power off, and the like.

FIG. 20 is a timing chart showing communication error occurrence and automatic recovery processing. In the reception of the PE and Pi packets (in the figure), if an error occurs, a PR requesting retransmission of the packet is sent out, and a Pc response from the other party and a retransmission packet are awaited (A in the figure).

When data is lost due to a reset or the like and an error occurs in a P packet (in the figure), P is transmitted and communication data is immediately recovered (B in the figure).

If the communication error is not recovered even after the error recovery processing, the IPC sets the erroneous channel to ER.
In the R register, the type of the error is ERRn (n = 1,
2, 3, and n correspond to error channels), and simultaneously generate an external interrupt request.

FIG. 21 shows the structure of the ERR register. In the ERR register, the bit corresponding to the erroneous channel is set to “1” (EU1: channel 1, EU
2: channel 2, EU3: channel 3). In ERRn, a bit corresponding to an error type of a register corresponding to an error channel is set (RXPR3: retransmitting the same packet three times, TXPR3: transmitting three times in the same packet during packet reception, TOUT: receiving data error,
PIER: The checksum of the data block for the partner station Tx does not match the checksum of the data block for the own station Rx).

1. Verification and error of memory checksum by Pi packet As described above, a Pi packet has a memory checksum (D0), and when a Pi packet is received, the D0 of the packet is compared with the memory checksum D0 of the own station reception block. And make sure they are the same. If they are different, Ps is transmitted to prompt initial communication, thereby keeping the data block of the partner station Tx and the data block of the own station Rx consistent.

2. If the received data has not been received for 12 ms or longer, an initial communication request Ps is sent as a time-out error, and the partner waits for a return.

3. Communication conditions Data transfer starts when the host CPU confirms that the BS of the transmission block has been set, or when the BS flag has not been set for about 100 ms even though data has been updated from the host. (The BS is reset 2 ms after the completion of the transfer).

Further, this is performed when an error occurs in the data for some reason and an initial communication request is generated or received.

Under the above conditions, that is, when a transmission request occurs,
The IPC detects the location of the updated data in the Tx block, and sends out the updated range from the highest address to the lowest address as a packet to improve the efficiency of communication processing.

FIG. 22 shows the efficiency of the data communication process. The updated data (the hatched portion in the figure) is detected (detected by a change in the access flag), and the detected data is transmitted as a PE packet having data of 12 bytes from 08H to 13H. If the detected data range exceeds 16 bytes, it is transmitted as a P packet of 16-byte data and a PE packet containing the remaining data. The data in the packet is always transmitted from the highest address.

[Application Example] Access of the IPC from the host side will be described. The hardware is configured in the same way as when an external memory device (RAM or the like) is accessed, and therefore will not be described in detail. The software will be described step by step.

[Initialization] FIG. 23 is a flowchart showing the procedure of the IPC initialization processing. Ready flag in communication register area (IPC_RDY)
Is "1" and the UART mode is specified.
An ART baud rate and an IPC operation mode are specified (steps S1 to S6). As described above, when using 3 ch, both the UART mode and the UART baud rate can be set independently. When the mode designation is completed and the TX BS of the used channel becomes “0”, the initialization ends (steps S7 and S8). Hereinafter, since all three channels are equivalent in the three-channel mode, only the case where channel 1 is used will be described.

[Transmission processing] When data to be transmitted occurs on the host side, after confirming that BS0 is "0", that is, that the previous transmission processing has been completed by the IPC, this data is transmitted to the TX. Write to the desired address in the block,
The transmission process is automatically performed by setting BS0 to “1”.

FIG. 24 is a flowchart showing the data transmission processing procedure. A case in which an operation start command is transmitted from the copier body to the additional device will be described. In this case, "operation mode", "operation parameter",
It is assumed that 3-byte data of “operation start command” is required.

First, it is confirmed whether or not BS0 is "0" (step S11). If affirmative, the "operation parameter" is set to 06H of the TX block of the IPC and the "operation mode" is set to the TX block of the TX block. At 05H, the "operation start command"
Each is stored in 04H of the X block (step S1).
2), BS0 is set to "1" to start transmission (step S13). In this case, even if BS0 is not set, transmission starts about 100 ms later as described above.

As described above, since the data of the TX block is transmitted from the upper address, the data arrives at the partner station (additional device) in the order of “operation parameter”, “operation mode”, and “operation start command”. Become. The transmission side may determine the arrangement of the data in the TX block in consideration of the priority of the transmission data, and does not need to perform cumbersome transmission data priority processing or the like at the time of actual transmission processing. Therefore, as the amount of data becomes larger and more complicated, the conventional communication I
As compared with C, the load on software for communication processing can be reduced.

In this embodiment, only the case of channel 1 has been described. However, since the channels are independent of each other, it is possible to perform processing independently on other channels on software even when transmitting three channels simultaneously. Thus, efficiency and simplification can be achieved.

When transmitting data from the host to all the channels connected to channel 1, after confirming that BS6 is "0", that is, the previous transmission processing is completed by the IPC, this data is shared by CH1. By writing to the transmission area (block 6 in the present embodiment) and setting BS6 to "1", transmission processing is automatically performed. The same operation is performed when transmitting shared data to another channel. Further, transmission to another channel after the data reaches the partner station is also possible.

[Reception Processing] When the host wants to read the received data, the data can be read by accessing the host in the same manner as when reading from the RAM or the like. However, as described above, when the writing from the IPC side to the dual port RAM and the reading from the host side collide, the value of the read data becomes indefinite, but the above-described problem is caused by reading the RAM data twice. Can be solved.

FIG. 25 is a flowchart showing the data reception processing procedure. For example, the contents of a desired address are loaded into the accumulator A (step S21), and further,
Subsequently, the contents of the same address are loaded into another register B (step S22), and compared with the contents of the accumulator A (step S23). As a result of the comparison, if they are equal, the contents of the accumulator A are determined as received data (step S25). If they are different, the contents loaded into the accumulator A can be determined again as received data (steps S24 and S25). ).

As another method, collision can be avoided in the dual port RAM by reading data after confirming that BS1 is set to "1". However, it is necessary to reset BS1 to "0" on the host side after reading. FIG. 26 is a flowchart showing another data reception processing procedure. When it is desired to read data received from the host in the shared area, the contents of the shared reception block are read in the same manner as described above (steps S31 to S34).

[Error Processing] When an error status is set in the "INTR" terminal or the error register, processing can be performed freely according to the system configuration on the host side.

FIG. 27 is a flowchart showing a master-side error processing procedure. On the master device (copier body) side of the system, after an error occurs, I
If the error is not automatically reset by the PC, it is regarded as a system error, and that fact is displayed on the display (steps S41 to S44). Although not shown, a system error is also defined when an error occurs three times or more per second.

FIG. 28 is a flowchart showing the procedure of error processing on the slave side. When the communication line on the transmitting side is disconnected, the IPC does not set an error status in principle. Therefore, if the transmission line of the master device is disconnected, no error status is generated for this device. However, since an error occurs as a timeout error on the receiving side, a timeout error occurs on the slave side (RDF, sorter, etc. in the present embodiment) due to the system configuration, and within a predetermined time (200 ms during device operation, non-operation If the IPC does not automatically recover from the error within 5000 ms), an error is generated in the master device (the copying machine body in this embodiment) by switching the communication baud rate of the IPC and a system error display is performed (step S).
51-S59). However, the master-slave relationship described above is not a master-slave relationship in communication processing, but is only an error process.

As described above, in this embodiment, when data is transmitted from the device connected to channel 1 to the devices connected to channel 2 and channel 3 without passing through the host, the connection to channel 1 occurs. When data from the device is received in the CH1 shared reception area of the shared data block area 924, the data is automatically transferred to the CH2 and CH3 shared transmission areas. Thereafter, the transmission processing to the shared reception area of the devices connected to the channels 2 and 3 is automatically performed. It is also possible to transfer data from the first device connected to channel 1 to the second device connected to channel 2 and from the second device to a third device cascaded. When the transfer of data to the shared area is prohibited by the designated parameter, the transfer of data to the prohibited shared data block area is not performed, and the data is not transmitted to channel 2, channel 3, or the like.

Although the above embodiment has been described with reference to an example of a system including a copying apparatus and an additional apparatus (sorter, RDF), the present invention is not limited to this. It is applicable to all systems that perform data communication.

[0088]

According to the communication control device of the present invention, the data accessed by the first device control means for controlling the first device and the second device control means for controlling the second device are provided. When performing communication of data accessed by the first device via the first communication port, the data received from the first communication port by the data receiving means is stored in the first data storage area, The data stored in the first data storage area is transferred to the second data storage area by data transfer means, and the data transferred to the second data storage area is transferred to the second data storage area by the data transmission means via the second communication port. When transmitting to the third device cascaded to the first device, data transfer from the first data storage area to the second data storage area by the data transfer means is prohibited. Or when the data transfer is set to be permitted by the setting device that sets the data transfer between the first device and the third device without intervening the first and second device control devices. Therefore, data transfer between a plurality of serial ports can be performed without involvement of a microprocessor used for load control of the device. Thereby, the influence on the load control in the device can be eliminated.

Further, since data transmission and reception between devices connected to a specific serial port is performed by a conventional method, it is effective for a device in which real-time performance is important such as a copying device without lowering efficiency.

Further, by having the function of suppressing the use of the bridge function, it is possible to prevent the communication path from being used and hindering the transfer of directly connected data. As described above, it is possible to perform high-accuracy system control that requires real-time performance without being affected by data transferred by the bridge function. The same effect can be obtained in the communication control method according to the seventh aspect and the communication control system according to the eighth aspect.

According to the communication control device of the second aspect,
In addition to the first and second data storage areas used for communication with the third device connected in cascade, a third data storage area used only for communication of data accessed by the second device control means , So that use suitable for the communication mode is enabled.

According to the communication control device of the third aspect,
Since the apparatus has the access information storing means for storing the access by the second device control means, the communication can be started based on the access information.

According to the communication control device of the fourth aspect,
Since a synchronization procedure storage unit for storing a synchronization procedure for performing communication is provided, transmission processing and the like can be automatically performed.

According to the communication control device of the fifth aspect,
Since the first and second data storage areas are selectively used for the third data storage area, a data storage area suitable for a communication mode can be used.

According to the communication control device of the sixth aspect,
Mounted on an image forming system that forms an image on a sheet,
The first device is a control device for controlling the image forming system, and the second and third devices are sorters for sorting the discharged sheets. Therefore, the image forming system includes a copying device and a sorter. The processing efficiency of the system can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of a copying apparatus according to an embodiment.

FIG. 2 is a diagram showing a configuration of a system centered on a communication control device.

FIG. 3 is a block diagram showing a configuration of a control device 800 in the copying apparatus main body 100.

FIG. 4 is a block diagram showing a configuration of a communication-specific IC 812.

FIG. 5 is a diagram showing a configuration of a data block used in each channel.

FIG. 6 is a diagram showing an access flag area.

FIG. 7 is a diagram showing memory mapping of the entire dual port RAM 920.

FIG. 8 is a diagram showing a configuration of an IPC synchronization register.

FIG. 9 is a timing chart showing a relationship between RxRDY and a block semaphore.

FIG. 10 is a diagram showing a relationship between parameters and modes.

FIG. 11 is a diagram illustrating a relationship between a parameter and a baud rate at a system clock of 9.216 Mz.

FIG. 12 is a diagram illustrating values of designated parameters.

FIG. 13 is a diagram showing a structure of a packet.

FIG. 14 is a diagram showing a configuration of a header section H.

FIG. 15 is a diagram illustrating types of packets.

FIG. 16 is a diagram illustrating a relationship between a packet type and a control code.

FIG. 17 is a diagram showing intervals during communication.

FIG. 18 is a timing chart showing initial communication.

FIG. 19 is a timing chart showing normal communication.

FIG. 20 is a timing chart showing a communication error occurrence and an automatic recovery process.

FIG. 21 is a diagram showing the structure of an ERR register.

FIG. 22 is a diagram showing the efficiency of data communication processing.

FIG. 23 is a flowchart illustrating an IPC initialization processing procedure;

FIG. 24 is a flowchart showing a data transmission processing procedure.

FIG. 25 is a flowchart showing a data reception processing procedure.

FIG. 26 is a flowchart showing another data reception processing procedure.

FIG. 27 is a flowchart showing a master-side error processing procedure.

FIG. 28 is a flowchart showing a slave-side error processing procedure.

FIG. 29 is a flowchart illustrating a shared data transmission processing procedure for transmitting data to a device without passing through a host.

[Explanation of symbols]

300 RDF 400, 500 Sorter 800 Controller 801 CPU 803 ROM 812, 351, 451, 551 Communication dedicated IC (IP
C, communication control device) 920 Dual port RAM 921 Non-shared data block area 924 Shared data block area 930 UART section

Claims (8)

[Claims] 1. Communication between data accessed by first device control means for controlling a first device and data accessed by second device control means for controlling a second device is performed via a first communication port. A communication control device for performing communication with the first device, a data receiving unit configured to store data received from the first communication port in a first data storage area, and a data reception unit configured to transfer data stored in the first data storage area to a first data storage area. (2) data transfer means for transferring data to the second data storage area; and data for transmitting the data transferred to the second data storage area to a third device cascaded to the first device via a second communication port. Transmission means; and setting means for setting data transfer from the first data storage area to the second data storage area by the data transfer means to be prohibited or permitted. It said first and second device control means without intervention of the communication control apparatus characterized by communicating data between the first device and the third device. 2. The method according to claim 2, wherein the first and second data storage areas used for communication with the third device connected in cascade are used only for communication of data accessed by the second device control means. The communication control device according to claim 1, further comprising a third data storage area. 3. The communication control device according to claim 2, further comprising access information storage means for storing the access by said second device control means. 4. The communication control device according to claim 1, further comprising a synchronization procedure storing means for storing a synchronization procedure for performing communication. 5. The communication control device according to claim 2, wherein the first and second data storage areas are selectively used for the third data storage area. 6. An image forming system for forming an image on a sheet, wherein the first device is a control device for controlling the image forming system, and the second and third devices are for sorting the discharged sheets. 2. The communication control device according to claim 1, wherein the communication control device is a sorter that performs the following. 7. Communication of data accessed by the first device control means for controlling the first device and data accessed by the second device control means for controlling the second device is performed via the first communication port. In the communication control method performed with the first device, data received from the first communication port is stored in a first data storage area, and data stored in the first data storage area is stored in a second data storage area. When the data transferred to the second data storage area is transmitted to a third device cascaded to the first device via a second communication port, the data is transferred from the first data storage area The data transfer to the second data storage area is set to be prohibited or permitted, and when the data transfer is set to be permitted, the data transfer to the second data storage area is performed without the first and second device control means. Communication control method, characterized in that for communicating data between the first device 3 device. 8. A first communication control device for communicating data accessed by a first device control means for controlling a first device with a second device via a first communication port; and A communication control system having a second communication control device for performing communication of data accessed by the second device control means for controlling with the first device via the first communication port; The apparatus includes: data receiving means for storing data received from the first communication port in a first data storage area; data transfer means for transferring data stored in the first data storage area to a second data storage area; Data transmission means for transmitting the data transferred to the second data storage area to a third device cascaded to the first device via a second communication port; Setting means for setting transfer of data from the first data storage area to the second data storage area by the transfer means to be prohibited or permitted; and A communication control system for performing data communication between one device and the third device.