JP3189727B2 - Packet-type memory LSI with built-in coprocessor, memory system using the same, and control method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-capacity memory LSI using a packet-type external interface technology, and more particularly to a dynamic random access memory LSI (packet-type DRAM).
The present invention relates to a packet-type memory LSI with a built-in coprocessor in which one or more coprocessors are added to I.

[0002]

2. Description of the Related Art Generally, a memory LSI is required to be able to access its storage contents with a larger data bandwidth as its storage capacity increases. This is easy to understand when the memory LSI is considered in analogy with a bag that closes an object. When the size of a bag (corresponding to the capacity of the memory LSI) becomes large and the size of the outlet of the bag (corresponding to the data band width of the memory LSI) remains small, the bag may not be able to carry out an object. When taking out (equivalent to writing and reading data), it becomes very difficult to use. In other words, in order to realize an easy-to-use memory LSI in the system,
It is very important to balance the storage capacity and data bandwidth. For these reasons, technology development for improving the data bandwidth of DRAM, which is a memory LSI having the largest capacity, has been actively conducted.

In order to improve the data bandwidth, it is necessary to increase the operating frequency of the external interface as much as possible. In this case, simultaneous operation of the external input / output signal terminals is an obstacle. In other words, when many signal terminals operate simultaneously at high speed, the power consumption of the chip increases and also causes large switching noise.
It may cause malfunction. Further, when the number of external input / output signal terminals is large, there is a problem that it is difficult to adjust the timing shift between the many signal terminals.

[0004] For this reason, as a conventional technique for increasing the data bandwidth of a DRAM, the number of signal lines of a memory bus connected to the DRAM is reduced as much as possible, and the number of external input / output signal terminals of the DRAM is further reduced. Methods for increasing the operating frequency of the memory bus have been developed. Typical examples are Rambus DRAM, SyncLink DRAM, and Mediacha.
nnel DRAM and the like. The Rambus DRAM is described in detail in various manuals issued by Rambus. SyncLink DRAM is Sy as standardization technology of IEEE.
The organization called ncLink Consortium is in the process of formulating specifications, and it is “Draft Standard for A High-Speed Memory Inter
face (SyncLink) ”, Draft xxx P1596.7-199x (http: /
/www.scizzl.com/P1596.7/index.html) provides a tentative draft specification. Regarding Mediachannel DRAM, a paper “Multi-Gigabyte / sec DRAM w” was published at COMPCON'96 (spring), a well-known international conference.
ith the MicroUnity MediaChannel Interface "by Tim
Robinson, et. Al. (Pp. 378) has a description.

A DRAM using these technologies is called a packet type or a protocol type in order to realize efficient DRAM access while realizing a memory bus with a small number of signal lines and a small number of external input / output signal terminals. The memory bus technology and the DRAM interface technology are used. For this reason, the DRAMs based on these prior arts are collectively referred to as packet-type DRAMs, and the memory bus is referred to as a packet-type memory bus. Hereinafter, the packet type DRAM and the packet type memory bus will be described.

FIG. 16 shows a packet type DRA according to the prior art.
An example of the configuration of M1001 has been shown. In the figure, a packet type DRAM 1001 includes a memory unit 11, a control unit 1012
And an interface unit 13. The memory unit 11 includes a DRAM core unit 15 and a memory control register unit 1
The DRAM core unit 15 includes a plurality of DRAM banks 17 and a plurality of sense amplifiers 18 corresponding thereto.
It is composed of The memory control register section 16 has a plurality of memory control registers 29 therein. The control unit 1012 includes a memory control logic circuit 1019, a control signal register 20, a write data register 21, a read data register 22, and a memory device ID collation circuit 10.
23. The input / output signal terminals of the control unit 1012 include a control signal terminal 24 and a write data terminal 25 as input terminals, and a read data terminal 2 as an output terminal.
6, and these input / output signal terminals are connected to the interface unit 13. The interface unit 13 is connected to the external input / output terminal 5. The memory unit 11 and the control unit 1012 are connected to the internal memory data bus 27 which is a bidirectional bus.
Are connected by

FIG. 17 shows a conventional packet type DRA.
The configuration of the M1001 and the connection relationship between the packet type DRAM 1001 using the packet type memory bus 1002 and the microprocessor 9 are shown. In the figure, the packet type DR
FIG. 1 shows three examples of the configuration of the interface unit 13 of the AM 1001 and the configuration of the packet-type memory bus 1002.
7 (a) to 7 (c). In the packet-type memory bus 1002, the number of bus masters on the packet-type memory bus 1002 is limited to only one. The plurality of packet DRAMs 1001 connected to the packet memory bus 1002 all work as slave devices. In general, a bus master is a device that can occupy the bus and issue a request to the bus, and a slave device returns a response in response to the bus master's request. Bus 1002
Means devices that do not make requests to them. As will be described later, by limiting the number of bus masters to one, the bus master can issue a request without arbitrating the bus occupation right of the packet-type memory bus 1002. Protocol can be simplified. In FIG. 17, the microprocessor 9 is connected as a bus master of the packet-type memory bus 1002, but actually, the bus master of another packet-type memory bus 1002, for example, a memory controller, a signal processor, a graphics accelerator, and others. ASIC may be used.

In the configuration of FIG. 17A, the packet type DRAM 1001 comprises a memory unit 11, a control unit 1012, and an interface unit 13, as in FIG. Control signal terminal 2 which is an input / output terminal of control unit 1012
4, write data terminal 25, read data terminal 26
Are all connected to the interface unit 13. The interface unit 13 includes a microprocessor 9 and a packet type D.
Packet type memory bus 100 connecting RAM 1001
2 are connected. The packet type memory bus 1002 is a bidirectional bus.

In the configuration shown in FIG. 17B, the interface unit 13 comprises a control interface unit 13-1 and a data interface unit 13-2. Control unit 101
2 control signal terminal 24 is connected to the control interface unit 13-1.
To the write data terminal 25 and the read data terminal 26
Are connected to the data interface unit 13-2. In this configuration, the packet type memory bus 1002
Is composed of a control bus 1002-1 and a data bus 1002-2. The control interface unit 13-1 sends the data interface unit 13-1 to the control bus 1002-1.
2 are respectively connected to the data bus 1002-2.
The control bus 1002-1 is a unidirectional bus from the microprocessor 9 to the packet type DRAM 1001, a data bus 1
002-2 is a bidirectional bus.

In the configuration shown in FIG. 17C, the interface unit 13 comprises a request interface unit 13-3 and a response interface unit 13-4. Control unit 1012
The control signal terminal 24 and the write data terminal 25 are connected to the request interface unit 13-3, and the read data terminal 26 is connected to the response interface unit 13-4. In this configuration, the packet type memory bus 1002 is
2-3 and a response bus 1002-4. The request interface unit 13-3 is a request bus 1002-3.
To the response interface 13-4.
-4, respectively. The request bus 1002-3 is transmitted from the microprocessor 9 to the packet type DRAM 1001.
The response bus 1002-4 is a unidirectional bus in the opposite direction.

FIG. 18 shows a classification of a process externally required for the packet type DRAM 1001. The processing types are classified into three types: memory access, initialization, and refresh. All processes are performed by the packet type memory bus 10
This is performed in response to a request from the bus master 02, ie, the microprocessor 9 in FIG. Regarding the memory access, first, the DRAM core unit 15 in the memory unit 11 is to be accessed, or the memory control register unit 1
6 is classified as an access target. DRAM
Each of the accesses to the core unit 15 or the memory control register unit 16 has two types of operation: reading and writing. Further, when accessing the DRAM core unit 15, the length of data to be read or written is specified. The data length is generally, for example, about 8 to 256 bytes. When accessing the memory control register 16, the data length of the memory control register 16 (e.g., 8 bytes) is usually fixed or less.
The initialization is mainly an operation of resetting the internal state of the memory control logic circuit 1019 and storing device information unique to the packet type DRAM 1001 in the memory control register unit 16.
This is an operation which is indispensable in the operation of M and periodically rewrites in order to retain the stored contents of the DRAM cell. The procedure for initialization will be described later. The specific procedure of the operation related to the refresh is not related to the gist of the present invention, and therefore, the description is omitted below.

Referring to FIG. 16 and FIG. 18, first, respective operations in DRAM access of packet type DRAM 1001 will be described. In any DRAM access, the operation type name, request destination, operation name, and data length instruction shown in FIG. Is specified. The DRAM bank 17 to be accessed is
And a memory address indicating a data position inside the memory,
Alternatively, a memory control register number indicating a specific memory control register 29 in the memory control register section 16 is also specified. Information given from these control signal terminals 24 is collectively called control signal information.

The control signal information includes a plurality of packet-type DRAMs 100 connected to a packet-type memory bus.
One or a plurality of packet type DRAMs 10
01 is selected. The device ID included in the control signal information is compared with the memory device ID unique to the packet type DRAM 1001 stored in the specific memory control register 29 in the memory control register unit 16 in the memory device ID comparison circuit 1023. By this comparison, it is determined whether or not the request for DRAM access or the like transmitted via the external input / output terminal 5 is to the packet type DRAM 1001. The packet type DRAM 100
If the access is not to DRAM, the following operation is not performed. Note that the device ID included in the control signal information may specify the memory device ID of a plurality of packet-type DRAMs 1001.

In the control unit 1012, the read data is output from the read data terminal 26 at the time of reading, and write data is given from the write data terminal 25 at the time of writing. The control signal register 20, the write data register 21, and the read data register 22 function as input latches (or input registers) or output latches (or output registers) of these input / output terminals. The memory control logic circuit 1019 determines what operation is to be performed in accordance with the control signal information given from the control signal terminal 24, and controls the DRAM access. In the control, the storage contents of the memory control register 29 in the memory control register section 16 are referred to as needed. In the case of accessing the DRAM core unit 15, a desired DRAM bank 17 is selected by designating an address, and data in the DRAM bank 17 is accessed via the sense amplifier 18. Here, the sense amplifier 18 plays a role as a cache memory or a high-speed buffer of the corresponding DRAM bank 17, and the address range to be accessed is
In this case, when data which is already temporarily stored is targeted, the sense amplifier 18 is accessed instead of the DRAM bank 17, thereby enabling high-speed DRAM access.

In the case of a DRAM access to the DRAM core unit 15, as described above, depending on whether or not desired data has already been temporarily stored in the sense amplifier 18, the DR is determined.
Whether or not to access the AM bank 17 is determined, and the access time varies greatly according to this. If the subsequent access is to data that is not currently held in the sense amplifier 18, the data temporarily stored in the sense amplifier 18 is transferred to the DRAM bank 17 in order to speed up the subsequent access. It may be more convenient to write it back to For this reason, DRAM
When the access request destination is the DRAM core unit 15, the control signal information indicates whether the DRAM bank 17 is accessed, whether the data of the sense amplifier 18 is written back to the DRAM bank 17, and the like. It is common to include information about the control of

In the three configuration examples of the prior art packet type memory bus 1002 described with reference to FIG. 17, as described above, the packet type memory bus 1002 has a very small number of signal lines, specifically, 10 to 10 signal lines. The feature is that it is composed of about 30 signal lines. Among the conventional technologies, Rambus technology is shown in FIG. 17A, and SyncLink technology is shown in FIG.
7 (b), the Medichannel technology has a configuration of the type shown in FIG. 17 (c), respectively. As described above, control signal information necessary for DRAM access is transmitted from the microprocessor 9 to the packet type DRAM 1 in such a small number of signal lines.
001 or exchange data between the microprocessor 9 and the packet-type DRAM 1001 by combining these pieces of information as packets and transmitting and receiving these packets over several cycles. Required. Further, in order to generate or decrypt such a packet, it is necessary to define a certain protocol.

FIG. 19 shows a packet type memory bus 1002.
The types of packets exchanged above are classified and shown. First, as shown in FIG. 19A, there are two types of packets transmitted from the microprocessor 9 to the packet type DRAM 1001, a request packet and a write data packet. The request packet is obtained by encoding the above-mentioned control signal information according to a certain protocol, and has a variable length. The write data packet contains write data of variable length size. On the other hand, as shown in FIG. 19B, there are two types of packets transmitted from the packet type DRAM 1001, a read data packet and an acknowledgment packet. The read data packet contains read data of variable length. The acknowledgment packet is generally of fixed length and may or may not be required, as described below.

When an acknowledgment packet is required, the microprocessor 9 serving as a bus master sends the packet type DRAM 1
When the DRAM access request 001 is requested, the microprocessor 9 cannot determine whether the packet-type DRAM 1001 can accept the requested DRAM access or can respond immediately. For example, the packet type DRAM 1
001 indicates that the DRAM core unit 15 is accessed during the refresh operation, and the case where the microprocessor 9 does not know whether or not the refresh is being performed corresponds to this. The data to be accessed is the sense amplifier 18.
Whether or not the data is temporarily stored in the microprocessor 9
Is not known. In such a case, the approval packet can accept the requested access (if approved) or not (if not approved)
If it cannot be accepted, it contains information indicating what operation the microprocessor 9 should take. Here, the content of the instruction is, for example, an instruction to re-access after a certain time or to wait for a certain time until the access is completed. On the other hand, when the acknowledgment packet is unnecessary, the microprocessor 9 manages all the internal states of the packet type DRAM 1001,
Therefore, when an access is requested, it is guaranteed that the request is always accepted. Rambus technology uses a method that requires an acknowledgment packet, and SyncLink technology uses a method that does not require an acknowledgment packet.

FIG. 20 shows three points (a) to (c) in FIG.
In each of the three configurations, how a packet is communicated on the packet type memory bus 1002 has been shown. In FIG. 20, as in FIG. 17, the microprocessor 9 as the bus master is located on the left side, and the packet type DRAM 1001 as the slave device is located on the right side.

In the configuration shown in FIG. 17A, all packets are exchanged on a bidirectional packet type memory bus 1002. Therefore, in FIG. 20A, the pattern of packet communication has been described for each of writing and reading. At the time of writing, first, a request packet is transmitted from the microprocessor 9 side, and then a write data packet is transmitted. The packet type DRAM 1001 transmits an acknowledgment packet, and when the acknowledgment is approved, the data is correctly written. At the time of reading, a request packet is transmitted from the microprocessor 9 side, and the packet type D
The RAM 1001 transmits an acknowledgment packet. If approved, the read data packet is transmitted from the packet type DRAM 1001 thereafter. As described above, in the above operation, it is possible to use no acknowledgment packet at all. In this case, only the acknowledgment packet is removed, and the remaining packet communication is the same as described here.

FIG. 20 (b) shows that in the configuration of FIG. 17 (b), each type of packet is
1 or the data bus 1002-2. The request packet is sent to the control bus 10
02-1, the write data packet, the read data packet, and the acknowledgment packet are transmitted on the data bus 1002-2.
Each is communicated above. Note that the acknowledgment packet may not be used in some cases.
No acknowledgment packet is used.

FIG. 20 (c) shows that in the configuration of FIG.
3 or the response bus 1002-4. The request packet and the write data packet are communicated on the request bus 1002-1, and the read data packet and the acknowledge packet are communicated on the response bus 1002-2. In some cases, the acknowledgment packet is not used.

FIG. 21 describes a processing procedure of the packet type DRAM 1001 when a request packet is received. FIG. 11A shows a case where an acknowledgment packet is required, and FIG. 10B shows a case where an acknowledgment packet is not required. In FIG. 21A, when a request packet is received, first, the memory device ID is collated to determine whether or not to respond to the request. If no response is received, the processing for this request packet is terminated. If it is determined that a response should be made, the request packet is decrypted to determine the access mode. Next, the DRAM core unit 15 or the memory control register unit 1 based on the determined access mode
A determination is made as to whether access to 6 is responsive as requested. An approval packet is assembled based on the determination result, and the approval packet is transmitted. The approval packet may be approved or unapproved, and the subsequent operation depends on either. In the case of approval, execute access. In the case of read access, a read data packet is transmitted, and a series of operations for the request packet is completed. In the case of write access, a series of operations on the request packet is completed after the access is completed. If not approved, prepare for access. Here, access preparation means
For example, during the refresh period, it is necessary to wait until the end of the refresh. When the address of the requested data does not match the address of the data temporarily stored in the sense amplifier 18, the DRAM bank 17 transfers the data to the sense amplifier 18.
And transferring the requested data. When the access preparation is completed, whether to proceed to access and perform the same operation as in the case of approval, or to end a series of operations for the request packet and wait for the request packet to be sent again Either way.

In FIG. 21B, since the acknowledgment packet is not required, the operation is very simple. After collation of the memory device ID, the request packet is decrypted to determine the access mode, the access is executed, the read data packet is transmitted as necessary, and a series of operations is completed.

FIG. 22 shows the case of SyncLink as an example.
The typical format of each packet is shown. FIG.
(A) to (c) are examples of a request packet, (d) is an example of an acknowledgment packet, and (e) is an example of a read data packet and write. In SyncLink, the control bus 1002-1 is 10
The bit / data bus 1002-2 has a 16-bit memory bus signal line configuration.

FIG. 22A shows a request packet for performing a write or read access to the DRAM core unit 15. In this case, the request packet is 1
The control bus 1002-1 of 0 bit is occupied for 4 cycles. In the first 1st cycle, device I is
D, the field of command 0 is designated by the remaining three bits. In the second cycle, a command 1 is specified by 3 bits, and a parameter 0 field is specified by 7 bits. In the remaining two cycles, the fields of parameters 1 and 2 are designated, respectively. Command field (command 0, command 1)
Specifies control signal information such as the operation type name, request destination, operation name, data length, and how to control the DRAM core unit 15 described with reference to FIG. The parameter fields (parameters 0, 1, and 2) specify addresses of data in the DRAM core unit 15.

FIG. 22B shows the memory control register section 16.
This shows a request packet for performing read access to the server. The 7-bit parameter 0 field in the second cycle specifies which memory control register 29 of the memory control register section 16 is to be accessed.

FIG. 22C shows the memory control register section 16.
5 shows a request packet for performing a write access to. 7-bit parameter 0 in the second cycle
The field specifies which memory control register 29 of the memory control register section 16 is accessed. The data to be written is indicated by using the parameters 1 and 2 fields in the third and fourth cycles.

As apparent from FIGS. 22A to 22C, the device ID field is common to all request packets, and the packet type DRAM 1001 to be responded to is uniquely determined by collating this part. Has become. Similarly, the fields of command 0 and command 1 are common to all request packets, and decoding this portion uniquely determines what access the packet DRAM 1001 should make. The parameter field specifies the address of the data in the DRAM core unit 15, the designation of the memory control register 29, the designation of the write data, and the like according to the requested access. Note that the device ID field does not always specify a single packet-type DRAM 1001. A plurality of packet-type DRAMs 1001 can be specified at the same time (called multicast), or a packet-type memory bus 10
In some cases, all the packet-type DRAMs 1001 connected to the H.02 may be specified (called broadcast) at the same time.

FIG. 22D shows an example of the format of the acknowledgment packet. Since there is no acknowledgment packet in the SyncLink technology, in this example, an acknowledgment packet of the Rambus technology is referred to,
The format when it is realized on 002-2 is shown.
The acknowledgment packet is transmitted for one cycle by the data bus 1002-2.
And acknowledgment of the request, that is, whether or not the request can be responded or whether there is any system error.

FIG. 22 (e) shows an example of the format of a write data packet and a read data packet. Both packets transmit and receive variable-length data by occupying the data bus 1002-2 for the required number of cycles.

In the initialization operation of the packet-type DRAM 1001, all the packet-type DRAMs 1001 connected to the packet-type memory bus 1002 can correctly receive packets on the packet-type memory bus 1002 or transmit packets. Make the initial settings required for Among them, each packet type DRAM 1
The setting of the memory device ID 001 is performed according to the following procedure.

As described above, the conventional packet type DRAM 1001 and packet type memory bus 1002 are
It implements the function of exchanging packets with each other based on a certain protocol. On the other hand, in a parallel processing system, a distributed processing system, and the like, a conventional technique of mutually communicating between a plurality of devices has been used for a long time. In these systems, a plurality of devices (or nodes) are connected by a bus or a network, and processing requests are mutually performed between these devices (nodes), or processing performed in parallel (or in parallel) In order to establish synchronization between them, packet communication and other mutual communication means are used.

There are many such prior arts,
One example is an Intel microprocessor.
PentiumPro's processor bus. Regarding this bus, a paper "AnOve published at COMPCON'96 (Spring)
rviewofthePentium (r) ProProcessorBus ", byNitinSarang
dhar, etal. (pp. 383) has the explanation. The PentiumPro processor bus is assumed to connect a plurality of PentiumPros, memory controllers, I / O controllers, and the like, and defines a physical / electrical connection method of these devices, a bus drive protocol, and the like. Also PentiumPro
The processor bus also defines standards for maintaining cache coherency between multiple PentiumPros. Here, the cache coherency means to manage the same data separately copied in the cache memory of each node so that each copy does not have a different value.

[0035]

The prior art packet type DRAM 1001 and packet type memory bus 100
2 realizes a function of mutually exchanging packets based on a certain protocol. In these prior arts, this function is provided by the DRA to the packet type DRAM 1001.
It is used only for M access, that is, write or read access to the DRAM core unit 15 and the memory control register unit 16 and control of initialization and refresh of the packet type DRAM 1001. However, the original application range of the function of realizing mutual communication by exchanging packets is not necessarily D
The present invention is not limited to RAM access and the like, and can be used as an intercommunication means for a wider purpose.

As another such purpose, a coprocessor having some kind of arithmetic processing function is used in a packet type DRAM 1.
001, and sends a packet from the bus master via the packet type memory bus 1002 to control the arithmetic processing function of the coprocessor to the bus master. In a packet type DRAM with a built-in coprocessor, an on-chip DRAM
, High-bandwidth, low-latency access is possible, so the on-board coprocessor has a high-bandwidth, low-latency access to the data stored in the large-capacity DRAM in the chip.
Performing low-latency DRAM access has the advantage that arithmetic processing can be executed efficiently. As described above, the prior art packet type DRAM 1001 does not consider the use of the packet communication function in addition to the limited use such as DRAM access or the like. There is a problem that it is insufficient as a memory bus technology for controlling the type DRAM.

On the other hand, if another conventional technique such as a processor bus in the parallel processing system described above is used, the external control of the arithmetic processing function mounted in the DRAM as described above can be easily realized. Seem at first glance. However, such a solution has the following problems.

The protocol of the processor bus and the like in the parallel processing system is much more complicated than the protocol of the packet type memory bus 1002. This is due to several causes. The first cause is that the processor bus is a bus on the assumption that a plurality of bus masters exist. For this reason, there is a possibility that a plurality of bus masters simultaneously issue requests to the processor bus, and it is necessary to control the exclusive right of the processor bus to determine which bus master can issue the request. Furthermore, flow control on the processor bus for avoiding deadlock and livelock is also required. In order to improve the efficiency of parallel processing and distributed processing, communication formats (packet formats) on many types of buses or communication patterns on many types of buses (what device Communication at the right time). In some cases, such as cache coherency, a mechanism for guaranteeing data consistency between a plurality of processors must be incorporated in the protocol. Since the protocol is complicated as described above, in these systems, there is a problem that mutual communication via the processor bus takes time.

On the other hand, arbitration of the memory bus is not necessary since there is generally only one bus master issuing a request in the memory bus. Also, since the number of supported packet formats is small, the protocol of the packet-type memory bus 1002 is relatively simple as described above. Further, if a bus master of the packet type memory bus 1002 such as a microprocessor or a memory controller manages the state of the packet type DRAM 1001,
As described above, since a protocol that does not require an acknowledgment packet can be realized, a very simple protocol can be realized. As described above, since the protocol is simple, the conventional packet type DRAM 10
01 and the packet-type memory bus 1002 can generate, communicate, and decode packets at high speed, and can perform mutual communication via the packet-type memory bus 1002 in a short time. have. How to reduce the delay time of DRAM access is a major design issue of DRAM along with the improvement of data bandwidth. Therefore, the above-mentioned features are used for the memory bus used when configuring a system using DRAM. It can be said that it is a property that fits very well.

As described above, a packet type DRAM using a conventional technique in a parallel processing system or a distributed processing system is used.
Implementing the packet memory 1001 and the packet-type memory bus 1002 causes a problem that it takes a long time to process a protocol and increases a delay time of a DRAM access. When realizing a packet-type DRAM with a built-in coprocessor that allows external read and write access as a normal packet-type DRAM 1001, access delay as the packet-type DRAM 1001 is realized in order to realize external control of the arithmetic processing function of the coprocessor. The increase in time is unacceptable. On the other hand, the conventional packet type DRAM 1001 and packet type memory bus 1002 cannot realize external control of the arithmetic processing function of the coprocessor mounted in the chip.

A first object of the present invention is to establish a flexible and high-performance packet-type DRAM with a built-in coprocessor that enables external control of the arithmetic processing function of a coprocessor mounted in a chip. Is to do.

It is a second object of the present invention to provide a spatially and physically efficient DRAM having a reduced number of external input / output signal terminals and a delay in DRAM access to an internal DRAM. An object of the present invention is to establish a technology of the packet type DRAM with a built-in coprocessor so as not to have a time overhead.

A third object of the present invention is to provide a packet type DRAM with a built-in coprocessor for controlling the arithmetic processing of a coprocessor mounted on a chip and accessing the DRAM of the DRAM mounted on the chip. An object of the present invention is to establish a technology of a packet type memory / coprocessor bus which can be performed from outside.

A fourth object of the present invention is to provide a spatially and temporally more efficient system in terms of both the number of signal lines constituting the bus and the bus timing at the time of accessing the DRAM, as compared with the conventional packet type memory bus. The purpose of the present invention is to establish a technique of the above-mentioned packet type memory / coprocessor bus which has no overhead.

A fifth object of the present invention is to mix and match an arbitrary number of packet-type DRAMs and an arbitrary number of packet-type DRAMs with a built-in coprocessor by using the packet-type DRAM with a built-in coprocessor and the packet-type memory / coprocessor bus. And a packet-type DRAM and a packet-type DR with a built-in coprocessor
A built-in coprocessor that allows the DRAM access to the AM and the control of the arithmetic processing function of the coprocessor to the coprocessor's built-in packet-type DRAM through the packet-type memory / coprocessor bus. The objective is to establish packet-type DRAM and packet-type memory / coprocessor bus technologies.

[0046]

Coprocessor Internal packet type memory LSI of the present invention According to an aspect of the memory unit, the control unit is configured from the interface unit and N (natural number) of the coprocessor unit, the outside of the chip by an external input and output terminal A packet type memory LSI with a built-in coprocessor connected to a packet type memory / coprocessor bus of the present invention, wherein a memory device ID is set for a memory unit and a coprocessor device ID is set for each of N coprocessors. Then, the memory device ID and the coprocessor device ID are stored in the chip, and the memory device ID or the coprocessor device ID is stored in the packet type memory /
It is possible to uniquely identify which memory unit or coprocessor unit is to be specified between any memory unit and any coprocessor unit in all coprocessor packet-type memory LSIs connected to the coprocessor bus. Characterized in that:

The packet type memory with a built-in coprocessor according to the present invention comprises an LSI memory unit, a control unit, an interface unit,
The memory unit includes a memory core unit and a memory control register unit, and includes N (natural number) coprocessor units .
The coprocessor unit includes an arithmetic core unit, an arithmetic control unit, and an arithmetic control register unit .
Has a predetermined number of the memory control register, the arithmetic control register unit having a second predetermined number of operation control register, the control unit and the memory unit are connected by an internal memory data bus, and control the N coprocessor unit A coprocessor built-in packet type memory LSI connected to a packet type memory / coprocessor bus outside the chip by external input / output terminals having an arbitrary number of signal terminals, each of which is connected by an internal coprocessor data bus, A memory device ID for each of the N coprocessors, and a coprocessor device ID for each of the N coprocessors. The coprocessor device ID is the number of all coprocessors connected to the packet type memory / coprocessor bus. Which is capable of uniquely identifying which memory unit or coprocessor unit is specified between an arbitrary memory unit and an arbitrary coprocessor unit in the packet type memory LSI with a built-in coprocessor. .

The packet type memory LSI with a built-in coprocessor according to the present invention is characterized in that the memory core is configured using a dynamic random access memory (DRAM).

The memory system according to the present invention comprises one bus master and the above-described packet type LSI with a built- in coprocessor.
And a packet-type memory / coprocessor bus connecting them, and
A type memory / coprocessor bus is a single bus master type bus that does not require arbitration of the bus ownership of the packet type memory / coprocessor bus when the bus master transmits a packet to the packet type memory / coprocessor bus. And a control bus which is a unidirectional bus from the bus master to the packet type memory LSI with a built-in coprocessor, and a data bus which is a bidirectional bus between the bus master and the packet type memory LSI with a coprocessor. It is characterized by having as a part thereof.

The memory system of the present invention comprises one bus master and the above-mentioned packet type LSI with a built- in coprocessor.
And a packet-type memory / coprocessor bus connecting them, and
A type memory / coprocessor bus is a single bus master type bus that does not require arbitration of the bus ownership of the packet type memory / coprocessor bus when the bus master transmits a packet to the packet type memory / coprocessor bus. A request bus which is a unidirectional bus from the bus master to the packet type memory LSI with built-in coprocessor, and a response bus which is a unidirectional bus from the packet type memory LSI with built-in coprocessor to the bus master. It is characterized by having as a part thereof.

The memory system of the present invention, and one bus master, the aforementioned coprocessor internal packet type LSI
When, a memory system comprising a packet type memory / coprocessor bus for connecting these, the packet
A type memory / coprocessor bus is a single bus master type bus that does not require arbitration of the bus ownership of the packet type memory / coprocessor bus when the bus master transmits a packet to the packet type memory / coprocessor bus. Further, the bus master has two packet types, a request packet and a write data packet, as packets that can be transmitted to the packet type memory / coprocessor bus.
A memory system wherein the SI has one packet type of a read data packet as a packet that can be transmitted to a packet type memory / coprocessor bus.

A memory system according to the present invention comprises a bus master, a packet type LSI with a built- in coprocessor according to claim 2 or 3 , and a packet type memory for connecting these.
/ Coprocessor bus with a memory system
This packet-type memory / coprocessor bus is a single bus that does not need to arbitrate the bus occupancy of the packet-type memory / coprocessor bus when the bus master transmits a packet to the packet-type memory / coprocessor bus. A bus memory having two packet types, a request packet and a write data packet, which can be transmitted to the packet type memory / coprocessor bus by the bus master. Has two packet types, a read data packet and an acknowledgment packet, as packets that can be transmitted to the packet type memory / coprocessor bus .

In the memory system of the present invention , the request packet has a device ID field, a command field, and a parameter field, and the device ID field indicates that the request packet is an arbitrary one connected to the packet type memory / coprocessor bus. The command field specifies one or more memory units or coprocessor units in the coprocessor built-in packet type memory LSI, and the command field indicates the processing requested by the request packet. The content is indicated, and the parameter field is for giving a parameter necessary for executing a process requested by the request packet.

The memory system of the present invention has a device ID
The field length of the field is fixed regardless of whether the device ID field specifies the memory unit or the coprocessor unit. It has a fixed length regardless of whether a processor section is specified.

The memory system of the present invention has a device ID
The field length of the field is fixed regardless of whether the device ID field specifies the memory unit or the coprocessor unit, and the command field specifies whether the device ID field specifies the memory unit. It is characterized in that the field length differs depending on whether the processor section is designated.

In the memory system of the present invention, the interface unit receives a request packet from a packet type memory / coprocessor bus via an external input / output terminal, and the control unit stores the device ID field in the request packet and the chip. The stored memory device ID and the plurality of coprocessor device IDs are collated, and the control unit is included in the request packet only when the device ID field specifies one of the memory device ID and the coprocessor device ID. A command field is decoded to instruct a memory unit or a coprocessor unit specified by the device ID field to execute a process requested by a request packet.

According to the memory system of the present invention, a memory device ID register is provided for a memory unit, and a coprocessor device ID register is provided for an arbitrary number of coprocessors. ID device and the coprocessor device ID register.
A memory / coprocessor device ID collation circuit connected to the D register and the coprocessor device ID register, wherein the memory / coprocessor device ID collation circuit performs collation between the device ID field of the request packet and the memory device ID register; , The collation between the device ID field of the request packet and the respective coprocessor device ID registers is performed in parallel, and it is determined whether the device ID field specifies any memory device ID or coprocessor device ID. It is characterized by the following.

In the memory system of the present invention , the memory device ID register is provided as one of the memory control registers, and the coprocessor device ID register is provided as one of the operation control registers in the memory control register section and the operation control register section, respectively. It is characterized by.

According to the memory system of the present invention, the decoding method of the command field in the control unit is changed according to whether the device ID field of the request packet specifies the memory unit or the coprocessor unit. A command field having the same bit pattern represents a request for a different process depending on which one is targeted.

According to the memory system of the present invention, when the device ID field in the request packet specifies the memory device ID, the control unit decodes the command field of the request packet, and the control unit decodes the command field according to the decoding result. Designates a write access or a read access to a memory core unit or a memory control register unit in the memory unit to the memory unit.

In the memory system of the present invention, when the device ID field in the request packet indicates the memory device ID, the control unit decodes the command field of the request packet, and in accordance with the decoding result, the control unit Determines whether the memory unit can perform the write access or the read access requested by the request packet, and transmits the determination result as an acknowledgment packet to the packet-type memory / coprocessor bus.
When the memory unit is executable, the control unit instructs the memory unit to perform write access or read access to the memory core unit or the memory control register unit in the memory unit.

According to the memory system of the present invention, when the device ID field in the request packet indicates one of the coprocessor sections , the control section decodes the command field, and in accordance with the decoding result, the control section decodes the command field. Instructs the coprocessor unit to perform either write access or read access to the operation control register unit in the coprocessor unit.

In the memory system according to the present invention, when the device ID field in the request packet indicates one of the coprocessor sections, the control section decodes the command field, and in accordance with the decoding result, the control section decodes the command field. Determines whether the coprocessor unit can perform the write access or the read access requested by the request packet, and transmits the result of the determination as an acknowledgment packet to the packet-type memory / coprocessor bus. Wherein, when the coprocessor unit is executable, the control unit instructs the coprocessor unit to perform one of a write access and a read access to the operation control register unit in the coprocessor unit. I do.

According to the memory system of the present invention, when the device ID field in the request packet specifies a memory device ID, the control unit decodes the command field of the request packet, and the control unit decodes the command field according to the decoding result. Instructs the memory unit to perform a write access or a read access to the memory core unit or the memory control register unit in the memory unit. When the device ID field in the request packet indicates one of the coprocessor units, the control is performed. Unit decodes the command field, and in accordance with the decoding result, the control unit determines whether the coprocessor unit can perform the write access or the read access requested by the request packet,
After transmitting the determination result as an acknowledgment packet to the packet-type memory / coprocessor bus, if the coprocessor unit is executable, the control unit writes the data into the operation control register unit in the coprocessor unit. One of access and read access is instructed to the coprocessor unit.

According to the memory system of the present invention, when the device ID field in the request packet specifies the memory device ID, the control unit decodes the command field of the request packet, and in accordance with the decoding result, the control unit Instructs the memory unit to perform write access or read access to the memory core unit or the memory control register unit in the memory unit, and when the device ID field in the request packet indicates one of an arbitrary number of coprocessor units. When the control unit decodes the command field and the decoding result indicates write access to the operation control register, the control unit determines whether the write access can be performed by the coprocessor unit. and, a packet type memory / coprocessor the determination result as acknowledgment packet After transmitting to the bus, if the coprocessor unit is executable, the control unit instructs the coprocessor unit to perform write access to the arithmetic control register unit in the coprocessor unit, and the decoding result is output. When instructing read access to the arithmetic control register, the control unit instructs the coprocessor unit to perform read access to the arithmetic control register unit in the coprocessor unit.

In the memory system of the present invention, in the write access to the memory core unit, the memory unit receives the write data packet received from the packet type memory / coprocessor bus via the interface unit via the control unit, It is characterized in that the data is written into the memory core unit using the memory address specified by the parameter field in the request packet.

According to the memory system of the present invention, in the write access to the memory control register,
A write data packet received from a packet type memory / coprocessor bus via an interface unit is received via a control unit, and is written into a memory control register specified by a parameter field in the request packet.

In the memory system of the present invention, in the write access to the memory control register,
By receiving the write data included in a part of the parameter field in the request packet via the control unit,
It is characterized in that a part of a parameter field in the request packet is written into a specified memory control register.

In the memory system of the present invention, in the read access to the memory core unit and the memory control register unit, the memory unit transmits the read data from the memory core unit or the memory control register unit in accordance with the specification of the parameter field in the request packet. The read data is transferred to the control unit, the control unit generates a read data packet, and the interface unit transmits the read data packet to the packet-type memory / coprocessor bus via the external input / output terminal.

In the memory system of the present invention, in the write access to the operation control register unit, the coprocessor unit writes the write data packet received from the packet type memory / coprocessor bus via the interface unit via the control unit. It is characterized in that it is received and written into an operation control register specified by a parameter field in the request packet.

In the memory system of the present invention, in the write access to the operation control register unit, the coprocessor unit receives, via the control unit, write data included in a part of the parameter field in the request packet. Then, the data is written into the operation control register specified by a part of the parameter field in the request packet.

In the memory system of the present invention, in the read access to the operation control register unit, the coprocessor unit passes data read from the operation control register specified by the parameter field in the request packet to the control unit. The control unit generates a read data packet,
The interface unit transmits a read data packet to a packet type memory / coprocessor bus via an external input / output terminal.

In the memory system according to the present invention, the packet memory with a built-in coprocessor transmits a read data packet to the packet type memory / coprocessor bus at the time of read access to the memory core unit, the memory control register unit, and the operation control register unit. The bus cycle for transmitting the acknowledgment packet to the packet-type memory / coprocessor bus at the time of write access to the operation control register unit is the same bus timing as the bus cycle for receiving the request packet. It is characterized by the following.

In the memory system of the present invention, an operation start register is provided in the operation control register section. The operation start register is an operation control register which is referred to when the coprocessor section starts execution of the operation processing. When write access to the operation start register is instructed by the command field and the parameter field of the packet, the write data included in the parameter field of the request packet or the data of the write data packet is used as the program pointer, and the program pointer is used. Is executed.

In the memory system of the present invention, when write access to the operation start register is instructed, information indicating whether execution of the instructed operation can be started is transmitted as an acknowledgment packet to the packet type memory / coprocessor bus. It is characterized by transmitting.

In the memory system according to the present invention, an operation result register is provided as one of the operation control registers. When the read access to the operation result register is instructed by the command field and the parameter field, the data stored in the operation result register is generated as a read data packet.

When a read access to the operation result register is instructed, the memory system of the present invention transmits, as an acknowledgment packet, information indicating whether or not the result of the operation processing has already been written to the specified operation result register. It is characterized by transmitting to a type memory / coprocessor bus.

When a read access to the operation result register is instructed, the memory system of the present invention stores information indicating whether or not the result of the operation processing has already been written in the indicated operation result register in the read data packet. And transmitting the packet to the packet type memory / coprocessor bus.

In the memory system of the present invention, after the parameters necessary for the coprocessor unit to execute the arithmetic processing are set in the arithmetic control register by the write access, the coprocessor is set by the write access to the arithmetic start register. The coprocessor unit starts arithmetic processing, and executes the arithmetic processing with reference to the arithmetic control register.

In the memory system of the present invention, the coprocessor unit writes the result of the operation processing to an arbitrary number of operation control registers, and a part of the operation result is successfully read by read access to the operation result register. Later, the remaining portion of the operation result is read by read access to the operation control register.

The memory system of the present invention uses a part of the operation control register for the purpose of holding an intermediate result when the coprocessor unit executes the operation process during the execution of the operation process. Features.

[0082] coprocessor internal packet type memory LSI of the present invention, the external select-in terminal and the external select-out terminal is provided as an external input and output terminals, the memory unit and N
An internal select-in terminal and an internal select-out terminal are provided in all of the coprocessor sections, and between the memory section and the N coprocessor sections, an internal select-out terminal of a certain memory section or a coprocessor section and another memory section or another By connecting the internal select-in terminals of the coprocessor unit in any order, a one-dimensional memory unit-coprocessor unit chain is formed, and the external select-in terminal and the memory unit or the first memory unit of the coprocessor unit chain are connected. The internal select-in terminal of the processor unit is connected, and the external select-out terminal is connected to the last memory unit of the memory-coprocessor unit chain or the internal select-out terminal of the coprocessor unit.

The method of controlling a packet-type memory LSI with a built-in coprocessor according to the present invention includes, as an initialization operation, an operation of setting a memory device ID or a coprocessor device ID to a predetermined same initial state value, An operation is performed to output a logical value 0 from the select-out terminal. After the initialization operation, the memory device ID or the coprocessor device ID is set to the initial state value.
The memory unit or coprocessor unit to which is set is written access to the memory unit or coprocessor unit while the logical value 0 is input from the internal select-in terminal of the memory unit or coprocessor unit. Ignored, and outputs a logical value 0 from the internal select-out terminal, and when a logical value 1 is input from the internal select-in terminal of the memory unit or the coprocessor unit, the memory unit or the coprocessor unit In response to the write access to the internal memory, the memory device ID register or the coprocessor device ID register is accessed for write access to the memory device ID or the coprocessor device ID specified by the parameter field in the request packet, and the internal select out is performed. Outputting a logical value of 1 from a terminal. .

The memory system of the present invention has a built-in coprocessor connected to a packet type memory / coprocessor bus.
External select out terminal of the packet type memory LSI together with the external select-in terminal connected to the one-dimensional chain constitutes a coprocessor internal packet type memory LSI chain,
The bus master is provided with an external select-in terminal and an external select-out terminal, and the external select-out terminal of the bus master is connected to the external select-in terminal of the coprocessor built-in packet type memory LSI at the head of the coprocessor built-in packet type memory LSI. The external select-out terminal of the last packet-type memory LSI with a coprocessor and the external select-in terminal of a bus master are connected.

According to the control method of the memory system of the present invention, the initialization operation is performed on all the packet type memory LSIs with built-in coprocessors, and all the memory device IDs and all the coprocessor device IDs are set to the initial state values. After setting all external select-out terminals and all internal select-out terminals to logical value 0, the bus master drives its own external select-out terminal to logical value 1 and sets the initial state value in the device ID field. By transmitting a write packet in which the specified new memory device ID or the coprocessor device ID is specified in the parameter field, the memory section in the coprocessor built-in packet type memory LSI at the head of the coprocessor built-in packet type memory LSI chain can be transmitted. The first memory section or A memory device ID or a coprocessor device ID is set for the processor unit, and subsequently, the logical value 1 is set to the memory unit or the coprocessor unit and the coprocessor unit through the memory unit-coprocessor unit chain and the coprocessor built-in packet type memory LSI chain. In response to the sequential transfer between packet-type memory LSIs with a built-in processor, the bus master transmits a write packet in which the initial state value is specified in the device ID field and a new memory device ID or coprocessor device ID is specified in the parameter field. Then, by sequentially setting the memory device ID or the coprocessor device ID of the memory unit or the coprocessor unit, all the packet type memory LSIs with built-in coprocessors connected to the packet type memory / coprocessor bus are set. A memory device ID and a coprocessor device ID that can uniquely identify which memory unit or coprocessor unit is specified between any memory unit and any coprocessor unit are set in the memory unit and coprocessor unit. It is characterized by doing.

In the packet type memory LSI with a built-in coprocessor of the present invention, device definition registers are provided as a memory control register and an operation control register, respectively, and the device definition information is stored in advance in the device definition register. It is information indicating which of the coprocessor units is.

In the method of controlling a packet type memory LSI with a built-in coprocessor according to the present invention, a bus master specifies a device ID and reads a device definition register in a memory control register or an operation control register to read device definition information. Upon receipt, the bus master recognizes whether the specified device ID is assigned to the memory unit or the coprocessor unit.

In the control method of the packet type memory LSI with a built-in coprocessor according to the present invention, the request packet for requesting the reading of the device definition register depends on whether the reading operation is directed to the memory section or the coprocessor section. However, only the specification of the device ID field is a different request packet.

The packet type memory LSI with a built-in coprocessor according to the present invention has a function definition register as an operation control register, and stores a function definition code in advance in the function definition register. It is a classified code.

According to the control method of the packet type memory LSI with a built-in coprocessor of the present invention, the bus master receives the function definition code by designating the device ID and reading the function definition register in the operation control register. The bus master recognizes the arithmetic processing function of the coprocessor corresponding to the designated device ID.

In the packet-type memory LSI with a built-in coprocessor of the present invention, a memory device ID and a coprocessor device ID are given to a memory portion and a coprocessor portion, respectively. Memory device ID or coprocessor device ID according to the ID field in the request packet
By specifying, the processing request to the memory unit and the processing request to the coprocessor unit are distinguished.

The packet-type memory / coprocessor bus of the present invention uses a single bus master configuration, thereby eliminating the need to control the occupation of the bus and simplifying the setting of bus timing and the like.

The packet type memory / coprocessor bus and coprocessor built-in packet type memory LSI of the present invention
The bus master is the coprocessor device I of the coprocessor section.
By performing write access or read access by designating D, external control of the coprocessor unit is realized.

[0094]

FIG. 1 shows an embodiment of a configuration of a packet type DRAM 1 with a built-in coprocessor according to the present invention.

In FIG. 1, the packet type DRAM 1 with a built-in coprocessor includes a memory unit 11, a control unit 12, an interface unit 13, and a coprocessor unit 14. The memory unit 11 includes a DRAM core unit 15 and a memory control register unit 16, and the DRAM core unit 15 includes a plurality of DRAM banks 17 and a plurality of sense amplifiers 18 corresponding thereto. The memory control register section 16 has a plurality of memory control registers 29 therein. The control unit 12 includes a memory / operation control logic circuit 19,
Control signal register 20, write data register 21,
It comprises a read data register 22 and a memory / coprocessor device ID verification circuit 23. There are three types of input / output signal terminals of the control unit 12, a control signal terminal 24 and a write data terminal 25 which are input terminals, and a read data terminal 26 which is an output terminal. Connected. The interface unit 13 is connected to an external input / output terminal 5 composed of a plurality of signal terminals. The memory unit 11 and the control unit 12 are connected by an internal memory data bus 27 which is a bidirectional bus. The coprocessor unit 14 includes an arithmetic core unit 30,
It comprises an arithmetic control unit 31 and an arithmetic control register unit 32. The operation control register section 32 has a plurality of operation control registers 33 therein. The coprocessor section 14 is connected to the control section 12 by an internal coprocessor data bus 28 which is a bidirectional bus.

In the present invention, the coprocessor unit 14 in the packet type DRAM 1 with a built-in coprocessor has a plurality of coprocessors.
Although a single coprocessor unit 14 can be mounted, the configuration of the embodiment of FIG. 1 shows a case where one coprocessor unit 14 is mounted for simplicity.

In FIG. 1, the memory control register section 16 in the memory section 11 and the operation control register section 32 in the coprocessor section 14 are connected to a memory / coprocessor device ID collation circuit 23, respectively. This is, as will be described later, connected to the control signal register 2
0, the designation of the device ID given to the memory / coprocessor device ID comparison circuit 23, the memory device ID stored in a certain memory control register 29 in the memory control register 16, and the device ID in the operation control register 32. By comparing with the coprocessor device ID stored in the arithmetic control register 33, it is determined whether or not the processing request received at the external input / output terminal 5 is to the memory unit 11 or the coprocessor unit 14. It is for doing. Here, the memory device ID and the coprocessor device ID are allocated to the respective memory units 11 and the coprocessor unit 14 one by one.

FIG. 2 is a block diagram showing an embodiment of the configuration of the packet type DRAM 1 and the packet type memory / coprocessor bus 2 based on the present invention. In the figure, a packet type DRAM 1 with a built-in coprocessor is shown.
3 embodiments of the configuration of the interface unit 13 and the configuration of the packet type memory / coprocessor bus 2
This is shown in the drawings from FIG. 2 (a) to FIG. 2 (c). In the packet type memory / coprocessor bus 2 of the present invention,
The number of bus masters on the packet-type memory / coprocessor bus 2 is limited to only one, and the plurality of packet-type DRAMs 1 with a built-in coprocessor connected to the packet-type memory / coprocessor bus 2 all work as slave devices. In general, a bus master is a device that can occupy the bus and issue a request to the bus. Devices that do not emit By limiting the number of bus masters to one and all the devices on the remaining buses as slave devices, the protocol of the packet type memory / coprocessor bus 2 can be simplified. In FIG. 2, the microprocessor 9 is connected as a bus master of the packet-type memory / coprocessor bus 2. However, other bus masters, such as a memory controller, a signal processor, a graphics accelerator, and other ASICs, are actually used. May be.

In the configuration shown in FIG. 2A, similarly to FIG.
It comprises a control unit 12, an interface unit 13, and a coprocessor unit 14. A control signal terminal 24, a write data terminal 25, and a read data terminal 26, which are input / output terminals of the control unit 12, are all connected to the interface unit 13. The interface unit 13 is connected via an external input / output terminal 5 to the packet type memory / coprocessor bus 2 connecting the microprocessor 9 and a plurality of packet type DRAMs 1 with a built-in coprocessor. The packet type memory / coprocessor bus 2 is a bidirectional bus and has an arbitrary number of signal lines.

In the configuration shown in FIG. 2B, the interface unit 13 comprises a control interface unit 13-1 and a data interface unit 13-2. The control signal terminal 24 of the control unit 12 is connected to the control interface unit 13-1, and the write data terminal 25 and the read data terminal 26 are connected to the data interface unit 13-2. In this configuration, the packet type memory / coprocessor bus 2 has a control bus 2-1 having an arbitrary number of signal lines.
And a data bus 2-2. The control interface unit 13-1 is connected to the control bus 2-1 and the data interface unit 13-2 is connected to the data bus 2-2 via the external input / output terminal 5. The control bus 2-1 is a unidirectional bus from the microprocessor 9 to a plurality of packet type DRAMs 1 with built-in coprocessors, and the data bus 2-2 is a bidirectional bus.

In the configuration shown in FIG. 2C, the interface unit 13 includes a request interface unit 13-3 and a response interface unit 13-4. The control signal terminal 24 and the write data terminal 25 of the control unit 12 are connected to the request interface unit 13-3, and the read data terminal 26 is connected to the response interface unit 13-4. In this configuration,
The packet type memory / coprocessor bus 2 includes a request bus 2-3 and an response bus 2-4 each having an arbitrary number of signal lines. The request interface unit 13-3 is connected to the request bus 2-3, and the response interface unit 13-4 is connected to the response bus 2-4 via the external input / output terminal 5. The request bus 2-3 is a unidirectional bus from the microprocessor 9 to the plurality of packet type DRAMs 1 with a built-in coprocessor, and the response bus 2-4 is a unidirectional bus in the opposite direction.

A memory device ID and a coprocessor device ID are respectively assigned to all memory units 11 and coprocessor units 14 in all the packet type DRAMs 1 with built-in coprocessors connected to the packet type memory / coprocessor bus 2 of the present invention. Has been given. In the present invention, as will be described later, these memory device IDs or coprocessor device IDs are assigned to the respective memory units 11 or the coprocessor unit 14 by a method such as assigning different numbers to the respective memory devices. Have been. By specifying a certain memory device ID (or coprocessor device ID), all the memory units 1 in all the packet type DRAMs 1 with built-in coprocessors connected to the packet type memory / coprocessor bus 2 are designated.
1 and one of the coprocessors 14, one memory 1
1 (or the coprocessor unit 14) can be specified.

In the packet type memory / coprocessor bus 2 of the present invention, the number of signal lines constituting the packet type memory / coprocessor bus 2 is equal to or smaller than that of the conventional packet type memory bus 1002. One of the purposes is to use the number of signal lines. For this reason, the packet type memory / coprocessor bus 2 of the present invention is characterized in that it has a very small number of signal lines, specifically, about 10 to 30 signal lines. As described above, in order to exchange necessary information between such a small number of signal lines between the microprocessor 9 of the bus master and the packet-type DRAM 1 with a built-in coprocessor, the information is collected into a packet. A mechanism for exchanging these packets over several cycles is required. Further, in order to generate or decrypt such a packet, it is necessary to define a certain protocol.

FIG. 3 is an explanatory diagram categorizing and showing embodiments of the types of packets exchanged on the packet type memory / coprocessor bus 2 of the present invention. First, FIG.
As shown in (1), there are two types of packets transmitted from the microprocessor 9 to the packet type DRAM 1 with a built-in coprocessor: a request packet and a write data packet. The request packet is obtained by encoding an instruction relating to a process requested to the packet type DRAM 1 with a built-in coprocessor according to a predetermined protocol, and has a variable length. The write data packet contains write data of variable length size. On the other hand, as shown in FIG. 3B, packets transmitted from the packet-type DRAM 1 with a built-in coprocessor are of two types: a read data packet and an acknowledgment packet. The read data packet contains read data of variable length. The acknowledgment packet is generally of a fixed length and may or may not be required depending on the embodiment, as described below.

FIG. 4 shows a packet type memory /
FIG. 3 is an explanatory diagram for describing an embodiment of a method of packet communication in a coprocessor bus 2. In FIG. 4, FIG.
Similarly, a description is given of a case where the microprocessor 9 as the bus master is located on the left side and the packet type DRAM 1 with a built-in coprocessor as the slave device is located on the right side. Indicates whether communication will take place. FIGS. 4A to 4C respectively correspond to the configurations of the three packet type memory / coprocessor buses 2 of FIGS. 2A to 2C.

As described in FIG. 4A, FIG.
In the configuration (a), all packets are exchanged on the bidirectional packet type memory / coprocessor bus 2.

As described in FIG. 4B, FIG.
In the configuration of (b), the request packet is transmitted to the control bus 2-
At 1, the write data packet, read data packet, and acknowledgment packet are communicated on data bus 2-2, respectively.

As described in FIG. 4C, FIG.
In the configuration (c), the request packet and the write data packet are communicated on the request bus 2-3, and the read data packet and the acknowledgment packet are communicated on the response bus 2-4.

FIG. 5 is an explanatory diagram showing an embodiment of the contents of the processing requested by the request packet for the packet type DRAM 1 with a built-in coprocessor according to the present invention. The processing types are divided into memory access to the memory unit 11, coprocessor access to the coprocessor unit 14, initialization, and refresh. In each case, the request source is the bus master. There are two types of memory access, one for the DRAM core unit 15 and one for the memory control register unit 16. In either case, there are two types of commands, write and read. In the case of coprocessor access, the request destination is the operation control register 3
The command is of two types, write and read. The initialization is required for the memory control register unit 16 and the operation control register unit 32. The refresh is an object of the processing request by the DRAM core unit 15. In each case, the request source is the bus master.

FIG. 6 is an explanatory diagram showing an embodiment of a configuration of a packet format of a packet communicated in the packet type memory / coprocessor bus 2 according to the present invention. In this embodiment, as the configuration of the packet type memory / coprocessor bus 2, the case where the configuration of the embodiment having the control bus 2-1 and the data bus 2-2 shown in FIG. 2B is used. Is shown. FIG. 2 particularly shows a case where the number of signal lines of the control bus 2-1 and the data bus 2-2 is 10 and 16, respectively. FIG. 6 (a)
(D) is a request packet, (e) is an acknowledgment packet,
(F) is an embodiment of the configuration of the packet format of the read data packet and the write data packet.

FIG. 6A shows an embodiment of a packet format of a request packet when writing or reading access to the DRAM core unit 15 is performed. In this embodiment, the request packet occupies the 10-bit control bus 2-1 for four cycles. In the first cycle, the device ID is specified by 7 bits, and the command 0 field is specified by the remaining 3 bits. In the second cycle, a command 1 is specified by 3 bits, and a parameter 0 field is specified by 7 bits. In the remaining two cycles, the fields of parameters 1 and 2 are designated, respectively.

FIG. 6B shows an embodiment of a packet format of a request packet when writing access or reading access to the memory control register section 16 is performed. In this embodiment, the request packet is 1
The control bus 2-1 of 0 bit is occupied for two cycles. In the first cycle, the device ID is specified by 7 bits, and the command 0 field is specified by the remaining 3 bits. In the second cycle, a command 1 is specified by 3 bits, and a parameter 0 field is specified by 7 bits.

When performing read access or write access to the operation control register section 32, the same packet format of the request packet as in FIG. 6B is used, or the command field (command 0,
Another embodiment having a different field length in 1) can be used. FIG. 6C shows an embodiment of a packet format of a request packet when performing write access or read access to the operation control register unit 32 in the latter case. In this case, the request packet occupies the 10-bit control bus 2-1 for two cycles.
In the first cycle, the device ID is specified by 7 bits, and the command 0 field is specified by the remaining 3 bits. 2
In the cycle, a command 1 is specified by 2 bits, and a parameter 0 field is specified by 8 bits.

FIG. 6D shows another embodiment of the packet format of the request packet when performing write access to the memory control register section 16 or the arithmetic control register section 32. In this embodiment,
The request packet occupies the 10-bit control bus 2-1 for four cycles. In the first cycle, the device ID is specified by 7 bits, and the command 0 field is specified by the remaining 3 bits. In the second cycle, command 1 with 3 bits,
The field of parameter 0 is specified by 7 bits. In the remaining two cycles, the fields of parameters 1 and 2 are designated, respectively.

In the packet format of the request packet shown in FIGS. 6A to 6D, the device ID field contains a plurality of coprocessor built-in packets connected to the packet type memory / coprocessor bus 2. Memory section 11 and any specific memory section 1 of coprocessor section 14 mounted on any packet type DRAM 1 with a built-in coprocessor in DRAM 1
1 or a field for designating a request to the coprocessor unit 14 for processing. The device ID specifies one memory unit 11 and coprocessor unit 14 as a target of a processing request, or a plurality of memory units 11 and coprocessor units 14 (multicast), or all memory units 11 and Processor unit 14
(Broadcast) can be specified at the same time.
Next, the command fields (commands 0, 1) indicate the specific contents of the processing requested by the request packet. Details of the embodiment of the processing content will be described later. Finally, the parameter fields (parameters 0, 1, and 2) are fields that provide parameters necessary for executing the processing requested by the request packet.

In the embodiment of the packet format of the request packet of the packet type memory / coprocessor bus 2 according to the present invention, as shown in FIGS. The memory unit 11 or the coprocessor unit 14 to which a response is made is uniquely determined by comparing this part with the packet format of the packet. FIG. 6 (a)
In the embodiments (a) to (d), since the device ID field is 7 bits, 128 different values from 0 to 127 can be designated. As an embodiment of a method of designating the memory unit 11 and the coprocessor unit 14, for example, 64 values from 0 to 63 are used to designate any one of the memory unit 11 or the coprocessor unit 14. A designation method such as using 64 values from to 127 for multicasting or broadcasting is possible. In this embodiment, the memory device ID and the coprocessor device ID take values from 0 to 63, and all the memories in all the coprocessor built-in packet type DRAMs 1 connectable to the packet type memory / coprocessor bus 2 The sum of the numbers of the units 11 and the coprocessor units 14 is up to 64.

In the embodiment of the packet format of the request packet of the packet type memory / coprocessor bus 2 according to the present invention, the command fields (commands 0 and 1) are described with reference to the request packets of FIGS. And the case where the field length is different depending on whether the target of the processing is the memory unit 11 or the coprocessor unit 14 as in the embodiment of the packet format of
Two embodiments can be adopted in the case where the field length is constant regardless of whether the processing request is for the memory unit 11 or the coprocessor unit 14.

FIG. 6E shows an embodiment of the packet format of the acknowledgment packet according to the present invention. The acknowledgment packet is transmitted on the 16-bit data bus 2-2.
Occupy during cycle. The first two bits specify the rejection field. The remaining 14 bits are used or not used as a parameter field. The acknowledgment field indicates whether or not the requested process is approved, that is, whether or not the request can be responded, or whether or not there is any system error. When the parameter field is used, the microprocessor 9 serving as a bus master is used to indicate parameters necessary for processing the acknowledgment packet.

FIG. 6 (f) shows an example of the format of a write data packet and a read data packet. Both packets exchange variable-length data by occupying the data bus 2-2 for the required number of cycles.

FIG. 7 shows the device ID field of the request packet, the memory device ID and the coprocessor held in the coprocessor built-in packet type DRAM 1 in the embodiment of the packet type DRAM 1 with built-in coprocessor according to the present invention of FIG. FIG. 4 is an explanatory diagram for describing an embodiment of a configuration of a memory / coprocessor device ID verification circuit 23 that verifies a device ID. In FIG.
The memory / coprocessor device ID verification circuit 23 includes a plurality of device ID verification circuits 52. The device ID matching circuit 52 compares the input device ID field with the input memory device ID or coprocessor device ID, and the device ID field specifies the memory device ID or coprocessor device ID. This is a circuit for determining whether or not the operation is performed. FIG. 7 shows an embodiment in which the packet type DRAM 1 with a built-in coprocessor has one memory unit 11 and two coprocessor units 14, and thus has three device ID matching circuits 52. In the figure, the device ID field is input from the control signal register 20 to each device ID matching circuit 52. The memory device ID or the coprocessor device ID is
The data is input from the D register 50 or the coprocessor device ID register 51 to each device ID matching circuit 52. In the present embodiment, the memory device ID register 50 and the coprocessor device ID register 51 are provided in the memory control register unit 16 or the operation control register unit 32 as the memory control register 29 or the operation control register 33, respectively. Each device ID
The matching circuit 52 outputs the matching result to the memory / operation control logic circuit 19, respectively. Here, the device ID collation circuit 52 may be the same as the conventional memory device ID collation circuit, and can be constituted only by a known technique.

Next, referring to FIGS. 1 and 7, an embodiment of a method of controlling a device ID field collating operation and a command field decoding operation when the packet DRAM 1 with a built-in coprocessor receives a request packet will be described. explain. The request packet is input from the external input / output terminal 5, applied to the control signal terminal 24 of the control unit 12 via the interface unit 13, and latched by the control signal register 20. From the control signal register 20, only the device ID field of the request packet is input to the memory / coprocessor device ID verification circuit 23, and the remaining fields of the request packet are directly supplied to the memory / operation control logic circuit 19. The memory / coprocessor device ID collating circuit 23 is provided with a device ID field and all the memory units 1 in the coprocessor built-in packet type DRAM 1.
1 and memory device ID for coprocessor unit 14
And the coprocessor device ID are collated in parallel, and as a result of the collation, whether or not a match with each memory unit 11 or coprocessor unit 14 is found is input to the memory / operation control logic circuit 19.

The memory / operation control logic circuit 19 is, as described above, a memory / coprocessor device ID collation circuit 2
3, whether the process requested by the request packet is a request for the memory unit 11 in the packet type DRAM 1 with built-in coprocessor as the collation result, and whether any process in the packet type DRAM 1 with built-in coprocessor is A determination result regarding whether the request is for the processor unit 14 is received. Therefore, the memory / operation control logic circuit 19 decodes the command field of the packet only when the memory unit 11 or the coprocessor unit 14 in the chip is specified, and determines what kind of processing is requested. , Memory unit 11 or coprocessor unit 1
4 is instructed to execute the processing.

As described above, in the packet type DRAM 1 with a built-in coprocessor according to the present invention, when the command field is decoded, the processing requested by the command field is performed for the memory unit 11 or the coprocessor unit 14 We can know whether it is targeted. Therefore, in the control method of the packet-type DRAM 1 with a built-in coprocessor according to the present invention, it is possible to use different command field decoding methods depending on whether the memory unit 11 or the coprocessor unit 14 is a target. This makes it possible to use a packet format of the request packet in which the command field length differs depending on which one is targeted, as shown in FIG. 6B and FIG. 6C. Further, a control method may be used in which command fields having the same field length and the same bit pattern are required to be processed completely differently depending on whether the command field is directed to the memory section 11 or the coprocessor section 14. For example, the memory unit 11
Using the same bit pattern of the command field as when the read access to the memory control register unit 16 is designated, the coprocessor unit 14 is used.
It is also possible to adopt a control method of designating write access to the operation control register unit 32 in the above.

By the device ID field collating operation and the command field decoding operation, the received packet requests memory access or coprocessor access for the memory unit 11 or coprocessor unit 14 in the chip. If it is determined that there is a request, the control method of the packet type DRAM 1 with a built-in coprocessor performs an operation of requesting access to the memory unit 11 or the coprocessor unit 14 according to the present invention.

The first of the access request operations in the control method of the packet type DRAM 1 with built-in coprocessor according to the present invention
In the embodiment, after the control unit 12 checks the device ID field of the request packet and decodes the command field, the control unit 12 instructs the memory unit 11 or the coprocessor unit 14 to perform write access or read access. In such an embodiment, the microprocessor 9
Bus master such as packet type DRAM with coprocessor
This is a method in the case where the content of the processing requested for the packet DRAM 1 is limited to the one that can always execute the packet type DRAM 1 with a built-in coprocessor. In order to guarantee that the requested processing can be always executed, the bus master must grasp the state of the memory unit 11 or the coprocessor unit 14 in the packet type DRAM 1 with a built-in coprocessor. Need to be. In the embodiment of the control method in this case, the acknowledgment packet shown in FIG. 3 is not necessary.

Second access request operation in the control method of the packet type DRAM 1 with a built-in coprocessor according to the present invention
In the embodiment, after the control unit 12 checks the device ID field of the request packet and decodes the command field, the control unit 12 determines whether it is possible to execute a write access or read access request to the memory unit 11 or the coprocessor unit 14. The result of the determination is transmitted to the packet type memory / coprocessor bus 2 as an acknowledgment packet. As shown in the embodiment of FIG. 6E, the acknowledgment packet includes information indicating whether or not execution is possible as an acknowledgment field. To convey. If it can be executed, the control unit 12 checks the device ID field of the request packet and decodes the command field, and then performs write access to the memory unit 11 or the coprocessor unit 14 as in the first embodiment. Alternatively, a read access instruction is issued. The operation when it is not executable will be described later. In this embodiment, the content of the processing requested by the bus master such as the microprocessor 9 to the packet-type DRAM 1 with built-in coprocessor is not always the one that the packet-type DRAM 1 with built-in coprocessor can necessarily execute. Is the way.

Packet type DR with built-in coprocessor of the present invention
In the embodiment of the access request operation in the control method of AM1, it is also possible to use the embodiments of the above first and second control methods in combination according to the request target and the command name.

FIG. 8 is an explanatory diagram showing a third embodiment of the access request operation in the control method of the packet type DRAM 1 with a built-in coprocessor according to the present invention in which such a combination is performed. In the third embodiment, when an access request is made to the memory unit 11, an embodiment of the first control method that does not require an acknowledgment packet is used. When a processing request is made, the embodiment of the second control method that requires an acknowledgment packet is used.

FIG. 9 shows a packet-type DRA with a built-in coprocessor according to the present invention in which such a combination is performed.
FIG. 14 is an explanatory diagram showing a fourth embodiment of the access request operation in the control method of M1. In the fourth embodiment, an acknowledgment packet is not required when an access request is made to the memory unit 11 and when a read access request is made to the coprocessor unit 14. Coprocessor unit 1 using the embodiment of the control method of
In the case where a write access request is made to No. 4, the embodiment of the second control method requiring an acknowledgment packet is used.

The memory access to the memory unit 11
When the acknowledgment packet is required, for example, in a situation where the DRAM core unit 15 accesses the DRAM core unit 15 during the refresh operation, the microprocessor 9 as the bus master does not know whether or not the refresh is being performed. For example, the microprocessor 9 does not know whether the data to be accessed is temporarily stored in the sense amplifier 18. In such a case, the approval packet indicates whether the requested access can be accepted (if approved) or not (if not approved), and if not, what kind of operation the microprocessor 9 performs. Contains information indicating what to do. Here, the content of the instruction is, for example, an instruction to re-access after a certain time or to wait for a certain time until the access is completed.

On the other hand, when an acknowledgment packet is required in coprocessor access to the coprocessor unit 14, the access is performed without knowing whether the microprocessor 9 serving as the bus master can write or read the operation control register unit 32. Is performed. For example,
If the data required by the coprocessor unit 14 is still to be written to the operation control register 33 in the operation control register unit 32,
2 still has the coprocessor unit 14 in the operation control register 33.
Corresponds to the case where the user is trying to read the data without writing the data. In such a case,
The approval packet can accept the requested access (if approved) or not (if not approved)
If not, it contains information indicating what action the microprocessor 9 should take. Here, the content of the instruction is, for example, an instruction to re-access after a certain time or to wait for a certain time until the access is completed.

Next, referring to FIGS. 1, 8, and 9, a packet type DRAM with a built-in coprocessor according to the present invention will be described.
An embodiment of the access operation of the memory unit 11 and the coprocessor unit 14 in FIG. Note that whether the request destination is the memory unit 11 or the coprocessor unit 14 is specified by the device ID field, and details of each requested access are given by the command field. In the embodiment in the case of a memory access to DRAM core unit 15, a desired DRAM bank 17 is designated by specifying an address given in a parameter field.
Is selected, and the data in the DRAM bank 17 is accessed via the sense amplifier 18. Here, the sense amplifier 18 plays a role as a cache memory or a high-speed buffer of the corresponding DRAM bank 17, and when the address range to be accessed targets data that is already temporarily stored in the sense amplifier 18,
High-speed DRAM access is enabled by making sense amplifier 18 an access target instead of DRAM bank 17. As described above, depending on whether or not desired data is already temporarily stored in the sense amplifier 18, the DR is determined.
Whether or not to access the AM bank 17 is determined, and the access time varies greatly according to this. If the subsequent access is to data that is not currently held in the sense amplifier 18, the data temporarily stored in the sense amplifier 18 is transferred to the DRAM bank 17 in order to speed up the subsequent access. It may be more convenient to write it back to For this reason, DRAM
In the case of memory access to the core unit 15, in one embodiment of the method of controlling the packet-type DRAM 1 with a built-in coprocessor according to the present invention, the command field is
Whether or not to access the AM bank 17 is determined by the sense amplifier 1
Information on control of the DRAM core unit 15 such as whether or not the data of No. 8 is to be written back to the DRAM bank 17 is included.

As shown in the embodiments of FIGS. 8 and 9, in the control method of the packet type DRAM 1 with the built-in coprocessor according to the present invention, the write access to the DRAM core unit 15 is performed by receiving the write data packet. hand,
The writing is performed by writing the variable-length write data in the DRAM core unit 15 using the control method and the address specified by the command field and the parameter field of the request packet. On the other hand, in the read access to the DRAM core unit 15, variable-length data is read from the DRAM core unit 15 using the control method and the address specified in the command field and the parameter field of the request packet, and is transmitted as a read data packet. It is done in. At this time, the control unit 12 receives write data from the write data terminal 25 at the time of writing, and outputs read data from the read data terminal 26 at the time of reading. The control signal register 20, the write data register 21, and the read data register 22 function as input latches (or input registers) or output latches (or output registers) of these input / output terminals. The read data and the write data are transferred to the control unit 12 and the DRAM via the internal memory data bus 27.
The data is transferred between the core units 15.

In the embodiment in the case of a memory access to the memory control register section 16, a parameter field specifies which memory control register 29 is to be accessed for writing or reading. In the write access, a write packet is received and fixed-length write data in the write packet is written. In the read access, the read fixed-length data is transmitted as a read packet. Command field specification is DRAM
This is significantly simpler than the case of memory access to the core unit 15. The controller 12 receives write data from the write data terminal 25 at the time of writing, and outputs read data from the read data terminal 26 at the time of reading. The read data and the write data are transferred between the control unit 12 and the memory control register unit 16 via the internal memory data bus 27.

As another embodiment in the case of the write access to the memory control register section 16, there is a method of making the write packet unnecessary by putting the write data in a part of the parameter field of the request packet. For example, in the request packet format shown in FIG. 6D, write data can be inserted into the parameters 1 and 2. The parameter 0 specifies which memory control register 29 is to be accessed for writing as described above. In the case of this embodiment, the control unit 12 receives write data from the control signal terminal 24 at the time of writing.

In the embodiment in the case of coprocessor access to the operation control register section 32, the parameter field specifies which operation control register 33 is to be accessed for writing or reading. In the write access, a write packet is received and the write data therein is written, and in the read access, the read data is transmitted as a read packet.
The read data and the write data are transferred between the control unit 12 and the operation control register unit 32 via the internal coprocessor data bus 28. The controller 12 receives write data from the write data terminal 25 at the time of writing, and outputs read data from the read data terminal 26 at the time of reading. In the embodiment of FIG. 8, a write packet is involved in a write access operation at the time of coprocessor access, and this embodiment corresponds to this embodiment.

As another embodiment in the case of a write access to the operation control register section 32, there is a method of making a write packet unnecessary by putting write data in a part of a parameter field of a request packet. For example, in the request packet format shown in FIG. 6D, write data can be inserted into the parameters 1 and 2. The parameter 0 specifies which operation control register 33 is to be accessed for writing, as described above. In this case, the control unit 12 receives write data from the control signal terminal 24 at the time of writing. In the embodiment of FIG. 9, the write packet is omitted in the write access operation at the time of the coprocessor access,
This corresponds to another embodiment.

FIG. 10 is an explanatory diagram for explaining an embodiment of a more specific function of coprocessor access to the coprocessor unit 14 in the packet type DRAM 1 with a built-in coprocessor according to the present invention. In FIG. 10, write access to the coprocessor unit 14 is divided into two subcommands, namely, an operation parameter write and an operation start request. In addition, read access to the coprocessor unit 14 is divided into two subcommands, namely, an operation result request and an operation state read.

The operation parameter writing is an operation of writing the operation parameters necessary for the coprocessor unit 14 to perform some operation processing from the bus master into the operation control register unit 32. Here, the operation parameter includes, for example, an address of data to be operated.

The operation start request is an operation for requesting the coprocessor unit 14 to start some operation processing from the bus master. The coprocessor unit 14 executes a desired operation process using the operation parameters written in advance in response to the operation start request.

The operation state is read by the coprocessor unit 14.
Is an operation in which the bus master reads the operation state from the operation control register unit 32. Here, the operation state includes, for example, intermediate data generated during the operation processing, information on whether or not the operation is being performed, and the like.

The operation result request is an operation in which the bus master reads the operation result after the coprocessor unit 14 completes some operation processing.

FIG. 11 is a block diagram showing an embodiment of the configuration of the coprocessor unit 14 according to the present invention. In FIG. 11, the operation control unit 31 of the coprocessor unit 14 of the present invention includes a program counter 61, an instruction decoder 6
2 and an instruction information register 64. The instruction decoder 62 has a status flag register 63 therein. The operation control register section 32 is composed of a plurality of operation control registers 33, among which a coprocessor device ID register 51, an operation start register 6
5 and an operation result register 66 are included.

Hereinafter, an embodiment of a specific operation of coprocessor access to the coprocessor unit 14 according to the present invention will be described in more detail with reference to FIGS.

At the time of the operation parameter writing operation, the operation parameters are given to the operation control register section 32 via the internal memory data bus 27 and the internal coprocessor data bus 28. Which operation control register 33 is to be written is determined by the memory / operation control logic circuit 19 from the operation control register 3.
Specified for 2. For the calculation parameter writing operation, two embodiments of a control method in which writing is always performed and a control method in which writing is approved or rejected can be adopted. In the embodiment in which the determination is made, the memory / arithmetic control logic circuit 19 notifies the arithmetic control unit 31 that the arithmetic parameter writing operation is to be performed. The operation control unit 31 refers to the state flag register 63 inside the instruction decoder 62, determines whether or not the operation parameter can be written, and transmits the determination result to the memory / operation control logic circuit 19. Here, the status flag register 6
Reference numeral 3 holds a status flag indicating whether or not the coprocessor unit 14 is currently executing an arithmetic operation. In this embodiment, while the arithmetic processing is being executed, writing of the arithmetic parameter is not accepted.

During the operation start request operation, the internal memory data bus 27 and the internal coprocessor data bus 28
A program pointer indicating the address of the first instruction of the operation processing program to be executed is given to the operation control register unit 32. In the operation start request operation, a designation is given from the memory / operation control logic circuit 19 to the operation control register unit 32 so that writing to the operation start register 65 is performed. The operation start request operation can adopt two embodiments of a control method in which writing is always performed and a control method in which writing is approved or rejected. In the embodiment in which the determination is made, the memory / operation control logic circuit 1 is instructed to perform an operation start request operation to the operation control unit 31.
9 to notify. The operation control unit 31 includes an instruction decoder 62
By referring to the internal state flag register 63, it is determined whether or not the writing of the program pointer is possible, and the result of the determination is transmitted to the memory / operation control logic circuit 19. In this embodiment, if the arithmetic processing is being executed, the arithmetic start request is not accepted. In any of the embodiments, when the operation start request is received, the value of the program pointer is written into the operation start register 65. In parallel with this, the value of the program pointer is directly written into the program counter 6.
Write also to 1. The instruction decoder 62 starts the arithmetic processing on this occasion. At the same time as the start of the arithmetic processing, the status flag register 63 is set to a state where the arithmetic is being executed.

The arithmetic processing is executed by sequentially executing a sequence of instructions constituting a desired arithmetic processing program in the order indicated by the program counter 61. This operation is started by an operation start request from the bus master, and thereafter, the coprocessor unit 14 performs the operation autonomously. The execution of one instruction is performed as follows. The instruction decoder 62 reads the value of the program counter 61, updates the value to point to the next instruction, writes it back to the program counter 61, and transmits the read value of the program counter to the memory / operation control logic circuit 19. Thereby, the instruction is read from the DRAM core unit 15 via the internal memory data bus 27 and the internal coprocessor data bus 28. The read instruction is decoded, and a request is made from the operation control register unit 32 to read register data required for executing the instruction in accordance with the decoded result.
The instruction information register 64 is a register that holds register data read from the operation control register unit 32 and instruction decode information that indicates what operation should be performed by the operation core unit 30. By transferring the information to the arithmetic core unit 30, the arithmetic core unit 30
Execute the instruction. The execution result of the instruction is written to the DRAM core unit 15 via the operation control register unit 32 or the internal memory data bus 27 and the internal coprocessor data bus 28. Further, the internal memory data bus 27 and the internal coprocessor data bus 28
In some cases, necessary data may be read from the DRAM core unit 15 via the CPU.

In the operation state reading operation, the operation state is read from the operation control register section 32 via the internal coprocessor data bus 28 and the internal memory data bus 27. Which operation control register 33 is read from is determined by the memory / operation control logic circuit 19 and the operation control register unit 32.
Is specified for This operation can be performed regardless of whether the arithmetic processing is being performed. This operation state reading operation can be used when the bus master wants to synchronize with the operation process being executed by the coprocessor unit 14. This is the coprocessor unit 14
The arithmetic processing being executed is programmed so that an arithmetic control register 33 is set to a specific value when an instruction is executed, and the value of the arithmetic control register 33 is read by the bus master. This is because the bus master can know whether the instruction has already been executed. This operation can also be used when the bus master wants to confirm whether or not the coprocessor unit 14 is currently performing any arithmetic processing. This is because the bus master reads the value of the operation control register 33 by, for example, mapping the value of the state flag to any one of the operation control registers 33 in the coprocessor unit 14, thereby terminating the operation processing. This is because the bus master can know whether or not the operation has been performed.

In the operation result request operation, the operation result is read from the operation result register 66 via the internal coprocessor data bus 28 and the internal memory data bus 27. At this time, the memory / operation control logic circuit 19 notifies the operation control unit 31 that the operation result is to be read. The operation result request operation can take two embodiments, a control method in which reading is always performed and a control method in which reading is approved or rejected. In the embodiment in which the rejection is performed, the operation control unit 31
(2) Referring to the internal state flag register 63, it is determined whether or not the arithmetic processing has already been completed, and the determination result is transmitted to the memory / operation control logic circuit 19. Here, the status flag register 63 holds a status flag indicating whether or not the coprocessor unit 14 is currently executing the arithmetic processing. In this embodiment, a request for a calculation result is not accepted while a calculation process is being performed.

As described with reference to FIGS. 10 and 11,
In the three coprocessor accesses of writing the operation parameter, requesting the start of operation, and requesting the operation result, the coprocessor unit 14
There may be an embodiment in which the coprocessor unit 14 does not receive a request for access to

In the control method of the packet type DRAM 1 with a built-in coprocessor according to the present invention, in the embodiment in which the operation parameter is written and the write is approved or rejected in the case of the operation start request, the approval or disapproval of the write is transmitted to the bus master using the acknowledge packet. Use a control method to transmit. The acknowledgment field of the acknowledgment packet indicates whether write access has been accepted, and the parameter field indicates information such as the reason for acknowledgment of access and how long access cannot be accepted afterward. The information on how long the access cannot be accepted is based on the predicted value of the arithmetic processing time previously written in the program at the start of the arithmetic processing. It can be obtained by setting the value in the register 67, reducing this value every clock or every several clocks, and copying the value of the processing time register 67 at the time of access to the parameter field of the acknowledgment packet.

In the control method of the packet type DRAM 1 with a built-in coprocessor according to the present invention, in the embodiment in which the read is approved or rejected in the case of the operation result request, the coprocessor is used by using the acknowledge packet or the read data packet. A control method of transmitting to the bus master whether the unit 14 has accepted the operation result request access is used. If an acknowledgment packet is used, as described above, the approval / denial field indicates whether access has been accepted,
In the parameter field, the reason for access denial,
Information indicating how long access cannot be accepted afterward is shown. When a read data packet is used, one bit of the read data packet is used to indicate whether the content of the read data packet is a read operation result or information about access rejection. Therefore, the data length of the read data is one bit smaller than the packet size. If the access is denied, the same information as the contents of the packet field of the above-mentioned acknowledgment packet is transmitted as a read data packet.

FIG. 12 is a timing chart illustrating an embodiment of a method of controlling access from a bus master to packet type DRAM 1 with a built-in coprocessor according to the present invention. Memory access, that is, the DRAM core unit 15,
An embodiment in which an acknowledgment packet is not required for accessing the memory control register 29 is used. The writing to the memory control register section 16 uses an embodiment in which a write data packet is not required by putting write data in a request packet.
In the coprocessor access, the operation control register unit 32
Read access (including operation result request and operation status read) to the
The embodiment uses no acknowledgment packet.
On the other hand, in the operation start request to the operation control register unit 32,
An embodiment requiring an acknowledgment packet is used. As described above, in the case of an operation result request in the read access to the coprocessor unit 14, a control method for transmitting to the bus master whether or not the coprocessor unit 14 has accepted the operation result request access by a read data packet. Embodiment is used. In response to an operation start request, the coprocessor unit 14 transmits an acknowledgment packet to inform the bus master whether the operation has actually started. Although there is no acknowledgment packet for the operation parameter writing, instead, the operation state read access is performed in advance, and after confirming that the coprocessor unit 14 has completed the operation processing, the operation parameter writing is performed. Writing to the operation control register unit 32 can be guaranteed.

FIG. 13 is a timing chart for explaining another embodiment of a method for controlling access from the bus master to the packet type DRAM 1 with a built-in coprocessor according to the present invention. Memory access, that is, DRAM core unit 1
5 and the access to the memory control register 29 use the embodiment of the control method when an acknowledgment packet is required. Similarly, an embodiment in which an acknowledgment packet is required for coprocessor access is used.
In the embodiment shown in FIG. 13, these acknowledgment packets notify the bus master of whether the coprocessor access has been processed as requested.

In each of the embodiments of the control method of the packet type DRAM 1 with a built-in coprocessor according to the present invention shown in FIGS. 12 and 13, it is determined whether the memory unit 11 or the coprocessor unit 14 is accessed. However, the bus timing on the packet type memory / coprocessor bus 2 is set to be the same. That is, in the embodiment of FIG. 12 which does not require any acknowledgment packet when accessing the memory unit 11, the acknowledgment packet for the operation start request to the operation control register unit 32 of the coprocessor unit 14 is viewed from the request packet It is set so as to be transmitted to the packet type DRAM 1 with a built-in coprocessor at the same bus timing as the read data packet and the write data packet. In the embodiment of FIG. 13, the bus timing between all access approval packets and request packets and the bus timing between all read data packets or write packets and request packets are the same. Is set to

In the embodiment of the configuration of the coprocessor unit 14 according to the present invention shown in FIG. 11, the case where the coprocessor unit 14 is programmable has been described. Sometimes, by using the embodiment of the coprocessor access shown in FIG.
The arithmetic processing in the coprocessor unit 14 can be controlled. In the embodiment of the configuration of the coprocessor unit 14 according to the present invention shown in FIG. 11, an instruction to be processed is read from the memory unit 11, and data used for processing the instruction is read from the memory unit 11 as necessary. , An instruction processing result is written to the memory unit 11 as necessary. As another embodiment of the present invention, a buffer memory or a cache memory is provided in the coprocessor unit 14. It is also possible to adopt a configuration in which the number of accesses to the memory unit 11 from the coprocessor unit 14 is reduced by accessing the memory unit 11 through the memory unit 11.

FIG. 14 is a block diagram showing the configuration of an embodiment of a packet type memory / coprocessor bus according to the present invention for setting a memory device ID and a coprocessor device ID in a packet type memory LSI with a built-in processor according to the present invention. FIG. In FIG. 14, the packet-type memory / coprocessor bus 200 includes the packet-type memory / coprocessor bus 2 and a packet-type DRAM chain 70 with a built-in coprocessor. The packet-type DRAM chain with built-in coprocessor 70 includes an external select-out terminal 76 of the microprocessor 9 serving as a bus master, an external select-in terminal 71 of the packet-type DRAM 1 with built-in coprocessor, and a packet-type DRAM 1 with built-in coprocessor.
The external select-out terminal 72 of the packet type DRAM 1 with a built-in coprocessor, the external select-out terminal 72 of the packet type DRAM 1 with a built-in coprocessor, and the external select-in terminal 75 of the microprocessor 9 are formed in a one-dimensional loop. It is configured by connecting to Also, packet type DRAM with built-in coprocessor
The first external select-in terminal 71 is connected to the internal select-in terminal 73 of the memory unit 11 or the coprocessor unit 14 inside the packet type DRAM 1 with a built-in coprocessor,
Memory unit 11 of packet type DRAM 1 with built-in coprocessor
The internal select-out terminal 74 and the internal select-in terminal 73 are connected to each other so as to form a one-dimensional chain, and the plurality of coprocessor units 14 are connected to each other. The internal select out terminal 74 is connected to the external select out terminal 72 of the packet type DRAM 1 with a built-in coprocessor.

By adopting the configuration as shown in FIG. 14, the respective memory units 11 or coprocessor units 1 are known as a so-called daisy chain system.
4 can be assigned a memory device ID or a coprocessor device ID, respectively, by using the following embodiment of the control method.

As an initialization operation, a memory device ID and a coprocessor device ID are set to predetermined initial state values, respectively. To realize this, for example, the memory device ID in the memory control register unit 16
When a reset signal is given to the register 50 and the coprocessor device ID register 51 in the operation control register unit 32, the initial state value (for example, in the case of 6 bits,
The value may be set to “111111” or “000000”. Similarly, as an initialization operation, all the memory units 11 and the internal select-out terminals 74 of the coprocessor unit 14 are set to output a logical value 0. After the initialization operation, the memory unit 11 and the coprocessor unit 14 receive a logical value 0 from the internal select-in terminal 73 until the memory device ID or the coprocessor device ID is rewritten from the initial state value. In this case, the write access is ignored, and if a logical value of 1 is given from the internal select-in terminal 73, the memory device ID is set according to the write access instruction.
Alternatively, the coprocessor device ID is rewritten from the initial state value. The memory unit 11 or the coprocessor unit 14 that has rewritten from the initial state value outputs a logical value 1 from its internal select-out terminal 74.

In such a configuration, a logical value 1 is output from the external select-out terminal 76 of the microprocessor 9, and an initial state value is specified as the device ID field of the request packet, and a different device ID value is set in the parameter field. By sequentially performing the write access specified as the write data, the packet type memory / memory is sequentially accessed from the first memory unit 11 or the coprocessor unit 14 in the first packet type DRAM 1 with built-in coprocessor in the packet type DRAM chain with built-in coprocessor 70. A unique memory device I is provided for all the memory units 11 and the coprocessor units 14 of all the packet type DRAMs 1 with built-in coprocessors connected to the processor bus 200.
D and the coprocessor device ID can be set.

FIG. 15 is an explanatory diagram illustrating an embodiment of the memory control register section 16 and the arithmetic control register section 32 in the packet type DRAM 1 with a built-in coprocessor according to the present invention. In the figure, the device definition register 8
Reference numeral 1 denotes a register that holds device definition information for distinguishing the memory unit 11 from the coprocessor unit 14. The storage of the device definition information in the device definition register 81 is as follows.
This is performed in advance at the time of manufacturing or shipping the packet type DRAM 1 with a built-in coprocessor. The bus master specifies a certain device ID and reads the device definition information from the device definition register 81, thereby recognizing whether the memory unit 11 or the coprocessor unit 14 corresponds to the device ID requested to be read. can do. As shown in the figure, by providing a device definition register 81 as the memory control register 29 or the operation control register 33 designated by the same register number in each of the memory control register section 16 and the operation control register section 32. The bus master can read the device definition register 81 in a situation where it is not known in advance whether the target to be read is the memory unit 11 or the coprocessor unit 14.
This is because read access of the device definition register 81 to the memory unit 11 and the coprocessor unit 14 can be performed using a request packet that differs only in the device ID field.

The function definition register 82 in the operation control register section 32 shown in the embodiment of FIG. 15 is a register for storing a function definition code in which the operation processing functions of the coprocessor section 14 are classified. The storage of the function definition code in the function definition register 82 is performed in advance at the time of manufacturing or shipping of the packet type DRAM 1 with a built-in coprocessor. The bus master can recognize the arithmetic processing function of the specified coprocessor unit 14 by specifying a certain device ID specifying the coprocessor unit 14 and reading the function definition code from the function definition register 82.

[0163]

A first effect of the present invention is that a packet type DRAM with a built-in coprocessor can be realized without increasing the number of external input / output terminals as compared with a conventional packet type DRAM. is there. Specifically, a packet-type DRAM with a built-in coprocessor can be realized with about 10 to 30 external input / output terminals.

The second effect of the present invention is that the packet DRAM with a built-in coprocessor is used by using the exact same external I / O terminal configuration as compared with the conventional packet DRAM.
Can be realized. Specifically, for example, packet type DR defined by SyncLink technology or Rambus technology
The packet type DRAM with a built-in coprocessor can be realized by using the terminal configuration exactly the same as the external input / output terminal configuration of the AM.

The third effect of the present invention is that any one of the memory access to the memory unit in the chip and the coprocessor access to the coprocessor unit in the chip requested via the packet type memory / coprocessor bus is required. And a packet-type DRAM with a built-in coprocessor that can also process the data.

A fourth effect of the present invention is that a packet-type memory / coprocessor bus can be realized by using exactly the same bus signal line configuration as compared with a conventional packet-type memory bus. . Specifically, for example, Sync
A packet-type memory / coprocessor bus can be realized by using a bus signal line configuration of a packet-type memory bus defined by Link technology and Rambus technology.

A fifth effect of the present invention is that the above memory access to the memory unit is realized so that there is no time overhead as compared with the conventional memory access in the packet type memory bus and the packet type DRAM. It is possible to realize a packet-type memory / coprocessor bus and a packet-type DRAM with a built-in coprocessor. Specifically, for example, SyncLink technology and Ramb
The above memory access to the memory unit in the packet type DRAM with a built-in coprocessor can be realized with exactly the same bus timing as the memory access in the us technology.

A sixth effect of the present invention is that the above-described memory access to the memory unit is realized by using exactly the same packet format and bus protocol as the memory access in the conventional packet-type memory bus and packet-type DRAM. It is possible to realize a packet-type memory / coprocessor bus and a packet-type DRAM with a built-in coprocessor. Specifically, for example, the above memory access to the memory unit in the packet type DRAM with a built-in coprocessor can be realized by using the exact same packet format and the same bus protocol as the memory access in the SyncLink technology or the Rambus technology. .

The seventh effect of the present invention is that the coprocessor unit responds to the coprocessor unit (write access and read access) from the bus master with the acknowledgment packet and the read data packet, and It is possible to realize a packet-type memory / coprocessor bus and a packet-type DRAM with a built-in coprocessor capable of realizing an operation start request and an operation result request for a coprocessor unit on a packet-type memory / coprocessor bus having a bus master configuration. What you can do.

The eighth effect of the present invention is that the bus timing between the request packet at the time of memory access, the read data packet and the write data packet, the request packet at the time of coprocessor access, the read data packet, and the write data packet. By making the bus timing between the packet and the acknowledgment packet exactly the same, it is possible to realize a packet-type memory / coprocessor bus that can simplify the setting of the bus timing in the bus master. . For example, the bus timing between the request packet and the read data packet and the write data packet at the time of memory access in the SyncLink technology, and the request packet and the read data packet, the write data packet, and the acknowledgment packet at the time of the coprocessor access. It is possible to make the bus timing between them exactly the same.

The ninth effect of the present invention is that the bus timing between the request packet and the acknowledgment packet at the time of memory access, the bus timing between the request packet and the read data packet and the write data packet, By making the bus timing between the request packet and the acknowledgment packet at the time of access, and the bus timing between the request packet, the read data packet, and the write data packet exactly the same, the bus master can set the bus timing. It is possible to realize a packet type memory / coprocessor bus which can be simplified. For example, bus timing between a request packet and an acknowledgment packet at the time of memory access in Rambus technology, bus timing between a request packet and a read data packet and a write data packet, and a request packet at the time of a coprocessor access. The bus timing between the acknowledgment packet and the bus timing between the request packet and the read data packet and the write data packet can be exactly the same.

A tenth effect of the present invention is that the same code (bit pattern) is different depending on which of the command field of the request packet for the memory unit and the command field of the request packet for the coprocessor unit is the request. A packet type memory / coprocessor bus and a coprocessor built-in packet type DRAM which can be defined to mean a command can be realized. This makes it possible to encode the command of the request packet to the memory unit by making full use of the command space determined by the command field length. For example, in the SyncLink technology or the like, in the command field specified by 6 bits, all code spaces other than the code 011010 are allocated to some memory access commands.

An eleventh effect of the present invention is that the coprocessor unit can execute arithmetic processing while using instructions and / or data stored in the memory unit in the chip. Packet type DRAM
Can be realized. Generally, within a single chip, data transfer with an extremely high bandwidth can be realized as compared with between chips. For example, high-speed DR
While the external data transfer bandwidth of the AM is about 1 GB / sec, it is possible to realize a data transfer bandwidth of about 10 GB / sec in the chip. Therefore, the packet-type DRAM with a built-in coprocessor of the present invention performs high-speed arithmetic processing utilizing high-bandwidth data transfer in the chip by reading or writing instructions and data from the memory unit in the chip. I can do it.

The twelfth effect of the present invention is that the packet type DRAM of the prior art and the packet type DRAM with a built-in coprocessor are used.
Packet type memory /
That is, a coprocessor bus can be realized.
It should be noted that the packet type DRAM of the prior art can be regarded as a packet type DRAM with a coprocessor of the present invention having zero coprocessors.

A thirteenth effect of the present invention is that a packet type DRAM of the prior art and a packet type DRAM with a built-in coprocessor are provided.
And a packet type memory / coprocessor bus in which both a memory access to a packet type DRAM and a memory access to a memory unit in a packet type DRAM with a built-in coprocessor can be performed at the same bus timing. A memory / coprocessor bus can be realized.

A fourteenth effect of the present invention is that the packet type DRAM with a built-in coprocessor and the packet type memory / coprocessor bus of the present invention provide
And a memory system with a built-in coprocessor, which can be easily replaced with an existing memory system configured using a packet-type memory bus. Therefore, the memory system with a built-in coprocessor according to the present invention can easily penetrate a processor system using an existing memory system.

A fifteenth effect of the present invention is that a packet type memory in which a bus master can set a unique memory device ID and a unique coprocessor device ID for a memory unit and a coprocessor unit by an initialization operation. / Packet DRAM with Coprocessor Bus and Coprocessor
And can be realized.

A sixteenth effect of the present invention is that, by setting device IDs by reading device definition information, the bus master recognizes whether the request for processing is a memory unit or a coprocessor unit. It is possible to realize a packet-type memory / coprocessor bus and a packet-type DRAM with a built-in coprocessor.

A seventeenth effect of the present invention is that, by reading the function definition code, the bus master can identify the arithmetic processing function implemented in the coprocessor unit to be requested for processing. A coprocessor bus and a packet type DRAM with a built in coprocessor can be realized. As a result, software such as a device driver and an operation library suitable for the installed coprocessor can be loaded and linked, and the user program can use the operation performed by the coprocessor through the software. . These software can accelerate the processing of the user program by causing the coprocessor to execute arithmetic processing suitable for the arithmetic processing function of each coprocessor. In other words, this makes it possible to dynamically change the hardware configuration and software configuration during initialization or during operation of the processor system,
A processor system using a packet type DRAM with a built-in coprocessor can be realized.

In the above description of the embodiment and the effects of the invention, the packet type DR with a built-in coprocessor has been described.
Although the AM has been described, the present invention can be more generally applied to a packet-type memory LSI with a built-in coprocessor.

[Brief description of the drawings]

FIG. 1 is a packet type DR with a built-in coprocessor according to the present invention.
It is a block diagram showing an embodiment of composition of AM.

FIG. 2 is a packet type DR with a built-in coprocessor according to the present invention;
FIG. 2 is a block diagram showing an embodiment of a configuration of an AM and a packet type memory / coprocessor bus.

FIG. 3 is an explanatory diagram illustrating types of packets communicated on a packet type memory / coprocessor bus according to the present invention.

FIG. 4 is an explanatory diagram for explaining an embodiment of a method of packet communication on a packet type memory / coprocessor bus according to the present invention.

FIG. 5 is an explanatory diagram showing an embodiment of a process requested by a request packet to a packet-type memory LSI with a built-in coprocessor according to the present invention;

FIG. 6 is an explanatory diagram showing an embodiment of a configuration of a packet format of a packet exchanged on a packet type memory / coprocessor bus according to the present invention.

FIG. 7 shows a device ID field, a memory device ID, and a coprocessor device I of a request packet in a packet-type memory LSI with a built-in coprocessor according to the present invention.
FIG. 2 is a block diagram showing an embodiment of a configuration of a memory / coprocessor device ID collation circuit for collating D.

FIG. 8 is an explanatory diagram showing an embodiment of a processing procedure of a control method of a packet type memory LSI with a built-in coprocessor according to the present invention.

FIG. 9 is an explanatory diagram showing another embodiment of the processing procedure of the control method of the packet-type memory LSI with a built-in coprocessor according to the present invention.

FIG. 10 is an explanatory diagram showing an embodiment of a function of coprocessor access to a coprocessor unit in a packet type memory LSI with a built-in coprocessor according to the present invention.

FIG. 11 is a block diagram showing an embodiment of a configuration of a coprocessor unit in a packet type memory LSI with a built-in coprocessor according to the present invention.

FIG. 12 is a timing chart showing an embodiment of a method for controlling a packet-type memory LSI with a built-in coprocessor according to the present invention;

FIG. 13 is a timing chart showing another embodiment of the control method of the packet type memory LSI with a built-in coprocessor according to the present invention.

FIG. 14 is a block diagram showing a configuration of an embodiment of a packet type memory / coprocessor bus according to the present invention for setting a memory device ID and a coprocessor device ID in a packet type memory LSI with a built-in coprocessor according to the present invention; .

FIG. 15 is an explanatory diagram illustrating an embodiment of a configuration of a memory control register unit and an operation control register unit in a packet-type memory LSI with a built-in coprocessor according to the present invention.

FIG. 16 is a block diagram showing an example of a configuration of a packet type DRAM according to the related art.

FIG. 17 is a block diagram showing an example of the configuration of a packet type DRAM and a packet type memory bus according to the related art.

FIG. 18 is an explanatory diagram for explaining an example of the operation of the packet DRAM according to the related art.

FIG. 19 is an explanatory diagram for explaining an example of the types of packets exchanged on a packet-type memory bus according to the related art.

FIG. 20 is an explanatory diagram for explaining an example of a packet communication method on a packet-type memory bus according to the related art.

FIG. 21 is an explanatory diagram illustrating an example of a processing procedure when a packet type DRAM according to the related art receives a request packet.

FIG. 22 is an explanatory diagram showing an example of a packet format of a packet used by a conventional packet type DRAM and a packet type memory bus.

[Explanation of symbols]

 Reference Signs List 1 packet type DRAM with built-in coprocessor 5 external input / output terminal 11 memory unit 12 control unit 13 interface unit 14 coprocessor unit 15 DRAM core unit 16 memory control register unit 17 DRAM bank 18 sense amplifier 19 memory / operation control logic circuit 20 control signal Register 21 Write data register 22 Read data register 23 Memory / coprocessor device ID comparison circuit 24 Control signal terminal 25 Write data terminal 26 Read data terminal 27 Internal memory data bus 28 Internal coprocessor data bus 29 Memory control register 30 Arithmetic core unit 31 Operation control unit 32 Operation control register unit 33 Operation control register 2 Packet type memory / coprocessor bus 2-1 Control bus 2-2 Data bus 2-3 Request bus 2-4 Bus 9 Microprocessor 13-1 Control interface unit 13-2 Data interface unit 13-3 Request interface unit 13-4 Response interface unit 50 Memory device ID register 51 Coprocessor device ID register 52 Device ID verification circuit 61 Program counter 62 Instruction decoder 63 status flag register 64 instruction information register 65 operation start register 66 operation result register 67 processing time register 70 packet type DRAM chain with coprocessor 71 external select-in terminal 72 external select-out terminal 73 internal select-in terminal 74 internal select-out terminal 75 external Select-in terminal 76 External select-out terminal 81 Device definition register 82 Function definition register 200 Packet type memory / computer Sessabasu 1001 packet type DRAM 1012 controller 1019 memory control logic circuit 1023 memory device ID verification circuit 1002 packet type memory bus 1002 - control bus 1002 - data bus 1002-3 request bus 1002-4 response bus

Continuation of the front page (56) References JP-A-1-22459 (JP, A) JP-A-58-192154 (JP, A) JP-A-6-215160 (JP, A) JP-A-10-49428 (JP, A) JP-A-8-227394 (JP, A) JP-A-10-143489 (JP, A) JP-A-3-154919 (JP, A) JP-A-63-41934 (JP, A) 5-507374 (JP, A) Kazuaki Murakami and two others, "Overview of the standard communication interface" PPR AM-Link Standard "Draft0.0 for the memory-multiprocessor integrated ASSP" PPRAM "", Information Processing Society of Japan research Report, Information Processing Society of Japan, August 1996, Vol. 96, No. 80 (96-ARC-119), pp. 155-160 (58) Fields surveyed (Int. Cl. ⁷ , DB G06F 9/38 G06F 12/00-12/06 G06F 13/14-13/18 G06F 15/16-15/177 G06F 15/78 G11C 7/00, 11/34

Claims (45)

(57) [Claims] A memory unit, a control unit, an interface unit,
A packet-type memory LSI with a built-in coprocessor, comprising N (natural number) coprocessor units and connected to a packet-type memory / coprocessor bus outside the chip through external input / output terminals. Device ID, N
A coprocessor device ID is set for each of the coprocessors, and the memory device ID and the coprocessor device ID are held in a chip. The memory device ID or the coprocessor device ID is Any one of the memory units or the coprocessor units between any one of the memory units and any one of the coprocessor units in all the coprocessor built-in packet type memory LSIs connected to the packet type memory / coprocessor bus. A packet-type memory LSI with a built-in coprocessor, which is capable of uniquely identifying whether to specify. 2. A memory unit, a control unit, an interface unit,
N (natural number) coprocessor units, the memory unit includes a memory core unit and a memory control register unit, the coprocessor unit includes an operation core unit, an operation control unit, and an operation control register unit; The memory control register section has a first predetermined number of memory control registers, the operation control register section has a second predetermined number of operation control registers, and the memory section and the control section have an internal memory data bus. And the N coprocessor units and the control unit are connected by an internal coprocessor data bus, respectively.
A coprocessor internal packet type memory LSI which is connected to the chip external packet memory / coprocessor bus by the external input and output terminal having a signal terminal of an arbitrary number, the memory device ID to the memory unit, the N Pieces
A coprocessor device ID is set for each of the coprocessors, and the memory device ID and the coprocessor device ID are held in a chip. The memory device ID or the coprocessor device ID is Any one of the memory units or the coprocessor units between any one of the memory units and any one of the coprocessor units in all the coprocessor built-in packet type memory LSIs connected to the packet type memory / coprocessor bus. A packet-type memory LSI with a built-in coprocessor, which is capable of uniquely identifying whether to specify. 3. The packet-type memory LSI with a built-in coprocessor according to claim 2, wherein said memory core is configured using a dynamic random access memory (DRAM). 4. One bus master and, Claim 2 or 3
StatedPacket type with built-in coprocessorLSI and theseTo
Packet type memory / coprocessor bus to be connectedWith
Memory system, the packet type memory /
The processor bus is  The bus master is the packet type memory / coprocessor;
When sending a packet to Sabus, the packet type memo
It is necessary to arbitrate the bus occupation rights of the re / coprocessor bus
A single bus master type bus having no bus, and further comprising a coprocessor built-in packet from the bus master.
A control bus, which is a unidirectional bus to a unit-type memory LSI;
A data bus, which is a bidirectional bus between memory LSIs,
A memory system characterized by having as a unit. 5. One bus master and, Claim 2 or 3
StatedPacket type with built-in coprocessorLSI and these
Packet type memory / coprocessor bus to be connectedWith
Memory system, the packet type memory /
The processor bus is  The bus master is the packet type memory / coprocessor;
When sending a packet to Sabus, the packet type memo
It is necessary to arbitrate the bus occupation rights of the re / coprocessor bus
A single bus master type bus having no bus, and further comprising a coprocessor built-in packet from the bus master.
A request bus that is a unidirectional bus to the packet-type memory LSI;
The response bus, which is a unidirectional bus to the bus master, is
A memory system characterized by having as a unit. 6. One bus master and, Claim 2 or 3
StatedPacket type with built-in coprocessorLSI and theseTo
It has a packet type memory / coprocessor bus to be connected.
Memory system,This packet type memory /
The processor bus is  The bus master is the packet type memory / coprocessor;
When sending a packet to Sabus, the packet type memo
It is necessary to arbitrate the bus occupation rights of the re / coprocessor bus
A single bus master type bus having no packet memory / computer.
Request packet as a packet that can be sent to the processor bus
And write data packet.
The packet type memory LSI with a built-in coprocessor
Packets that can be sent to a packet-type memory / coprocessor bus
One packet type of the read data packet as
A memory system comprising a memory system. 7. A bus master and one or more bus masters.
A packet-type LSI with a built-in coprocessor and a packet-type memory / coprocessor bus for connecting the packet-type LSI and the packet-type memory / coprocessor bus. A single bus master type bus which does not require arbitration of the bus occupation right of the packet type memory / coprocessor bus when transmitting a packet to the coprocessor bus; The packet type memory / coprocessor bus has two packet types, a request packet and a write data packet, which can be transmitted to the packet type memory / coprocessor bus. Read data packet and acknowledgment Memory system characterized by having two packet types ket. 8. The request packet has a device ID field, a command field, and a parameter field, and the device ID field indicates that the request packet is an arbitrary one connected to the packet type memory / coprocessor bus. The coprocessor built-in packet type memory LSI designates one or a plurality of the memory units or the coprocessor units in the coprocessor unit to request processing, and the command field indicates whether the request packet is 7. The method according to claim 6 , wherein the content of the requested process is indicated, and the parameter field gives a parameter necessary for executing the process requested by the request packet.
8. The memory system according to 7 . 9. The field length of the device ID field is fixed regardless of whether the device ID field specifies the memory unit or the coprocessor unit. 9. The memory system according to claim 8, wherein said device ID field has a fixed length regardless of whether said memory unit or said coprocessor unit is specified. 10. The device ID field has a fixed length regardless of whether the device ID field specifies the memory unit or the coprocessor unit. wherein depending on whether the device ID field specifies the coprocessor unit to specify the memory portion, the eye of claim 8, wherein that the field lengths are different for
Moly system . 11. via the external input-output terminal from said packet type memory / coprocessor bus to receive the interface unit is the request packet, the control unit is the device ID field and the chip in the request packet of the The memory device ID and a plurality of the coprocessor device IDs stored in the
Field only when specifying one of the memory device ID and the coprocessor device ID, and decodes the command field of the control unit is included in the request packet, the said device I
Claims, characterized in that for instructing the execution of the process where the request for the request packet to the specified the memory unit or the coprocessor unit by D field
11. The memory system according to any one of 8 to 10 . 12. A memory device for a memory unit.
Copies the D register to any number of the coprocessors.
A processor device ID register is provided, and the memory device ID and the coprocessor device ID are stored in the memory device ID register and the coprocessor device ID register, respectively, and connected to the memory device ID register and the coprocessor device ID register. A memory / coprocessor device ID verification circuit, wherein the memory / coprocessor device ID verification circuit performs a verification between the device ID field of the request packet and the memory device ID register; A collation between a device ID field and each of the coprocessor device ID registers is performed in parallel, and the device ID field indicates any one of the memory device ID or the coprocessor device ID. 12. The memory system according to claim 11, wherein it is determined whether a chair ID is specified. 13. The memory control register unit and the operation control register unit, wherein the memory device ID register is one of the memory control registers and the coprocessor device ID register is one of the operation control registers. The memory system according to claim 12, wherein: 14. A method for decoding the command field in the control unit depending on whether the device ID field of the request packet specifies the memory unit or the coprocessor unit, thereby obtaining the memory unit or the coprocessor. memory system of claim 11, wherein the represented by any one of the processor unit of interest, a request for differentially processed is the command field having the same bit pattern. 15. The device ID in the request packet
When the field specifies the memory device ID, the control unit decodes the command field of the request packet, and according to a decoding result, the control unit decodes the command field in the memory core unit or the memory in the memory unit. 15. The memory system according to claim 11, wherein a write access or a read access to a control register unit is instructed to the memory unit. 16. The device ID in the request packet
When the field indicates the memory device ID, the control unit decodes the command field of the request packet, and the control unit writes the command field of the request packet according to the decoding result. Determining whether the memory unit can perform access or read access, transmitting the result of the determination as the acknowledgment packet to the packet-type memory / coprocessor bus, and if the memory unit is executable, 15. The memo according to claim 11, wherein the control unit instructs the memory unit to perform the write access or the read access to the memory core unit or the memory control register unit in the memory unit.
Resystem . 17. The device ID in the request packet
When the field indicates one of the coprocessor sections, the control section decodes the command field, and in accordance with the decoding result, the control section sets the operation control register in the coprocessor section. 15. The memory system according to claim 11, wherein one of a write access and a read access to a unit is instructed to the coprocessor unit. 18. The device ID in the request packet
When the field is an instruction to one of said coprocessor unit, the control unit decodes the command field, according to the decode result, write at which the control unit requests said request packet of the The coprocessor unit determines whether the access or read access is executable by the coprocessor unit, and transmits the result of the determination as the acknowledgment packet to the packet type memory / coprocessor bus. When executable, the control unit instructs the coprocessor unit to perform either the write access or the read access to the arithmetic control register unit in the coprocessor unit. The memory system according to claim 11. 19. The device ID in the request packet
When the field specifies the memory device ID, the control unit decodes the command field of the request packet, and the control unit responds to the decoding result according to the decoding result. It instructs the write access or read access to the memory control register unit to the memory unit, the device ID field in the request packet before
When an instruction to one of the serial coprocessor unit,
The control unit decodes the command field, and determines whether the coprocessor unit can execute a write access or a read access requested by the request packet according to the decoding result. Then, after transmitting the determination result as an approval packet to the packet type memory / coprocessor bus, if the coprocessor unit is executable,
15. The control unit according to claim 11, wherein the control unit instructs the coprocessor unit to perform one of the write access and the read access to the operation control register unit in the coprocessor unit. Note
Resystem . 20. The device ID in the request packet
When the field specifies the memory device ID, the control unit decodes the command field of the request packet, and according to a decoding result, the control unit decodes the command field in the memory core unit or the memory in the memory unit. When the memory unit instructs a write access or a read access to a control register unit, and when the device ID field in the request packet indicates one of an arbitrary number of the coprocessor units, the control unit Decodes the command field, and when the decoded result indicates a write access to the operation control register, the control unit determines whether the coprocessor unit can execute the write access. determination, and the packet type memory / co the determination result as acknowledgment packet After having transmitted to Rosessabasu, when the coprocessor portion of the executable is
When the control unit instructs the coprocessor unit to perform the write access to the operation control register unit in the coprocessor unit, and when a decoding result indicates a read access to the operation control register, is Memorishi the control unit according to claim 11 or 14, wherein the read access to the operation control register unit in the coprocessor of the is characterized by instructing the coprocessor portion of the
Stem. 21. In the write access to the memory core unit, the memory unit transmits the write data packet received from the packet type memory / coprocessor bus via the interface unit via the control unit. 16. The method according to claim 15, further comprising the step of receiving and writing to the memory core unit using a memory address specified by the parameter field in the request packet.
21. The memory system according to 6, 19 or 20. 22. In the write access to the memory control register unit, the memory unit transmits the write data packet received from the packet type memory / coprocessor bus via the interface unit via the control unit. 20. The memory control register according to claim 15, wherein said data is received and written into said memory control register specified by said parameter field in said request packet.
21. The memory system according to 20. 23. In the write access to the memory control register unit, the memory unit receives, via the control unit, write data included in a part of the parameter field in the request packet. hand,
21. The memory control register according to claim 15, wherein the memory control register specified by a part of the parameter field in the request packet is written.
Memory system . 24. In the read access to the memory core unit and the memory control register unit, the memory unit performs the memory core unit or the memory control unit according to the specification of the parameter field in the request packet. The data read from the register unit is passed to the control unit, the control unit generates the read data packet, and the interface unit transmits the read data packet to the packet type memory / coprocessor bus via the external input / output terminal. 21. The memory according to claim 15, 16, 19, or 20, wherein the data is transmitted to a memory.
System . 25. In the write access to the operation control register unit, the coprocessor unit transmits the write data packet received from the packet type memory / coprocessor bus via the interface unit to the control unit. 20. The method according to claim 17, further comprising the steps of:
21. The memory system according to 20. 26. In the write access to the operation control register unit, the coprocessor unit writes, via the control unit, write data included in a part of the parameter field in the request packet. 21. The memory system according to claim 17, wherein said received data is written into said operation control register specified by a part of said parameter field in said request packet. 27. In the read access to the operation control register unit, the coprocessor unit sends data read from the operation control register specified by the parameter field in the request packet to the control unit. 18. The method according to claim 17, wherein the control unit generates the read data packet, and the interface unit transmits the read data packet to the packet-type memory / coprocessor bus via the external input / output terminal. , of 18, 19 or 20, wherein the Memorishisu
Tem . 28. The memory core section, the memory control register section, the reading the coprocessor internal packet memory said read the data packet Packet type memory / coprocessor bus during access to the operation control register section And a bus cycle for transmitting the acknowledgment packet to the packet-type memory / coprocessor bus at the time of the write access to the operation control register unit, as seen from the bus cycle for receiving the request packet. Wherein the bus timings are the same.
28. The memory system according to 6 or 27. 29. An arithmetic start register provided in the arithmetic control register unit, wherein the arithmetic start register is the arithmetic control register referred to when the coprocessor unit starts execution of arithmetic processing. When the write access to the operation start register is instructed by the command field and the parameter field of the packet, the write data included in the parameter field of the request packet or the data of the write data packet is written. 29. The memory system according to claim 25, wherein the memory system is used as a program pointer and executes an arithmetic operation indicated by the program pointer. 30. When the write access to the operation start register is instructed, information as to whether execution of the instructed operation can be started is transmitted to the packet type memory / coprocessor bus as the acknowledgment packet. 30. The memory system according to claim 29, wherein: 31. An operation result register provided as one of the operation control registers, wherein the operation result register is an operation control register for writing a result of the operation performed by the coprocessor unit, and the request packet When the read access to the operation result register is instructed by the command field and the parameter field, data stored in the operation result register is generated as the read data packet. Memorishisu of section 27 or 28
Tem . 32. When the read access to the operation result register is instructed, information as to whether the result of the operation processing has already been written in the instructed operation result register is used as the acknowledgment packet as the packet. 32. The memory system of claim 31, transmitting to a type memory / coprocessor bus. 33. When the read access to the operation result register is instructed, information indicating whether or not the result of the operation processing has already been written in the instructed operation result register is included in the read data packet. 32. The memory system according to claim 31, wherein the data is transmitted to the packet type memory / coprocessor bus. 34. The parameters necessary for the coprocessor portion of the said operation control register to perform an arithmetic process after setting by the write access, the co said by write access the to the calculation start register 31. The memory system according to claim 29, wherein the arithmetic processing of a processor unit is started, and the coprocessor unit executes the arithmetic processing with reference to the arithmetic control register. 35. The coprocessor unit writes a result of an operation process to an arbitrary number of the operation control registers, and a part of the operation result is successfully read by the read access to the operation result register. 34. The method according to claim 31, wherein the remaining portion of the operation result is read by the read access to the operation control register.
Memory system . 36. The computing control register during execution of a computing process.
Claim a portion of static said coprocessor unit in question, characterized by using for the purpose of holding the intermediate result in executing the arithmetic processing of the 29,30,31,32,3
36. The memory system according to 3, 34, or 35. 37. An external select-in terminal and an external select-out terminal are provided as external input / output terminals, and an internal select-in terminal and an internal select-out terminal are provided in all of said memory section and said N coprocessor sections. The internal select-out terminal of a certain memory unit or the coprocessor unit and the internal select-in terminal of another memory unit or the coprocessor unit are connected in any order between the unit and the N coprocessor units. To form a one-dimensional memory unit-coprocessor unit chain, and connect the external select-in terminal and the memory unit at the head of the memory unit-coprocessor unit chain or the internal select-in terminal of the coprocessor unit. Connected to the external select-out terminal and the memory at the end of the chain of the memory unit and the coprocessor unit. Li portion or the coprocessor unit the internal select-out claims, characterized in that to connect the terminal 1, 2 or 3 coprocessor internal packet type memory LSI according, of. 38. As an initialization operation, an operation of setting the memory device ID or the coprocessor device ID to the same predetermined initial state value, and outputting a logical value 0 from all the internal select-out terminals. After the initialization operation, the memory section or the coprocessor section in which the memory device ID or the coprocessor device ID is set in the initial state value is the memory section or the coprocessor section. While the logical value 0 is being input from the internal select-in terminal of the coprocessor unit, the write access to the memory unit or the coprocessor unit is ignored, and a logical value is input from the internal select-out terminal. Outputs a value of 0, and the internal selection of the memory unit or the coprocessor unit. When a logical value of 1 is input from the input terminal, the request is sent to the memory device ID register or the coprocessor device ID register in response to the write access to the memory unit or the coprocessor unit. The write access of the memory device ID or the coprocessor device ID specified by the parameter field in the packet is performed, and a logical value of 1 is output from the internal select-out terminal.
38. The method of controlling a packet-type memory LSI with a built-in coprocessor according to claim 37, wherein 39. The external select-out terminal and the external select-in terminal of a plurality of packet-type memory LSIs with a built-in coprocessor connected to a packet-type memory / coprocessor bus according to claim 38. connect to constitute a coprocessor internal packet type memory LSI chain, an external select-in terminal and the external select-out terminal is provided to the bus master, said external select-out terminal and said coprocessor internal packet type memory LSI chain of said bus master Connecting the external select-in terminal of the coprocessor built-in packet type memory LSI at the head of
A memory system, comprising: connecting the external select-out terminal of the coprocessor built-in packet type memory LSI at the end of the coprocessor built-in packet type memory LSI to the external select-in terminal of the bus master. 40. The initialization operation is performed on all of the packet-type memory LSIs with built-in coprocessors to set all of the memory device IDs and all of the coprocessor device IDs to the initial state values, and After setting the external select-out terminal and all the internal select-out terminals to a logical value of 0, the bus master drives its own external select-out terminal to a logical value of 1 to change the initial state value to the device value. By transmitting the write packet in which the new memory device ID or the coprocessor device ID specified in the ID field is specified in the parameter field, the coprocessor built-in packet type memory LSI chain at the head of the coprocessor built-in packet type The memory unit in the memory LSI Tsu sets the memory device ID or the coprocessor device ID to the memory unit or said coprocessor portion of the top of the support unit chain,
Subsequently, the logical value 1 is sequentially transferred between the memory unit or the coprocessor unit and the coprocessor built-in packet type memory LSI through the memory unit-coprocessor unit chain and the coprocessor built-in packet type memory LSI chain. In response, the bus master transmits the write packet in which the initial state value is specified in the device ID field and the new memory device ID or the coprocessor device ID is specified in the parameter field. , The memory device I of the memory unit or the coprocessor unit
By setting D or the coprocessor device ID, any of the memory units and any of the coprocessor units in all the coprocessor built-in packet type memory LSIs connected to the packet type memory / coprocessor bus are set. The memory device ID and the coprocessor device ID capable of uniquely identifying which of the memory unit or the coprocessor unit is specified between the memory unit and the coprocessor unit are set. The method for controlling a memory system according to claim 39. 41. A device definition register is provided as each of the memory control register and the operation control register, and device definition information is stored in advance in the device definition register, and the device definition information is stored in the memory unit and the coprocessor unit. 4. The packet-type memory LSI with a built-in coprocessor according to claim 2, wherein the information is information indicating which one is. 42. A bus master receives the device definition information by designating the device ID and reading the device definition register in the memory control register or the operation control register.
The coprocessor built-in packet according to claim 41, wherein the bus master recognizes whether the specified device ID is given to the memory unit or to the coprocessor unit. Type memory LS
I control method. 43. A request packet for requesting a read from the device definition register, regardless of whether the read operation is performed on the memory section or the coprocessor section, only when the device ID field is specified. 43. The packet memory with built-in coprocessor LS according to claim 42, wherein the request packets are different.
I control method. 44. A function definition register is provided as the operation control register, and a function definition code is stored in the function definition register in advance, and the function definition code is a code that classifies an operation processing function of the coprocessor unit. The packet-type memory LSI with a built-in coprocessor according to claim 2 or 3, wherein: 45. The bus master receives the function definition code by designating the device ID and reading the function definition register in the operation control register. The method of controlling a packet-type memory LSI with a built-in coprocessor according to claim 44, wherein an operation processing function of the coprocessor unit corresponding to the following is recognized.