JPH11205284A - Code division multiplex communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by providing a current source to a current delay means and an adder subtractor means and cutting off a current from the current source through the current delay means within a transfer period when a current signal is transferred to a post-stage sample-and-hold circuit. SOLUTION: A current delay means 102 consists of sample-and-hold circuits that are current flip-flop circuits 1021 -102n . Number of the current flip-flop circuits 1021 -102n . are selected to be an integer multiple of 128 when number of arranged chip information sets are 128. A current signal corresponding to a voltage signal reaches the top current flip-flop 1021 every moment. The top sample-and-hold circuit of the current delay means 102 receives the current signal to sample and hold the current signal based on a clock signal and the means 102 delays the current signal that is respectively sampled and held in pre-stages and transfers the delayed signal to post-stages sequentially. The voltage signal is spread-modulated by the chip information and the current delay means 102 generates the current signals including inherent arrangement of the chip information in time series.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to spread spectrum communication, and more particularly to a low power consumption type code division multiplex communication apparatus capable of high-speed synchronization.

[0002]

2. Description of the Related Art Code division multiplex communication (CDMA)
Division Muitiple Access) has an elegant quality deterioration characteristic that the communication quality gradually deteriorates while other multiplex communication systems (FDMA, TDMA) are unacceptable for a certain user or more. (Graceful deg
radation), setting of code synchronization is as permissible as possible, and an increase in the number of users can be expected. In addition, they are excellent in interference resistance, signal concealment, and fading resistance, and are being widely used.

[0003] A CDMA communication apparatus includes:
The baseband data to be transmitted is multiplied by a spreading code and further multiplied by a carrier and transmitted from an antenna. Then, the receiving apparatus prepares a despreading code having the same phase as the spreading code at the time of transmission, and extracts it as baseband data using a correlator.

Conventionally, a sliding correlator and a SAW (Surface Acoustic Wa) have been used as correlators.
ve) Matched filters, digital LIS matched filters and the like are known.

[0005] The sliding correlator circulates the spreading code earlier than the received signal, and generates a DLL (Delay Lock).
ed Loop) and the like, the synchronization is pulled in. The sliding correlator is supplied with a signal having a carrier component removed by synchronous detection or a means equivalent thereto, that is, a signal having a frequency of about the chip rate. This sliding correlator has the disadvantage that chip synchronization is required and that synchronization acquisition takes time. There is a drawback that a received signal containing a carrier component cannot be input to a sliding correlator.

The SAW matched filter is capable of high-speed chip synchronization and can be used in the RF and IF bands. However, since the spreading code is determined by the physical pattern of the SAW device, it is difficult to change the code. There are drawbacks that are difficult to deal with.

The digital LSI matched filter has the advantage that chip synchronization is not required and that the spreading code can be easily changed, but has the disadvantage of large power consumption. The digital LSI matched filter based on the conventional CMOS integrated circuit technology has a disadvantage that it can be generally used only in the baseband band because of its low operation speed.

[0008]

In recent years, mobile communication (such as a mobile phone) has been widely used. And
As the communication system used for this mobile communication, the above-mentioned CDMA has received the most attention. It is desirable that the CDMA correlator used in the mobile communication satisfies all of the following requirements.

1. 1. Can support long spreading codes. 2. Operable in RF and IF bands. 3. Programmability of spreading code. 4. Low power consumption. However, none of the above-mentioned conventional correlators can satisfy all of the above-described requirements.

Therefore, recently, a correlator using the switched capacitor method has been developed and is being put to practical use. This correlator is a further improvement of the digital LSI matched filter, and can reduce the power consumption to about 1/10 as compared with the digital LSI matched filter. However, the operation speed is slow (up to 25 MHz), and the RF, IF There is a drawback that cannot be used for band matching.

The present invention has been made under such a background, and can cope with long spreading codes, can be operated in RF and IF bands, and can easily change spreading codes.
It is another object of the present invention to provide a code division multiplex communication device that consumes less power.

[0012]

According to a first aspect of the present invention, there is provided a code division multiplex communication apparatus which receives a transmission radio wave generated by multiplying an information signal by spread data comprising an array of chip information and outputs a voltage signal. Receiving means, a voltage / current converting means for converting the voltage signal into a current signal, and a sample and hold circuit whose number is an integral multiple of the array number of the chip information. The current information signal is sampled and held based on the input clock signal, and the current signal held by the previous sample and hold circuit is sequentially delayed and transferred to the subsequent sample and hold circuit. Current delay means for generating a time series of the output current signal, and a time series current held by each of the sample and hold circuits. And a current source is provided in the current delay means and the addition / subtraction means. It is characterized in that a current cut means for cutting in a transfer period for transferring to the hold circuit is provided.

According to a second aspect of the present invention, in the code division multiplex communication apparatus, the adding / subtracting means includes a first addition system and a second addition system, and the first addition system and the second addition system are connected to each other. Only the positive current signal is collected when the array of chip information potentially implicit in the time series of the current signal matches the predetermined array of chip information of the despread data corresponding to the array of chip information. Connected to each of the sample-and-hold circuits in accordance with the arrangement of the chip information of the despread data so as to obtain an added current obtained by adding the negative current signal and an added current obtained by collecting and adding only the negative current signal.
The correlation current signal is generated by subtracting the addition current of the second addition system from the addition current of the addition system.

According to a third aspect of the present invention, in the code division multiplex communication apparatus, the adding / subtracting means is provided with a current cutting means for cutting a current flowing from the current source during a transfer period for transferring the current to a subsequent sample and hold circuit. It is characterized by being.

According to a fourth aspect of the present invention, in the code division multiplex communication apparatus, the voltage / current converting means outputs a negative current signal when the voltage signal is positive and a positive current signal when the voltage signal is negative. , And a differential amplifier circuit and a voltage follower circuit are connected.

According to a fifth aspect of the present invention, in the code division multiplex communication apparatus, a correlator is constituted by at least the current delay means and the addition / subtraction means.

According to a sixth aspect of the present invention, in the code division multiplex communication apparatus, each of the sample-and-hold circuits comprises a current flip-flop.

According to a seventh aspect of the present invention, in the code division multiplex communication apparatus, the first clock pulse is generated in time series with the clock signal, and the second clock pulse is generated in time series with a phase opposite to the first clock pulse. A first sample-and-hold circuit for sampling the current signal at a rising edge of the first clock pulse and holding the current signal at a falling edge to delay the current signal; The current signal held by the sample-and-hold circuit is sampled at the rising edge of the second clock pulse and held at the falling edge, and the held current signal is transferred to the next-stage current flip-flop and output to the addition / subtraction means. And a two-sample hold circuit.

The code division multiplex communication apparatus according to claim 8, wherein the correlator includes a despread data generator for generating an array of chip information of the despread data, and the current delay means and the addition / subtraction means are connected to each other. In the meantime, based on the despread data output from the despread data generator, an array of chip information potentially implicit in the time series of the current signal is set corresponding to the array of chip information. The first addition is performed so that an added current obtained by collecting and adding only positive current signals and an added current obtained by collecting and adding only negative current signals are obtained when the arrangement matches the chip information arrangement of the despread data. Connection state switch means for switching a connection state between the system and the second addition system with respect to each of the current flip-flops is provided.

According to a ninth aspect of the present invention, in the code division multiplex communication device, the first sample-and-hold circuit includes a first current source, a first MOS transistor, a first sample-and-hold switch, and a second sample-and-hold switch. The drain of the first MOS transistor is connected to the first current source, the source of the first MOS transistor is grounded, the first and second sample and hold switches are turned on and off simultaneously based on the first clock pulse, and the current signal is Input to the drain of the first MOS transistor via the first sample and hold switch;
The second sample hold switch is connected to the first MOS.
A second transistor connected between the gate and the drain for short-circuiting the gate and the drain of the transistor;
The sample-and-hold circuit comprises a first system which is composed of a second current source and a second MOS transistor and outputs a held current signal to a next-stage current flip-flop, and which is composed of a third current source and a third MOS transistor and is held. A second system for outputting a current signal to the addition / subtraction means; a third sample / hold switch; and a fourth sample / hold switch. The drain of the second MOS transistor is connected to a second current source and the third sample / hold is connected. The second MOS transistor is connected to the drain of the first sample and hold circuit via a switch, the source of the second MOS transistor is grounded, and the fourth sample and hold switch is connected to the gate of the second MOS transistor to short-circuit the gate and the drain of the second MOS transistor. The third M The drain of the S transistor is connected to a third current source, the source of the third MOS transistor is grounded, the gate of the third MOS transistor is connected to the gate of the second MOS transistor, and the third and fourth sample hold switches are The switch is turned on and off at the same time based on the second clock pulse.

According to a tenth aspect of the present invention, in the code division multiplex communication apparatus, each of the MOS transistors is an n-channel MOSFE.
T.

According to a twelfth aspect of the present invention, in the code division multiplex communication apparatus, each of the current sources comprises a p-channel MOSFET.

According to a twelfth aspect of the present invention, in the code division multiplex communication apparatus, each of the MOS transistors has an n-channel MOSFET and a p-channel MOSF so that a saturation characteristic is improved.
It is characterized by comprising an equivalent MOSFET combined with ET.

A code division multiplex communication apparatus according to claim 13, wherein said equivalent MOSFET is provided with said n-channel MOS.
It is characterized in that three FETs are used, one p-channel MOSFET is used, and the whole operates as an n-channel MOSFET.

According to a fourteenth aspect of the present invention, in the code division multiplex communication apparatus, each of the current sources comprises an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined so as to improve a saturation characteristic. I do.

The code division multiplex communication apparatus according to claim 15, wherein said equivalent MOSFET is provided with said p-channel MOS.
It is characterized in that three FETs are used, one n-channel MOSFET is used, and the whole operates as a p-channel MOSFET.

In the code division multiplex communication apparatus according to the present invention, the first sample-and-hold circuit may include a first current source M
An OS transistor, a first sample and hold MOS transistor, a first sample and hold switch, and a second sample and hold switch are provided, and the drain of the first sample and hold MOS transistor is connected to the drain of the first current source MOS transistor. A source of the first sample and hold MOS transistor is grounded, the current signal is input to a drain of the first sample and hold MOS transistor via a first sample and hold switch, and the second sample and hold switch is The first sample-hold MOS transistor is connected between the gate and the drain to short-circuit the gate and the drain of the MOS transistor, and the first sample-hold switch is turned on / off based on the first clock pulse. A synchronous switch that is turned on and off in synchronization with the second sample and hold switch is connected to the gate of the flow source MOS transistor, and is injected into a parasitic capacitance between the gate and the source of the first sample and hold MOS transistor. A first short-circuit switch for short-circuiting the gate and the drain of the first current source MOS transistor is connected between the gate and the drain of the first current source MOS transistor to generate a fluctuation current corresponding to a current fluctuation based on the injection current. The first synchronous switch and the second sample-and-hold switch receive a third clock pulse and are turned on in the first half of the on-period of the first sample-and-hold switch. Is input and turned on in the latter half of the ON section, and the current fluctuation is compensated for by the fluctuation current. Characterized in that it.

The code division multiplex communication apparatus according to claim 17, wherein the second sample-and-hold circuit comprises a second current source M
A first system that includes an OS transistor and a second sample-hold MOS transistor and outputs a held current signal to a current flip-flop at the next stage; a third current source MOS transistor and a third sample-hold MOS transistor
A second system comprising a transistor and outputting the held current signal to the addition / subtraction means; a third sample / hold switch and a fourth sample / hold switch;
The drain of the second sample and hold MOS transistor is connected to the drain of the second current source MOS transistor and to the drain of the first sample and hold circuit via the third sample and hold switch. The source of the sample and hold MOS transistor is grounded, the held current signal is input to the drain of the second sample and hold MOS transistor via the third sample and hold switch, and the fourth sample and hold switch is connected to the fourth sample and hold switch. The third sample and hold switch is connected between the gate and the drain to short-circuit the gate and the drain of the two-sample and hold MOS transistor, and the third sample and hold switch is turned on and off based on the second clock pulse.
A second synchronous switch that is turned on and off in synchronization with the fourth sample and hold switch is connected to the gate of the current source MOS transistor.
The gate of the second current source MOS transistor and the drain are short-circuited to generate a variation current corresponding to a current variation based on an injection current injected into a parasitic capacitance between the gate and the source of the OS transistor. Connected to the second sample-and-hold MO
The drain of the S transistor is connected to the drain of the third current source MOS transistor, the source of the third sample and hold MOS transistor is grounded, and the gate of the third sample and hold MOS transistor is connected to the second sample and hold MOS transistor. A gate of the third current source MOS transistor is connected to a gate of the second current source MOS transistor, and the second synchronous switch and the fourth sample hold switch are connected to a fifth clock. A pulse is input and turned on in the first half of the on-period of the third sample and hold switch, and the second short-circuit switch is turned on in the latter half of the on-period of the third sample and hold switch when the sixth clock pulse is input and Offset the current variation by the variation current And wherein the door.

The code division multiplex communication apparatus according to claim 18 is characterized in that each of the sample MOS transistors comprises an n-channel MOSFET.

The code division multiplex communication apparatus according to claim 19, wherein each of the current source MOS transistors is a p-channel MOS transistor.
It is characterized by comprising an OSFET.

According to a twentieth aspect of the present invention, in the code division multiplex communication apparatus, each of the sample-and-hold MOS transistors includes:
Equivalent MOS in which an n-channel MOSFET and a p-channel MOSFET are combined to improve the saturation characteristics
It is characterized by comprising an FET.

The code division multiplex communication apparatus according to claim 21, wherein said equivalent MOSFET is provided with said n-channel MOS.
It is characterized in that three FETs are used, one p-channel MOSFET is used, and the whole operates as an n-channel MOSFET.

In the code division multiplex communication apparatus according to the present invention, each of the current source MOS transistors comprises an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined so as to improve a saturation characteristic. It is characterized by the following.

The code division multiplex communication apparatus according to claim 23, wherein said equivalent MOSFET has said p-channel MOS.
It is characterized in that three FETs are used, one n-channel MOSFET is used, and the whole operates as a p-channel MOSFET.

According to a twenty-fourth aspect of the present invention, in the code division multiplex communication apparatus, each of the switches comprises a MOS transistor, and each of the MOS transistors has an n-channel MOSFET and a p-channel MOSFET so that the saturation characteristics are improved.
It is characterized by comprising an equivalent MOSFET in which T is combined.

According to a twenty-fifth aspect of the present invention, in the code division multiplex communication apparatus, each of the switches comprises a CMOS switch.

According to a twenty-sixth aspect of the present invention, there is provided a code division multiplex communication apparatus for suppressing a current variation based on an injection current injected into a parasitic capacitance between a gate and a source of each of the sample and hold MOS transistors. The ratio W / L of the gate width W to the gate length L of each MOS transistor is about 62.5 times.

The code division multiplex communication apparatus according to claim 27, wherein the number of said sample and hold circuits is twice the number of arrayed chip information and the number of said sample and hold circuits is the same as said array number. The current signal is sampled with a clock signal having a frequency twice the frequency of the clock signal.

A code division multiplex communication apparatus according to claim 28, wherein current / voltage conversion means for converting the correlation current signal into a voltage signal is provided between the addition / subtraction means and the demodulator. And

A code division multiplex communication apparatus according to claim 29, wherein said current / voltage conversion means receives said correlation current signal and applies a bias voltage, and a sum of a current signal conversion voltage and a bias voltage. Output the first voltage signal
A differential amplifier circuit, a voltage corresponding to the correlation current signal by receiving the sum voltage signal, applying a bias voltage having the same value as the bias voltage, and removing the bias voltage from the sum voltage signal; And a second differential amplifier circuit for outputting a signal.

According to a thirty-fifth aspect of the present invention, in the code division multiplex communication apparatus, the current cutting means is provided on the second current source MOS type transistor side and the third current source MOS type transistor side. I do.

A code-division multiplex communication apparatus according to claim 31, wherein the correlator is provided with a subclock oscillator for receiving the clock signal and generating each clock pulse.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

[0044]

FIG. 1 is a block diagram showing a configuration of a receiving-side code division multiplex communication apparatus according to the present invention. In FIG. 1, 1 is a receiving antenna, 2 is a mixer, 3 is a local oscillator, 4 is a synchronous detector, 5 is a correlator, 6 is a PN code generator, and 7 is a demodulator. The receiving antenna 1 receives a transmission radio wave transmitted by a transmitting device (not shown). This transmission radio wave is generated by multiplying the information signal by spread data composed of an array of chip information. The information signal is bit information in this embodiment. The bit information is composed of “0” and “1”, and this bit information is generated in time series, and a frequency that is the reciprocal of a generation cycle of the bit information is a baseband frequency. The bit information “1” corresponds to, for example, a positive voltage, and the bit information “0” corresponds to a negative voltage (a voltage having an opposite phase).

FIG. 2A shows a section of bit information “1” (one symbol of a data packet). This bit information “1” is multiplied by spread data composed of an array of chip information “0” and chip information “1”. A PN code (pseudo-noise code) is used for the spread data. The PN code includes an M-sequence code, a Gold code, an orthogonal M-sequence code,
There are orthogonal Gold codes, orthogonal codes generated by a Walsh function, and the like, and any of these may be used. An orthogonal M-sequence code, an orthogonal Gold code, and an orthogonal code generated by a Walsh function are suitable for channel division of a code division multiplex communication device because they have correlation characteristics described below. That is, in the case of an orthogonal code, the autocorrelation function has a maximum correlation value when the phase difference is zero. The cross-correlation function has a correlation value of zero when the phase difference is zero. In this embodiment, description will be made assuming that an M-sequence code is used as the PN code.

The number of arrayed chip information is, for example, 128. Note that the arrangement number of chip information is sometimes referred to as “chip length”. FIG. 2B shows a signal voltage corresponding to the arrangement of the chip information. “+1” corresponds to the chip information “1”, and “−1” corresponds to the chip information “0”. The signal shown in FIG. 2B is multiplied by the signal shown in FIG. 1A to generate the spread modulated wave shown in FIG. 2C, and the spread modulated wave shown in FIG. 2) to generate a spread-spectrum transmission radio wave shown in FIG. 2 (2), whereby the bit information "1" is divided into 128 chips and transmitted.

In this embodiment, the information bits are described as being divided into 128 chips. However, for convenience of understanding, the bit information "1" is assumed when the number of arrayed chip information is seven. FIG. 2 (f) and FIG. 2 (g) show the relationship between the chip information and the signal voltage. Here, FIG.
“1110010” is one of the 7-chip H series. When transmitting the bit information “0”, since the bit information “0” corresponds to a negative voltage, the spread modulated wave has an opposite phase to the spread modulated wave shown in FIG. FIG.
In the description, one symbol of a data packet is "code 1 seq
uence "is assigned, but two or more code sequences may be assigned to one symbol of a data packet.

The mixer 2 mixes the received radio wave with the signal output from the local oscillator 3 and outputs an IF (intermediate frequency) signal. The carrier synchronous detector 4 synchronously detects the output of the mixer 2.

The receiving means comprises the receiving antenna 1, the mixer 2, the local oscillator 3, and the carrier synchronous detector 4. The carrier synchronous detector 4 outputs a voltage signal corresponding to the received radio wave to the correlator 5. FIG. 3A shows the received radio wave. FIG. 3B shows a voltage signal corresponding to the spread modulated wave detected by the carrier synchronous detector 4.

As shown in FIG. 4, in this embodiment, the correlator 5 includes a voltage / current conversion means (V / IC) 101, a current delay means 102, and a connection state switching switch means 10.
3, the addition / subtraction means 105, and the current. Voltage conversion means 107
And

As shown in FIG. 5, the voltage / current converting means 101 outputs a negative current signal Iout when the voltage signal Vin is positive, and outputs a positive current signal Iout when the voltage signal Vin is negative. like,
It comprises a circuit in which a differential amplifier circuit 101A and a voltage follower circuit 101B are connected. The differential amplifier circuit 101A has an operation amplifier (hereinafter abbreviated as an operational amplifier) OP1. A resistor R1 is connected to the negative input terminal of the operational amplifier OP1.
, A voltage signal Vin input to the terminal T1 is applied. The positive input terminal of the operational amplifier OP1 is grounded via the resistor R4. The output terminal of the operational amplifier OP1 is connected to its negative input terminal via a resistor R2.

The voltage follower circuit 101B has an operational amplifier OP2. The output terminal of the operational amplifier OP1 is connected to the plus input terminal of the operational amplifier OP2 via a resistor R5. The output terminal of the operational amplifier OP2 is connected to its negative input terminal and to the positive input terminal of the operational amplifier OP1 via a resistor R3. The operational amplifier OP1 operates as a differential amplifier, the operational amplifier OP2 operates as a voltage follower, and the current signal Iout is output from the output terminal T2 to the current delay unit 102 as a current signal Iin.

Here, the ratio R2 / R1 of the resistors R1 and R2 is set to (R2 / R1 = 1), and the ratio R4 / R1 of the resistors R3 and R4.
3 is (R4 / R3 = β), the current signal Iout
Is obtained by the following equation. Iout = − (2β / (1 + β)) × (Vin / R5) The above expression holds whether the voltage signal Vin is positive or negative, and R4
If / R3 = β = 1, it is transformed into the following equation. Iout = − (Vin / R5) For example, when the amplitude value of Vin is ± 1 volt, the resistance R5
Is 20 kohms, the current signal Iout
Is a current of minus plus 50 microamps. This voltage / current converting means 101 may be provided in the receiving means.

The current delay means 102 comprises a sample-and-hold circuit.
As shown in (1), it is composed of a current flip-flop (CDF / F). Reference numerals 102 ₁ , 102 ₂ , 102 ₃ ,
.., 102 _n indicate current flip-flops (CDF / F) as sample hold circuits. Also,
Code T6 ₁ to T6 _n is an input terminal of the current signal, symbol T
Input terminals of _{7 1 ~T7 n, T8 1 ~T8} n clock signals,
Code _{T9 1 ~T9 n, T10 1 ~T10} n ho - an output terminal for field current signal. The number of the current flip-flops (CDF / F) is 128
Number, N times this number 128 (N is an integer of 1 or more)
Is the number of In particular, in the following description, it is assumed that N = 1 unless otherwise specified.

FIG. 6 shows each current flip-flop (CDF /
It is a principle diagram which shows the internal structure of F). FIG. 6 shows the current flip-flop 102 ₁ , but the same applies to the other current flip-flops 102 ₂ , 102 ₃ ,..., 102 _n . The CDF / F 102 ₁ includes a first sample hold circuit SH1 and a second sample hold circuit SH
And 2. First sample hold circuit S
H1 has sample-hold n-type MOS transistors (n-channel MOSFETs) M1 and M2 and current cut-off n-type MOS transistors M100 and M101. The sources of the n-type MOS transistors M100 and M101 are grounded. Each n-type MOS transistor M10
0, M101 are drains of each n-type MOS transistor M
1, connected to the source of M2. The drain of the n-type MOS transistor M1 is connected to a power supply Vd via a constant current source A1.
is connected to d, it is connected to the input terminal T6 _1. The gate of the n-type MOS transistor M1 is connected to its drain. n-type MOS transistor M
2 is connected to a power supply Vdd via a constant current source A2. The gate of the n-type MOS transistor M2 is connected to the gate of the n-type MOS transistor M1 via the sample hold switch SW1.

The second sample-and-hold circuit SH2 has sample-and-hold n-type MOS transistors (n-channel MOSFETs) M3 to M5 and current cut-off n-type MOS transistors M102 to M104. The sources of the n-type MOS transistors M102 to M104 are grounded. The drains of the n-type MOS transistors M102 to M104 are connected to the sources of the n-type MOS transistors M3 to M5. The drain of the n-type MOS transistor M3 is connected to the power supply Vdd via the constant current source A3 and to the drain of the n-type MOS transistor M2. The gate of the n-type MOS transistor M3 is connected to its drain. n-type MOS transistor M4
The drain is connected to the output terminal T9 ₁ is connected to the power source Vdd via a constant current source A4. n-type MO
The gate of the S transistor M4 is connected to the gate of the n-type MOS transistor M3 via the sample hold switch SW2. The drain of the n-type MOS transistor M5 is connected to an output terminal T10 ₁ is connected to the power source Vdd via a constant current source A5. Each n-type MOS
The gates of the transistors M100 to M104 are connected to each other, and the current application clock pulse WS is input to each of these gates. The gate of the n-type MOS transistor M5 is connected to the gate of the n-type MOS transistor M4. The symbol C1 is a parasitic capacitance between the gate and the source of the n-type MOS transistor M2, and the symbol C2 is
This is a parasitic capacitance between the gate and the source of the OS transistors M4 and M5.

Sample hold switches SW1, SW2
Are turned on and off by the clock signal W. Each n-type MO
The S transistors M100 to M104 are turned on and off by the current energizing clock pulse WS. Clock signal W
As shown in FIGS. 7A and 7B, the first clock pulse W1 generated in time series and the on-period of the first clock pulse W1 having the same period as the first clock pulse W1 and having the same phase. And a second clock pulse W2 generated in a time series with a shift of the width T01. The width T02 of the ON period of the second clock pulse W2 is the same as T01.
The energizing clock pulse WS is turned on when either the first clock pulse W1 or the second clock pulse W2 is turned on. Here, the width T03 of the on-period of the current energizing clock pulse WS is the width of the on-period of the pulse of the clock signal W (T01 + T02). Constant current source A
1. The current value J flowing through A2 is the same under ideal conditions. The current value J flowing through the constant current sources A3 to A5 is also the same as A1 and A2 under ideal conditions. Also, n
The ratio (W / L) of the gate width W to the gate length L of the type MOS transistors M1 and M2 is the same. Also, n-type M
The ratio of the gate width W to the gate length L of the OS transistors M3 to M5 is also the same (see FIG. 8 for the gate length L and the gate width W of the MOS transistor).

With this configuration, the magnitude of the current signal Iin input to the first sample and hold circuit SH1 and the magnitude of the current signal Is transferred to the second sample and hold circuit SH2 after being held by the first sample and hold circuit SH1. Ideally, the absolute values can be equal. The current signal Iou output from the second sample hold circuit current signal Is and the output terminal T9 ₁ to be input to SH2, T10 ₁
Ideally, the absolute values of the magnitudes of t can be made equal. Also,
When the current values of the constant current sources A1 to A5 are made equal, all of the n current flip-flops can be constituted by the same circuit, which facilitates circuit design.

Sample hold switches SW1, SW2
For example, an n-type MOS transistor is used.
This n-type MOS transistor has a power supply voltage V
When dd is applied, the drain-source becomes conductive (on), and when the voltage applied to the gate is zero, the drain-source is cut off (off).

"1" of the clock pulses W1 and W2 corresponds to the power supply voltage Vdd, and "0" of the first clock pulse W1 corresponds to the power supply voltage of zero. Accordingly, the sample and hold switches SW1 and SW2 are turned on when "1", and turned off when "0". The phases of the first clock pulses W1 and W2 are different between the sample and hold switches SW1 and SW2. T01
, They will not be turned on at the same time.

When both the first clock pulse W1 and the second clock pulse W2 are off, the current supply clock pulse WS is off, so that the constant current sources A1-A
5 from the n-type MOS transistors M1 to M5
Does not flow to the ground through the drain-source of the IGBT, that is, since J = 0, no power is consumed. Here, as shown in FIG. 7 (c), when the first clock pulse W1 is inputted at time t _1,
The current energizing clock pulse WS is input, and each n-type M
The OS transistors M100 to M104 are turned on, and the current J flows. At time t ₁ the first clock pulse W1
Is "1". On the other hand, the second clock pulse W
2 remains "0". When the first clock pulse W1 becomes "1", the sample hold switch S
W1 is turned on (closed). Since the second clock pulse W2 remains "0", the sample hold switch S
W2 remains off (open). By closing the sample hold switch SW1, the gate of the n-type MOS transistor M1 and the n-type MOS transistor M2
Is short-circuited to the gate. Sample hold switch S
Since W2 remains open, the gate of the n-type MOS transistor M3 and the gate of the n-type MOS transistor M4 remain disconnected.

Here, assuming that the current signal Iin is inputted slightly before the time t ₁ , the current signal Iin becomes n
The current Ia flows between the drain and source of the type MOS transistor M1, and the current Ia becomes "J + Iin".

The current system of the n-type MOS transistor M1 and the current system of the n-type MOS transistor M2 form a current mirror circuit by closing the sample-and-hold switch SW1. The same current “J + Iin” as the current “J + Iin” flowing through the n-type MOS transistor M1 is provided between the sources.
Iin "flows. Thus, the current signal Is transferred from the drain side of the n-type MOS transistor M2 to the drain side of the n-type MOS transistor M3 is Is = −Ii
n, and the transfer current Is (= −Iin) is generated.
The transfer current Is causes the n-type MOS transistor M3
As shown in FIG. 7 (f), a current "J-Iin" flows between the drain and the source of the n-type MOS transistor M2. Samples the current signal Iin by this process.

Next, at time t ₂ , when the clock pulse W 1 becomes “0” and the clock pulse W 2 becomes “1”,
The sample hold switch SW1 is turned off (open),
The sample hold switch SW2 is turned on (closed). When the sample and hold switch SW1 is opened, the gate of the MOS transistor M1 is separated from the gate of the MOS transistor M2. However, the current “J + Iin” flows due to the presence of the parasitic capacitance C1 between the drain and the source of the MOS transistor M2. Since the charge that can continue to flow continues to be accumulated, the current signal Is also becomes “−Iin”.
Will continue to be held.

[0065] In addition, at time t _2, by the sample-and-hold switch SW2 is closed, the gate and the MOS transistor of the MOS transistor M3 M4, M
The gate of 5 is shorted. The current system of the MOS transistor M3 and the current system of the MOS transistors M4 and M5 similarly form a current mirror circuit by closing the sample-and-hold switch SW2. Is "J-Iin". as a result,
Terminal T9 _1, current signal Iou output from the terminal T10 ₁
t is the current signal “I” input as shown in FIG.
in ". Also, the MOS transistor M
4. Charge is injected into the parasitic capacitance C2 between the drain and source of M5 to be charged.

Next, at time t _3, the second clock pulse W2 becomes "0", and accordingly, current energizing clock pulse WS is turned off. As a result, each MO
The S transistors M100 to M104 are turned off, and the current flowing between the drain and source of each of the MOS transistors M1 to M5 is cut off. When the sampling switch SW2 is opened, the MOS transistor M
3 is separated from the gates of the MOS transistors M4 and M5.
The electric charge enough to keep the current “J-Iin” flowing is held.

[0067] Then, Ts is turned on again at time t _4, the n-type MOS transistor M100~M104 becomes conductive, the gate of the MOS transistor M4, M5 - the parasitic capacitance (floating capacitance) C2 between the source "J-Iin As a result, the electric charge enough to flow the current of “I” continues to be stored.
n current flows. That is, Iin sampled in the sampling section from t _{1 to} t ₂ (portion A in FIG. 7D).
But, in the next sampling interval (t ₄ ~t _5), it is output (A 'portion in FIG. 7 (g)). Similarly, the current zero sampled in the sampling interval from t ₄ to t ₅ (FIG. 7)
Shown by B in (d)), the next sampling interval t ₇ ~t ₈
Is also output as zero (FIG. 7 (g)).
B '). Thus t ₃ ~t ₄ or t ₆ ~t ₇
In the section indicated, even if the time interval in which no current flows until the ground from the power supply via a current source A1 to A5, the input current sampled at a sampling interval (e.g., t ₁ ~t ₂₎ follows the sampling It is possible to transfer to a section (for example, t _{4 to} t ₅ ), that is, delay by one clock.

In the above description, the order of the first and second clock pulses W1 and W2 is temporally "W1 → W2" while the current-supplying clock pulse WS is on. The operation is possible even if the current application clock pulse WS is turned on in the order of “W2 → W1” within the on time.

Therefore, the second sample and hold circuit SH2
Samples the current signal held by the first sample-and-hold circuit SH1 at the rising edge of the second clock pulse SW2 and holds it at the falling edge to transfer the held current signal to the next-stage current flip-flop and add / subtract means 105 Will be output.

A current signal corresponding to the voltage signal arrives at the head current flip-flop 102 _{1 every} moment, and the current delay means 102 inputs the current signal to the head sample-hold circuit and converts the current signal based on the clock signal. The sample and hold is performed, and the current signal held by the preceding sample and hold circuit is sequentially delayed and transferred to the subsequent sample and hold circuit. Since the voltage signal is spread modulated by the chip information, the current delay means 102 generates a time series of the current signal in which the arrangement of the chip information is potentially implicit.

The connection state changeover switch means 103 is provided between the current delay means 102 and the addition / subtraction means 105. This connection state changeover switch means 103 includes input terminals T11 ₁ to T11 ₁ to which a held current signal is input.
T11 _n, PN code generator 6 input terminals T12 ₁ to despread data is input to generate a sequence of chip information of the despread data generated from ~T12 _n, output terminals T13, T1
4. The switches 104 _{1 to} 104 _n are provided. The PN code generator 6 functions as a despread data generator. This P
When the information bits are subjected to spread modulation by the spread data of the array of chip information “1110010” (array number 7), for example (when n = 7), the N code generator 6 sets the array of chip information of the spread data “1110010”. Is generated from the array of chip information “1110010” corresponding to. The despread data is input terminal T12 ₁ through T
Inputted to the switch 104 _{1-104 7} through 12 _7.

Each of the switches 104 _{1 to} 104 _n is, for example, as shown in FIG.
And an n-type MOS transistor M20 and a p-type MOS transistor M21. FIG. 9 typically shows the switch 104 ₁ . The n-type MOS gate of the transistor M20 and p-type gate of the MOS transistor M21 is connected to the input terminal T12 _1, the drain of the n-type MOS transistor M20 and p-type MOS transistor M
The 21 source is connected to the input terminal T11 _1, n-type M
The source of the OS transistor M20 is connected to the output terminal T13 _1, the drain of the p-type MOS transistor M21 is connected to the output terminal T14 _1. When chip information “1” of despread data is input to input terminal T12 ₁ , n-type M
The OS transistor M20 is turned on (conduction between the drain and source), the p-type MOS transistor M21 is turned off (nonconduction between the drain and source), and when the chip information of the despread data is "1", the input terminal T11 ₁ and the output terminal T13 ₁ are connected. Also, the input terminal T
12 ₁ When the despread data chip information "0" is input to the n-type MOS transistor M20 is turned off - is (drain-source non-conducting state), p-type MOS transistor M
When the chip information of the despread data is "0", the input terminal T1 is turned on (conduction between the drain and the source).
1 ₁ and the output terminal T14 ₁ is connected. For example, sequences of despread data, when "1110010", the input terminals T11 ₁ ~T11 ₇ and the output terminals T13 _1, T14 ₁
FIG. 10 shows the state of connection with. Each output terminal T13 ₁ ~T13 _n are commonly connected to a terminal T13, T14 ₁ ~T14 _n each output terminal is connected in common to the terminal T14.

The addition / subtraction means 105 simultaneously receives the time-series current signals held by the respective sample-and-hold circuits, and outputs a correlation current signal. The addition / subtraction means 105 includes a first addition system 106A and a second addition system 106B. As shown in FIG. 11A, the first addition system 106A includes n-type MOS transistors M32 and M32 having a common source.
33, constant current sources A32 and A33, an input terminal T15, and an output terminal T17. The second addition system 106B has common source n-type MOS transistors M30 and M31, constant current sources A30 and A31, and an input terminal T16. The input terminal T15 is connected to the terminal T13, and the input terminal T16 is connected to the terminal T14. n-type MOS transistor M3
The drain of 0 is connected to the input terminal T16 and to the power supply Vdd via the current source A30. n-type M
The gate of the OS transistor M30 is connected to its drain. The drain of the n-type MOS transistor M31 is connected to the power supply Vdd via the current source A31 and to the drain of the n-type MOS transistor M32. The gate of the n-type MOS transistor M31 is n-type M
It is connected to the gate of OS transistor M30. n
The drain of the MOS transistor M32 is a current source A32
To the power supply Vdd. The gate of the n-type MOS transistor M32 is connected to the drain.
The gate of the n-type MOS transistor M33 is connected to the gate of the n-type MOS transistor M32. n-type MO
The drain of the S transistor M33 is connected to the power supply Vdd via the current source A33 and to the output terminal T17. The terminal T16 has a current Im from the terminal T14.
Flows into the terminal T15 and the current Ip from the terminal T13
Flows in. The current system of the n-type MOS transistor M30 and the current system of the n-type MOS transistor M31 constitute a current mirror circuit, and a current “J + Im” flowing between the drain and the source of the n-type MOS transistor M30.
The same current "J + Im" as n-type MOS transistor M3
1 flows between the drain and the source. Similarly, n-type MOS
The current system of the transistor M32 and the current system of the n-type MOS transistor M33 also constitute a current mirror circuit. A current "J + (Ip-Im) obtained by adding a current J from the current source A32 to a current" (Ip-Im) "obtained by subtracting the current Im from the current Ip flowing into the terminal T15 between the drain and the source of the n-type MOS transistor M32. ) "Flows and n
The same current “J + (Ip−Im)” as the current flowing between the drain and source of the n-type MOS transistor M32 flows between the drain and source of the type MOS transistor M33,
As a result, output current I output from output terminal T17
out is "-(Ip-Im)".

An array of chip information is potentially implicit in the time series of the current signal. When the time series of the current signal corresponding to the array "1110010" of the chip information of the spread data is held, that is, the array "1110010" of the chip information of the despread data predetermined in correspondence with the array of the chip information When they match, the time series of the current signal is, for example, "+ i", "+ i", "+ i", "-i".
i "," -i "," + i ", and" -i ". Four +
The current of i is collected via terminal T13 and the input terminal T1
5 and becomes the current Ip. The three currents of -i are collected via the terminal T14, flow into the input terminal T16, and become the current Im (see FIG. 10). Therefore, the output current Iout becomes “−7i”. The time series of the current signal of the current delay unit 102 changes every moment. Now, for example, when the time series of the current signal corresponding to the array of chip information “0111001” is held, that is, the array of chip information “1110010” of the despread data predetermined corresponding to the array of chip information , The time series of the current signal is, for example, “−i”, “+ i”, “+ i”.
i "," + i "," -i "," -i "," + i ". Therefore, the current Ip is “0” and the current Im is “+ i”. Therefore, the output current Iout becomes “+ i”. Based on the characteristics of the PN code, the output current Iout has a peak when the arrangement of the chip information of the spread data and the arrangement of the chip information of the despread data predetermined in correspondence with the arrangement of the chip information are obtained. Otherwise, no peak output is obtained, and the output current Iout becomes a correlation current signal. In an M sequence having a chip length of N, the peak value becomes N and 1
When a chip is displaced, it becomes "-1".

That is, the first addition system 106A and the second addition system 106B are composed of despread data in which the array of chip information potentially embedded in the time series of the current signal is set in correspondence with the array of chip information. The chip information array of the despread data is obtained so that an added current obtained by collecting and adding only the positive current signals and an added current obtained by collecting and adding only the negative current signals are obtained when they match the array of chip information. Is connected to each sample-and-hold circuit according to the equation (1).
06B is subtracted to generate a correlation current signal. Further, the connection state switching switch means 103 switches the connection state of the first addition system 106A and the second addition system 106B to each current flip-flop based on the despread data.

The output current Iou as the correlation current signal
t is a current / voltage converting means (I
/ VC) 107 is input to the input terminal T18. The current / voltage conversion means 107 includes an addition / subtraction means 105 and a demodulator 7
And converts the correlated current signal into a voltage signal.
As shown in FIG. 12, the current / voltage conversion means 107 includes a first differential amplifier circuit 107A and a second differential amplifier circuit 10A.
7B. First differential amplifier circuit 107A
Is the operation amplifier OP3 and the resistor R10
And The second differential amplifier circuit 107B has an operation amplifier OP4 and resistors R11 to R14. The bias voltage V is applied to the plus terminal of the operational amplifier OP3.
bias is applied. The negative terminal of the operational amplifier OP3 is connected to the input terminal T18, and the output current Iout
Flows in. The resistor R10 is connected between the output terminal of the operational amplifier OP3 and the minus terminal. Operational amplifier O
The plus terminal of P4 is connected to one end of the resistor R11. A bias voltage Vbias having the same value as the bias voltage Vbias applied to the plus terminal of the operational amplifier OP3 is applied to the other end of the resistor R11. Resistance R12
Is connected to the plus terminal of the operational amplifier OP4, and the other end of the resistor R12 is grounded. One end of the resistor R13 is connected to the output terminal of the operational amplifier OP3.
The other end of 3 is connected to the minus terminal of the operational amplifier OP4. The output terminal of the operational amplifier OP4 is an output terminal T19.
Is connected to the input side of the demodulator 7 through the
14 is connected to the minus terminal. Resistance R1
The resistance value of the resistor R3 and the resistance value of the resistor R11 are the same, and the resistance value of the resistor R14 and the resistance value of the resistor R12 are the same.

The bias voltage Vbias is equal to the operational amplifier OP
3, the voltage applied to the minus terminal of the operational amplifier OP3 is equivalently grounded, so that the output current Iout is applied to the resistor R10.
(= Ip−Im) will not flow. Therefore, the bias voltage Vb is applied to the plus terminal of the operational amplifier OP4 so that the output current Iout (= Ip−Im) flows through the resistor R10.
Apply ias. As a result, the drain voltage of the n-type MOS transistor M33 is clamped to the bias voltage Vbias, and the output current Iout (= Ip−
Im) will flow. n-type MOS transistor M
33, the current flowing between the drain and the source hardly changes even if the drain voltage changes, and the bias voltage Vbi
The value of as may be about 1/2 of the power supply voltage Vdd. Here, when the output voltage of the operational amplifier OP3 and _{V 1, V 1 = Vbias- (} R10 × Iout) = Vbias
-R10 (Ip-Im).

The output voltage V ₁ includes the output current Iout
And a bias voltage added to the output voltage corresponding to the output voltage Vout generated at the output terminal T19.
And to the output voltage corresponding to the output current Iout, it must be removed Vbias from the output voltage V _1.

Therefore, the resistor R11 of the second differential amplifier circuit
If the ratio of the resistor R12 (the ratio between the resistors R13 and R14) is designed so that the current flowing through the resistors R12 and R14 becomes (Ip-Im), the bias voltage Vbias is removed from the output terminal of the operational amplifier OP4. Output voltage Vout
(= R14 ((Ip−Im))).

Therefore, the first differential amplifier circuit 107A receives the correlation current signal and receives the bias voltage, and outputs a voltage signal that is the sum of the current signal conversion voltage and the bias voltage. The amplifier circuit 107B receives the sum voltage signal, receives the same bias voltage as the bias voltage, removes the bias voltage from the sum voltage signal, and outputs a correlation voltage signal corresponding to the correlation current signal. The waveform of the correlation voltage signal is shown in FIG.

In this embodiment, the correlator 5 comprises a voltage / current means 101, a current delay means 102, a connection state changeover switch means 104, an addition / subtraction means 105, and a current / voltage conversion means 107. , A current delay unit 102, a connection state changeover switch unit 104, and an addition / subtraction unit 105, it operates as a current input / output correlator. The output terminal of the CDF / F may be directly connected to the addition / subtraction means without providing the connection state switch 104. However, at this time, since the received code string cannot be arbitrarily changed, a fixed code type matched filter is used.

The correlator 5 outputs a peak voltage to the positive side when the bit information is “1” and outputs a peak voltage to the negative side when the bit information is “0” when the correlation is obtained. And a correlation voltage signal generated in time series is input to the demodulator 7. The demodulator 7 integrates the correlation voltage signal and demodulates the information signal (raw information signal) of the original baseband frequency.

In the above description, the current sources A1 to A5, A3
0 to A33 have been described using an equivalent circuit.
A5 to A5 and A30 to A33 can use the p-type MOS transistor M303 shown in FIG. FIG.
3A shows a state in which the current source is represented by an equivalent symbol A301 and the equivalent symbol A301 is connected to an n-type MOS transistor M301 for sample and hold. The n-type MOS transistor M301 is representative of the n-type MOS transistors M1 to M5 and M30 to M33. FIG. 3B is a diagram in which the equivalent symbol A301 is re-expressed by the p-type MOS transistor M303. The drain of the p-type MOS transistor M303 is n-type MO.
The drain of the S transistor M301 is connected, the source is connected to the power supply Vdd, and the gate voltage VEE is appropriately applied to the gate of the p-type MOS transistor M303. This p-type MOS transistor M303 operates as a constant current source when a voltage is applied to its gate.

The current J is determined by the gate length L of the p-type MOS transistor, the gate width W, the ratio W / L of the gate width W to the gate length L, and the gate voltage VEE. The current J is obtained by changing the gate voltage VEE. Can be adjusted and controlled.

In the above description, the number of arrayed chip information n
= 128, the number of current flip-flops was the same (n = 128), that is, N = 1. This sampling method is called a single sampling method. The number of current flip-flops can be increased N times (N is an integer of 2 or more) with respect to the array number n = 128 of chip information. In particular, a sampling method when N is 2 is called a double sampling method. In this case, the number of current flip-flops is 256 and the number of analog switches is also 2.
There are 56 clock signals, and the frequency of the clock signal of the double sampling method is twice the frequency f of the clock signal used in the single sampling method. The connection state of the double sampling type analog switch when the number of arrayed chip information is seven is, for example, as shown in FIG.

In the case of the double sampling system, the frequency (2
In f), since the current signal is sampled, "1110
When the time series of the current signal containing the diffusion chip information “010” is correlated, the time series of the held current signal is “+ i”, “+ i”, “+ i”, “+ i”,
"+ I", "+ i", "-i", "-i", "-i",
"-I", "+ i", "+ i", "-i", and "-i". Therefore, the output current Iout output from the addition / subtraction means 105 is “−14i”, which is a correlation current signal double that of the single sampling method. Next, when the arrangement of the diffusion chip information is shifted by one to “0111001”,
The time series of the current signal held based on the clock signal is shifted by one, and the time series of the held current signal is “−
i "," + i "," + i "," + i "," + i "," +
i "," + i "," -i "," -i "," -i ","-"
i "," + i "," + i ", and" -i ". In this case, the output current Iout output from the addition / subtraction means 105
Becomes “−10i”. Next, when a clock signal is input, the time series of the held current signal is “−i”,
"-I", "+ i", "+ i", "+ i", "+ i",
"+ I", "+ i", "-i", "-i", "-i",
"-I", "+ i", and "+ i". In this case, the output current Iout output from the addition / subtraction means 105 is "-2
i ".

For this reason, in the case of the double sampling method, when a correlation is obtained, the correlation current signal becomes twice as large as that of the single sampling method. No correlation output is obtained.

The current adder 105 can also be configured as shown in FIG. In this figure, M70
Is an n-type MOS transistor, the drain is connected to the power supply Vdd via the constant current source A70 and the n-type MOS transistor M74 and to the terminal T16, the gate is connected to the drain, and the source is grounded. Have been.

M71 is an n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A71 and the n-type MOS transistor M75 and to the terminal T15, and the gate is connected to the n-type MOS transistor. It is connected to the gate of M70, and the source is grounded.

M72 is an n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A72 and the n-type MOS transistor M76, is connected to the terminal T15, and the gate is connected to the drain. , The source is grounded.

M73 is an n-type MOS transistor. The drain is connected to the power supply Vdd via the constant current source A73 and the n-type MOS transistor M77 and to the terminal T17, and the gate is connected to the n-type MOS transistor. M72 is connected to the gate, and the source is grounded.

The n-type MOS transistors M74, M75,
M76 and M77 have their gates connected to the terminal Ts, and are turned on when a voltage higher than the threshold voltage of the n-type MOS transistor is applied to each gate.

Here, the current values of the constant current sources A70 to A73 are the same. Further, a circuit composed of the n-type MOS transistors M70, M71, M74 and M75 and the constant current sources A72 and A73 is an n-type MOS transistor.
When the S-transistors M74, M75, M76, and M77 are in the ON state, that is, in the conductive state, each constitutes a current mirror circuit.

As a basic configuration, the constant current sources A70 and A7
1 are equal, and the "gate width / gate length" ratio of the n-type MOS transistors M70 and M71 is equal. Similarly, the current values of the constant current sources A72 and A73 are equal, and the “gate width / gate length” ratio of the n-type MOS transistors M72 and M73 is equal. Thus, the following operation is performed.

That is, in the above configuration, the terminal T1
Assuming that the current flowing from the terminal 6 is Im, n
The current flowing into the type MOS transistor M71 is also Im. As a result, assuming that the total current flowing from the terminal T15 is Ip, the n-type MOS transistor M72
Is Ip−Im, and therefore, the current Iout output from the output terminal T17 to the outside is −Im.
(Ip-Im).

The current values of the constant current sources A70 and A71, n-type M
"Gate width / gate length" ratio of OS transistors M70 and M71, current values of constant current sources A72 and A73, n-type MOS
"Gate width / gate length" of transistors M72 and M73
If the ratios are not equal, the output current will generally be − (αIp−
βIm). Here, α and β are values determined by each current value and the “gate width / gate length” ratio of each n-type MOS transistor.

The n-type MOS transistors M74, M
The “gate width / gate length” ratio of 75, M76, and M77 is
It is desirable that they be the same so as to have the same on-resistance.

[0098]

Second Embodiment In the first embodiment, a current flip-flop is formed using five constant current sources. From the viewpoint of power consumption, it is desirable that the number of current sources be as small as possible. FIG. 15 shows a specific example of a current flip-flop when three constant current sources are used.

The first sample and hold circuit SH1 has a first
It comprises a current source A51, a first MOS transistor M50, a first sample and hold switch SW11, a second sample and hold switch SW12, and an n-type MOS transistor M53 for interrupting current. The drain of the first MOS transistor M50 is connected to the power supply V via the first current source A51.
dd. n-type MOS transistor M50
Is connected to the drain of the n-type MOS transistor M53. The source of the n-type MOS transistor M53 is grounded. The first and second sample hold switches SW11 and SW12 are turned on and off based on a first clock pulse W1 shown in FIG. Current signal I
in is input to the drain of the first MOS transistor M50 via the first sample and hold switch SW11. The second sample hold switch SW12 is connected to the first M
The OS transistor M50 is connected between the gate and the drain to short-circuit the gate and the drain.

The second sample-and-hold circuit SH2 has the second
A first system 52A comprising a current source A52, a second MOS transistor M51, and an n-type MOS transistor M54 for interrupting current and outputting a held current signal to a current flip-flop of the next stage; a third current source A53 and a third MOS transistor The second system 53A is composed of M52 and an n-type MOS transistor M55 for interrupting current, and outputs a held current signal to the adding / subtracting means 105. The second system 53A includes a third sample hold switch SW21 and a fourth sample hold switch SW22. . The drain of the second MOS transistor M51 is connected to the power supply V via the second current source A52.
dd and the drain of the first sample and hold circuit SH1 via the third sample and hold switch SW21. Second MOS transistor M5
1 is connected to the drain of the n-type MOS transistor M54. The source of the n-type MOS transistor M54 is grounded. The fourth sample hold switch SW22 is connected between the gate and the drain of the second MOS transistor M51 to short-circuit the gate and the drain. Third MOS transistor M5
The drain of No. 2 is connected to the power supply Vdd via the third current source A53. The source of the third MOS transistor M52 is connected to the drain of the n-type MOS transistor M55. The source of the n-type MOS transistor M55 is grounded. The gate of the third MOS transistor M52 is connected to the gate of the second MOS transistor M51. Third and fourth sample hold switches SW2
1, SW22 is turned on and off based on the second clock pulse W2 shown in FIG.

Each n-type MOS transistor M for interrupting current
Gates 53 to M55 are connected to each other, and a current-supplying clock pulse WS shown in FIG.

Here, at time t ₁ , FIG.
As shown in FIG. 16A, the first clock pulse W1 becomes "1", and as shown in FIG.
It is assumed that 2 remains “0”. First clock pulse W
When 1 becomes "1", the sample hold switches SW11 and SW12 are turned on (closed), and the second clock pulse W2 remains "0", so that the sample hold switches SW21 and SW22 are turned off (open). Remains. Since the sample hold switch SW21 remains off, the first MOS transistor M50
Is separated from the drain of the second MOS transistor M51.

Sample hold switches SW11, SW
By 12 is closed, FIG. 16 as shown in (d), the input current signal Iin from V / C101 terminal T6 ₁
Flows into the first sample-and-hold circuit SH1 via
The current signal Iin is input to the drain of the MOS transistor M50, and the current flowing between the drain and the source of the MOS transistor M50 is “J + Iin”. As a result, the current signal Iin is supplied to the sample hold circuit SH1.
Is sampled.

Next, at time t ₂ , it is assumed that the first clock pulse W1 has become “0” and the second clock pulse W2 has become “1”. Then, the first and second sample hold switches SW11 and SW12 are turned off, and the third and
And fourth sample and hold switches SW21 and SW22
Is turned on. The sampling of the current signal is stopped by turning off the first and second sample hold switches SW11 and SW12. The drain of the MOS transistor M50
"J + Ii" exists between the sources due to the presence of the parasitic capacitance C1.
The current “n” continues to flow, whereby the sample and hold circuit SH1 holds the current signal Iin. On the other hand, the third and fourth sample hold switches SW21, SW2
2 is turned on, the drain of the first MOS transistor M50 and the drains of the second and third MOS transistors M51 and M52 are connected, and the first sample and hold circuit S
The current system of H1 and the current system of the second sample and hold circuit SH2 are connected via the third sample and hold switch SW21, and the second and third MOS transistors M51 and M51 are connected.
52, the current signal Is transferred to the drain side is
−Iin, and a transfer current “−Iin” is generated as shown in FIG.

Next, at time t ₃ , when the first clock pulse W 1 remains “0” and the second clock pulse W 2 becomes “0”, the sample and hold switch SW 11
SW12 remains off and the sample hold switch S
W21 and SW22 are turned off. At this time, the second MOS
The current "J-Iin" of the transistor M51 is held by its gate / source parasitic capacitance,
Current "Iin" flows as the current Iout from the constant current source A52 to the terminal T9 _1. At this time, a current “Iin” also flows from the drain of the third MOS transistor M52 to the terminal T101. At this time, the current supply clock pulse WS becomes "0", whereby the MOS transistors M53 to M55 are turned off. Thereafter, at time t
Until ₄ this state continues, the 1MOS transistor M50, the 2MOS transistor M51, the electric charge stored in the parasitic capacitance between the gate / source of the 3MOS transistor M52, the time t ₄ in the same state as the state at time t ₃ Can be resumed.

According to the circuit shown in FIG. 11, the number of constant current sources can be reduced as compared with the circuit shown in FIG.

[0107]

Embodiment 3 n-channel MOSFET, p-channel MO
When the channel length of the SFET is sufficiently large, the drain resistance rd in the saturation region of the drain current-drain voltage characteristic has a very large value, and can be considered to be substantially infinite. However, if the channel length is 1μ
When the size is reduced to m or less, the drain resistance cannot be treated as infinity. That is, the effect of the finite rd becomes apparent, and the characteristics as shown in FIGS. FIG. 17A shows an n-channel MOSFET, and FIG. 17B shows the operating characteristics of the n-channel MOSFET. FIG. 17C shows a p-channel MOSF.
FIG. 17 (2) shows the p-channel MOSFE of FIG.
4 shows the operating characteristics of T.

In FIG. 17A, the sign FETN
(N) is used to mean representatively an n-channel MOSFET. In FIG. 17C, the symbol FETN (p) is used as a representative meaning that it is a p-channel MOSFET. n-channel MOSF
When the drain voltage rd of the ET (FETN (n)) is finite, when the gate voltage Vg is changed to 2 V, 3 V, and 4 V in the increasing direction, the current Idn flowing between the drain and the source increases the drain voltage Vdn. FIG. 17
It changes in a direction to increase as shown in (b).

A p-channel MOSFET (FETN
(P)), when the drain resistance rd is finite and the gate voltage Vg is changed in a decreasing direction to −1 V, −2 V and −3 V, the current Idp flowing between the drain and the source is obtained.
Changes as the drain voltage Vdp decreases, as shown in FIG.

Therefore, when the circuit is designed using the MOS transistors shown in FIGS. 17B and 17B, the correlation current signal output from the correlator 5 accurately corresponds to the input current signal Iin. Will not do.

Therefore, FIG. 17 (b), FIG.
An n-channel MOSFET having the operating characteristics shown in (2)
(FETN (n)) and p-channel MOSFET (FET
N (p)) to form an equivalent MOSFET with improved saturation characteristics.

FIG. 18 (a) shows an equivalent MOSFET corresponding to an n-channel MOSFET, and is denoted by a symbol EFETN (n) in the sense of being equivalent. Also, FIG.
Is the equivalent MOSFET corresponding to the p-channel MOSFET
And the symbol EFETN (p) in the sense of being equivalent
Indicated by

Here, an n-channel MOS equivalent FET
(EFETN (n)) has an n-channel MOSFET
(FETN (n)) are used, and a p-channel MOS
One FET (FETN (p)) is used and operates as an n-channel MOSFET as a whole. Three n-channel MOSFETs (FETN (n)) are sequentially connected to FET1
(N), FET2 (n) and FET3 (n), and their connection states will be described below.

An n-channel MOSFET (FET1
The source of (n) is grounded, and its drain is connected to the source of the n-channel MOSFET (FET2 (n)) and the gate of the n-channel MOSFET (FET3 (n)). n-channel MOSFET (FET1 (n))
Is applied with a gate voltage Vgn. The drain of the n-channel MOSFET (FET2 (n)) is the terminal V
out. Terminals Vout are current sources A1 to A5 shown in FIG. 6, current sources A30 to A33 shown in FIG.
It is connected to current sources A51 to A53 shown in FIG. The gate of the n-channel MOSFET (FET2 (n)) is connected to the drain of the p-channel MOSFET (FETN (p)) and n
It is connected to the drain of a channel MOSFET (FET3 (n)). n-channel MOSFET (FET3
The source of (n)) is grounded. p-channel MOS
The source of the FET (FETN (p)) is connected to the power supply Vdd, and the gate voltage Vreg is applied to the gate of the p-channel MOSFET (FETN (p)).

An n-channel MOS equivalent FET (EFETN)
(N)) shows a p-channel MOSFET (FETN
(P)) operates as a current source. Now, the terminal Vout
When the voltage applied to the MOSFET rises, the n-channel MOSFET
The current Idn flowing between the drain and the source of the (FET2 (n)) increases, and the n-channel MOSFET (FET1
The potential Vdn on the drain side of (n)) is about to rise. When the potential Vdn on the drain side increases, the gate voltage of the n-channel MOSFET (FET3 (n)) increases, and the n-channel MOSFET (FET3 (n))
The current flowing between the drain and the source of the IGBT tends to increase.

However, the p-channel MOSFET (FE
TN (p)) and an n-channel MOSFET (FET3
(N)) is kept constant, the potential Vd on the drain side of the n-channel MOSFET (FET3 (n)) decreases, and as a result, the n-channel M
The gate potential applied to the gate of the OSFET (FET2 (n)) decreases. n-channel MOSFET (FET2
When the gate potential of (n) decreases, the increase of the current Idn is prevented, and as a result, the n-channel MOSFET (FET)
2 (n)), the potential difference between the drain and the source increases, the drain voltage Vdn of the n-channel MOSFET (FET1 (n)) is kept constant, and the current Id
n will be kept constant.

As a result, an n-channel equivalent MOSFET
, The drain resistance rd becomes ∞, and the saturation characteristics shown in FIG. Actually, the magnitude of the current Idn is approximately 50 to 150 microamps and the current Ireg may be approximately 2 microamps. The power consumption based on the current Ireg flowing toward is almost negligible.

The n-channel equivalent MOSFET (EFETN (n)) shown in FIG. 18A is called a so-called regulated cascade circuit, and the circuit itself is known. This n-channel equivalent MOSFET
(EFETN (n)) are n-channel MOSFETs (M1 to M5, M30 to M33, M5
0 to M52).

A p-channel equivalent MOS shown in FIG.
The FET (EFETN (p)) is a p-channel M
It operates as an OSFET. p-channel equivalent MOSFE
T (EFETN (p)) has a p-channel MOSFET
(FETN (p)) are used, and an n-channel MOS
One FET (FETN (n)) is used. Here, three p-channel MOSFETs (FETN (p))
To (FET1 (p)), (FET2 (p)), (F
ET3 (p)), and the connection state will be described next.

P-channel MOSFET (FET1
The drain of (p)) is connected to the terminal Vout.
The source of the p-channel MOSFET (FET1 (p)) is connected to the drain of the p-channel MOSFET (FET2 (p)) and the gate of the p-channel MOSFET (FET3 (p)). p-channel MOSFET (FET1
The gate of (p) is an n-channel MOSFET (FETN
(N)) drain and p-channel MOSFET (FET)
3 (p)). The source of the p-channel MOSFET (FET2 (p)) is the power supply Vdd
, And a gate voltage Vgp is applied to its gate. p-channel MOSFET (FET3 (p))
Are connected to the power supply Vdd. n channel M
The source of the OSFET (FETN (n)) is grounded, and its gate is applied with a gate voltage Vreg. In FIG. 19A, Vdp is a p-channel MOSF
ET (FET1 (p)) is the source-side potential, and Id
p indicates a current flowing between the source and the drain of the p-channel MOSFET (FET1 (p)). The saturation characteristic of this p-channel equivalent MOSFET (EFETN (p)) is as shown in FIG. The reason is omitted because it can be easily analogized from the description of the operation characteristics of the n-channel equivalent MOSFET (EFETN (n)). This p-channel equivalent MOSFET includes current sources A1-A5, A30-A
33, A51 to A53.

[0121]

Embodiment 4 FIG. 20 shows an embodiment in which the current flip-flop shown in FIG. 15 is improved. FIG. 20 is intended to prevent the fluctuation of the current signal caused by the charge redistribution phenomenon (referred to as charge injection phenomenon). Before describing the circuit of FIG. 20, the charge injection phenomenon will be described with reference to FIG.

The sample-and-hold switches SW11, SW12, SW21, and SW22 shown in FIG. 15 can be configured using n-channel MOSFETs, and are transfer gate switches. The n-channel MOSFET constituting this transfer gate switch is denoted by the symbol MT.
(N), n-channel MOS for sample hold
The FET is denoted by the symbol MS (n). FIG. 21 shows a second sample / hold switch SW12 (SW22) and a sample / hold n-channel MOSFET M50 (M51, M51).
52) indicates a circuit indicating a connection state with the circuit 52).

When the voltage Vsw applied to the gate of the n-channel MOSFET (MT (n)) is high (the first clock signal W1 is "1", for example, 5V), the n-channel MOSFET
The OSFET (MT (n)) conducts, and the n-channel MOS
The voltage Vin is applied to the gate of the FET (MS (n)). This voltage Vin is generated by the current signal Iin. When the voltage Vin is high (for example, 5 V), the gate potential Vg of the n-channel MOSFET (MS (n)) is 5
V. That is, when Vsw and Vin become high, Vsw
g goes high and the n-channel MOSFET (MS
(N)) The parasitic capacitance Cqs1 between the gate and the source is Q
1 = Cqs1 · Vh (for example, 5 V) is accumulated. On the other hand, the parasitic capacitance Cqs2 between the gate and the source of the n-channel MOSFET (MT (n)) includes Vsw, Vi
Since n is high, no charge is stored.

Next, when the voltage Vsw becomes low (the first clock signal W1 is "0"), that is, the n-channel MO
When the SFET (MT (n)) is turned off, the charge of the parasitic capacitance Cqs2 is “0”, and the parasitic capacitance Cqs1 has Q
1 = Cqs1 × Vh charge is conserved.

However, if the parasitic capacitance Cqs2 is not negligible, the charge Q1 (= Cqs1 · Vh) is redistributed into the parasitic capacitances Cqs1 and Cqs2 when the voltage Vsw is low. Subsequent gate potential V
g ′ is Vg ′ = (Cqs1 / (Cqs1 + Cqs2)) × Vg

The current Id flowing between the drain and the source of the n-channel MOSFET (MS (n)) is Id = β (V
g-Vth) ⁿ becomes, when Vg is a very large value compared to the threshold voltage Vth, Id is proportional to βVg ^n.
Therefore, the current Id is obtained by charge redistribution, and the current Id ′ after the redistribution is Id ′ / Id = (Cqs1 / (Cqs1)
+ Cqs2)) ⁿ .

Here, n is a value between 1 and 2. If the channel length of the MOSFET is very long, the value is 2, and the MOSFET having a channel length of 0.25 μm to 0.8 μm is used.
At T, the value is approximately 1.5. Theoretically, it approaches 1 as the channel length decreases.

The parasitic capacitance Cqs1 is proportional to the gate width W between the gate and the source, and
(MT (n)) gate width W and n-channel MOSFET
When the gate width W of (MS (n)) is the same, Vg ′ = V
g / 2, and Id '/ Id = (1/2) ⁿ . n
= 2, Id ′ / Id = 1/4.

Therefore, the current variation due to the charge redistribution can be suppressed by devising the gate width W, but the current variation due to the charge redistribution can also be suppressed in terms of the circuit.

The setting of the gate width W will be described later. An embodiment of an improved current flip-flop in which current fluctuation is suppressed by modifying the circuit first will be described with reference to FIG.

In this improved current flip-flop, the first
The sample and hold circuit SH1 includes a first current source MOS transistor M2, a first sample and hold MOS transistor M1, a first sample and hold switch SW11, and a second sample and hold switch SW1a (1). First sample hold MOS transistor M
The drain of 1 is connected to the drain of the first current source MOS transistor M2. M for 1st sample hold
The source of the OS transistor M1 is grounded. The current signal Iin is supplied to the first sample and hold MOS transistor M1 via the first sample and hold switch SW11.
Is input to the drain. The second sample hold switch SW1a (1) is connected to the first sample hold MO.
The S transistor M1 is connected between the gate and the drain to short-circuit the gate and the drain. The first sample hold switch SW11 is turned on and off based on the first clock pulse W1. The gate of the first current source MOS transistor M2 is connected to a synchronous switch SW1a (2) which is turned on / off in synchronization with the second sample hold switch SW1a (1). In order to generate a fluctuating current corresponding to a current fluctuating based on an injection current injected into a parasitic capacitance C1 between the gate and the source of the first sample-hold MOS transistor M1,
A first short-circuit switch SW1b for short-circuiting the gate and the drain is connected between the gate and the drain of the first current source MOS transistor M2. The third clock pulse W3 is input to the first synchronous switch SW1a (2) and the second sample hold switch SW1a (1). As shown in FIG. 22, the first synchronous switch SW1a (2) and the second sample hold switch SW1a (1) are turned on in the first half of the ON period of the first sample hold switch SW11. The fourth clock pulse W4 is input to the first short-circuit switch SW1b. The first short-circuit switch SW1b is connected to the first sample-hold switch SW11.
Is turned on in the latter half of the ON period, and the current fluctuation based on the injection current injected into the parasitic capacitance C1 between the gate and the source of the first sample-hold MOS transistor M1 is changed by the fluctuation of the first current-source MOS transistor M2. Cancel by current.

The second sample-and-hold circuit SH2 is connected to the second sample-and-hold circuit SH2.
A first current flip-flop comprising a current source MOS transistor M4 and a second sample-and-hold MOS transistor M3 for outputting a held current signal to a next-stage current flip-flop;
A system 52A, a second system 53A comprising a third current source MOS transistor M6 and a third sample and hold MOS transistor M5, and outputting the held current signal to the addition / subtraction means 105; a third sample and hold switch SW21; 4 sample hold switch SW2a
(1) and SW2a (2). The drain of the second sample-and-hold MOS transistor M3 is the second
It is connected to the drain of the current source MOS transistor M4 and to the drain of the first sample and hold circuit SH1 via the third sample and hold switch SW21. The source of the second sample-and-hold MOS transistor M3 is grounded. The current signal held by the first sample and hold circuit SH1 is input to the drain of the second sample and hold MOS transistor M3 via the third sample and hold switch SW21. The fourth sample and hold switch SW2a (1) is connected between the gate and the drain of the second sample and hold MOS transistor M3 to short-circuit the gate and the drain. The third sample and hold switch SW21 is turned on and off based on the second clock pulse W2. The fourth sample hold switch SW2a (1) is connected to the gate of the second current source MOS transistor M4.
Synchronous switch SW2a which is turned on and off in synchronization with
(2) is connected. MO for 2nd sample hold
In order to generate a fluctuating current corresponding to a current fluctuating based on the injection current injected into the parasitic capacitance C2 between the gate and the source of the S transistor M3, the gate and the drain of the second current source MOS transistor M4 are A second short-circuit switch SW for short-circuiting the gate and the drain.
2b is connected. Third sample hold MOS
The drain of the transistor M5 is connected to the drain of the third current source MOS transistor M6. The source of the third sample-and-hold MOS transistor M5 is grounded. The gate of the third sample-and-hold MOS transistor M5 is connected to the gate of the second sample-and-hold MOS transistor M3. MO for third current source
The gate of the S transistor M6 is connected to the gate of the second current source MOS transistor M4. The source of the third current source MOS transistor M6 is connected to the power supply Vdd. The fifth clock pulse W5 is input to the second synchronous switch SW2a (2) and the fourth sample hold switch 2a (1). The second synchronous switch SW2a and the fourth sample hold switch 2a are turned on in the first half of the ON period of the third sample hold switch SW21.
The sixth clock pulse W is supplied to the second short-circuit switch SW2b.
6 is input. The second short-circuit switch SW2b is turned on in the latter half of the ON period of the third sample-and-hold switch SW21, and the parasitic capacitance C2 between the gates and sources of the second and third sample-and-hold MOS transistors M3 and M5.
Current fluctuations based on the injection current injected into the second and third
The fluctuation is offset by the fluctuation current of the current source MOS transistors M4 and M6.

Details will be described with reference to a timing chart shown in FIG. 22 and schematic diagrams showing circuit connection states shown in FIGS. As shown in FIG. 23, when the first sample hold switch SW11 and the second sample hall switch SW1a (1) are on, the first synchronous switch SW1a (2) is on and the first short circuit switch SW1 is turned on.
b, the third sample hold switch SW21 is turned off. First sample hold MOS transistor M1
The current Id (J + Iin) between the drain and source of (n)
Flows. The current J flowing through this current source is defined as J0.

Next, as shown in FIG. 24, the second sample and hold switch SW1a (1) and the first synchronous switch S1
W1a (2) is turned off, and the short-circuit switch SW1b is turned on. At this time, the third sample-and-hold switch S
W21 remains off. M for 1st sample hold
The charge Q0 stored in the parasitic capacitance Cgs between the gate and the source of the OS transistor M1 (n) changes from Q0 to Q0 ′ due to charge redistribution based on the turning off of the second sample-and-hold switch SW1a. The current Id flowing between the drain and source of the MOS transistor M1 (n) changes to Id = J0 + Iin + ΔI.

At this time, however, the first current source MOS
Since the gate and the drain of the transistor M2 (p) are short-circuited by the short-circuit switch SW1b, the electric charge accumulated in the gate-source parasitic capacitance of the first current source MOS transistor M2 (p) is released. Then, the current J of the current source changes from J = J0 to J = J0 + ΔI.

Next, as shown in FIG. 25, the third sample and hold switch SW21 and the fourth sample and hold switch SW2a (1) are turned on. At this time, the first sample and hold switch SW11, the second sample and hold switch SW1a (1), the first synchronous switch SW1a
(2) The short-circuit switch SW1b is off. When the short-circuit switch SW1b is turned off, the parasitic capacitance Cq between the gate and the source of the first current source MOS transistor M2 (p).
The charge accumulated in s changes, that is, charge redistribution occurs, and the current J flowing through the first current source MOS transistor M2 (p) changes from J = J0 + ΔI to J = J0 + ΔI−
Changes to Δβ. However, the current variation △ β is the current variation △
Very small compared to I. Therefore, the output current Iout
(Iin- △ β) becomes Iin.

Therefore, as shown in FIG.
Flows into the n-channel MOS transistor M1 (n)
When the current flowing through the p-channel MOS transistor M2 (p) changes from time t1 to time t2 when the current flowing through the p-channel MOS transistor M2 (p) becomes J, the short-circuit switch SW1b is turned on. F1 and changes by n channel MOS transistor M1
The current fluctuation ΔI based on the turning on of the sample-and-hold switch SW1a (1) of (n) is canceled out, and as a result, the transfer current Is corresponding to the current Iin is transferred to the second sample-and-hold via the third sample-and-hold switch SW21. It flows into the circuit SH2 and is transferred to the n-channel MOS transistor M3 (n). n-channel MOS
A similar phenomenon occurs at the time t at the transistor M3 (n).
3, which occurs at the beginning of the sampling,
Since the current flowing through the OS transistor M4 (p) changes when the second short-circuit switch SW2b is turned on at the time t4, this causes the sample-and-hold switch SW2a of the n-channel MOS transistor M3 (n) to change.
The fluctuation due to the turning off of (1) is suppressed, and as a result, the output current Iout has a value exactly corresponding to the current signal Iin. The number “1” indicates the period of the chip information “1”, and the number “0” indicates the period of the chip information “0”.

[0138]

[Embodiment 6] A current prototype flip-flop circuit will be described below. FIG. 26 is an overall view of the prototype circuit. In this prototype circuit, the sample-and-hold MOS transistors M1 (n), M3 (n) and M5 (n) are constituted by n-channel equivalent MOSFETs (EFET (n)). , Current source MOS transistors M2 (p), M4
(P) and M6 (p) are p-channel equivalent MOSFETs (E
FET (p)). Further, each sample hold switch SW11, SW1a (1), SW2
1, SW2a (1), each synchronous switch SW1a (2),
SW2a (2), short-circuit switches SW1b, SW2b
Are composed of CMOS switches. In this embodiment, the current means MOS transistors M53, M54, M
55, M55 'are provided.

In an nMOS switch, the threshold voltage may not be transmitted accurately depending on the direction of current flow. Therefore, a CMOS switch is used in the prototype circuit in order to transmit the threshold voltage accurately.

When this CMOS switch is used, each of the input gates φ1, φ2, φ1a, φ1a1,.
First to first input to φ2a, φ2a1, φ1b, φ2b
Seventh to twelfth phases opposite to the sixth clock pulses W1 to W6
Clock pulses W7 to W12 are applied to input gates φ1 ′, φ1
2 ′, φ1a ′, φ1a1 ′, φ2a ′, φ2a1 ′,
Input to φ1b ′ and φ2b ′. The clock pulses W7 to W12 having the opposite phases are shown in FIG. The same clock pulse is input to the gates φ1a ′ and φ1a1 ′, the same clock pulse is input to the gates φ2a ′ and φ2a1 ′, and the same clock pulse is input to the gates φ2a ′ and φ2a1 ′. Is 1
It becomes two.

The clock signal is generated from a reference clock signal generator 300 shown in FIG.
The sub clock oscillators 300 _{1 to} 300 _n are formed. The sub clock oscillators 300 _{1 to} 300 _n are:
It has a function of dividing the frequency with reference to the third clock pulse W3 input to the second sample and hold switch SW1a and a function of generating a clock pulse of the opposite phase. The first clock pulse W1, the second clock pulse W2, 4th to 1st
Two clock pulses W4 to W12 are generated. These first to twelfth clock pulses W1 to W12 are input to each CMOS switch of each current flip-flop 102 _{1 to} 102 _n .

In this prototype circuit, in order to suppress the influence of the current variation based on the injected charge injected into the parasitic capacitance between the gate and the source of each sample-and-hold MOS transistor, that is, the influence of each charge injection,
The ratio (W / L) of the gate width W to the gate length L of the OS transistor was set to about 50 / 0.8 = 62.5 times. M1
(N), M2 (p), M3 (n), M4 (p), M5
(N), the numerical value of 50 / 0.8 described in the MOS transistors constituting M6 (p) is
This is the (gate width / gate length) ratio of the transistor, that is, the value of (W / L). Specifically, when this circuit is configured according to the 0.8 μm rule, (50 / 0.8)
The gate width of the MOS transistor described as 50 μm
It is. When designing with the 0.2 μm rule, (5
The gate width of the MOS transistor described as (0 / 0.8) is 12.5 μm. Each CMOS switch has
“P = numerical value” and “n = numerical value” are described.
“P = numerical value” indicates a “gate width / gate length” ratio of a p-channel MOS transistor included in the CMOS switch, that is, W / L. For example, "p = 2.1 / 0.
8 "indicates that the W / L ratio of the p-channel MOS transistor of the CMOS switch is 2.1 / 0.8. This means that when designing according to the 0.8 μm rule, the gate width is set to 2.1 μm. When designing with the 0.2 μm rule, 0.52
This means designing at 5 μm. Similarly, “n = numerical value” indicates an n-channel MOS constituting a CMOS switch.
The “gate width / gate length” ratio of the transistor, ie, W
/ L. For example, when "n = 3.2 / 0.8" is described, the n-channel MO of the CMOS switch is used.
It shows that the W / L ratio of the S transistor is 3.2 / 0.8. This means that when designing with the 0.8 μm rule, the gate width should be 3.2 μm. Also,
Designing with the 0.2 μm rule means designing with 0.4 μm.

The procedure for determining the gate width W is as follows. The n-channel MOS transistor FET1 (n) of the equivalent MOSM1 (n) and the second sample hold switch S
The gate width W of W1a (1) is determined. In order to minimize the influence of the charge redistribution and accurately sample and hold the current, the second sample and hold switch SW1a
The gate width W of the CMOS switch constituting (1) is minimized, and the n-channel M of the equivalent MOSFET M1 (n) is
The gate width W of the OS transistor FET1 (n) is increased.

Therefore, the second sample hold switch S
The gate width W of the pMOS of W1a (1) was 3.2 μm, and the gate width W of the nMOS was 2.1 μm. The reason why the gate width W of the pMOS is increased is as follows.

The current driving capability of a pMOS transistor is generally smaller than that of an nMOS transistor.
Therefore, in order to increase the current driving capability, the gate width W of the pMOS is made larger than the gate width of the nMOS.

On the other hand, since the magnitude of the current Iin is approximately constant at about 20 μm, the equivalent MOSFET M1 (n)
If the gate width W of the n-channel MOS transistor FET1 (n) is increased unnecessarily, it takes time to charge up the parasitic capacitance between the gate and the source.
It is disadvantageous in terms of charge transfer speed.

From the viewpoint of charge transfer speed (operating speed),
There is a trade-off relationship that the gate width W of the n-channel MOS transistor FET1 (n) is small and it is desirable to increase the gate width of the n-channel MOS transistor FET1 (n) for accurate current transport.

Therefore, when configuring a current flip-flop in which the number of arrayed chip information corresponds to 128, since an SN ratio equivalent to 7 bits is required as a quantization error, transfer of current per one stage of the current flip-flop is performed. An n-channel MOS transistor FET that sets a condition so that an error is equal to or less than (1/128)% and operates at a maximum speed.
The gate width W of 1 (n) was determined. As a result, the gate width W of each sample-and-hold nMOS transistor is set to 0.
Under the 8μ rule, it was 50μ. That is, the second
NMOS of sample and hold switch SW1a (1)
Is about 25 times the gate width W (= 2.1 μ).

Next, n-channel MOS transistor M1
(N) n-channel MOS transistor FET2 (n)
Since the FET2 (n) is connected in series with the FET1 (n), the gate width W is also 50 μm. n
The gate width W of the channel MOS transistor FET3 (n) and the p-channel MOS transistor FETN (p) is not limited, but was set to 50 μm in this prototype. F
The gate width W of ET3 (n) and FETN (p) can be 2 μm.

In accordance with this idea, the first sample hold switch SW11 and the third sample hold switch SW
21, the first short-circuit switch SW1b, the second short-circuit switch S
The gate width W of W2b was determined. First sample hold switch SW11 and third sample hold switch SW
The gate width W of 21 is not particularly limited, but was set to a value that did not affect the operation speed and the sample hold by simulation, that is, 6 μm. First short-circuit switch SW
1b, the gate width W of the second short-circuit switch SW2b is appropriately set to 2.2 μm and 2.1 μm for the n-channel gate width W.
And the gate width W of the p-channel was 6.4 μ and 6.1 μ.

[0151]

Seventh Embodiment FIG. 29 is a block diagram showing a configuration of a code division multiplex communication apparatus (receiving side) according to another embodiment of the present invention. In this figure, reference numeral 201 denotes an antenna, which receives a transmission wave from a transmitter (not shown). 202
Denotes a mixer, which mixes a received transmission wave with a signal wave transmitted from the local oscillator 3, and outputs an IF signal. 204
Is a correlator configured in the same manner as the correlator 5 shown in FIG. 4, and correlates a PN code generated by a programmable PN code generator 205 with an IF signal and outputs a correlation signal. A demodulator 206 reproduces a signal of a baseband frequency based on the input correlation signal.

It is to be noted that M correlators 5 shown in FIG. 1 are provided in parallel, and an A / D converter having a quantization bit number of M bits is provided before the terminal T1.
A converter is connected, and an M bit D /
By connecting the A converter, a digital correlator can be configured. As shown in FIG.
F (Intermediate Frequency)
When using in a belt, design as follows. The problem is,
The number of CDF / Fs and the operating clock frequency. If the IF frequency is fIF, the chip length is N, the chip rate is Cchip, and the sampling coefficient is Ms, [the number of CDF / Fs] = (N × fIF × MS) ÷
Given by Cchip. Here, the sampling coefficient MS becomes 2 at the time of double sampling. If the IF frequency (fIF) is 200 MHz, the chip length (N) is 128, the chip rate (Cchip) is 50 Mcps, and the double sampling (Ms = 2) is performed, the number of CDF / Fs is (128 × 200 [MHz] × 2) $ 50 [Mcps]
= 1024.

In the case of double sampling, it is necessary to sample at a sampling frequency of 400 MHz, which is twice the 200 MHz. The maximum operating clock frequency of the current adding type correlator according to the present invention is limited by the operating speed of each CDF / F. The addition / subtraction unit 105 does not affect the operating frequency even when the number of stages of the CDF / F increases. Therefore,
Even if the number of CDF / F is increased to 1024 as described above,
High-speed operation up to 4.46 GHz is possible. Therefore,
Sampling at 400 MHz is quite possible. On the other hand, in a conventional CMOS / LSI digital matched filter, even if a 0.2 μm process is used, the speed is controlled by an adder circuit, and sampling can be performed only at about 100 MHz.

(Effects of the above embodiment) As is clear from the above description, the current addition type correlator 5 according to the above embodiment sets the circuit to the disable state once during one cycle of the clock pulse, thereby The power consumption is reduced. Hereinafter, the effect of reducing power consumption will be described.

(A) to (d) are as follows: (a): In the circuit of FIG.
11 except for M105, and as a current adder 105 in FIG.
When the circuit shown in (a) is used, (b): In FIG. 15, transistors M53 to M55
In addition, when the circuit shown in FIG. 11A is used as the current adder 105, (c): The circuit shown in FIG. 6 is used, and the circuit shown in FIG. (D): The case where the circuit of FIG. 15 is used and the circuit shown in FIG.

(A) Baseband correlation (a) (b) (c) (d) Chip length 128 128 128 128 Chip rate * 1 * 2 14Mcps 14Mcps Sampling double ← ← ← Sampling frequency 28MHz ← ← ← CDF / Number of F 256 256 256 256 Number of Trs / CDF / F 12 10 17 13 Number of current sources / CDF / F 5 3 5 3 Current per CDF / F current source 150μA 150μA 150μA 150μA Number of Trs in switch matrix 512 512 512 512 Number of Trs in current addition circuit 8 8 12 12 Number of current sources in current addition circuit 4 4 4 4 Current per current source in current addition circuit 2.56 mA 2.56 mA 2.56 mA 2.56 mA Total number of Trs 3592 3080 4876 3852 CDF / Power of F 192.0mW 115.2mW 4.3mW 2.58mW Power of current adding circuit 10.2mW 10.2mW 0.23mW 0.23mW Total power 202.2mW 125.4mW 4.5mW 2.8mW (* 1, * 2): (a) and (b) In case (2), the total power is independent of the chip rate.

(B) In case of IF correlation (a) (b) (c) (d) Chip length 128 128 128 128 Chip rate 14Mcps 14Mcps 14Mcps 14Mcps Sampling double (140MHz) ← ← ← Sampling frequency 280MHz ← ← ← CDF / Number of F 2560 2560 2560 2560 Tr / CDF / F 10, 12, 8, 10, 14, 17, 10, and 13 Number of current sources / CDF / F 4, 5, 2, 3, 4, 5, 2, and 3 CDF / F Current per switch 150μA 150μA 150μA 150μA Number of Trs in switch matrix 512 512 512 512 Number of Trs in current adder circuit 8 8 12 12 Number of current sources in current adder circuit 4 4 4 4 Current per current source in current adder circuit 2.56mA 2.56mA 2.56mA 2.56mA Total number of transistors 26632 21512 37132 26892 CDF / F power 1574.4mW 806.4mW 352.8mW 180.7mW Current addition circuit power 10.2mW 10.2mW 2.3mW 2.3mW Total power 1584.6mW 816.6mW 355.1mW 180.0mW In (A), sampling is double sampling. That is, the input signal to the matched filter is sampled at twice the frequency of the chip rate. At this time, because of the double sampling, the number of C · DFFs is twice the chip length.

In the example of (A), since there are 128 chips, the number of CDF / F is 2 × 128 = 256. The sampling may be an integral multiple of the number of chips. Further, the operation is possible even if the value is not exactly an integral multiple.

In the case of the IF band correlation in (B), the number of CDFs / Fs is determined as follows. That is, the IF frequency
Assuming that fIF, chip length is N, chip rate is Cchip, and sampling coefficient is Ms, [CDF / F] = (N × fIF × Ms) ÷ Cchip. Here, the sampling coefficient Ms is set to 2 at the time of double sampling.

In the current addition type correlator, the operating speed is determined by the circuit response time of the CDF / F. CDF
The response speed (τ) of / F is 0.0357 nsec when the 0.2 μm Si process is used. That is, the maximum operating frequency [fmax = 1 / (2πτ)] is 4.46.
GHz. The on-time of the clock pulses W1 and W2, that is, “t ₂ −t ₁ ” and “t ₃ −t ₂ ” in FIGS. 7 and 16 was simulated as 0.4 nsec, which is about 10 times τ.

As described above, when used for correlation of the PN data of (A) and (B), the correlator (c) provided with the transistor for disabling is compared with the correlator (a). As a result, power consumption has been greatly reduced. Similarly, the correlator (d) provided with a transistor for disabling is:
The power consumption is greatly reduced as compared with the correlator (b).

From the above results, CDF / F101 ₁ ,.
,... Only in the sampling / hold operation of the 101 _n current, the transistor for disabling uses the drive current of CD
By controlling the supply to the F / Fs 101 ₁ ,..., 101 _n , the power consumption of the correlator can be significantly reduced.

Since the current addition method is used as these correlators, the maximum operating frequency of the circuit is 4 G
Hz or higher, and can operate at high speed.

[0164]

As described above, according to the present invention,
Since the current cut means for cutting the current flowing from the current source during the transfer period for transferring the current to the subsequent sample and hold circuit is provided, the power consumption can be significantly reduced as compared with the conventional one.

In particular, when the current cut means is provided in the current delay means, it is possible to provide a code division multiplex communication apparatus having a high operation speed and low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram of a code division multiplex communication device according to the present invention.

FIG. 2 is a timing chart for explaining generation of a transmission radio wave.

FIG. 3 is a timing chart for explaining a relationship between a voltage signal based on a received radio wave and a correlation current signal.

FIG. 4 is a block diagram showing an internal configuration of the correlator shown in FIG.

FIG. 5 is a circuit diagram showing an example of a configuration of a current-voltage converter shown in FIG.

6 is a detailed circuit diagram showing a basic configuration of the current flip-flop shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIG. 8 is a perspective view of an nMOS transistor for explaining a relationship between a gate width and a gate length.

FIG. 9 is a detailed circuit diagram showing an example of the analog switch shown in FIG.

FIG. 10 is a connection diagram illustrating a connection state of an analog switch when the arrangement number of chip information is 7 and the arrangement of chip information of despread data is “1110010”.

11 is a circuit diagram showing a detailed configuration of an addition / subtraction unit shown in FIG.

FIG. 12 is a circuit diagram showing an example of a configuration of a current-voltage converter shown in FIG.

13A and 13B are diagrams for explaining the details of the circuit configuration of the current source shown in FIGS. 6 and 11, wherein FIG. 13A illustrates the current source by an equivalent symbol, and FIG. This shows a case in which the MOS transistors are used.

FIG. 14 shows a case where the array number of chip information is 7, and the array of chip information of despread data of double sampling is “111”.
FIG. 9 is a connection diagram illustrating a connection state of the analog switch when “0010”.

FIG. 15 is a detailed circuit diagram showing another embodiment of the current flip-flop.

FIG. 16 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIGS. 17A and 17B are diagrams for explaining the operation characteristics of the MOS transistor. FIG. 17A shows an n-channel MOS transistor as a representative, and FIG.
(C) representatively shows a p-channel MOS transistor, and (2) shows its operating characteristics.

FIG. 18 shows an example of a circuit configuration of an n-channel equivalent MOSFET, and (b) is a diagram showing improved operation characteristics.

FIG. 19 shows an example of a circuit configuration of a p-channel equivalent MOSFET, and (b) is a diagram showing improved operation characteristics.

FIG. 20 is a detailed circuit diagram of a current flip-flop in a case where charge fluctuation based on an injection current is improved.

FIG. 21 is a diagram for explaining charge fluctuation (charge injection) based on an injection current.

FIG. 22 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIG. 23 shows a first sampling switch shown in FIG.
FIG. 9 is a diagram illustrating a connection state of the first sample and hold circuit when a second sampling switch and a first synchronization switch are on and a third sampling switch and a short circuit switch are off.

24. The first sampling switch shown in FIG. 20,
FIG. 10 is a diagram illustrating a connection state of the first sample and hold circuit when the first short-circuit switch is on and the second sampling switch, the second synchronization switch, and the third sampling switch are off.

25 shows a first sampling switch shown in FIG. 20,
FIG. 7 is a diagram illustrating a connection state of the first sample and hold circuit when a second sampling switch, a first synchronization switch, and a first short circuit switch are off and a third sampling switch is on.

FIG. 26 is a circuit diagram showing a detailed configuration of one stage of a current prototype flip-flop actually manufactured.

FIG. 27 shows a connection relationship between a clock signal generator and a correlator, and shows a case where the correlator is provided with a division period of a clock signal.

28 is a diagram for explaining a gate width of the current flip-flop shown in FIG.

FIG. 29 is a diagram for explaining another embodiment of the code division multiplex communication device according to the present invention.

[Explanation of symbols]

 101: voltage-current conversion means 102: current delay means 103: connection state switching means 105: addition / subtraction means

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[Procedure amendment]

[Submission date] January 21, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a block diagram of a code division multiplex communication device according to the present invention.

FIG. 2 is a timing chart for explaining generation of a transmission radio wave.

FIG. 3 is a timing chart for explaining a relationship between a voltage signal based on a received radio wave and a correlation current signal.

FIG. 4 is a block diagram showing an internal configuration of the correlator shown in FIG.

FIG. 5 is a circuit diagram showing an example of a configuration of a current-voltage converter shown in FIG.

6 is a detailed circuit diagram showing a basic configuration of the current flip-flop shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIG. 8 is a perspective view of an nMOS transistor for explaining a relationship between a gate width and a gate length.

FIG. 9 is a detailed circuit diagram showing an example of the analog switch shown in FIG.

FIG. 10 is a connection diagram illustrating a connection state of an analog switch when the arrangement number of chip information is 7 and the arrangement of chip information of despread data is “1110010”.

11 is a circuit diagram showing a detailed configuration of an addition / subtraction unit shown in FIG.

FIG. 12 is a circuit diagram showing an example of a configuration of a current-voltage converter shown in FIG.

13A and 13B are diagrams for explaining the details of the circuit configuration of the current source shown in FIGS. 6 and 11, wherein FIG. 13A illustrates the current source by an equivalent symbol, and FIG. This shows a case in which the MOS transistors are used.

FIG. 14 shows a case where the array number of chip information is 7, and the array of chip information of despread data of double sampling is “111”.
FIG. 9 is a connection diagram illustrating a connection state of the analog switch when “0010”.

FIG. 15 is a detailed circuit diagram showing another embodiment of the current flip-flop.

FIG. 16 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIGS. 17A and 17B are diagrams for explaining the operation characteristics of the MOS transistor. FIG. 17A shows an n-channel MOS transistor as a representative, and FIG.
(C) representatively shows a p-channel MOS transistor, and (2) shows its operating characteristics.

FIG. 18 shows an example of an n-channel equivalent MOSFET .
(A) is a circuit configuration of an n-channel equivalent MOSFET.
Yes, (b) is a diagram showing the improved operational characteristics.

FIG. 19 shows an example of a p-channel equivalent MOSFET .
(A) is a circuit configuration of a p-channel equivalent MOSFET.
Yes, (b) is a diagram showing the improved operational characteristics.

FIG. 20 is a detailed circuit diagram of a current flip-flop in a case where charge fluctuation based on an injection current is improved.

FIG. 21 is a diagram for explaining charge fluctuation (charge injection) based on an injection current.

FIG. 22 is a timing chart for explaining the operation of the current flip-flop shown in FIG.

FIG. 23 shows a first sampling switch shown in FIG.
FIG. 9 is a diagram illustrating a connection state of the first sample and hold circuit when a second sampling switch and a first synchronization switch are on and a third sampling switch and a short circuit switch are off.

24. The first sampling switch shown in FIG. 20,
FIG. 10 is a diagram illustrating a connection state of the first sample and hold circuit when the first short-circuit switch is on and the second sampling switch, the second synchronization switch, and the third sampling switch are off.

25 shows a first sampling switch shown in FIG. 20,
FIG. 7 is a diagram illustrating a connection state of the first sample and hold circuit when a second sampling switch, a first synchronization switch, and a first short circuit switch are off and a third sampling switch is on.

FIG. 26 is a circuit diagram showing a detailed configuration of one stage of a current prototype flip-flop actually manufactured.

FIG. 27 shows a connection relationship between a clock signal generator and a correlator, and shows a case where the correlator is provided with a division period of a clock signal.

28 is a diagram for explaining a gate width of the current flip-flop shown in FIG.

FIG. 29 is a diagram for explaining another embodiment of the code division multiplex communication device according to the present invention.

[Description of Signs] 101: voltage-current conversion means 102: current delay means 103: connection state switching means 105: addition / subtraction means

Claims (31)

[Claims] 1. A receiving means for receiving a transmission radio wave generated by multiplying an information signal by spread data comprising an array of chip information and outputting a voltage signal, and a voltage / current converting the voltage signal into a current signal Conversion means, and sample-and-hold circuits of an integral multiple of the number of arrays of the chip information. The current signal is input to the first sample-and-hold circuit, and the current signal is sampled and held based on a clock signal. Current delay means for successively delaying and transferring the current signal held by the sample and hold circuit to a subsequent sample and hold circuit to generate a time series of a current signal in which the array of chip information is potentially implicit; Adding / subtracting means for simultaneously inputting a time-series current signal held by the sample-and-hold circuit and outputting a correlation current signal; A current source is provided in the current delay means and the addition / subtraction means, and the current delay means cuts a current flowing from the current source in a transfer period for transferring the current to a subsequent sample-hold circuit. Is provided, a code division multiplex communication device. 2. The method according to claim 1, wherein the adding and subtracting means includes a first addition system and a second addition system.
An addition system is provided, and the first addition system and the second addition system are configured such that an array of chip information that is potentially implicit in the time series of the current signal corresponds to the array of the chip information. The despread data so that an added current obtained by collecting and adding only a positive current signal and an added current obtained by collecting and adding only a negative current signal when the arrangement of the chip information of the obtained despread data coincides are obtained. Connected to each of the sample and hold circuits according to an array of chip information of
The code division multiplex communication device according to claim 1, wherein the correlation current signal is generated by subtracting the addition current of the second addition system from the addition current of the first addition system. 3. The method according to claim 1, wherein said adding / subtracting means is provided with a current cutting means for cutting a current flowing from said current source in a transfer period for transferring the current to a subsequent sample-hold circuit. Code division multiplex communication device. 4. The differential amplifier according to claim 1, wherein said voltage / current converting means outputs a negative current signal when said voltage signal is positive and outputs a positive current signal when said voltage signal is negative. The code division multiplex communication device according to claim 1, wherein the code division multiplex communication device comprises a circuit in which a circuit and a voltage follower circuit are connected. 5. The code division multiplex communication apparatus according to claim 1, wherein a correlator is constituted by at least said current delay means and said addition / subtraction means. 6. The code division multiplex communication device according to claim 5, wherein each of said sample and hold circuits comprises a current flip-flop. 7. The current flip-flop according to claim 1, wherein the clock signal comprises a first clock pulse generated in a time series and a second clock pulse generated in a time series in an opposite phase to the first clock pulse. A first sample-and-hold circuit that samples the current signal at the rise of the first clock pulse and holds the current signal at the fall to delay the current signal; and converts the current signal held by the first sample-and-hold circuit into the first sample and hold circuit. A second sample-and-hold circuit that samples the signal at the rising edge of the second clock pulse and holds the signal at the falling edge, transfers the held current signal to the next-stage current flip-flop, and outputs the current signal to the addition / subtraction means. The code division multiplex communication device according to claim 5, wherein: 8. The despread data generator includes a despread data generator for generating an array of chip information of the despread data. The despread data generator is provided between the current delay means and the addition / subtraction means. Based on the output despread data,
Only the positive current signal is collected when the array of chip information potentially implicit in the time series of the current signal matches the array of chip information of the despread data set corresponding to the array of chip information. A connection state for switching a connection state of the first addition system and the second addition system to each of the current flip-flops so as to obtain an addition current obtained by adding the current signals and an addition current obtained by collecting and adding only negative current signals. The code division multiplex communication device according to claim 7, further comprising a changeover switch means. 9. The first sample-and-hold circuit comprises a first
A current source, a first MOS transistor, a first sample and hold switch, and a second sample and hold switch; a drain of the first MOS transistor is connected to the first current source; a source of the first MOS transistor is grounded; The first and second sample and hold switches are simultaneously turned on and off based on the first clock pulse, the current signal is input to the drain of the first MOS transistor via the first sample and hold switch, and the second sample and hold switch is Connected between the gate and the drain of the first MOS transistor to short-circuit the gate and the drain of the first MOS transistor, the second sample-and-hold circuit comprises a second current source and a second MOS transistor, Signal to the next stage A first system to be output to the flop, the hold current signal and a third current source and a 3MOS transistor outputs to said adder means 2
And a drain of the second MOS transistor is connected to a second current source and connected to the first sample and hold circuit via the third sample and hold switch. Connected to a drain, the source of the second MOS transistor is grounded, and the fourth sample-hold switch is connected between the gate and the drain of the second MOS transistor to short-circuit the gate and the drain of the second MOS transistor. The drain of the third MOS transistor is connected to a third current source, the source of the third MOS transistor is grounded, the gate of the third MOS transistor is connected to the gate of the second MOS transistor, and the third and fourth sample hold switches are The second clock pal Code division multiple access communication system according to claim 8, characterized in that is turned on and off at the same time based on. 10. The code division multiplex communication device according to claim 9, wherein each of the MOS transistors comprises an n-channel MOSFET. 11. Each of the current sources is a p-channel MOSFET.
10. The code division multiplex communication device according to claim 9, wherein the code division multiplex communication device is constituted by T. 12. Each of the MOS transistors is an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined so as to improve saturation characteristics.
The code division multiplex communication device according to claim 9, comprising: 13. The equivalent MOSFET includes three n-channel MOSFETs.
One OSFET is used, and as a whole an n-channel MO
The code division multiplex communication device according to claim 12, which operates as an SFET. 14. Each of the current sources has an n-channel MOSFET and a p-channel MOSFET so that a saturation characteristic is improved.
The code division multiplex communication device according to claim 9, comprising an equivalent MOSFET combined with ET. 15. The three equivalent p-channel MOSFETs are used as the equivalent MOSFETs.
One OSFET is used, and as a whole a p-channel MO
The code division multiplex communication device according to claim 14, which operates as an SFET. 16. The first sample and hold circuit, comprising: a first current source MOS transistor, a first sample and hold MOS transistor, a first sample and hold switch, and a second sample and hold switch. A drain of the MOS transistor is connected to a drain of the first current source MOS transistor, a source of the first sample and hold MOS transistor is grounded, and the current signal is supplied to the first sample and hold switch via a first sample and hold switch. MOS for
The second sample-and-hold switch is input to the drain of the transistor, and is connected to the first sample-and-hold MO.
The first sample-hold switch is connected between the gate and the drain to short-circuit the gate and the drain of the S transistor, and is turned on and off based on the first clock pulse. A synchronous switch that is turned on and off in synchronization with the second sample and hold switch is connected to the gate, and a current variation based on an injection current injected into a parasitic capacitance between the gate and the source of the first sample and hold MOS transistor. A first short-circuit switch for short-circuiting the gate and the drain of the first current source MOS transistor is connected between the gate and the drain of the first current source MOS transistor so as to generate a variation current corresponding to the first synchronization. The switch and the second sample and hold switch receive the third clock pulse and The first sample-and-hold switch is turned on in the first half of the on-period, and the first short-circuit switch is turned on in the latter half of the on-period upon input of a fourth clock pulse, thereby offsetting the current fluctuation by the fluctuation current. The code division multiplex communication device according to claim 8, wherein: 17. The second sample-and-hold circuit includes a first system that includes a second current source MOS transistor and a second sample-hold MOS transistor and outputs a held current signal to a next-stage current flip-flop. A second system comprising a third current source MOS transistor and a third sample and hold MOS transistor and outputting a held current signal to the addition / subtraction means;
A sample-and-hold switch and a fourth sample-and-hold switch, wherein the drain of the second sample-and-hold MOS transistor is connected to the drain of the second current-source MOS transistor and the third sample-and-hold switch is connected to the drain of the second current-source MOS transistor. The second sample-and-hold M is connected to the drain of one sample-and-hold circuit.
The source of the OS transistor is grounded, the held current signal is input to the drain of the second sample and hold MOS transistor via the third sample and hold switch, and the fourth sample and hold switch is connected to the second sample and hold switch. The third sample-and-hold switch is connected between the gate and the drain to short-circuit the gate and the drain of the second MOS transistor, based on the second clock pulse. A second synchronous switch that is turned on and off in synchronization with the fourth sample and hold switch is connected to a gate of the second sample and hold switch, and a second synchronous switch is connected to a parasitic capacitance between the gate and the source of the second sample and hold MOS transistor. Fluctuating power equivalent to the current fluctuation based on A second short-circuit switch for short-circuiting the gate and the drain of the second current source MOS transistor to generate a current, the drain of the third sample and hold MOS transistor being connected to the third current source MOS transistor , The source of the third sample-and-hold MOS transistor is grounded, the gate of the third sample-and-hold MOS transistor is connected to the gate of the second sample-and-hold MOS transistor, and the third current source The gate of the MOS transistor for use is connected to the gate of the MOS transistor for the second current source, and the second synchronous switch and the fourth sample hold switch receive the fifth clock pulse and turn on the third sample hold switch. Turned on in the first half of the section, Use switch the sixth
17. The code division multiplex communication device according to claim 16, wherein a clock pulse is input and turned on in a latter half of an ON period of the third sample hold switch, so that the current fluctuation is canceled by the fluctuation current. 18. The code division multiplex communication device according to claim 17, wherein each of the sample MOS transistors is formed of an n-channel MOSFET. 19. The current source MOS transistor comprises a p-channel MOSFET.
2. The code division multiplex communication device according to item 1. 20. Each of the sample-and-hold MOS transistors has an n-channel MOS transistor so that a saturation characteristic is improved.
2. The semiconductor device according to claim 1, wherein the equivalent MOSFET is a combination of an OSFET and a p-channel MOSFET.
8. The code division multiplex communication device according to 7. 21. The equivalent MOSFET includes the three n-channel MOSFETs, and the p-channel MOSFETs.
One OSFET is used, and as a whole an n-channel MO
The code division multiplex communication device according to claim 20, which operates as an SFET. 22. Each of the current source MOS transistors is an n-channel MOSFE so that a saturation characteristic is improved.
Equivalent M combining T and p-channel MOSFET
18. The code division multiplex communication device according to claim 17, comprising an OSFET. 23. The three equivalent p-channel MOSFETs are used as the equivalent MOSFETs, and the n-channel MOSFETs
One OSFET is used, and as a whole a p-channel MO
23. The code division multiplex communication device according to claim 22, which operates as an SFET. 24. Each of the switches is composed of a MOS transistor, and each of the MOS transistors is composed of an equivalent MOSFET in which an n-channel MOSFET and a p-channel MOSFET are combined so as to improve a saturation characteristic. The code division multiplex communication device according to claim 17. 25. The code division multiplex communication device according to claim 17, wherein each of said switches comprises a CMOS switch. 26. A gate width with respect to a gate length L of each MOS transistor, in order to suppress a current variation based on an injection current injected into a parasitic capacitance between a gate and a source of each sample and hold MOS transistor. W
18. The code division multiplex communication apparatus according to claim 16, wherein the ratio W / L of the code division multiplex communication is about 62.5 times. 27. A clock having a frequency twice as high as the frequency of a clock signal when the number of sample and hold circuits is twice the number of arrayed chip information and the number of sample and hold circuits is the same as the number of arrayed chip information. The code division multiplex communication device according to claim 1, wherein the current signal is sampled by a signal. 28. Code division multiplexing according to claim 1, further comprising current / voltage conversion means for converting said correlation current signal into a voltage signal between said addition / subtraction means and said demodulator. Communication device. 29. The first differential amplifier, wherein the current / voltage conversion means receives the correlation current signal and applies a bias voltage, and outputs a voltage signal of a sum of a current signal conversion voltage and a bias voltage. And a circuit, to which the sum voltage signal is input, a bias voltage having the same value as the bias voltage is applied, and the bias voltage is removed from the sum voltage signal to output a voltage signal corresponding to the correlation current signal. 29. The code division multiplex communication apparatus according to claim 28, further comprising a second differential amplifier circuit. 30. The current cut means is provided on the side of the MOS transistor for the second current source and on the side of the MOS transistor for the third current source. 18. The code division multiplex communication device according to item 17. 31. The code division multiplex communication apparatus according to claim 5, wherein the correlator is provided with a subclock oscillator that receives the clock signal and generates each clock pulse.