JP3868864B2 - Matched filter for code division multiplexing - Google Patents

Description

【００８７】
また、電流メモリＣＭ’１〜ＣＭ’５、ＣＭ’６〜ＣＭ’１０に保存されている部分相関電流信号は以下に示す表２の通りである。
【００８８】
【表２】

【００８９】
従って、例えば、時刻ｔ＋１１Δｔ後に、電流メモリＣＭ’５に保存されている部分相関電流信号と電流メモリＣＭ’１０に保存されている部分相関電流信号とを、基礎系列Ｓの符号に従って各切り替えスイッチＳＷｂ５’とＳＷｂ’１０とを符号非反転側接続線４０、符号反転側接続線４１に切り替え接続して、部分相関電流信号を取り出すと、全ての電流信号ａ１〜ａ５、−ａ１〜−ａ５に対応する相関が含まれかつ逆拡散データに対応する最も大きな相関信号が得られることになる。なお、残余の切り替えスイッチは切断状態に維持する。
【００９０】
ここでは、基礎系列Ｓの要素の個数をｎ＝５、基礎系列Ｓの繰り返し回数をＮ＝２として説明したが、一般に、各切り替えスイッチＳＷｂ’（ｎ）、ＳＷｂ’（２ｎ）、…、ＳＷｂ’（ｎＭ）を同時に基礎系列Ｓの符号に従って符号非反転側接続線４０、符号反転側接続線４１に接続すれば、最終的な相関電流信号の出力を得ることができる。
【００９１】
すなわち、一般に、基礎系列Ｓの要素の個数ｎ個毎に相関が得られるので、ｎ個おきの第２電流メモリに記憶されている部分相関電流信号をＮ個加算すれば、基礎系列ＳをＮ個組み合わせたものからなる拡散符号の相関信号を得ることができる。
【００９２】
この構成によれば、入力された電流信号は、いずれの符号のクロック期間でも２回の転送で、相関信号を出力させることができ、電流信号の転送回数を大幅に削減できる。従って、電流信号の転送誤差の累積による相関信号の劣化を避けることができる。
【００９３】
これに対して、図２に示す場合には、相関を取る際に転送回数が異なる電流信号を加算することにより、誤差の累積発生度合いが各電流信号で異なることになるが、この発明の場合には、全ての電流信号を２回のみで転送で相関を取ることができ、かつ、一般的に使用される符号は「＋１」、「−１」で数が等しいという性質を有する。従って、各電流メモリで生じる電流オフセットによる電流誤差は、互いにキャンセルすることになり、一つの電流メモリにオフセットによる電流誤差があったとしても、相関電流信号ではこれらがキャンセルされる。
【００９４】
また、基本系列の「１」と「−１」の個数と基本系列Ｓの繰り返し数「＋」、「−」の個数が一致しているとき、オフセット誤差もキャンセルされる。
【００９５】
この相関器を用いた場合の消費電力は、同時に作動する電流源の個数で推定でき、一クロック時間Δｔ内に動作する電流源の個数は、電流メモリＣＭについてｎ個、電流メモリＣＭ’でＮ個であり、合計（ｎ＋Ｎ）個であり、従来は、ｎ×Ｎ個の電流源を動作させなければならなかったが、この発明によれば、（ｎ＋Ｎ）個の電流源を作動させるのみですむので、大幅に消費電力を削減できる。
【００９６】
【発明の効果】
本発明に係わるマッチドフィルタは、電流転送誤差に起因する相関電流信号の出力誤差を低減することができると共に、同時に動作する電流メモリの個数を減少させることによりカレントカット率以上の低消費電力の動作を実現でき、特に短周期の基礎系列の繰り返しにより生成する拡散符号に用いるのに好適である。
【図面の簡単な説明】
【図１】 基礎系列の要素個数に対応するｎ個の電流メモリを有する相関器をＮ個直列に接続して相関器を構成した例を示す図である。
【図２】 基礎系列の要素個数に対応するｎ個の電流メモリを有する１個の相関器を遅延回路を用いて遅延させて相関器を構成した例を示す図である。
【図３】 本発明に係わる相関器の発明の実施の形態を示す説明図である。
【図４】 電流メモリの構成の一例を示す図である。
【図５】 電流メモリのサンプリング状態を示す説明図である。
【図６】 電流メモリのホールド状態を示す説明図である。
【図７】 電流メモリの出力状態を示す説明図である。
【図８】 第１電流メモリへの電流保持タイミングと第１電流メモリからの電流出力タイミングと示すタイミングチャートある。
【図９】 第２電流メモリへの電流保持タイミングと第２電流メモリからの電流出力タイミングとを示すタイミングチャートである。
【符号の説明】
３０…第１入力切り替えスイッチ回路
３１…第１電流メモリ回路
３２…第１出力切り替えスイッチ回路
３３…＋側接続線
３４…−側接続線
３５…第１電流加算回路
３７…第２入力切り替えスイッチ回路
３８…第２電流メモリ回路
３９…第２電流加算回路
４０…符号反転側接続線
４０’…第２出力切り替えスイッチ回路
４１…符号非反転側接続[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a matched filter of a code division multiplex communication system, and more particularly to a matched filter that can operate with low power consumption while reducing a current transfer error.
[0002]
[Prior art]
Conventionally, in the communication field using Code Division Multiple Access (CDMA), baseband data (baseband information signal) is multiplied by a spreading code (spreading code) and this is multiplied by a carrier (wireless). The transmission carrier is multiplied and transmitted from the antenna of the transmitter. As a result, the band of the baseband information signal is spread to a wider band than the band of the baseband information signal by a predetermined spreading code set, superimposed on the radio transmission carrier, and transmitted from the antenna. Sent.
[0003]
In the receiving apparatus, a despread code having the same phase as the spread code used at the time of transmission is prepared, and baseband data is demodulated using a correlator (matched filter).
[0004]
In this code division multiplex communication system, other multiplex communication systems (FDMA, TDMA) have an upper limit on the number of users, and a certain number of users cannot be allowed. Since the number of users can be increased, and the communication quality is elegantly and gradually deteriorated, it has excellent interference resistance, signal concealment, and fading resistance.
[0005]
As the correlator, a sliding correlator, a SAW (Surface Acoustic Wave) matched filter, a digital LSI matched filter, and the like are known.
[0006]
The sliding correlator circulates the spreading code earlier than the received signal, and performs synchronization pull-in by a determination circuit having a DLL (Delay Locked Loop) or the like. This sliding correlator has a drawback in that it takes time to acquire synchronization because a frequency signal having a chip rate of which carrier component has been removed by synchronous detection or equivalent means is input and chip synchronization is required. .
[0007]
On the other hand, the SAW matched filter can perform high-speed chip synchronization and can be used in the RF band and IF (intermediate frequency) band, but the spreading code is determined by the physical pattern of the SAW device. There are drawbacks that it is difficult to change the code and it is difficult to cope with a long spreading code.
[0008]
The digital LSI matched filter does not require chip synchronization and has an advantage that the spread code can be easily changed, but has a disadvantage of high power consumption. Furthermore, the conventional digital LSI matched filter based on the CMOS integrated circuit technology has a drawback that it is generally usable only in the baseband because of its low operation speed.
[0009]
In this code division multiplexing communication device, the same band can be shared by a number of communication channels by spreading the information signal using a longer spreading code by expanding the band and using a longer spreading code. It has the advantage that it can improve the resistance to multipath and fading, which are degradation factors, and improve the radio wave usage efficiency. In addition, to perform handoff between cells following the rapid change of radio wave environment Therefore, it is required to further shorten the time required for synchronization and to reduce power consumption as much as possible for use as a mobile phone or the like.
[0010]
In order to meet these requirements, a correlator that operates at a high speed using a wider band (longer spreading code) and consumes less power is required.
[0011]
[Problems to be solved by the invention]
As means for solving these problems, Japanese Patent Application No. 10-7998 proposes a current mode matched filter (Switched Current (I) Matched Filter (SIMF)). In the one disclosed in Japanese Patent Application No. 10-7998, a received signal is converted into a current signal by a voltage-current converter, and a number (N) of current flip-flops (CDFFs) corresponding to spreading codes are serially connected. Then, the current signal is stored in the first current flip-flop (CDFF) of the N current flip-flops, and (N-1) ) Transfer times.
[0012]
Simultaneously with this transfer, the same current data (N) as the current data (N) respectively stored in the N current flip-flops (CDFF) is output to the switch matrix corresponding to the current multiplication circuit, and the spreading code is output. Is added to perform current addition.
[0013]
This current multiplication circuit has a feature that the multiplication circuit can be realized only by switching the current path, and the addition circuit can be realized only by connection of the current path, so that the multiplication circuit and the addition circuit can be realized with a very simple configuration.
[0014]
In the case of the conventional digital matched filter, the power consumption increases as the operating frequency increases, that is, the clock frequency increases. In the case of the digital matched filter disclosed in Japanese Patent Application No. 10-7998, the circuit The power consumption of the current memory circuit that occupies the majority hardly increases even if the operating frequency (clock frequency) increases.
[0015]
Also, the current mode matched filter has a fast maximum operating frequency because the parasitic capacitance of the current memory MOS diode of the current memory circuit as the basic configuration of the current mode circuit is very small.
[0016]
Therefore, when the operating frequency is lower than the maximum frequency of the current memory circuit, the current source that drives the current mode circuit is operated only for a minimum time necessary for storing current and outputting current data. At other times, it is possible to adopt a power consumption reduction method called current cut that reduces power consumption by temporarily stopping the current of the driving constant current source.
[0017]
However, in the current mode matched filter disclosed in Japanese Patent Application No. 10-7998, the current memory stores the current data, and the current is only the number of times corresponding to the number of codes of the spread code (the code length is −1). Data must be transferred. Therefore, as the number of current data transfers increases, current transfer errors per stage accumulate, and there is a problem that the correlation current signal (correlation output data) that is finally output deteriorates.
[0018]
In order to suppress the transfer error per stage of the current memory, a configuration method such as a 2-stage current memory circuit has been proposed. However, the circuit configuration becomes complicated, and at the same time, error accumulation occurs due to repeated transfer. The influence on the correlation value is still large.
[0019]
As a method for reducing this current transfer error, Japanese Patent Application No. 11-251954 (Japanese Patent Application Laid-Open No. 2000-224074) has proposed that the number of times of current transfer is one and the accumulation of current transfer errors is reduced.
[0020]
In this case, the accumulated current transfer error can be reduced to reduce the error in the dynamic range of the output of the correlated current signal, and the means for storing the current data is one current memory for one spreading code. As a result, the number of current sources can be reduced to about 1/3 compared to the case of using a current flip-flop, and the power consumption can be reduced. This current mode matched filter is called a parallel SIMF.
[0021]
Both the current mode matched filter disclosed in Japanese Patent Application No. 10-7998 and the current mode matched filter disclosed in Japanese Patent Application No. 11-251954 can reduce power consumption by adopting a current cut method. In any case, when performing the correlation operation, all the current memories of n × N corresponding to the number of codes of the spread code must be operated at the same time, so that the power consumption more than the current cut rate is reduced. There is an inconvenience that cannot be done.
[0022]
Further, power consumption is large even when a long-period spreading code is generated by repeating a short-period basic sequence S used for the basis of spreading code generation a plurality of times.
[0023]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the output error of the correlation current signal due to the current transfer error and to the number of current memories that operate simultaneously. Is to provide a matched filter that can achieve low power consumption operation that is equal to or higher than the current cut rate by reducing the frequency, and in particular, provides a matched filter suitable for use in spreading codes generated by repetition of a short-cycle basic sequence There is to do.
[0024]
[Means for Solving the Problems]
  The matched filter according to claim 1, wherein the matched filter is a spreading code configured by combining N basic sequences that are composed of n elements and exhibit the same state in a predetermined cycle, and the basic sequence has positive and negative codes. In a matched filter of a code division multiplex communication method in which a receiver receives radio waves transmitted by distributing information using a spreading code composed of a combination of inverted ones and demodulates the information,
  A voltage-current conversion circuit that converts a received output voltage received by the receiver into a received input current;
  A first current memory circuit having n current memories corresponding to the number of elements constituting the basic sequence and storing the received input current as current data in time series for each clock time;
  In order to store the current signal as the current data by switching the received input current from each voltage-current conversion circuit in time series for each clock time and delaying in time in each current memory of the first current memory circuit A first input changeover switch circuit having n first input changeover switches in parallel;
  The current data stored in each current memory of the first current memory circuit is directly connected to the + side connection line and the current data stored in each current memory is inverted and taken out. A first current adding circuit for simultaneously taking out and adding / subtracting current data stored in each of the current memory circuits;
  Current data stored in each of the current memories is provided with n first output changeover switches that are respectively switched according to the despreading code of the basic sequence between the + side connection line and the − side connection line. A first output changeover switch circuit that simultaneously adds and outputs a partial correlation current signal;
  A second current memory circuit having n × N current memories for storing a partial correlation current signal output in time series from the first current addition circuit in time series as partial correlation data;
  Provided between the first current adding circuit and the second current memory circuit, the partial correlation current signal is switched in time series for each clock time, and each current memory of the second current memory circuit is time-sequentially A second input changeover switch circuit having n × N second input changeover switches in parallel for storing the partial correlation current signal as the partial correlation data after being delayed
  A sign non-inversion side connection line that extracts current data stored in each current memory of the second current memory circuit as it is and a sign inversion side connection line that inverts and extracts current data stored in each current memory. A second current adding circuit connected to the current data stored in each of the current memory circuits for simultaneous extraction, addition and subtraction;
  There are n × N second output changeover switches that are respectively switched according to the code of the basic sequence between the non-inversion-side connection line and the inversion-side connection line, and are stored in the current memories. A second output changeover switch circuit for adding N pieces of data out of the partial correlation data and outputting them as a correlation current signal;
  Current-voltage conversion circuit for converting the correlation current signal output from the second current addition circuit into a voltageAnd
  Each of the n first input changeover switches connects the corresponding first current memory and the voltage-current conversion circuit only once in the first half of the clock time and within one period of the basic sequence. Controlled by
The n first output changeover switches are configured so that the n current memories are simultaneously connected to either the + side connection line or the − side connection line at a timing in the second half of the clock time. Controlled according to the despreading code of the sequence,
The n × N second input change-over switches correspond to second times corresponding to the second half of the clock time and after the connection timing of the first output change-over switch, and only once in one period of the basic sequence. Control to connect a current memory and the first current adding circuit And
The n × N second output changeover switches are configured so that the N second current memory circuits at the first half of the clock time and the n second current memory circuits are connected to the sign non-inversion side connection line and the sign inversion side connection line at the same time. Controlled according to the code of the base sequence to be connected to eitherIt is characterized by that.
[0026]
    Claim 2The listed matched filter is
  Each current memory includes one current source, one memory MOS transistor, a first on / off switch, and a second on / off switch, and the current source is connected to a drain of the memory MOS transistor, The source of the memory MOS transistor is grounded, the input changeover switches are provided between the voltage-current conversion circuit and the drain of the memory MOS transistor, and the first on / off switch is connected between the gate of the memory transistor and the drain. The second on / off switch is provided between the drain and the first output changeover switch circuit.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Here, it is assumed that a short-cycle basic sequence S used as a basis for generating a spreading code includes the following elements.
[0028]
That is, the basic sequence S = (a₁, a₂, a_Three, ..., a_i, ..., a_n) And element a_i(I is an integer from 1 to n) is either “+1” or “−1”. Element a_iThe number of is n.
[0029]
Spreading code (correlation code) S_NnIs composed of a plurality of repetitions of the basic sequence S. That is, the basic series S_j(J is an integer from 1 to N) as an element._jN correlation codes S_NnIs generated.
[0030]
S_Nn= {S₁, S₂, ..., S_j, ..., S_N}
Where {S₁, S₂, ..., S_j, ..., S_N} Is S_j= (A_1i, a_2i, ..., a_ji, ..., a_jnOr S_j= (-A_1i, -A_2i, ...,-a_ji, ...,-a_jn). That is, an element in which the code of the element of the basic sequence S is used as it is and an element in which the code of the element of the basic sequence S is inverted are used in appropriate combination.
[0031]
For example, the basic series S_jWhen the value of (−1, 1, −1,..., 1,..., −1) is the basic sequence −S obtained by inverting the sign of the value of the basic sequence Sj._jIs (1, -1,1, ...,-1, ..., 1).
[0032]
These are called Golay codes and are used for code multiplex communication synchronization codes and spreading codes.
[0033]
Basic series S_jThe spreading code S generated using the repetition of_NnAn example of the circuit configuration of the correlator is shown in FIG.
[0034]
In FIG. 1, reference numeral 1 denotes a voltage / current conversion circuit constituting a part of a correlator. The voltage-current conversion circuit 1 is composed of, for example, a differential amplifier and a voltage follower circuit described in Japanese Patent Application No. 7998.
[0035]
This basic series S_jWhen a correlator using the repetition of the above is manufactured according to a general general idea, the following configuration is obtained.
[0036]
Since this correlator uses repetitions of N basic sequences S, in general, N basic sequence correlators SC are used._j(J is an integer from 1 to N). That is, the basic sequence correlator SC_jN is the basic sequence S_iIs equal to the number of repetitions N.
[0037]
Correlator SC for each basic series_jComprises a current delay means 2, a first connection state switching means 3, and a first current adding means 4.
[0038]
Each current delay means 2 includes n current delay flip-flops SD._k(K is an integer from 1 to n). Current delay flip-flop SD_kN is the element a of the basic sequence S_iIs equal to n. Each current delay flip-flop SD_kSamples and holds the current signal.
[0039]
The first output changeover switch circuit 3 is provided with a + side connection line 5 and a − side connection line 6. Each current delay flip-flop SD_kHas one input terminal 7 and two output terminals 8 and 9, each input terminal 7 having a current delay flip-flop SD of the previous stage._kCurrent output from one output terminal 8 of the current delay flip-flop SD of the preceding stage_k-1The current signal (current data) stored in the memory is input.
[0040]
However, the first basic sequence correlator SC₁The first current delay flip-flop SD₁The current signal from the voltage-current conversion circuit 1 is input to the input terminal 7. The Nth basic sequence correlator SC_NThe output of the n-th one output terminal 8 is not used.
[0041]
The current signal output from one output terminal 8 of the last-stage current-correlator SCj of each basic series correlator SCj is the input terminal 7 of the first current-delay flip SD1 of the next-stage basic series correlator SCj. Is input.
[0042]
Each current delay flip-flop SD_kThe other output terminal 9 is connected to each first output selector switch SW._rIt is possible to switch between the + side connection line 5 and the − side connection line 6 via (r is an integer from 1 to n). Each first output selector switch SW_rNumber n of basic series S_jElement a_iIs equal to the number of
[0043]
Each first output selector switch SW_rAre switched by input of despread data from a control circuit (not shown). Each first output selector switch SW_rWhen the despread data “+1” is input, it is connected to the + side connection line 5, and when the despread data “−1” is input, it is connected to the − side connection line 6.
[0044]
The first current adding circuit 4 has an inverting circuit 10, and the output of the − side connection line 6 is inverted and added to the output of the + side connection line 5, whereby each base series correlator SC._jCurrent multiplication and addition are executed for, a process corresponding to the correlation process is executed, and a partial correlation signal is output.
[0045]
Correlator SC for each basic series_jEach correlation process corresponds to the correlation process in the case where the basic sequence is not repeated, and details thereof are described in the invention of the detailed description of the invention of 1998 Patent Application No. 7998 (Japanese Patent Laid-Open No. 11-205282). The detailed description will be omitted here because it is well known in the embodiment.
[0046]
The output terminal 11 of each first current adding circuit 4 is connected to the second output changeover switch circuit 12 at the subsequent stage. The second output changeover switch circuit 12 includes a sign non-inversion connection line 13 and a sign inversion connection line 14. The output terminal 11 of the first current adding circuit 4 is connected to each second output changeover switch SW._pThe sign non-inversion connection line 13 and the sign inversion connection line 14 can be connected via (p is an integer from 1 to N).
[0047]
Each second output selector switch SW_pAre switched by the input of non-inverted data and inverted data from a control circuit (not shown). That is, the basic series SC_jIs a non-inverted one, the first output selector switch SW_pIs connected to the non-inverted connection line 13 and the basic sequence SC_jIs inverted, it is connected to the sign inversion connection line 14.
[0048]
The output of the sign inverting connection line 14 is inverted through an inverting circuit 16 constituting a part of the second current adding means 15 and added to the output of the sign non-inverting connection line 13. A correlated current signal is obtained as the final output. This correlation current signal is converted into a voltage by the current-voltage conversion circuit 17 and finally outputted as a correlation output signal.
[0049]
In the case of this normal correlator, the current delay flip-flop SD_kIs the correlator SC for the basic sequence_jN is the number of correlators SC for each basic sequence_jCurrent delay flip-flop SD constituting a part of_kN × N, so that the current signal is converted into a current delay flip-flop SD in the subsequent stage n × N times._kEach current delay flip-flop SD must be transferred to_kTo the next-stage current delay flip-flop SD_kThe degree of accumulation of transfer errors when transferring a current signal (current data) to increases, and the final correlation output signal deteriorates.
[0050]
As explained above, the basic sequence S_jWhen a correlator (matched filter) corresponding to the repetition of the above is simply manufactured, a number of correlators corresponding to the number of repetitions of the basic sequence S can be prepared and manufactured in series. Has a large accumulation degree of current transfer error.
[0051]
Therefore, a short-cycle basic sequence S_jAs shown in FIG. 2, one basic sequence correlator SC is used as a correlator (matched filter).₁The first output changeover switch circuit 3, the first current adder circuit 4, the current distribution circuit 20, and the (N-1) current delay circuits SI._qAnd a second output changeover switch circuit 12, a second current addition circuit 15, and a current-voltage conversion means 17.
[0052]
Correlator SC for basic series₁The first output changeover switch circuit 3, the first current adder circuit 4, the second output changeover switch circuit 12, and the second current adder circuit 15 have the same configurations as those in FIG. 1, and therefore correspond to the circuit elements in FIG. The circuit elements to be described are denoted by the same reference numerals as those in FIG. The partial distribution current output from the first current adding means 4 is input to the current distribution circuit 20 as current data.
[0053]
The current distribution circuit 20 has two output terminals 21 and 22. The current distribution circuit 20 distributes current data having the same sign and the same absolute value, and one output terminal 21 is connected to the changeover switch SW.₁The connection is switched between the sign non-inversion connecting line 13 and the sign inversion connecting terminal 14 via the.
[0054]
Current delay circuit SI_qThe number of the current delay circuits SI is (N-1)._qHas one input terminal 23 and two output terminals 24, 25. Each current delay circuit SI_qConsists of a series connection of n current delay flip-flops, for example, and delays current data (partial correlation signal) for a time n times the period t of the clock signal. This delay time n × t is the basic sequence S_jIs equal to one period T.
[0055]
Each current delay circuit SI_qOne output terminal 24 (q is an integer from 1 to n) is connected to the changeover switch SW._pThe connection is switched between the sign non-inversion connection line 13 and the sign inversion connection terminal 14 via (an integer from p = 2 to n). Each current delay circuit SI_qThe other output terminal 25 (an integer from p = 2 to n) is connected to each current delay circuit SI in the next stage._qIt is connected to input terminals 23 (integers from p = 2 to n).
[0056]
The output of the second output changeover switch circuit 12 is input to the second current addition circuit 15 and is output as a final correlation output signal by the current-voltage conversion circuit 17.
[0057]
Also in the correlator having the configuration shown in FIG. 2, the current data transfer count is n + (N−1) × n = n × N, and the current data transfer count is the current data transfer of the correlator having the configuration shown in FIG. It is the same as the number of times.
[0058]
The embodiment of the present invention will be described below with reference to FIG.
[0059]
Here, the basic series S₁Is element a_iN is “5”, that is, S₁= (A1, a2, a3, a4, a5). Here, for example, element a₁= 1, element a₂= -1, element a_Three= 1, element a_Four= 1, element a_Five= -1.
[0060]
The spreading code S_NnThe number N of “2” is “2”. Basic series S₁And basic series S₁Basic sequence with the sign of -S reversed₁It is assumed that a signal composed of the combination of signals arrives from time t0.
[0061]
An output voltage including these signals is input to the voltage / current signal converter 1. These voltage signals are converted into input current signals by the voltage-current signal converter 1. The first input changeover switch circuit 30 has a number of first input changeover switches SWa1 to SWa (n) corresponding to the number n of elements of the basic sequence S (here, n = 5).
[0062]
The first input changeover switches SWa1 to SWa (n) serve to connect the n current memories CM1, CM2,..., CM (k), ..., CM (n) and the voltage / current signal converter 1. . Each of the current memories CM <b> 1 to CM (n) constitutes a first current memory circuit 31.
[0063]
As shown in FIG. 4, each current memory CM includes a constant current source 32, two on / off switches SWo <b> 1 and SWo <b> 2, and a memory MOS transistor 33. The on / off switch SWo1 is provided between the drain and gate of the memory MOS transistor 33. The input current signal Iin is input to the memory MOS transistor 33 via the first input changeover switch SWa. The on / off switch SWo1 and the first input selector switch SWa are turned on simultaneously when sampling the input current signal Iin. The on / off switch SWo2 is turned on when a current signal stored in the memory MOS transistor 33 is taken out as current data.
[0064]
When the on / off switch SWo1 and the first input changeover switch SWa are simultaneously turned on, the current is added to the current J of the constant current source 32 and a current signal of J + Iin flows into the memory MOS transistor 33 as shown in FIG. , A unique gate voltage Vg is provided and the input current signal Iin is sampled. At this time, the on / off switch SWo2 is in the off state.
[0065]
Subsequently, when the first input selector switch SWa and the on / off switch SWo1 are turned off, the gate voltage Vg is stored as a parasitic capacitance Cp between the gate and the source of the memory MOS transistor 33 as shown in FIG. Here, even if the current J of the current source 32 flowing through the memory MOS transistor 33 is temporarily stopped, the gate voltage Vg is stored and held as the parasitic capacitance Cp, and the input current signal Iin is held. In other words, the so-called current cut can save the power consumption required to pass the current J to the memory MOS transistor 33.
[0066]
Next, when the on / off switch SWo2 is turned on simultaneously with the turning on of the first output changeover switch SWb, the current of J + Iout flows to the first output changeover switch SWb, but when an ideal current source is connected to the output side, The current value Iout can be drawn. As a result, as shown in FIG. 7, current data having the opposite sign to the current data stored and held in the memory MOS transistor 33 is output via the on / off switch SWo2. The configuration of a current memory CM ′ described later is also the same.
[0067]
The first input changeover switches SWa1 to SWa (n) are connected to the basic series S as shown in FIG.₁Are turned on in time series only once every n times the clock time Δt. That is, the basic series S₁In the first half of the clock time Δt of one cycle T, it is turned on only once in time series, and the remaining period is turned off.
[0068]
Thus, for example, time t = T₀After + 5Δt, the current signal corresponding to the element a1 is stored in the current memory CM1, the current signal corresponding to the element a2 is stored in the current memory CM2, and the current signal corresponding to the element a3 is stored in the current memory CM3. The current signal corresponding to the element ak is stored and held in the current signal CM (k), and the current signal corresponding to the element an is stored and held in the current memory CM (n).
[0069]
In this case, the oldest data is stored in the current memory CM1, new data is stored in the order from the current memory CM2 to the current memory CM (n−1), and the newest data is stored in the current memory CM (n). It will be.
[0070]
For example, after time t = T0 + 6Δt, the current signal corresponding to the element −a1 is stored and held in the current memory CM1, the current signal corresponding to the element a2 is stored and held in the current memory CM2, and the element a3 is stored in the current memory CM3. The current signal corresponding to element an is stored and held in the current signal CM (k), and the current signal corresponding to element an is stored and held in the current memory CM (n). Will be. In this case, the newest data is stored in the current memory CM1.
[0071]
The current memories CM <b> 1 and CM <b> 2 are connected to the first current addition circuit 35 via the first output changeover switch circuit 32. The first output changeover switch circuit 32 has n first output changeover switches SWb1, SWb2, ..., SWb (k), ..., SWb (n) corresponding to the number of current memories CM1 to CM (n). . Each of the current memories CM1 to CM (n) is connected between the + side connection line 33 and the − side connection line 34 by the first output changeover switches SWb1, SWb2,..., SWb (k),. Is switched and connected. The first current adding circuit 35 includes a + side connection line 33, a − side connection line 34, and an inverting circuit 36, and the − side connection line 34 is connected to the + side connection line 33 via the inverting circuit 36.
[0072]
Each of the first output selector switches SWb1, SWb2,..., SWb (k),.₁Are simultaneously turned on during the latter half of the clock time Δt of one cycle T. The changeover switches SWb1, SWb2,..., SWb (k),..., SWb (n) are simultaneously connected to the + side connection line 33 and the − side connection line 34 according to the despread code. That is, the basic series S₁When a current signal based on is arriving, the basic sequence S₁The connection state is switched to the + side connection line 33 and the −side connection line 34 according to the despreading code corresponding to the base sequence −S.₁When a current signal based on is arriving, the basic sequence -S₁The connection state is switched to the + side connection line 33 and the -side connection line 34 according to the despread code corresponding to
[0073]
Which of the current memories CM1 to CM (n) is the newest data is determined based on which of the first input changeover switches SWa1 to SWa (n) is on within the clock time Δt. It is judged by whether or not. Further, whether the basic sequence S or the basic sequence of sign inversion -S can be determined by counting the number of clock times Δt.
[0074]
For example, after the time t0 + 5Δt, in the previous example in which the oldest data (element an) is stored and held in the current memory CM1 and the newest data is stored and held in the current memory CM (n), the element a1 of the basic sequence S In accordance with the despread code corresponding to .about.a (n), the first changeover switches SWb1 to SWb (n) are switched so as to be simultaneously connected to either the + side connection line 33 or the -side connection line.
[0075]
Further, for example, in the previous example in which the latest data (element -an) is stored in the current memory CM1 after the time t0 + 6Δt, the first changeover switch SWb1 corresponds to the element (-an) of the basic sequence -S. The remaining first change-over switches SWb2 to SWb (n) are connected to either the + side or the − side according to the despreading code, and the remaining first change-over switches SWb2 to SWb (n) are set to the + side according to the despreading code corresponding to the elements a2 to a (n) It is connected to either the connection line 33 or the minus side connection line 34.
[0076]
Accordingly, if the ON / OFF relationship of the first input changeover switches SWa1 to SWa (n) and the changeover relationship of the first output changeover switches SWb1 to SWb (n) are controlled, the partial correlation current signal (partial correlation data) can be maintained. ) Can be obtained.
[0077]
As a result, the current data stored in each of the current memories Ma1 to Ma (n) is added by the first current adding circuit 35, and the partial correlation data from the first current adding circuit 35 is added to the second-stage partial correlation data every clock time ΔT. It is output toward the 2-input changeover switch circuit 37.
[0078]
The second input changeover switch circuit 37 includes n × N second input changeover switches SWa′1, SWa′2,..., SWa ′ (k),..., SWa ′ (n), SWa ′ (n + 1), SWa. '(N + 2), ..., SWa' (n + k), ..., SWa '(2n), SWa' {(2n) +1}, ..., SWa '{(2n) + k}, ..., SWa' {(2n) + n }, SWa ′ {n (N−1) +1},..., SWa ′ {n (N−1) + k},..., SWa ′ {n (N−1) + n}.
[0079]
The second input changeover switch circuit 37 is provided between the second current memory circuit 38 and the first current adder circuit 35. The second current memory circuit 38 has a number of second current memories CM′1, CM′2,..., CM ′ equal to the product n × N of the number n of elements a of the basic sequence S and the repetition number N of the basic sequence S. (J),..., CM ′ (n × N).
[0080]
As shown in FIG. 9, the second input changeover switch SWa ′ is turned on in synchronization with each of the first output changeover switches SWb1 to SWb (n) within the clock time of the element a of the basic sequence S1, and each second current memory. In CM′1 to CM ′ (n × N), partial correlation currents are stored and held in time series for each clock time ΔT.
[0081]
A second output changeover switch circuit 40 ′ is provided between the second current memory circuit 38 and the second current addition circuit 39. The second current adding circuit 39 includes a sign non-inversion side connection line 40, a sign inversion side connection line 41, and an inversion circuit 42, and the sign inversion side connection line 41 is connected to the sign non-inversion side connection line 40 via the inversion circuit 42. It is connected to the.
[0082]
The second output changeover switch circuit 40 'has the same number of second output changeover switches SWb'1, SWb'2, ..., SWb' (k), ..., SWb '(n) as the number of second current memories CM'. , SWb '(n + 1), SWb' (n + 2), ..., SWb '(n + k), ..., SWb' (2n), ..., SWb '(jn), ..., SWb' (jn + k), ..., SWb '( , SWb ′ {n (N−1) +1},..., SWb ′ {n (N−1) +2},..., SWb ′ {n (N−1) + n}.
[0083]
The second output changeover switch SWb 'has three types of states: a connection state to the sign non-inversion side connection line 40, a state to the sign inversion side connection line 41, and a disconnection state.
[0084]
For example, if the time t is immediately after the time t0 + 10Δt and immediately before t0 + 11Δt, the current memories CM1 to CM5 store −a1, −a2, −a3, −a4, and −a5, respectively, and the current memory CM5 The stored current signal is the newest data.
[0085]
At this time, the current signals (current data) stored in the current memories CM1 to CM5 between time t0 and time t0 + 10Δt are as shown in Table 1 below.
[0086]
[Table 1]

[0087]
The partial correlation current signals stored in the current memories CM′1 to CM′5 and CM′6 to CM′10 are as shown in Table 2 below.
[0088]
[Table 2]

[0089]
Therefore, for example, after the time t + 11Δt, the changeover switch SWb5 is switched between the partial correlation current signal stored in the current memory CM′5 and the partial correlation current signal stored in the current memory CM′10 according to the sign of the basic sequence S. When 'and SWb'10 are switched and connected to the sign non-inversion side connection line 40 and the sign inversion side connection line 41 and the partial correlation current signal is extracted, all current signals a1 to a5 and -a1 to -a5 are supported. And the largest correlation signal corresponding to the despread data is obtained. Note that the remaining changeover switches are maintained in a disconnected state.
[0090]
Here, the number of elements of the basic sequence S is described as n = 5 and the number of repetitions of the basic sequence S is described as N = 2. However, in general, each changeover switch SWb ′ (n), SWb ′ (2n),. If '(nM) is simultaneously connected to the sign non-inversion side connection line 40 and the sign inversion side connection line 41 according to the code of the basic sequence S, the final output of the correlation current signal can be obtained.
[0091]
That is, in general, since a correlation is obtained for every n elements of the basic sequence S, if N partial correlated current signals stored in every second n current memory are added, the basic sequence S is represented as N. It is possible to obtain a correlation signal of a spreading code composed of a combination of these.
[0092]
According to this configuration, the input current signal can output a correlation signal by transferring twice in any clock period, and the number of current signal transfers can be greatly reduced. Accordingly, it is possible to avoid deterioration of the correlation signal due to accumulation of current signal transfer errors.
[0093]
On the other hand, in the case shown in FIG. 2, by adding the current signals having different transfer counts when obtaining the correlation, the accumulated occurrence degree of the error differs for each current signal. Can be correlated by transferring all current signals only twice, and the commonly used codes are “+1”, “−1” and the number is equal. Therefore, the current errors caused by the current offsets generated in the respective current memories cancel each other, and even if there is a current error caused by the offset in one current memory, these are canceled by the correlation current signal.
[0094]
Further, when the number of basic sequences “1” and “−1” and the number of repetitions “+” and “−” of the basic sequence S match, the offset error is also canceled.
[0095]
The power consumption when this correlator is used can be estimated by the number of current sources operating simultaneously. The number of current sources operating within one clock time Δt is n for the current memory CM and N for the current memory CM ′. In total, (n + N) units had to be operated in the past. However, according to the present invention, only (n + N) current sources were operated. Therefore, power consumption can be greatly reduced.
[0096]
【The invention's effect】
The matched filter according to the present invention can reduce the output error of the correlation current signal due to the current transfer error, and reduce the number of current memories that operate at the same time, thereby reducing the power consumption over the current cut rate. This is particularly suitable for use in spreading codes generated by repeating a short-period basic sequence.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example in which N correlators having n current memories corresponding to the number of elements of a basic sequence are connected in series to form a correlator.
FIG. 2 is a diagram illustrating an example in which a correlator is configured by delaying one correlator having n current memories corresponding to the number of elements of a basic sequence using a delay circuit.
FIG. 3 is an explanatory diagram showing an embodiment of a correlator according to the present invention.
FIG. 4 is a diagram illustrating an example of a configuration of a current memory.
FIG. 5 is an explanatory diagram showing a sampling state of a current memory.
FIG. 6 is an explanatory diagram showing a hold state of a current memory.
FIG. 7 is an explanatory diagram showing an output state of a current memory.
FIG. 8 is a timing chart showing a current holding timing to the first current memory and a current output timing from the first current memory.
FIG. 9 is a timing chart showing a current holding timing to the second current memory and a current output timing from the second current memory.
[Explanation of symbols]
30. First input changeover switch circuit
31. First current memory circuit
32. First output changeover switch circuit
33 ... + side connection line
34 ...- side connection line
35. First current adding circuit
37. Second input changeover switch circuit
38. Second current memory circuit
39. Second current adding circuit
40 .. sign inversion side connection line
40 '... second output changeover switch circuit
41 ... Sign non-inversion side connection

Claims (2)

A spread code composed of a combination of N elements composed of N elements and having N basic sequences exhibiting the same state in a predetermined cycle, wherein the codes of the basic sequences are inverted to positive and negative In a matched filter of a code division multiplex communication system that receives a radio wave transmitted by distributing information using a code by a receiver and demodulates the information,
A voltage-current conversion circuit that converts a received output voltage received by the receiver into a received input current;
A first current memory circuit having n current memories corresponding to the number of elements constituting the basic sequence and storing the received input current as current data in time series for each clock time;
In order to store the current signal as the current data by switching the received input current from each voltage-current conversion circuit in time series for each clock time and delaying in time in each current memory of the first current memory circuit A first input changeover switch circuit having n first input changeover switches in parallel;
The current data stored in each current memory of the first current memory circuit is extracted as it is, and connected to the + side connection line and the current data stored in each current memory is inverted and extracted. A first current adding circuit for simultaneously taking out and adding / subtracting current data stored in each of the current memory circuits;
Current data stored in each of the current memories is provided with n first output changeover switches that are respectively switched according to the despreading code of the basic sequence between the + side connection line and the − side connection line. A first output changeover switch circuit that simultaneously adds and outputs a partial correlation current signal;
A second current memory circuit having n × N current memories for storing a partial correlation current signal output in time series from the first current addition circuit in time series as partial correlation data;
Provided between the first current adding circuit and the second current memory circuit, the partial correlation current signal is switched in time series for each clock time, and each current memory of the second current memory circuit is time-sequentially switched. A second input changeover switch circuit having n × N second input changeover switches in parallel for storing the partial correlation current signal as the partial correlation data after being delayed
A sign non-inversion side connection line that extracts current data stored in each current memory of the second current memory circuit as it is and a sign inversion side connection line that inverts and extracts current data stored in each current memory. A second current adding circuit connected to the current data stored in each of the current memory circuits for simultaneous extraction, addition and subtraction;
There are n × N second output changeover switches that are respectively switched according to the code of the basic sequence between the non-inversion-side connection line and the inversion-side connection line, and are stored in the current memories. A second output changeover switch circuit for adding N pieces of data out of the partial correlation data and outputting them as a correlation current signal;
A current-voltage conversion circuit that converts the correlation current signal output from the second current addition circuit into a voltage ;
Each of the n first input changeover switches connects the corresponding first current memory and the voltage-current conversion circuit only once in the first half of the clock time and within one period of the basic sequence. Controlled by
The n first output changeover switches are configured so that the n current memories are simultaneously connected to either the + side connection line or the − side connection line at a timing in the second half of the clock time. Controlled according to the despreading code of the sequence,
The n × N second input change-over switches correspond to second times corresponding to the second half of the clock time and after the connection timing of the first output change-over switch, and only once in one period of the basic sequence. Controlled to connect a current memory and the first current adder circuit;
The n × N second output changeover switches are configured so that the N second current memory circuits at the first half of the clock time and the n second current memory circuits are connected to the sign non-inversion side connection line and the sign inversion side connection line at the same time. The matched filter is controlled according to the code of the basic sequence so as to be connected to any one of them .   Each current memory includes one current source, one memory MOS transistor, a first on / off switch, and a second on / off switch, and the current source is connected to a drain of the memory MOS transistor, The source of the memory MOS transistor is grounded, each input changeover switch is provided between the voltage-current conversion circuit and the drain of the memory MOS transistor, and the first on / off switch is connected between the gate of the memory transistor and the drain. The matched filter according to claim 1, wherein the second on / off switch is provided between the drain and the first output changeover switch circuit.

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