JPH11204572A - Mounting structure of semiconductor device and manufacture thereof - Google Patents
Mounting structure of semiconductor device and manufacture thereofInfo
- Publication number
- JPH11204572A JPH11204572A JP448498A JP448498A JPH11204572A JP H11204572 A JPH11204572 A JP H11204572A JP 448498 A JP448498 A JP 448498A JP 448498 A JP448498 A JP 448498A JP H11204572 A JPH11204572 A JP H11204572A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- electrode pad
- bump
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子をフェ
ースダウンで回路基板に実装する半導体装置の実装方法
及び実装構造体に関する。The present invention relates to a semiconductor device mounting method and a mounting structure for mounting a semiconductor element face down on a circuit board.
【0002】[0002]
【従来の技術】近年、ノートパソコン、携帯電話を、P
HS、PDA、またはムービ、カメラなどの情報機器に
おいて高密度実装のニーズが益々高くなっている。これ
に対応すべく、半導体素子の実装は従来のパッケージ品
を実装する方法から、半導体素子を直接回路基板に実装
する、いわゆるベアチップ実装方式が主流になりつつあ
る。2. Description of the Related Art In recent years, notebook computers and mobile phones have been
There is an increasing need for high-density packaging in information devices such as HS, PDA, movie, and camera. In order to cope with this, the so-called bare chip mounting method, in which the semiconductor element is directly mounted on a circuit board, is becoming the mainstream, instead of the conventional method of mounting a packaged product.
【0003】従来のベアチップ実装方法は半導体素子を
フェースアップで回路基板に接着し、半導体素子と回路
基板のパッド間をワイヤボンディング工法で接続する方
法である。The conventional bare chip mounting method is a method of bonding a semiconductor element to a circuit board face-up and connecting the semiconductor element and pads of the circuit board by a wire bonding method.
【0004】従来のベアチップの実装構造体は、半導体
素子の面積以外にもワイヤボンディング用のパッド面積
及びワイヤボンディングによる配線長を必要とする。こ
れに対し、はんだ、金、導電性接着剤、異方導電性フィ
ルムなどを電気的な接続材料として半導体素子をフェー
スダウンで回路基板に接着接続する方法(Flip Chip
Attach:FCAと略)は、回路基板上の必要搭載面積は
チップサイズであり、接続配線長も数十μmであるた
め、究極の高密度実装方式である。The conventional bare chip mounting structure requires a pad area for wire bonding and a wiring length by wire bonding in addition to the area of the semiconductor element. On the other hand, a method of adhesively connecting a semiconductor element to a circuit board face down using solder, gold, a conductive adhesive, an anisotropic conductive film, or the like as an electrical connection material (Flip Chip)
Attach: FCA) is the ultimate high-density mounting method because the required mounting area on the circuit board is the chip size and the connection wiring length is several tens of μm.
【0005】該従来のFCAの実装方法は、半導体素子
の電極パッド上に突起電極(バンプ)を形成し、フェー
スダウンで回路基板に搭載と同時に加圧して半導体素子
のバンプと回路基板の電極パッドの電気的な接続を確保
し、接続信頼性の向上を目的として半導体素子と回路基
板の間に異方導電性フィルムや充填樹脂等の封止樹脂を
充填し加熱硬化する方法である。In the conventional mounting method of the FCA, a protruding electrode (bump) is formed on an electrode pad of a semiconductor element, and the bump is mounted on a circuit board face down and pressurized simultaneously with the bump of the semiconductor element and the electrode pad of the circuit board. In this method, an electric connection between the semiconductor element and the circuit board is filled with a sealing resin such as an anisotropic conductive film or a filling resin and the mixture is heated and cured for the purpose of securing electrical connection and improving connection reliability.
【0006】[0006]
【発明が解決しようとする課題】上記FCAの接続部
は、半導体素子のバンプ及び回路基板の電極パッドの高
さばらつきと、バンプと回路基板の電極パッドとの接触
面積にばらつきを持っているため、バンプと回路基板の
電極パッドの高さばらつき及び接触面積ばらつきに対応
した加圧力ばらつきが回路基板の電極パッドに加わり、
最大応力が加わった回路基板の電極パッド部は、回路基
板の電極パッドの抗張力を越えて電極パッドに亀裂を生
じる場合もあり、接続信頼性に乏しいという問題を有し
ていた。The connection portion of the FCA has a variation in the height of the bump of the semiconductor element and the electrode pad of the circuit board, and a variation in the contact area between the bump and the electrode pad of the circuit board. , The pressure variation corresponding to the height variation and the contact area variation of the bump and the electrode pad of the circuit board is applied to the electrode pad of the circuit board,
The electrode pad portion of the circuit board to which the maximum stress has been applied sometimes has a problem that the electrode pad may be cracked by exceeding the tensile strength of the electrode pad of the circuit board, resulting in poor connection reliability.
【0007】本発明の目的は、上記問題を解決すべく、
半導体素子をフェースダウンで回路基板に実装する際に
加える加圧力によって回路基板の電極パッドに加わる応
力を低減し、回路基板の電極パッドに亀裂が生じること
なく接続信頼性が向上した半導体装置の実装構造体を提
供することにある。[0007] An object of the present invention is to solve the above problems.
A semiconductor device that reduces the stress applied to the electrode pads on the circuit board due to the pressure applied when the semiconductor element is mounted face down on the circuit board, and improves the connection reliability without cracking the electrode pads on the circuit board To provide a structure.
【0008】また、本発明の他の目的は、半導体素子を
フェースダウンで回路基板に実装する際に加える加圧力
によって回路基板の電極パッドに加わる応力を低減し、
回路基板の電極パッドに亀裂が生じることなく接続信頼
性が向上した半導体装置の実装構造体の製造方法を提供
することにある。Another object of the present invention is to reduce a stress applied to an electrode pad of a circuit board by a pressing force applied when a semiconductor element is mounted face down on a circuit board,
An object of the present invention is to provide a method of manufacturing a mounting structure of a semiconductor device in which connection reliability is improved without cracking of an electrode pad of a circuit board.
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、ワイヤバンピィング工法により回路基板
の電極パッド上に金、はんだ等の接続材料を用いてバン
プを形成した回路基板に、半導体素子をフェースダウン
で実装することを特徴とする半導体装置の実装構造体で
ある。In order to achieve the above object, the present invention provides a circuit board having a bump formed by using a connection material such as gold or solder on an electrode pad of the circuit board by a wire bumping method. And a semiconductor device mounting structure in which a semiconductor element is mounted face down.
【0010】また、本発明は、前記半導体装置の実装構
造体において、前記バンプの先端を半導体素子の電極パ
ッドとの接触により塑性変形させてバンプ及び回路基板
の電極パッドの高さばらつきを吸収することを特徴とす
る半導体装置の実装構造体である。Further, according to the present invention, in the mounting structure of the semiconductor device, the tip of the bump is plastically deformed by contact with an electrode pad of a semiconductor element to absorb a variation in height of the bump and the electrode pad of the circuit board. A mounting structure for a semiconductor device.
【0011】また、本発明は、前記半導体装置の実装構
造体において、前記バンプと回路基板の電極パッドとの
接触面積のばらつきを低減したことを特徴とする半導体
装置の実装構造体である。Further, the present invention is a mounting structure for a semiconductor device, wherein the variation in the contact area between the bump and the electrode pad of the circuit board is reduced in the mounting structure for the semiconductor device.
【0012】また、本発明は、複数の電極パッドを配列
した回路基板の電極パッド上にワイヤバンピィング工法
により金、はんだ等の接続材料を用いてバンプを形成す
る第1の工程と、前記回路基板の半導体素子搭載面に封
止樹脂を充填する第2の工程と、複数の電極パッドを配
列した半導体素子をフェースダウンして前記回路基板に
実装する第3の工程とを有することを特徴とする半導体
装置の実装構造体の製造方法である。The present invention is also directed to a first step of forming a bump by using a connection material such as gold or solder by a wire bumping method on an electrode pad of a circuit board on which a plurality of electrode pads are arranged; A second step of filling the semiconductor element mounting surface of the substrate with a sealing resin, and a third step of face-down mounting the semiconductor element on which a plurality of electrode pads are arranged and mounting the semiconductor element on the circuit board. This is a method for manufacturing a mounting structure of a semiconductor device.
【0013】以上説明したように、前記構成によれば、
半導体素子をフェースダウンで回路基板に実装する際に
加える加圧力によって回路基板の電極パッドに加わる応
力の平均値及びばらつきを低減して接続信頼性を向上す
ることができる。As described above, according to the above configuration,
The average value and the variation of the stress applied to the electrode pads of the circuit board due to the pressure applied when the semiconductor element is mounted face down on the circuit board can be reduced, and the connection reliability can be improved.
【0014】[0014]
【発明の実施の形態】本発明に係わる半導体装置の実装
構造体の実施の形態について、説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a mounting structure for a semiconductor device according to the present invention will be described.
【0015】図1は、本発明に係わる半導体装置の主要
部の実装プロセスの一実施例の形態を示す工程図、図2
は、本発明に係わる半導体装置の実装構造図の実装プロ
セスの一実施例の形態を示す工程図である。FIG. 1 is a process diagram showing one embodiment of a mounting process of a main part of a semiconductor device according to the present invention.
FIG. 2 is a process diagram showing an embodiment of a mounting process of a mounting structure diagram of a semiconductor device according to the present invention.
【0016】図1および図2において、1はバンプ、2
は回路基板の電極パッド、3は回路基板、4は封止樹
脂、5は半導体素子、6は半導体素子の電極パッドであ
る。1 and 2, reference numeral 1 denotes a bump;
Is an electrode pad of a circuit board, 3 is a circuit board, 4 is a sealing resin, 5 is a semiconductor element, and 6 is an electrode pad of a semiconductor element.
【0017】本発明に係わる半導体装置の実装構造体の
一実施例の形態について、図1を参照しながら説明す
る。まず、図1(a),(b)に示すように、回路基板
3の電極パッド2上に金、はんだ等の電気的な接続材料
を用いてワイヤバンピィング工法によりバンプ1を形成
し、回路基板3上に異方導電性フィルムもしくは充填樹
脂等の封止樹脂4を充填する。この時、回路基板3の電
極パッド2とバンプ1の接触面積の平均値及び面積ばら
つきは、ワイヤバンピィングのボール形状と回路基板3
の電極パッド2の接触面積に依存する。One embodiment of a semiconductor device mounting structure according to the present invention will be described with reference to FIG. First, as shown in FIGS. 1A and 1B, a bump 1 is formed on an electrode pad 2 of a circuit board 3 by using a wire bumping method using an electrical connection material such as gold or solder. A sealing resin 4 such as an anisotropic conductive film or a filling resin is filled on the substrate 3. At this time, the average value and the area variation of the contact area between the electrode pad 2 and the bump 1 of the circuit board 3 are determined by the ball shape of the wire bumping and the circuit board 3.
Depends on the contact area of the electrode pad 2.
【0018】次いで、図1(c)に示すように、半導体
素子1の電極パッド6を、フェースダウンで回路基板3
上のバンプ1の所定の位置に位置合わせを行い、加圧し
ながら搭載する。ここで、半導体素子5の電極パッド6
とバンプ1との接触時にバンプ1を塑性変形させて高さ
ばらつきを吸収することができる。Next, as shown in FIG. 1C, the electrode pads 6 of the semiconductor element 1 are
The bump 1 is positioned at a predetermined position, and is mounted while being pressed. Here, the electrode pad 6 of the semiconductor element 5
The bumps 1 can be plastically deformed at the time of contact between the bumps 1 and the bumps 1 to absorb height variations.
【0019】次いで、図1(d)示すように、半導体素
子5を加圧しながら半導体素子側もしくは回路基板側か
ら加熱して、異方導電性フィルムもしくは充填樹脂等の
封止樹脂4を硬化させて半導体素子5と回路基板3が接
着する。ここで、図1(d)に示すように、回路基板3
の電極パッド2とバンプ1との接触面積が半導体素子5
の電極パッド6とバンプ1との接触面積に比べ、3倍以
上となるので、回路基板3の電極パッド2に加わる応力
を低減することができる。Then, as shown in FIG. 1D, the semiconductor element 5 is heated from the semiconductor element side or the circuit board side while being pressurized to cure the sealing resin 4 such as an anisotropic conductive film or a filling resin. Thus, the semiconductor element 5 and the circuit board 3 are bonded. Here, as shown in FIG.
The contact area between the electrode pad 2 and the bump 1 of the semiconductor device 5
The contact area between the electrode pad 6 and the bump 1 is three times or more, so that the stress applied to the electrode pad 2 of the circuit board 3 can be reduced.
【0020】以上説明したように、回路基板3の電極パ
ッド2上にバンプ1を形成することで、半導体素子5を
フェースダウンで回路基板3に実装する際に加える加圧
力によって回路基板3の電極パッド2に加わる応力の平
均値およびばらつきを低減することができ、その結果、
接続信頼性を向上した半導体装置の実装構造体を得るこ
とができる。As described above, by forming the bumps 1 on the electrode pads 2 of the circuit board 3, the electrodes of the circuit board 3 are applied by the pressure applied when the semiconductor element 5 is mounted face down on the circuit board 3. The average value and the variation of the stress applied to the pad 2 can be reduced, and as a result,
A mounting structure of a semiconductor device with improved connection reliability can be obtained.
【0021】なお、封止樹脂4は、半導体素子5と、回
路基板3とをバンプ1を介して接続した後に、その間隙
に注入しても、前述と同様の効果が得られることは言う
までもない。It is needless to say that the same effect as described above can be obtained even if the sealing resin 4 is injected into the gap after the semiconductor element 5 and the circuit board 3 are connected via the bumps 1. .
【0022】[0022]
【発明の効果】本発明によれば、回路基板の電極パッド
とバンプの接触面積の平均値が大きくなり、しかも接触
面積ばらつきを低減できるので、半導体素子をフェース
ダウンで回路基板に実装する際に加える加圧力によって
回路基板の電極パッドに加わる応力の平均値およびばら
つきを低減することができ、その結果、回路基板の電極
パッドに亀裂が生じることなく半導体装置の実装構造体
を信頼性高く実装することができる効果を奏する。According to the present invention, the average value of the contact area between the electrode pads and the bumps on the circuit board is increased, and the variation in the contact area can be reduced. The average value and the variation of the stress applied to the electrode pads of the circuit board by the applied pressure can be reduced, and as a result, the mounting structure of the semiconductor device can be mounted with high reliability without the occurrence of cracks in the electrode pads of the circuit board. The effect that can be achieved.
【0023】また、本発明によれば、バンプ及び回路基
板の電極パッドの高さばらつきは、バンプが塑性変形す
ることで高さばらつきを吸収できるため、回路基板の電
極パッドに加わる応力の平均値およびばらつきを低減す
ることができ、その結果、回路基板の電極パッドに亀裂
が生じることなく半導体装置の実装構造体を信頼性高く
実装することができる効果を奏する。Further, according to the present invention, the variation in height between the bumps and the electrode pads on the circuit board can be absorbed by the plastic deformation of the bumps, so that the average value of the stress applied to the electrode pads on the circuit board can be reduced. In addition, the variation can be reduced, and as a result, there is an effect that the mounting structure of the semiconductor device can be mounted with high reliability without causing cracks in the electrode pads of the circuit board.
【0024】また、本発明によれば、回路基板の電極パ
ッドに加わる応力の平均値及びばらつきを低減できるの
で、加圧力の上限値を増加することができ、その結果、
封止樹脂に加わる圧力範囲の上限値の増加によってボイ
ド量を低減することが可能となり接続信頼性を向上させ
る効果を奏する。Further, according to the present invention, since the average value and the variation of the stress applied to the electrode pads of the circuit board can be reduced, the upper limit value of the applied pressure can be increased.
By increasing the upper limit of the pressure range applied to the sealing resin, the amount of voids can be reduced, and the effect of improving connection reliability is achieved.
【図1】本発明に関わる半導体装置の主要部の実装プロ
セス及び構造を示す図である。FIG. 1 is a diagram showing a mounting process and a structure of a main part of a semiconductor device according to the present invention.
【図2】本発明に関わる半導体装置の実装プロセス及び
構造を示す図である。FIG. 2 is a diagram showing a mounting process and a structure of a semiconductor device according to the present invention.
【図3】従来の半導体装置の実装構造体を示す図であ
る。FIG. 3 is a diagram illustrating a mounting structure of a conventional semiconductor device.
1…バンプ、 2…回路基板の電極パッド、3…回路
基板、4…封止樹脂、5…半導体素子、6…半導体素子
の電極パッド。DESCRIPTION OF SYMBOLS 1 ... Bump, 2 ... Electrode pad of a circuit board, 3 ... Circuit board, 4 ... Sealing resin, 5 ... Semiconductor element, 6 ... Electrode pad of a semiconductor element.
Claims (4)
電極パッド上に金、はんだ等の接続材料を用いてバンプ
を形成した回路基板に、半導体素子をフェースダウンで
実装することを特徴とする半導体装置の実装構造体。1. A semiconductor device wherein a semiconductor element is mounted face down on a circuit board in which bumps are formed by using a connection material such as gold or solder on electrode pads of the circuit board by a wire bumping method. Mounting structure.
記バンプの先端を半導体素子の電極パッドとの接触によ
り、塑性変形させてバンプ及び回路基板の電極パッドの
高さばらつきを吸収することを特徴とする半導体装置の
実装構造体。2. The mounting structure of the semiconductor device according to claim 1, wherein a tip of the bump is plastically deformed by contact with an electrode pad of a semiconductor element to absorb a height variation of the bump and the electrode pad of the circuit board. Mounting structure of a semiconductor device.
記バンプと回路基板の電極パッドとの接触面積のばらつ
きを低減したことを特徴とする半導体装置の実装構造
体。3. The mounting structure of a semiconductor device according to claim 1, wherein a variation in a contact area between the bump and an electrode pad of a circuit board is reduced.
極パッド上にワイヤバンピィング工法により金、はんだ
等の接続材料を用いてバンプを形成する第1の工程と、
前記回路基板の半導体素子搭載面に封止樹脂を充填する
第2の工程と、複数の電極パッドを配列した半導体素子
をフェースダウンして前記回路基板に実装する第3の工
程とを有することを特徴とする半導体装置の実装構造体
の製造方法。4. A first step of forming bumps by using a connection material such as gold or solder by a wire bumping method on electrode pads of a circuit board on which a plurality of electrode pads are arranged;
A second step of filling a sealing resin on a semiconductor element mounting surface of the circuit board; and a third step of face-down mounting a semiconductor element on which a plurality of electrode pads are arranged and mounting the semiconductor element on the circuit board. A method for manufacturing a mounting structure of a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP448498A JPH11204572A (en) | 1998-01-13 | 1998-01-13 | Mounting structure of semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP448498A JPH11204572A (en) | 1998-01-13 | 1998-01-13 | Mounting structure of semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11204572A true JPH11204572A (en) | 1999-07-30 |
Family
ID=11585381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP448498A Pending JPH11204572A (en) | 1998-01-13 | 1998-01-13 | Mounting structure of semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11204572A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001127102A (en) * | 1999-10-25 | 2001-05-11 | Sony Corp | Semiconductor device and manufacturing method thereof |
JP2002373966A (en) * | 2001-06-13 | 2002-12-26 | Matsushita Electric Ind Co Ltd | Mounting structure for semiconductor chip and method for manufacturing the same |
CN111755405A (en) * | 2019-03-29 | 2020-10-09 | 丰田自动车株式会社 | Semiconductor device with a plurality of semiconductor chips |
JP2020178044A (en) * | 2019-04-18 | 2020-10-29 | パナソニックIpマネジメント株式会社 | Semiconductor device, implementation structure of semiconductor device, and manufacturing method of semiconductor device |
-
1998
- 1998-01-13 JP JP448498A patent/JPH11204572A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001127102A (en) * | 1999-10-25 | 2001-05-11 | Sony Corp | Semiconductor device and manufacturing method thereof |
JP2002373966A (en) * | 2001-06-13 | 2002-12-26 | Matsushita Electric Ind Co Ltd | Mounting structure for semiconductor chip and method for manufacturing the same |
JP4536291B2 (en) * | 2001-06-13 | 2010-09-01 | パナソニック株式会社 | Semiconductor chip mounting structure and manufacturing method thereof |
CN111755405A (en) * | 2019-03-29 | 2020-10-09 | 丰田自动车株式会社 | Semiconductor device with a plurality of semiconductor chips |
JP2020178044A (en) * | 2019-04-18 | 2020-10-29 | パナソニックIpマネジメント株式会社 | Semiconductor device, implementation structure of semiconductor device, and manufacturing method of semiconductor device |
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