JP4035949B2 - Wiring board, semiconductor device using the same, and manufacturing method thereof - Google Patents

Wiring board, semiconductor device using the same, and manufacturing method thereof Download PDF

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JP4035949B2
JP4035949B2 JP2000311721A JP2000311721A JP4035949B2 JP 4035949 B2 JP4035949 B2 JP 4035949B2 JP 2000311721 A JP2000311721 A JP 2000311721A JP 2000311721 A JP2000311721 A JP 2000311721A JP 4035949 B2 JP4035949 B2 JP 4035949B2
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wiring
elastic body
wiring board
semiconductor chip
protruding
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JP2002118197A (en
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達也 大高
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、配線テープ及びそれを用いた半導体装置、ならびにその製造方法に関し、特に、半導体チップを、配線テープ上に弾性体（エラストマ）を介在させてフリップチップ接合する半導体装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、配線及びその外部接続端子が設けられた配線基板上に半導体チップを搭載し、前記半導体チップの外部電極と配線基板の配線を接続する方法の一つとしてフリップチップ接合があげられる。
【０００３】
前記フリップチップ接合を用いて製造される半導体装置は、例えば、図１０（ａ）及び図１０（ｂ）に示すように、絶縁性基板１０１に配線１０２Ａ及びその外部接続端子１０２Ｂが設けられた配線基板１上に、例えば二つの弾性体（エラストマ）２Ａ，２Ｂが設けられ、前記弾性体２Ａ，２Ｂ上に半導体チップ３が設けられている。前記半導体チップ３は、図１０（ｂ）に示すように、その外部電極形成面が前記弾性体２Ａ，２Ｂと向かい合うように設けられ、前記外部電極３０１と前記配線基板１の配線１０２Ａが突起導体（バンプ）５により接合されている。このとき、前記弾性体２Ａ，２Ｂは、前記半導体チップ３の外部電極３０１が形成された領域をはさんだ両側に設けられており、前記突起導体（バンプ）５の周辺にできる隙間には、レジンなどの封止樹脂（アンダーフィル）１３を流し込んで前記突起導体（バンプ）５の周辺を封止している。前記弾性体２Ａ，２Ｂは、前記配線基板１と半導体チップ３とを接着する接着剤であるとともに、前記配線基板１と半導体チップ３の熱膨張係数の違いにより生じる熱応力を緩和するための緩和材としても機能するものを用いており、例えば、熱硬化性のエポキシ系樹脂などが用いられる。また、前記配線基板１の外部接続端子１０２Ｂは、前記テープ状基材１０１に設けられたビア孔に充填されたはんだビアを介して、はんだボールなどのボール端子４と接続されている。
【０００４】
前記フリップチップ接合された半導体装置の製造方法は、まず、テープ状基材１０１に配線１０２Ａ及びその外部接続端子１０２Ｂ、前記外部接続端子１０２Ｂ部分のビア孔を形成した配線基板１を形成したのち、前記配線基板１の所定位置に弾性体（エラストマ）２Ａ，２Ｂを配置し、前記弾性体２Ａ，２Ｂ上に半導体チップ３を、その外部電極３０１が前記弾性体２Ａ，２Ｂと向かい合うように配置する。このとき、例えば、前記外部電極３０１上に突起電極５が設けておき、前記突起電極５と前記配線１０２Ａが接するようにしておく。そして、前記弾性体２Ａ，２Ｂ及び突起電極５を加熱して、前記半導体チップ３と配線基板１を前記弾性体２Ａ，２Ｂにより接着するとともに、前記半導体チップ３の外部電極３０１と配線基板１の配線１０２を前記突起導体（バンプ）５により接続する。その後、前記突起導体（バンプ）５を封止するために、図１１に示すように、樹脂注入用ノズル１４を用いて、前記半導体チップ３の側面方向から前記二つの弾性体２Ａ，２Ｂ間にレジン等の封止樹脂１３を流し込む。前記封止樹脂１３によりバンプ５を封止した後、前記配線基板１のビア孔上にはんだボール等のボール端子４を載せて加熱し、部分的に融解させて前記はんだボールと外部接続端子１０２Ｂを接続する。
【０００５】
【発明が解決しようとする課題】
しかしながら、前記従来の技術では、前記弾性体２Ａ，２Ｂを介して半導体チップ３と配線基板１をフリップチップ接合する工程と、前記突起導体（バンプ）２を封止する工程が別の工程であるため、製造工程が増え、製造コストが上昇するという問題があった。
【０００６】
また、前記弾性体（エラストマ）２Ａ，２Ｂを介して半導体チップ３と配線基板１をフリップチップ接合する工程の後に、前記弾性体２Ａ，２Ｂ間に封止樹脂１３を流し込んで突起導体（バンプ）３を封止する工程が行われているが、前記封止樹脂１３を流し込むときに、図１１に示すように、前記バンプ５間に封止樹脂１３が流れ込まずにボイド１５ができてしまうことが多い。前記ボイド１５が生じると、その後の製造工程での加熱処理、例えば、前記ボール端子４を接続するためのリフロー工程等で、前記ボイド１５内の空気が加熱されて膨張し、前記バンプ５が配線１０２Ａあるいは外部電極３０１から剥がれて接続不良になるという問題があった。また、前記ボイド１５の膨張により、前記封止樹脂１３と半導体チップ３あるいは配線基板１の接着面が剥がれ、パッケージクラックの原因になるという問題があった。
【０００７】
本発明の目的は、配線基板上に、弾性体を介して半導体チップをフリップチップ接合した半導体装置において、製造工程を簡略化することが可能な技術を提供することにある。
【０００８】
本発明の他の目的は、配線基板上に、弾性体を介して半導体チップをフリップチップ接合した半導体装置において、半導体チップの外部電極と配線の接続不良を低減することが可能な技術を提供することにある。
【０００９】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面によって明らかになるであろう。
【００１０】
【課題を解決するための手段】
本発明において開示される発明の概要を説明すれば、以下のとおりである。
【００１１】
（１）絶縁性基材と、前記基材の表面に設けられた配線及びその外部接続端子とを備える配線基板において、前記配線の所定位置に突起導体が設けられ、前記絶縁性基材の配線及びその外部接続端子上に、前記突起導体の表面が露出しその一部が突出するように弾性体（エラストマ）が設けられていることを特徴とする配線基板である。
【００１２】
前記（１）によれば、前記配線基板の配線上に突起電極を設け、前記突起電極が露出するように弾性体（エラストマ）を設けておくことで、前記配線基板上に半導体チップを接着して、前記半導体チップの外部電極と配線を接続する際の製造工程を簡略化させることができる。
【００１３】
（２）絶縁性基材の表面に配線及びその外部接続端子が設けられ、前記配線の所定位置に突起導体が設けられ、前記絶縁性基材の配線及びその外部接続端子上に、前記突起導体の表面が露出しその一部が突出するように弾性体（エラストマ）が設けられた配線基板を設け、前記配線基板の弾性体上に、半導体チップをその回路形成面が前記弾性体と向かい合うように設け、前記半導体チップの回路形成面に設けられた外部電極と前記配線基板の配線が、前記弾性体（エラストマ）で密封されて接続されていることを特徴とする半導体装置である。
【００１４】
前記（２）によれば、前記半導体チップの外部電極と配線基板の配線を接続する導体（突起導体）が、前記弾性体（エラストマ）により密封されているため、前記導体の周辺にボイドができて、接合部の剥がれや、パッケージクラックが発生することを低減できるので、半導体装置の信頼性が向上する。
【００１５】
（３）テープ状の絶縁性基材の配線基板形成領域に、配線及びその外部接続端子を形成し、前記配線の所定位置に突起導体を形成し、前記配線基板形成領域の配線及び外部接続端子上に、前記突起導体と平面的に重なる位置に開口部を有する弾性体（エラストマ）を前記突起導体が前記開口部内に挿入され且つ前記突起導体の一部が前記開口部から突出するように貼り付けることを特徴とする配線基板の製造方法である。
【００１６】
前記（３）によれば、前記配線基板の配線上に突起電極を設け、前記突起電極が露出するように弾性体（エラストマ）を設けておくことで、前記配線基板上に半導体チップを接着して、前記半導体チップの外部電極と配線を接続する際の製造工程を簡略化させることができる。
【００１７】
（４）テープ状の絶縁性基材の配線基板形成領域に、配線及びその外部接続端子を形成し、前記配線の所定位置に突起導体を形成し、前記配線基板形成領域の配線及び外部接続端子上に、前記突起導体と平面的に重なる位置に開口部を有する弾性体（エラストマ）を前記突起導体が前記開口部内に挿入され且つ前記突起導体の一部が前記開口部から突出するように貼り付け、前記弾性体上に、半導体チップを、その外部電極形成面が前記弾性体と向かい合うように配置し、前記半導体チップを、前記弾性体を介して前記配線基板に接着するとともに、前記半導体チップの外部電極と前記配線基板の配線を、前記弾性体で密封される突起導体により接続することを特徴とする半導体装置の製造方法である。
【００１８】
前記（４）によれば、前記配線基板の配線上に突起電極を設け、前記突起電極が露出するように弾性体（エラストマ）を設けておくことで、前記配線基板上に半導体チップを接着して、前記半導体チップの外部電極と配線を接続する際の製造工程を簡略化させることができる。そのため、前記半導体装置の製造コストを低減させることができる。また、前記半導体チップの外部電極と配線基板の配線をフリップチップ接合する際に、前記導体 （突起導体）がその周辺のエラストマにより密封されるため、前記導体の周辺にボイドができて、接合部分の剥がれやパッケージクラックが発生することを低減でき、半導体装置の信頼性を向上させることができる。
【００１９】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００２０】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号をつけ、その繰り返しの説明は省略する。
【００２１】
【発明の実施の形態】
（実施例）
図１及び図２は、本発明による一実施例の半導体装置の概略構成を示す模式図であり、図１（ａ）は半導体装置の平面図、図１（ｂ）は図１（ａ）の裏面図、図１（ｃ）は図１（ａ）の左側面図、図２（ａ）は図１（ａ）の半導体チップを省略して示した平面図、図２（ｂ）は図２（ａ）のＡ−Ａ’線での断面図である。
【００２２】
図１（ａ）、図１（ｂ）、及び図１（ｃ）において、１は配線基板、２は弾性体（エラストマ）、３は半導体チップ、４はボール端子である。また、図２（ａ）及び図２（ｂ）において、１０１は絶縁性基板、１０２Ａは配線、１０２Ｂは外部接続端子、３０１は半導体チップの外部電極、５は導体（突起導体）である。
【００２３】
本実施例の半導体装置は、例えば、図１（ａ）、図１（ｂ）、及び図１（ｃ）に示すように、配線基板１の一主面（表面）上に、弾性体（エラストマ）２を介在させて半導体チップ３が接着されており、前記配線基板１の前記表面と対向する面（裏面）には、例えば、Ｐｂ−Ｓｎ系はんだ等のボール端子４が接続されたＢＧＡ（Ball Grid Array ）型の半導体装置である。また、図１では示していないが、本実施例の半導体装置で用いている半導体チップ３は、外部電極が、回路形成面の中心線付近に線状に設けられたセンターパッド型の半導体チップであるとする。
【００２４】
また、本実施例の半導体装置では、図２（ａ）及び図２（ｂ）に示すように、前記配線基板１は、絶縁性基板１０１とその表面に設けられた配線１０２Ａ及びその外部接続端子１０２Ｂにより構成される。また、前記配線１０２Ａ及びその外部接続端子１０２Ｂ上には、前記弾性体２を介して前記半導体チップ３が、その外部電極３０１が形成された面を向かい合わせるように接着されており、前記半導体チップ３の外部電極３０１と前記配線基板の配線１０２Ａは、前記弾性体（エラストマ）２で密封された導体（突起導体）５により電気的に接続されている。また、前記外部接続端子１０２Ｂは、前記絶縁性基板１０１に設けられたビア孔を介して前記ボール端子４と接続されている。
【００２５】
図３乃至図８は、本実施例の半導体装置の製造方法を説明するための模式図であり、図３（ａ）、図４（ａ）、図５（ａ）、及び図６（ａ）は配線基板の製造方法を説明するための模式平面図、図３（ｂ）、図４（ｂ）、図６（ｂ）はそれぞれ、図３（ａ）、図４（ａ）、図６（ａ）のＢ−Ｂ’線での断面図、図５（ｂ）は図５（ａ）のＣ−Ｃ’線での断面図、図７（ａ）及び図８（ａ）は前記配線基板を用いた半導体装置の製造方法を説明するための模式平面図、図７（ｂ）及び図８（ｂ）はそれぞれ、図７（ａ）及び図８（ａ）のＢ−Ｂ’線での断面図である。以下、図３乃至図８に沿って、本実施例の半導体装置の製造方法について説明する。なお、前記半導体装置で用いる半導体チップ３は、外部電極が、回路形成面の中心線付近に線状に設けられた、センターパッド型の半導体チップであるとする。
【００２６】
まず、図３（ａ）及び図３（ｂ）に示すように、例えば、ポリイミドなどの絶縁性のテープ状基材６の配線基板形成領域１’に、所定の配線パターンの配線１０２Ａ及び外部接続端子１０２Ｂを形成し、前記テープ状基材６の前記外部接続端子１０２Ｂ部分にビア孔１０３を開口する。前記配線１０２Ａ及び外部接続端子１０２Ｂは、前記テープ状基材６の表面に設けられた、例えば、銅箔のような導電性薄膜上に、所定の配線パターンに対応したレジストを形成し、前記レジストをマスクとして前記導電性薄膜上にめっき層を形成し、その後、前記レジストを除去して、今度は前記めっき層をマスクとして前記導電性薄膜をエッチング処理することにより形成される。また、前記ビア孔１０３は、例えば、レジスト膜をマスクとしたエッチング処理や、レーザによる開口などで形成する。また、前記テープ状基材６上には、図３（ａ）に示したような配線基板形成領域１’が複数個あり、各配線基板形成領域１’に同様の配線パターンが形成される。
【００２７】
次に、図４（ａ）及び図４（ｂ）に示すように、前記配線１０２Ａの所定位置に突起導体（バンプ）５を形成する。前記突起導体５は、例えば、Ｐｂ−Ｓｎ系はんだ等のはんだボールを前記配線１０２Ａ上に載せて、部分的に融解させて形成する方法や、金（Ａｕ）ワイヤを用いてスタッドバンプを形成する方法などがある。
【００２８】
次に、図５（ａ）及び図５（ｂ）に示したような、前記配線１０２Ａに形成された突起導体５と対応する位置に開口部２０１を有する弾性体（エラストマ）２を準備する。前記弾性体２は、例えば、熱硬化性のエポキシ系樹脂にフィラーなどの添加剤を所定の割合で配合して所定の弾性率が得られるようにしておく。またこのとき、前記弾性体２の一主面には、図５（ｂ）に示したようにカバーフィルム７を設けておく。また、前記開口部２０１は、前記突起電極５と同じ大きさ、もしくは突起電極５よりも少し小さく形成する。
【００２９】
次に、図６（ａ）及び図６（ｂ）に示すように、前記テープ状基板６の配線基板形成領域１’に形成された配線１０２Ａ及びその外部接続端子１０２Ｂ上に、図５（ａ）及び図５（ｂ）に示したカバーフィルム７が設けられた弾性体２を配置する。このとき、前記弾性体２は、前記開口部２０１が前記配線１０２Ａ上の突起導体５と平面的に重なるように位置あわせをして、前記開口部２０１内に突起導体５が挿入されるように配置される。またこのとき、前記弾性体２の開口部２０１を前記突起導体５よりも小さくしておくことにより、前記突起導体５が前記開口部２０１に押し込まれるように、隙間なく挿入することができる。
【００３０】
以上の手順に沿って、本実施例の半導体装置に用いる配線基板１が各配線基板形成領域１’に形成されたテープ状基材６が形成される。
【００３１】
次に、図６（ａ）及び図６（ｂ）に示したようなテープ状基材６の配線基板形成領域１’上に設けられた弾性体（エラストマ）２の表面のカバーフィルム７を剥がして、図７（ａ）及び図７（ｂ）に示すように、前記弾性体２上に、センターパッド型の半導体チップ３を、その外部電極形成面が前記弾性体２と向かい合うようにして、前記外部電極３０１と前記突起電極５の位置あわせを行い、配置する。
【００３２】
次に、例えば、前記弾性体２を加熱するとともに、前記半導体チップ３を押圧して、前記半導体チップ３と前記弾性体２を接着するとともに、前記半導体チップ３の外部電極３０１と前記突起導体５を接続する。このとき、前記突起導体５は、図２（ａ）及び図２（ｂ）に示したように、その周囲が前記弾性体（エラストマ）２で囲まれているため、前記半導体チップ３の外部電極３０１と前記配線基板１の配線１０２Ａを突起導体５によりフリップチップ接合されると同時に、前記接合部分が前記弾性体２により封止（密封）される。すなわち、本実施例の半導体装置の製造方法では、前記半導体チップの外部電極と配線基板の配線をフリップチップ接合する工程と、前記接合部を封止する工程を一工程で行うことができる。
【００３３】
その後、前記テープ状基材６に設けられたビア孔１０３上に、例えば、Ｐｂ−Ｓｎ系はんだ等のボール端子４を配置して、前記ボール端子４を部分的に融解させて前記ビア孔１０３内に流し込み、図８（ａ）及び図８（ｂ）に示すように、前記ボール端子４と前記外部接続端子１０２Ｂと電気的に接続する。その後、前記テープ状基材６を前記配線基板形成領域１’の外周部分で切断すると、図２（ａ）及び図２（ｂ）に示したような半導体装置が得られる。
【００３４】
以上説明したように、本実施例によれば、絶縁性基材１０１の表面に形成された配線１０２Ａの所定位置に突起導体（バンプ）５を設け、前記配線１０２Ａ及びその外部接続端子１０２Ｂ上に、前記突起導体５の表面が露出するように弾性体（エラストマ）２を設けた配線基板１を用いることにより、半導体チップ３を、その外部電極３０１形成面が前記弾性体２と向かい合うようにして前記外部電極３０１と配線１０２Ａをフリップチップ接合すると同時に、前記接合部の封止をすることができる。そのため、従来２つの工程だった、フリップチップ接合をする工程と、接合部を封止する工程を一工程で行い、製造工程を少なくすることができる、半導体装置の製造コストを低減させることができる。
【００３５】
また、前記配線基板１を用いてフリップチップ接合を行うと、前記外部電極３０１と配線１０２Ａを電気的に接続する導体（バンプ）５は、前記弾性体（エラストマ）により封止（密封）されるので、導体５の周辺にボイドができて、接合部分の剥離や、パッケージクラックなどが発生することを低減でき、半導体装置の信頼性が向上する。
【００３６】
図９（ａ）及び図９（ｂ）は前記実施例の半導体装置の応用例を示す模式断面図である。
【００３７】
前記実施例では、一つのセンターパッド型の半導体チップ３を配線基板１上にフリップチップ接合した半導体装置を例に挙げて説明したが、これに限らず、例えば、図９（ａ）に示したように、前記実施例で説明した配線基板１上にフリップチップ接合されたセンターパッド型の半導体装置３上に、接着剤８を介して、例えば、回路形成面の２方向の辺に沿って外部電極９０１が設けられた半導体チップ９を積層した半導体装置であっても良い。この場合、前記半導体チップ９の外部電極９０１はボンディングワイヤ１０により前記配線基板上の配線１０２Ａと接続され、積層されたセンターパッド型の半導体チップ３及び半導体チップ９、ボンディングワイヤ１０、及びその接続部はモールド樹脂１１により封止される。
【００３８】
また、前記実施例で説明した配線基板１上にフリップチップ接続される半導体チップ前記実施例で挙げたセンターパッド型の半導体装置３に限らず、図９（ｂ）に示したような、回路形成面の２方向の辺に沿って外部電極が形成された半導体チップであっても良い。この場合も、前記実施例で説明したように、絶縁性基板１０１上に形成された配線１０２Ａの所定位置に突起電極５を設け、前記突起電極５に対応する位置に開口部が形成された弾性体（エラストマ）を設けた配線基板を製造することにより、フリップチップ接合する工程と接合部を封止する工程を一工程で行うことができ、製造工程が少なくなり製造コストが低減する。
【００３９】
以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることはもちろんである。
【００４０】
【発明の効果】
本発明において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【００４１】
（１）配線基板上に、弾性体を介して半導体チップをフリップチップ接合した半導体装置において、製造工程を簡略化することができる。
【００４２】
（２）配線基板上に、弾性体を介して半導体チップをフリップチップ接合した半導体装置において、半導体チップの外部電極と配線の接続不良を低減することができる。
【図面の簡単な説明】
【図１】本発明による一実施例の半導体装置の概略構成を示す模式図である。
【図２】本発明による一実施例の半導体装置の概略構成を示す模式図である。
【図３】本実施例の半導体装置の製造方法を説明するための模式図である。
【図４】本実施例の半導体装置の製造方法を説明するための模式図である。
【図５】本実施例の半導体装置の製造方法を説明するための模式図である。
【図６】本実施例の半導体装置の製造方法を説明するための模式図である。
【図７】本実施例の半導体装置の製造方法を説明するための模式図である。
【図８】本実施例の半導体装置の製造方法を説明するための模式図である。
【図９】前記実施例の半導体装置の応用例を示す模式断面図である。
【図１０】従来のフリップチップ接合した半導体装置の概略構成を示す模式図である。
【図１１】従来のフリップチップ接合した半導体装置の封止方法を説明するための模式図である。
【符号の説明】
１ 配線基板
１０１ 絶縁性基材
１０２Ａ 配線
１０２Ｂ 外部接続端子
１０３ ビア孔
２ 弾性体（エラストマ）
２０１ エラストマの開口部
３ センターパッド型の半導体チップ
３０１ 外部電極
４ ボール端子
５ 突起導体（バンプ）
６ テープ状基材
７ カバーフィルム
８ 接着剤
９ 半導体チップ
９０１ 外部電極
１０ ボンディングワイヤ
１１ 封止樹脂
１２ 半導体チップ
１２０１ 外部電極
１３ 封止樹脂（アンダーフィル）
１４ ノズル
１５ ボイド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring tape, a semiconductor device using the same, and a method for manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is flip-chip bonded with an elastic body (elastomer) interposed on the wiring tape. Technology.
[0002]
[Prior art]
Conventionally, flip chip bonding is one of the methods for mounting a semiconductor chip on a wiring board provided with wiring and its external connection terminals and connecting the external electrode of the semiconductor chip and the wiring of the wiring board.
[0003]
The semiconductor device manufactured using the flip chip bonding is, for example, a wiring in which a wiring 102A and its external connection terminal 102B are provided on an insulating substrate 101 as shown in FIGS. 10 (a) and 10 (b). For example, two elastic bodies (elastomers) 2A and 2B are provided on the substrate 1, and a semiconductor chip 3 is provided on the elastic bodies 2A and 2B. As shown in FIG. 10B, the semiconductor chip 3 is provided so that the external electrode formation surface faces the elastic bodies 2A and 2B, and the external electrode 301 and the wiring 102A of the wiring board 1 are protruding conductors. Bonded by (bump) 5. At this time, the elastic bodies 2A and 2B are provided on both sides of the semiconductor chip 3 across the region where the external electrode 301 is formed, and in the gap formed around the protruding conductor (bump) 5, the resin A sealing resin (underfill) 13 such as is poured to seal the periphery of the protruding conductor (bump) 5. The elastic bodies 2A and 2B are adhesives for bonding the wiring board 1 and the semiconductor chip 3, and relaxation for relaxing thermal stress caused by a difference in thermal expansion coefficient between the wiring board 1 and the semiconductor chip 3. What functions also as a material is used, for example, a thermosetting epoxy resin or the like is used. The external connection terminal 102B of the wiring board 1 is connected to a ball terminal 4 such as a solder ball via a solder via filled in a via hole provided in the tape-like base material 101.
[0004]
In the manufacturing method of the flip chip bonded semiconductor device, first, after forming the wiring substrate 1 in which the wiring 102A and its external connection terminal 102B and the via hole of the external connection terminal 102B are formed on the tape-like base material 101, Elastic bodies (elastomers) 2A and 2B are arranged at predetermined positions on the wiring board 1, and the semiconductor chip 3 is arranged on the elastic bodies 2A and 2B so that the external electrode 301 faces the elastic bodies 2A and 2B. . At this time, for example, the protruding electrode 5 is provided on the external electrode 301 so that the protruding electrode 5 is in contact with the wiring 102A. Then, the elastic bodies 2A, 2B and the protruding electrodes 5 are heated to bond the semiconductor chip 3 and the wiring board 1 with the elastic bodies 2A, 2B, and between the external electrodes 301 of the semiconductor chip 3 and the wiring board 1 The wiring 102 is connected by the protruding conductor (bump) 5. Thereafter, in order to seal the protruding conductors (bumps) 5, as shown in FIG. 11, a resin injection nozzle 14 is used between the two elastic bodies 2A and 2B from the side surface direction of the semiconductor chip 3. A sealing resin 13 such as a resin is poured. After the bumps 5 are sealed with the sealing resin 13, the ball terminals 4 such as solder balls are placed on the via holes of the wiring board 1 and heated to be partially melted, and the solder balls and the external connection terminals 102 </ b> B. Connect.
[0005]
[Problems to be solved by the invention]
However, in the conventional technique, the step of flip-chip bonding the semiconductor chip 3 and the wiring substrate 1 via the elastic bodies 2A and 2B and the step of sealing the protruding conductor (bump) 2 are separate steps. Therefore, there is a problem that the manufacturing process increases and the manufacturing cost increases.
[0006]
In addition, after the step of flip-chip bonding the semiconductor chip 3 and the wiring substrate 1 through the elastic bodies (elastomers) 2A and 2B, a sealing resin 13 is poured between the elastic bodies 2A and 2B to form protruding conductors (bumps). 3 is performed, but when the sealing resin 13 is poured, as shown in FIG. 11, the sealing resin 13 does not flow between the bumps 5 and a void 15 is formed. There are many. When the void 15 is generated, the air in the void 15 is heated and expanded in a heating process in a subsequent manufacturing process, for example, a reflow process for connecting the ball terminal 4, and the bump 5 is wired. There has been a problem that it is peeled off from 102A or the external electrode 301, resulting in poor connection. Further, due to the expansion of the voids 15, there is a problem that the bonding surface between the sealing resin 13 and the semiconductor chip 3 or the wiring substrate 1 is peeled off, causing a package crack.
[0007]
An object of the present invention is to provide a technique capable of simplifying a manufacturing process in a semiconductor device in which a semiconductor chip is flip-chip bonded to a wiring board via an elastic body.
[0008]
Another object of the present invention is to provide a technique capable of reducing a connection failure between an external electrode of a semiconductor chip and a wiring in a semiconductor device in which a semiconductor chip is flip-chip bonded to a wiring board via an elastic body. There is.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The outline of the invention disclosed in the present invention will be described as follows.
[0011]
(1) In a wiring board comprising an insulating base material, wiring provided on the surface of the base material and external connection terminals thereof, a protruding conductor is provided at a predetermined position of the wiring, and wiring of the insulating base material The wiring board is characterized in that an elastic body (elastomer) is provided on the external connection terminal so that the surface of the protruding conductor is exposed and a part thereof protrudes .
[0012]
According to (1), a protruding electrode is provided on the wiring of the wiring board, and an elastic body (elastomer) is provided so that the protruding electrode is exposed, whereby a semiconductor chip is bonded onto the wiring board. Thus, the manufacturing process for connecting the external electrode and the wiring of the semiconductor chip can be simplified.
[0013]
(2) A wiring and its external connection terminal are provided on the surface of the insulating substrate, a protruding conductor is provided at a predetermined position of the wiring, and the protruding conductor is provided on the wiring of the insulating substrate and its external connection terminal. A wiring board provided with an elastic body (elastomer) is provided so that the surface of the wiring board is exposed and a part thereof protrudes , and the circuit formation surface of the semiconductor chip faces the elastic body on the elastic body of the wiring board. The semiconductor device is characterized in that the external electrode provided on the circuit forming surface of the semiconductor chip and the wiring of the wiring board are sealed and connected by the elastic body (elastomer).
[0014]
According to (2) above, since the conductor (projection conductor) that connects the external electrode of the semiconductor chip and the wiring of the wiring board is sealed by the elastic body (elastomer), a void is formed around the conductor. As a result, it is possible to reduce the peeling of the bonding portion and the occurrence of package cracks, which improves the reliability of the semiconductor device.
[0015]
(3) A wiring and its external connection terminal are formed in a wiring board formation region of a tape-like insulating base material, a protruding conductor is formed at a predetermined position of the wiring, and the wiring and external connection terminal in the wiring substrate formation region On top, an elastic body (elastomer) having an opening at a position overlapping with the protruding conductor is pasted so that the protruding conductor is inserted into the opening and a part of the protruding conductor protrudes from the opening. A method of manufacturing a wiring board.
[0016]
According to the above (3), by providing a protruding electrode on the wiring of the wiring board and providing an elastic body (elastomer) so that the protruding electrode is exposed, the semiconductor chip is bonded onto the wiring board. Thus, the manufacturing process for connecting the external electrode and the wiring of the semiconductor chip can be simplified.
[0017]
(4) A wiring and its external connection terminal are formed in a wiring board formation region of a tape-like insulating base material, a protruding conductor is formed at a predetermined position of the wiring, and the wiring and external connection terminal in the wiring substrate formation region On top, an elastic body (elastomer) having an opening at a position overlapping with the protruding conductor is pasted so that the protruding conductor is inserted into the opening and a part of the protruding conductor protrudes from the opening. The semiconductor chip is disposed on the elastic body so that the external electrode forming surface faces the elastic body, and the semiconductor chip is bonded to the wiring board via the elastic body. A method for manufacturing a semiconductor device comprising: connecting external wiring of the wiring board and wiring of the wiring board by a protruding conductor sealed by the elastic body.
[0018]
According to the above (4), a protruding electrode is provided on the wiring of the wiring board, and an elastic body (elastomer) is provided so that the protruding electrode is exposed, whereby a semiconductor chip is bonded onto the wiring board. Thus, the manufacturing process for connecting the external electrode and the wiring of the semiconductor chip can be simplified. Therefore, the manufacturing cost of the semiconductor device can be reduced. Further, when the external electrode of the semiconductor chip and the wiring of the wiring substrate are flip-chip bonded, the conductor (projection conductor) is sealed by the peripheral elastomer, so that a void is formed around the conductor, and the bonded portion The occurrence of peeling and package cracks can be reduced, and the reliability of the semiconductor device can be improved.
[0019]
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
[0020]
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals, and repeated explanation thereof is omitted.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
(Example)
1 and 2 are schematic views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device, and FIG. 1B is a plan view of FIG. 1C is a left side view of FIG. 1A, FIG. 2A is a plan view in which the semiconductor chip of FIG. 1A is omitted, and FIG. 2B is FIG. It is sectional drawing in the AA 'line of (a).
[0022]
In FIGS. 1A, 1B, and 1C, 1 is a wiring board, 2 is an elastic body (elastomer), 3 is a semiconductor chip, and 4 is a ball terminal. 2A and 2B, reference numeral 101 denotes an insulating substrate, 102A denotes a wiring, 102B denotes an external connection terminal, 301 denotes an external electrode of the semiconductor chip, and 5 denotes a conductor (projection conductor).
[0023]
For example, as shown in FIGS. 1A, 1B, and 1C, the semiconductor device according to the present embodiment has an elastic body (elastomer) on one main surface (surface) of the wiring board 1. ) 2, and a semiconductor chip 3 is bonded to the surface (back surface) facing the front surface of the wiring board 1, for example, a BGA (Pb—Sn solder ball terminal 4 or the like connected to the BGA ( Ball Grid Array) type semiconductor device. Although not shown in FIG. 1, the semiconductor chip 3 used in the semiconductor device of this embodiment is a center pad type semiconductor chip in which the external electrodes are linearly provided near the center line of the circuit formation surface. Suppose there is.
[0024]
Further, in the semiconductor device of this embodiment, as shown in FIGS. 2A and 2B, the wiring substrate 1 includes an insulating substrate 101, wirings 102A provided on the surface thereof, and external connection terminals thereof. 102B. The semiconductor chip 3 is bonded on the wiring 102A and its external connection terminal 102B via the elastic body 2 so that the surface on which the external electrode 301 is formed faces each other. The external electrode 301 and the wiring 102 </ b> A of the wiring board are electrically connected by a conductor (projection conductor) 5 sealed with the elastic body (elastomer) 2. The external connection terminal 102 </ b> B is connected to the ball terminal 4 through a via hole provided in the insulating substrate 101.
[0025]
3 to 8 are schematic views for explaining the method of manufacturing the semiconductor device according to the present embodiment. FIGS. 3 (a), 4 (a), 5 (a), and 6 (a). FIG. 3B, FIG. 4B, and FIG. 6B are respectively a schematic plan view for explaining a method of manufacturing a wiring board, and FIG. 3A, FIG. 4A, and FIG. 5A is a cross-sectional view taken along line BB ′, FIG. 5B is a cross-sectional view taken along line CC ′ of FIG. 5A, and FIGS. 7A and 8A are the wiring boards. FIG. 7B and FIG. 8B are schematic plan views for explaining a method of manufacturing a semiconductor device using, respectively, along the BB ′ line in FIG. 7A and FIG. 8A. It is sectional drawing. A method for manufacturing the semiconductor device according to the present embodiment will be described below with reference to FIGS. It is assumed that the semiconductor chip 3 used in the semiconductor device is a center pad type semiconductor chip in which external electrodes are linearly provided near the center line of the circuit formation surface.
[0026]
First, as shown in FIGS. 3 (a) and 3 (b), for example, a wiring 102A having a predetermined wiring pattern and an external connection are formed in a wiring board forming region 1 ′ of an insulating tape-like base material 6 such as polyimide. A terminal 102B is formed, and a via hole 103 is opened in the external connection terminal 102B portion of the tape-shaped substrate 6. The wiring 102A and the external connection terminal 102B are formed by forming a resist corresponding to a predetermined wiring pattern on a conductive thin film such as a copper foil provided on the surface of the tape-like base material 6, As a mask, a plating layer is formed on the conductive thin film, and then the resist is removed, and then the conductive thin film is etched using the plating layer as a mask. The via hole 103 is formed by, for example, an etching process using a resist film as a mask or an opening by a laser. Further, there are a plurality of wiring board forming regions 1 ′ as shown in FIG. 3A on the tape-like substrate 6, and a similar wiring pattern is formed in each wiring board forming region 1 ′.
[0027]
Next, as shown in FIGS. 4A and 4B, protruding conductors (bumps) 5 are formed at predetermined positions of the wiring 102A. The protruding conductor 5 is formed by, for example, forming a solder ball such as Pb—Sn solder on the wiring 102A and partially melting it, or forming a stud bump using a gold (Au) wire. There are methods.
[0028]
Next, as shown in FIGS. 5A and 5B, an elastic body (elastomer) 2 having an opening 201 at a position corresponding to the protruding conductor 5 formed on the wiring 102A is prepared. The elastic body 2 is prepared, for example, by adding an additive such as a filler to a thermosetting epoxy resin at a predetermined ratio so as to obtain a predetermined elastic modulus. At this time, a cover film 7 is provided on one main surface of the elastic body 2 as shown in FIG. The opening 201 is formed to have the same size as the protruding electrode 5 or slightly smaller than the protruding electrode 5.
[0029]
Next, as shown in FIGS. 6A and 6B, the wiring 102A formed in the wiring board formation region 1 ′ of the tape-like board 6 and the external connection terminal 102B are formed on the wiring board A shown in FIG. ) And the elastic body 2 provided with the cover film 7 shown in FIG. At this time, the elastic body 2 is aligned so that the opening 201 is planarly overlapped with the protruding conductor 5 on the wiring 102 </ b> A, and the protruding conductor 5 is inserted into the opening 201. Be placed. At this time, by making the opening 201 of the elastic body 2 smaller than the protruding conductor 5, the protruding conductor 5 can be inserted without a gap so as to be pushed into the opening 201.
[0030]
According to the above procedure, the tape-like base material 6 in which the wiring board 1 used in the semiconductor device of this embodiment is formed in each wiring board forming region 1 ′ is formed.
[0031]
Next, the cover film 7 on the surface of the elastic body (elastomer) 2 provided on the wiring board forming region 1 ′ of the tape-like base material 6 as shown in FIGS. 6 (a) and 6 (b) is peeled off. As shown in FIGS. 7A and 7B, a center pad type semiconductor chip 3 is placed on the elastic body 2 so that the external electrode forming surface faces the elastic body 2. The external electrode 301 and the protruding electrode 5 are aligned and arranged.
[0032]
Next, for example, while heating the elastic body 2 and pressing the semiconductor chip 3, the semiconductor chip 3 and the elastic body 2 are bonded together, and the external electrode 301 and the protruding conductor 5 of the semiconductor chip 3 are bonded. Connect. At this time, as shown in FIGS. 2A and 2B, the protruding conductor 5 is surrounded by the elastic body (elastomer) 2, so that the external electrode of the semiconductor chip 3 is formed. 301 and the wiring 102 </ b> A of the wiring substrate 1 are flip-chip bonded by the protruding conductor 5, and at the same time, the bonded portion is sealed (sealed) by the elastic body 2. That is, in the manufacturing method of the semiconductor device of this embodiment, the step of flip-chip bonding the external electrode of the semiconductor chip and the wiring of the wiring board and the step of sealing the bonding portion can be performed in one step.
[0033]
Thereafter, a ball terminal 4 made of, for example, Pb—Sn solder is disposed on the via hole 103 provided in the tape-shaped substrate 6, and the ball terminal 4 is partially melted to form the via hole 103. As shown in FIGS. 8A and 8B, the ball terminal 4 and the external connection terminal 102B are electrically connected. Thereafter, when the tape-like base 6 is cut at the outer peripheral portion of the wiring board forming region 1 ′, a semiconductor device as shown in FIGS. 2A and 2B is obtained.
[0034]
As described above, according to the present embodiment, the protruding conductor (bump) 5 is provided at a predetermined position of the wiring 102A formed on the surface of the insulating base 101, and the wiring 102A and the external connection terminal 102B are provided on the wiring 102A. By using the wiring substrate 1 provided with the elastic body (elastomer) 2 so that the surface of the protruding conductor 5 is exposed, the semiconductor chip 3 is arranged so that the surface on which the external electrode 301 is formed faces the elastic body 2. At the same time as the external electrode 301 and the wiring 102A are flip-chip bonded, the bonded portion can be sealed. Therefore, the process of flip-chip bonding and the process of sealing the joint, which were two processes in the past, can be performed in one process, and the manufacturing process can be reduced, and the manufacturing cost of the semiconductor device can be reduced. .
[0035]
When flip chip bonding is performed using the wiring substrate 1, the conductor (bump) 5 that electrically connects the external electrode 301 and the wiring 102A is sealed (sealed) by the elastic body (elastomer). Therefore, it is possible to reduce the occurrence of voids around the conductor 5 and the occurrence of peeling of the joint portion, package cracks, and the like, and the reliability of the semiconductor device is improved.
[0036]
FIG. 9A and FIG. 9B are schematic cross-sectional views showing application examples of the semiconductor device of the above embodiment.
[0037]
In the above embodiment, the semiconductor device in which one center pad type semiconductor chip 3 is flip-chip bonded to the wiring substrate 1 has been described as an example. However, the present invention is not limited to this. For example, as shown in FIG. As described above, on the center pad type semiconductor device 3 that is flip-chip bonded to the wiring substrate 1 described in the above embodiment, for example, externally along the two sides of the circuit formation surface via the adhesive 8. A semiconductor device in which the semiconductor chips 9 provided with the electrodes 901 are stacked may be used. In this case, the external electrode 901 of the semiconductor chip 9 is connected to the wiring 102A on the wiring substrate by the bonding wire 10, and the center pad type semiconductor chip 3 and the semiconductor chip 9, the bonding wire 10 and the connection portion thereof laminated. Is sealed with mold resin 11.
[0038]
Further, the semiconductor chip flip-chip connected to the wiring substrate 1 described in the above embodiment is not limited to the center pad type semiconductor device 3 described in the above embodiment, and the circuit formation as shown in FIG. It may be a semiconductor chip in which external electrodes are formed along two sides of the surface. Also in this case, as described in the embodiment, the protruding electrode 5 is provided at a predetermined position of the wiring 102A formed on the insulating substrate 101, and the opening is formed at a position corresponding to the protruding electrode 5. By manufacturing the wiring board provided with the body (elastomer), the flip chip bonding process and the sealing process of the bonding portion can be performed in one process, and the manufacturing process is reduced and the manufacturing cost is reduced.
[0039]
The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. .
[0040]
【The invention's effect】
The effects obtained by typical ones of the inventions disclosed in the present invention will be briefly described as follows.
[0041]
(1) In a semiconductor device in which a semiconductor chip is flip-chip bonded to a wiring board via an elastic body, the manufacturing process can be simplified.
[0042]
(2) In a semiconductor device in which a semiconductor chip is flip-chip bonded to a wiring board via an elastic body, poor connection between external electrodes of the semiconductor chip and wiring can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 4 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 5 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 6 is a schematic view for explaining the method for manufacturing a semiconductor device according to the present embodiment.
FIG. 7 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 8 is a schematic view for explaining the method for manufacturing the semiconductor device according to the present embodiment.
FIG. 9 is a schematic cross-sectional view showing an application example of the semiconductor device of the embodiment.
FIG. 10 is a schematic diagram showing a schematic configuration of a conventional flip-chip bonded semiconductor device.
FIG. 11 is a schematic diagram for explaining a conventional method of sealing a flip-chip bonded semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Wiring board 101 Insulating base material 102A Wiring 102B External connection terminal 103 Via hole 2 Elastic body (elastomer)
201 Opening of elastomer 3 Center pad type semiconductor chip 301 External electrode 4 Ball terminal 5 Protruding conductor (bump)
6 Tape-shaped substrate 7 Cover film 8 Adhesive 9 Semiconductor chip 901 External electrode 10 Bonding wire 11 Sealing resin 12 Semiconductor chip 1201 External electrode 13 Sealing resin (underfill)
14 Nozzle 15 Void

Claims (4)

絶縁性基材と、前記基材の表面に設けられた配線及びその外部接続端子とを備える配線基板において、
前記配線の所定位置に突起導体が設けられ、
前記絶縁性基材の配線及びその外部接続端子上に、前記突起導体の表面が露出しその一部が突出するように弾性体（エラストマ）が設けられていることを特徴とする配線基板。In a wiring board comprising an insulating base material, wiring provided on the surface of the base material and its external connection terminals,
Protruding conductors are provided at predetermined positions of the wiring,
A wiring board, wherein an elastic body (elastomer) is provided on the wiring of the insulating base and the external connection terminal so that the surface of the protruding conductor is exposed and a part of the protruding conductor protrudes . 絶縁性基材の表面に配線及びその外部接続端子が設けられ、
前記配線の所定位置に突起導体が設けられ、前記絶縁性基材の配線及びその外部接続端子上に、前記突起導体の表面が露出しその一部が突出するように弾性体（エラストマ）が設けられた配線基板を設け、前記配線基板の弾性体上に、半導体チップをその回路形成面が前記弾性体と向かい合うように設け、前記半導体チップの回路形成面に設けられた外部電極と前記配線基板の配線が、前記弾性体（エラストマ）で密封されて接続されていることを特徴とする半導体装置。Wiring and its external connection terminals are provided on the surface of the insulating base,
A protruding conductor is provided at a predetermined position of the wiring, and an elastic body (elastomer) is provided on the insulating substrate wiring and its external connection terminal so that the surface of the protruding conductor is exposed and a part thereof protrudes. A semiconductor chip is provided on an elastic body of the wiring board such that a circuit forming surface thereof faces the elastic body, and an external electrode provided on the circuit forming surface of the semiconductor chip and the wiring board The semiconductor device is characterized in that the wiring is sealed and connected by the elastic body (elastomer). テープ状の絶縁性基材の配線基板形成領域に、配線及びその外部接続端子を形成し、
前記配線の所定位置に突起導体を形成し、
前記配線基板形成領域の配線及び外部接続端子上に、前記突起導体と平面的に重なる位置に開口部を有する弾性体（エラストマ）を前記突起導体が前記開口部内に挿入され且つ前記突起導体の一部が前記開口部から突出するように貼り付けることを特徴とする配線基板の製造方法。In the wiring substrate forming region of the tape-like insulating base material, the wiring and its external connection terminal are formed,
Forming a protruding conductor at a predetermined position of the wiring;
An elastic body (elastomer) having an opening at a position overlapping the protruding conductor on the wiring and the external connection terminal in the wiring board forming region is inserted into the opening and the protruding conductor is one of the protruding conductors. A method of manufacturing a wiring board, wherein the part is pasted so as to protrude from the opening . テープ状の絶縁性基材の配線基板形成領域に、配線及びその外部接続端子を形成し、
前記配線の所定位置に突起導体を形成し、
前記配線基板形成領域の配線及び外部接続端子上に、前記突起導体と平面的に重なる位置に開口部を有する弾性体（エラストマ）を前記突起導体が前記開口部内に挿入され且つ前記突起導体の一部が前記開口部から突出するように貼り付け、
前記弾性体上に、半導体チップを、その外部電極形成面が前記弾性体と向かい合うように配置し、
前記半導体チップを、前記弾性体を介して前記配線基板に接着するとともに、前記半導体チップの外部電極と前記配線基板の配線を、前記弾性体で密封される突起導体により接続することを特徴とする半導体装置の製造方法。In the wiring substrate formation region of the tape-like insulating base material, wiring and its external connection terminals are formed,
Forming a protruding conductor at a predetermined position of the wiring;
An elastic body (elastomer) having an opening at a position overlapping with the protruding conductor on the wiring and external connection terminal in the wiring board forming region is inserted into the opening and the protruding conductor is one of the protruding conductors. Pasted so that the part protrudes from the opening ,
On the elastic body, a semiconductor chip is arranged so that the external electrode formation surface faces the elastic body,
The semiconductor chip is bonded to the wiring board through the elastic body, and the external electrode of the semiconductor chip and the wiring of the wiring board are connected by a protruding conductor sealed by the elastic body. A method for manufacturing a semiconductor device.
JP2000311721A 2000-10-05 2000-10-05 Wiring board, semiconductor device using the same, and manufacturing method thereof Expired - Fee Related JP4035949B2 (en)

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JP3721986B2 (en) * 2000-12-20 2005-11-30 日立電線株式会社 Semiconductor device and manufacturing method thereof
KR100713932B1 (en) * 2006-03-29 2007-05-07 주식회사 하이닉스반도체 Flip chip bonded package
JP4243621B2 (en) 2006-05-29 2009-03-25 エルピーダメモリ株式会社 Semiconductor package
JP2009038142A (en) * 2007-07-31 2009-02-19 Elpida Memory Inc Semiconductor stacked package
US9064757B2 (en) * 2012-02-29 2015-06-23 Mediatek Inc. Enhanced flip chip structure using copper column interconnect
US9437534B2 (en) 2012-02-29 2016-09-06 Mediatek Inc. Enhanced flip chip structure using copper column interconnect

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