JPH11203253A - Exclusive access control method for shared resource - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a exclusive access control method for shared resource to realize a data transfer on a high speed shared bus by eliminating the use of a shared bus for semaphore control in a multiprocessor system having a shared resource. SOLUTION: At the time of simultaneous access requests to a shared resource 7, processors 1a and 1b write an access request in semaphore registers 10a and 10b and is mediated by an exclusive access mediation circuit 12. Any one of the processors is given an access right by the processors 1a and 1b's reading the semaphore registers 10a and 10b and, at the time of access completion to the shared resource 7, the exclusive access mediation circuit 12 mediates an access request of other processors anew by the processors 1a and 1b's writing the access completion and the processors 1a and 1b are notified of the mediation result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an exclusive access control method for a shared resource on a shared bus in a multiprocessor system.

[0002]

2. Description of the Related Art In recent years, with a system using a processor, the processing content has become more complicated, and one processor cannot process the processing in time, and the processing is often shared by a plurality of processors. Also, with the high integration of semiconductors,
Increasingly, such a plurality of processors are integrated into a system on a single chip.

In such a multiprocessor system, for example, when a shared database is updated by a plurality of processors, a shared resource such that another processor does not access while one of the processors is updating the database. Exclusive access control is required. Conventionally, such exclusive access to a shared resource has been realized by a semaphore flag. A plurality of processors exclusively access the semaphore flag, and set (in use) if the flag value indicates a reset state (unused state), and acquire an access right to the shared resource. The processor that has failed to acquire the access right realizes exclusive access to the shared resource by waiting until the semaphore flag is reset (unused state).

FIG. 6 is a block diagram showing a circuit configuration of a multiprocessor system having shared resources in a conventional system using a semaphore flag. 7 and 8 are explanatory diagrams of the operation in the circuit configuration of FIG. In FIG. 6, 1a and 1b each represent a processor. The processors 1a and 1b share the same address space, and are connected to the shared memory 3 via the shared bus 2. The shared bus 2 is shared by the processors 1a and 1b but cannot be used at the same time. Therefore, the processors 1a and 1b request the shared bus arbitration circuit 4 to use the shared bus 2 via the bus request signals 5a and 5b, respectively. The shared bus arbitration circuit 4 is a circuit for arbitrating the use request of the shared bus 2 and, when a use request of the shared bus 2 comes at the same time, arbitrates the request.
Exclusive control is performed such that only one processor is permitted to use the shared bus. The use permission is given to only one of the two processors 1a and 1b via the bus grant signals 6a and 6b output from the shared bus arbitration circuit 4. Reference numeral 7 denotes a shared resource in the shared memory 3;
Is a semaphore flag indicating whether the shared resource 7 is being used.

In the above configuration, the access right acquisition when a plurality of processors simultaneously access the shared resource 7 will be described with reference to the operation explanatory diagram of FIG. When the processors 1a and 1b request access to the shared resource 7 at the same time, first, each of the processors 1a and 1b performs access to the semaphore flag 8,
The bus request signal 5a and the bus request signal 5b are output to the shared bus arbitration circuit 4. In FIG. 7, the section is “j”. The shared bus arbitration circuit 4 gives the use permission to only one of them by exclusive control. FIG. 7 shows an example in which the use permission is given to the processor 1a. The use permission is notified via a bus grant signal 6a which is an output of the shared bus arbitration circuit 4.

The processor 1a permitted to use the shared bus 2 reads the data of the address including the semaphore flag 8 in the next section "k". Then, in the next section “l”, the semaphore flag 8 in the read data is checked to confirm that the shared resource 7 is not in use, and only the semaphore flag 8 of the data is set (when the shared resource is being used). Declaration), and write to the address including the semaphore flag 8 in the next section “m”. This allows
The processor 1a acquires an access right to the shared resource 7 on the shared memory 3.

A series of processes (semaphore read, modify, write) from section "k" to section "m" must be performed continuously without the access right of the shared bus 2 being transferred to the processor 1b. No. The reason is that if the access right is transferred to the processor 1b during a series of processes from the section “k” to the section “m”, both the processors 1a and 1b recognize that the shared resource 7 is in the unused state. To do that. Therefore, the processor 1a keeps issuing the bus request request 5a to the bus arbitration circuit 4 during the section "k" to the section "m" so that the shared bus access right does not shift.

The processor 1a obtains the access right to the shared resource 7 by the above processing. After obtaining the right, the processor 1a sends the access right to the shared bus arbitration circuit 4 via the bus request signal 5a once at the completion of the section "m". The shared bus use request is notified and the shared bus 2 is released. The shared bus arbitration circuit 4 notifies the processor 1b of the right to use the shared bus via the bus grant signal 6b in the section "n", and the processor 1b reads the address including the semaphore flag 8 in the section "o". Therefore, the semaphore flag 8 is continuously read via the shared bus 2 until the semaphore flag 8 is reset.

Through the above operation, arbitration of access requests of the plurality of processors 1a and 1b to the shared resource 7 is realized. Next, with reference to FIG. 8, a description will be given of the relinquishment of the access right of a processor using a shared resource and the transfer of the access right to another processor. In FIG. 8, processor 1
a performs access C (section “p”) and access D (section “r”) to the shared resource 7 to complete the access to the shared resource 7, but the processor 1b alternates with the section.
Is the semaphore flag 8 in the section “q” and the section “s”.
And check whether it has been reset (not unused).

In the section "t", the processor 1a
Writes a reset (unused) to the semaphore flag 8 and relinquishes the access right. The processor 1b reads the semaphore flag 8 in the section "u", and modifies the semaphore flag in the section "v", sets the semaphore flag in the section "w" (in use), and resets the semaphore flag 8 in the section "w". Get access rights.

As described above, the exclusive access control for the shared resource 7 having the multiprocessor configuration is realized by the operation described with reference to FIGS.

[0012]

However, in the case of the conventional circuit configuration shown in FIG. 6, since the semaphore flag 8 exists on the shared bus 2, a plurality of processors 1a,
When 1b tries to access the shared resource 7, there is a problem that the data transfer speed on the shared bus 2 is reduced due to the semaphore flag access.

The use of the shared bus 2 for semaphore access is in the section “k” to the section “n” in FIG.
In FIG. 8, section “q” and section “s” to section “w”. In particular, in FIG. 8, while the processor 1a is accessing the shared resource 7 (section “p”, section “r”), the processor 1b alternately uses the shared bus 2 for semaphore access (section “q”). , Section “s”), so the shared resource 7
As the number of processors competing for access requests to
The access speed of the processor 1a to the shared memory 3 is significantly reduced.

The present invention solves the above-mentioned conventional problems, and realizes high-speed data transfer on a shared bus by eliminating the use of a shared bus for semaphore control in a multiprocessor system having shared resources. It is an object of the present invention to provide a shared resource exclusive access control method that can be used.

[0015]

SUMMARY OF THE INVENTION The present invention relates to an exclusive access control method for a shared resource on a shared bus in a multiprocessor system, which comprises a plurality of processors and a local bus which is a unique space of each processor. A connected readable / writable semaphore register, and an exclusive access arbitration circuit for granting access to any one of the processors via the semaphore register in response to a shared resource access request written to each semaphore register by the processor. When a simultaneous access request to the shared resource is made, the processor writes the access request to the semaphore register existing in each unique space, the access request is arbitrated by the exclusive access arbitration circuit, and the processor reads the semaphore register. Processor arbitration results An access right is given to any one of the processors, and when the access to the shared resource is completed, the processor writes the access completion to the semaphore register on the local bus, so that the exclusive access arbitration circuit is newly provided. And arbitrates the access request of the processor, and notifies the processor of the arbitration result via the semaphore register.

According to the shared resource exclusive access control method of the present invention, since the semaphore register for acquiring the access right to the shared resource is provided on each local bus,
No shared bus is used. As a result, it is possible to prevent a decrease in access speed of the shared resource due to the semaphore access at the time of contention for access to the shared resource, and it is possible to use the shared bus efficiently.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 2 is a block diagram illustrating a circuit configuration of a multiprocessor system having shared resources. In FIG. 1, the same components as those in FIG. 6 are denoted by the same reference numerals 1a, 1b,
Reference numerals 6a, 6b, 7, and 8 are added, and description thereof is omitted.

Reference numerals 9a and 9b denote local buses of the processors 1a and 1b, respectively, which are address-mapped in an internal space unique to the processor. Reference numerals 10a and 10b connected to the local buses 9a and 9b are semaphore registers to which addresses are mapped for exclusive control of the shared resource 7, respectively. When an access request to the shared memory 3 occurs, the processor 1a and the processor 1b write the access request to the shared resource 7 to the semaphore registers 10a and 10b via the local buses 9a and 9b, respectively. The written contents are held until the processor next sets new values in the semaphore registers 10a and 10b. The access request set in the semaphore registers 10a and 10b is a shared resource access request signal 11
The exclusive access arbitration circuit 12 is notified via a and 11b. The exclusive access arbitration circuit 12 gives access permission to a single processor from a plurality of shared resource access requests.
The processor is notified via a and 13b. The processors 1a and 1b respond to an access request to the shared resource 7 by
Whether or not the access is permitted can be known by reading the semaphore registers 10a and 10b, respectively.

FIG. 2 shows a block diagram of the exclusive access arbitration circuit 12. In FIG. 2, 14 is a combinational circuit, 1
5 is a holding circuit, and 16 is a basic clock which also enters the processors 1a and 1b and the shared bus arbitration circuit 4. In the above-described circuit configuration, the acquisition of an access right when a plurality of processors simultaneously access a shared resource will be described with reference to the operation explanatory diagram of FIG.

When the processors 1a and 1b simultaneously request access to a shared resource, the semaphore registers 10a and 10b are connected via local buses 9a and 9b, respectively.
Write a shared resource access request to In FIG. 3, the section is “a”. The access request is notified to the exclusive access arbitration circuit 12 via the shared resource access request signals 11a and 11b.

The exclusive access arbitration circuit 12 gives an access right to only one of access requests from a plurality of processors. FIG. 3 shows an example in which an access right is given to the processor 1a. Whether or not the access right has been granted can be known by each processor 1a, 1b reading the semaphore registers 10a, 10b. The section "b" corresponds to the semaphore registers 10a, 1
0b is a lead section. The processor 1a reads the semaphore register 10a and learns that it has acquired the right to access the shared resource. In the next section "c", the processor 1a sends a request to use the shared bus 2 to the shared bus arbitration circuit 4 and sends a bus request signal. Notify via 5a. Then, the processor 1a starts accessing the shared resource 7 from the next section “d”. Further, the processor 1b reads the semaphore register 10b in the section "b" and, since access to the shared resource 7 is not permitted, continues reading the semaphore register 10b and waits until it is permitted.

Next, with reference to FIG. 4, a description will be given of the relinquishment of the access right of a processor using a shared resource and the transfer of the access right to another processor. In FIG. 4, the processor 1a continuously performs access A (section “e”) and access B (section “f”) to the shared resource 7,
The access to the shared resource 7 is completed. And section “g”
In, the processor 1a writes a reset (unused) to the semaphore register 10a and relinquishes the access right. The release of the access right is notified to the exclusive access arbitration circuit 12 via the shared resource access request signal 11a. Thereby, the access request is sent to the processor 1b.
The exclusive access arbitration circuit 12 cancels the access permission to the processor 1a, and instead notifies the processor 1b of the access permission via the access permission signal 13b. The processor 1b knows that the access right to the shared resource 7 has been acquired by reading the semaphore register 10b in the section "h". Then, the processor 1b starts accessing the shared resource 7 from the next section “i”.

FIG. 5 is a state transition diagram of the exclusive access arbitration circuit 12. STATE1 is a state in which a shared resource is not used, ST
ATE2 is a state where the processor 1a is using the shared resource, STATE3 is a state where the processor 1b is using the shared resource, and the following transition conditions are not satisfied in the input signals (shared resource access request signals) 11a and 11b. As long as the current STATE is maintained.

I: input signal 11a = “H ₁ ” II: input signal 11a = “L ₁ ” and input signal 11b =
“L ₁ ” III: input signal 11 a = “L ₁ ” and input signal 11 b =
"H _1" IV: Input signal 11a = "H _1" and the input signal 11b =
"L _1" V: the input signal 11a = "L _1" and the input signal 11b =
“L ₁ ” VI: input signal 11a = “L ₁ ” and input signal 11b =
“H ₁ ” Note that “H ₁ ” indicates that there is a shared resource access request and “L ₁ ”
Are assigned without a shared resource access request.

That is, when a shared resource access request comes from the processors 1a and 1b at the same time, the STA
Transit to TE2. The processor 1a acquires the shared resource access right and stays in STATE2 until the access is completed.
Since 1a is withdrawn, the above transition condition III is satisfied and S
Transition to TATE3. The same applies to other state transitions.

Output signals (shared resource access permission signals) 13a, 13 in each of the states STATE1 to STATE3
b is as follows. STATE 1: Output signal 13a = "L _2" and the output signal 13b = "L _2" STATE2: Output signal 13a = "H _2" and the output signal 13b = "L _2" STATE3: Output signal 13a = "L _2" and the output Signal 13b = “H ₂ ” Note that “H ₂ ” is assigned to permit shared resource access, and “L ₂ ” is assigned to disable shared resource access.

In the above transition conditions, the processor 1a is given priority when a shared resource access request occurs simultaneously, but if the processor 1b is to be given priority, the transition conditions of I and VI may be changed as follows. I: input signal 11a = “H ₁ ” and input signal 11b =
“L ₁ ” VI: input signal 11 b = “H ₁ ” As described above, exclusive access control to the shared resource of the multiprocessor configuration using the semaphore register is realized.

According to the shared resource exclusive access control system configured as described above, the semaphore registers 10a and 10b for acquiring the access right to the shared resource 7 are provided on the local buses 9a and 9b, respectively. Not used. As a result, it is possible to prevent a decrease in the speed of shared resource access due to semaphore access at the time of contention for access to the shared resource 7, which has occurred in the conventional configuration, and the shared bus 2 can be used efficiently.

Although the above embodiment has been described with reference to the case of two processors 1a and 1b, the same applies to the case of three or more processors.

[0030]

According to the shared resource exclusive access control method of the present invention, since the semaphore registers for acquiring the access right to the shared resource are provided on each local bus, the shared bus is not used. As a result, it is possible to prevent a decrease in access speed of the shared resource due to the semaphore access at the time of contention for access to the shared resource, and it is possible to use the shared bus efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of an exclusive access arbitration circuit according to one embodiment of the present invention;

FIG. 3 is a timing chart illustrating access right acquisition when a plurality of processors simultaneously access a shared resource according to an embodiment of the present invention;

FIG. 4 is a timing chart showing a relinquishment of an access right of a processor and a transfer of an access right to another processor during use of a shared resource according to an embodiment of the present invention;

FIG. 5 is a state transition diagram of the exclusive access arbitration circuit according to the embodiment of the present invention;

FIG. 6 is a block diagram showing a circuit configuration of a conventional example.

FIG. 7 is a timing chart showing access right acquisition when a plurality of processors simultaneously access a shared resource in a conventional example.

FIG. 8 is a timing chart showing a relinquishing of an access right of a processor and a transfer of an access right to another processor during use of a shared resource in a conventional example.

[Explanation of symbols]

 1a, 1b Processor 2 Shared bus 3 Shared memory 4 Shared bus arbitration circuit 5a, 5b Bus request signal line 6a, 6b Bus grant signal line 7 Shared resource 9a, 9b Local bus 10a, 10b Semaphore register 11a, 11b Shared resource access request signal 12 Exclusive access arbitration circuit 13a, 13b Shared resource access permission signal

Claims (1)

[Claims] 1. An exclusive access control method for a shared resource on a shared bus in a multiprocessor system, comprising: a plurality of processors; and a read / write enabled connected to a local bus which is a unique space of each of the processors. A semaphore register, and an exclusive access arbitration circuit for granting access to any one of the processors via the semaphore register to a shared resource access request written to each of the semaphore registers by the processor, At the time of a request for simultaneous access to resources, the processor writes an access request to the semaphore register existing in each unique space, the access request is arbitrated by the exclusive access arbitration circuit, and the processor reads the semaphore register. The result of the arbitration Then, an access right is given to any one of the processors, and when the access to the shared resource is completed, the processor writes the access completion to the semaphore register on the local bus, A shared resource exclusive access control method, wherein the exclusive access arbitration circuit newly arbitrates an access request from another processor and notifies the processor of the arbitration result via the semaphore register.