JPH11187002A - Code detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a code detecting circuit with which operation for discriminating a code such as a header byte code is accelerated. SOLUTION: A code detecting circuit CDDT successively and alternately serially connects flip-flops FF41-FF49 to be operated according to a received clock signal RXC and to selectively turn their non-inverted output signals Q to a high level when a prescribed bit just before received serial data is coincident with the correspondent bit of a COMMA code as a detection object and two-input WAND gates NA1-NA9 for identifying the coincidence of one bit next to serial data with one correspondent bit of the COMMA code and transmitting it to the FF 42-49 when two leading bits of serial data are coincident with two correspondent bits of the COMMA code or the non-inverted output signals Q of the FF 41-48 on the preceding stage are turned to the high level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code detection circuit, for example, a communication LSI for a fiber channel standard.
The present invention relates to a detection circuit for a header byte code included in a transmission / reception macro cell of a (large-scale integrated circuit device) and a technique particularly effective when used for speeding up the detection circuit.

[0002]

2. Description of the Related Art A CMOS (complementary MOS) circuit is used as a basic element, and for example, 1.0625 Gbps (gigabit /
There is a high-speed communication LSI that supports the Fiber Channel standard, which supports high-speed serial transfer in seconds. A serial-parallel conversion circuit mounted on such a high-speed communication LSI for converting received data input serially into parallel data in byte units, and a serial-parallel converter converting transmission data input parallel in byte units into serial data. There is a transmission / reception macrocell including a serial conversion circuit. The transmission / reception macrocell further includes a code detection circuit for detecting, for example, a header bytecode for byte alignment from received data input serially.

[0003]

Prior to the present invention, the present inventors engaged in the development of a transmission / reception macrocell including the above-mentioned code detection circuit and mounted on a high-speed communication LSI.
I noticed the following problems: That is, as shown in FIG. 6, the code detection circuit CDDT of the transmission / reception macrocell includes flip-flops FF60 to FF69 constituting a shift register for serial-parallel conversion of the reception serial data RSD.
-Input NAND (NAND) gates NA10 and NA1 receiving a non-inverted or inverted output signal of the same in a predetermined combination
1 and a NOR (NOR) gate NO1 receiving the output signals of these NAND gates NA10 and NA11.
The output signal of the NOR gate NO1 is the reception clock signal RX
C, which is transmitted to the flip-flop FF70 operating according to C, and the non-inverted output signal Q of the flip-flop FF70 is
A flip-flop that operates according to an inverted reception byte align signal RAB (here, a so-called inverted signal or the like which is selectively set to a low level when it is made valid is denoted by suffixed with B at the end of the name. The same applies hereinafter). FF
After passing through 71, it becomes a code detection signal COMD.

The output signals of the NAND gates NA10 and NA11 are simultaneously set to a low level when 10 consecutive bits of the received serial data RSD coincide with, for example, a logic "00111111010", that is, a COMMA code which is a header byte code. Thus, the output signal of the NOR gate NO1 is set to the high level. The non-inverted output signal Q of the flip-flop FF70 receiving the high level of the output signal of the NOR gate NO1, that is, F70Q
Is set to the high level in the next cycle of the reception clock signal RXC, and the inverted reception byte alignment signal RAB is set to the low level in the next cycle of the reception clock signal RXC in response to the high level of the non-inversion output signal F70Q of the flip-flop FF70. Is done. As a result, the code detection signal CO
In the MD, consecutive 10 bits of the reception serial data RSD of the reception clock signal RXC are logic “00111110”.
High level in the next cycle after 10 ",
In response, parallel transfer of the received serial data RSD is performed.

However, in the case of a high-speed communication LSI using a CMOS circuit as a basic element, the NAND gates NA10 to NA11 of the code detection circuit CDDT are connected with five N-channel MOSFETs (metal oxide semiconductor Type field effect transistor, where M
OSFETs, which are collectively referred to as insulated gate field effect transistors), and a relatively long time is required until the logic level of the output signal is determined.
For this reason, the speed of a communication system including a high-speed communication LSI has been increased, and the data rate has become, for example, 1.0625 Gb.
ps and the period of the reception clock signal RXC is 1n
s (nanosecond) or less, the NAND gates NA10 to N
The code determination operation by A11 and the NOR gate NO1 cannot be realized within one cycle of the reception clock signal RXC, and this limits the speed of the high-speed communication LSI and the speed of the communication system including the same.

SUMMARY OF THE INVENTION An object of the present invention is to realize a code detection circuit which speeds up the operation of judging a code such as a header byte code. It is another object of the present invention to increase the speed of a transmission / reception macro cell including a code detection circuit, a high-speed communication LSI including the same, and a communication system including the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a code detection circuit constituting a transmission / reception macro cell or the like of a communication LSI conforming to the Fiber Channel standard operates in accordance with a reception clock signal, and a predetermined bit immediately before input data serially input in synchronization with the reception clock signal is detected. A flip-flop whose output signal is selectively set to a valid level when it matches the corresponding bit of the code, and a flip-flop in which a predetermined bit at the head of the input data matches the corresponding bit of the code, or Of the input data is set to a valid level and, for example, a two-input logic gate for transmitting to a subsequent flip-flop by identifying that the next one bit of the input data coincides with the corresponding bit of the code, for example. It is configured by alternately connecting in series.

According to the above-mentioned means, the input data serially input at a high rate is compared with the corresponding bit of the code to be detected bit by bit, and the result is held by the flip-flop and sequentially transmitted. It can be determined within one cycle that the input data matches the above code. As a result, it is possible to speed up the operation of determining a code such as a header byte code by the code detection circuit, and thereby to realize a transmission / reception macrocell including the code detection circuit, a high-speed communication LSI including the same, and a communication system including the same. Higher speed can be achieved.

[0010]

FIG. 1 shows a transmission / reception macro cell TRM including a code detection circuit CDDT to which the present invention is applied.
A block diagram of one embodiment of C is shown. First, the outline of the configuration and operation of the transmission / reception macro cell TRMC including the code detection circuit CDDT of this embodiment will be described with reference to FIG. The transmission / reception macro cell TRM of this embodiment
C is mounted on a fiber channel standard compliant high-speed communication LSI having a CMOS circuit as a basic element. The high-speed communication LSI constitutes a communication system having a data rate of, for example, 1.0625 Gbps. The circuit elements constituting each block of FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon together with other circuit elements constituting a high-speed communication LSI by a known CMOS integrated circuit manufacturing technique. You.

In FIG. 1, a transmission / reception macrocell TRMC of this embodiment includes a serial / parallel conversion circuit S / P and a parallel / serial conversion circuit P / S as its basic components. The serial / parallel converter S / P is supplied with the reception serial data RSD from the input buffer IB, the predetermined reception clock signal RXC from the reception PLL circuit PLLR, and the predetermined frequency from the frequency divider FD. An inverted receive byte align signal RAB is provided. Further, the serial-parallel conversion circuit S
/ P, a 10-bit parallel output signal, that is, received data RXD0 to RXD9, is supplied to a protocol device PD (not shown) on the left side of the drawing, and flip-flops FF1 to FF3 (not shown) constituting a serial-parallel conversion circuit S / P.
Are output to the code detection circuit CDDT. The code detection circuit CDDT includes:
The reception clock signal RXC and the inverted reception byte alignment signal RAB are supplied, and the output signal, that is, the code detection signal COMD is supplied to the protocol device PD.

The input buffer IB of the transmission / reception macro cell TRMC is supplied with non-inverted input data + DIN and inverted input data DOUT, which are complementary signals, from a transmission circuit TM (not shown) on the right side of the figure. , As described above,
P and supplied to the receiving PLL circuit PLLR. The output signal of the reception PLL circuit PLLR, that is, the reception clock signal RXC is supplied to the serial / parallel conversion circuit S / P and the code detection circuit CDDT as described above, and is also supplied to the frequency dividing circuit FD. On the basis of the RXC and the non-inverted output signal F49Q of the flip-flop FF49 constituting the code detection circuit CDDT, the inverted receive byte align signal RAB and the receive byte clock signal RBC0 having the frequency of 1/10 of the receive clock signal RXC. RBC1 is formed. The inverted reception byte alignment signal RAB is supplied to the serial / parallel conversion circuit S / P and the code detection circuit CDDT as described above, and the reception byte clock signals RBC0 and RBC1 are supplied to the protocol device PD.

The input buffer IB converts the non-inverted input data + DIN and the inverted input data -DIN supplied from the transmission system circuit TM including the transmission line into reception serial data RSD, and performs serial / parallel conversion circuit S / P and reception PLL. Circuit PL
Transmit to LR. The reception PLL circuit PLLR is a so-called phase-locked loop circuit, which extracts a clock component from the reception serial data RSD and generates a reception clock signal RXC whose center frequency is 1.0625 GHz (gigahertz). Parallel conversion circuit S /
P, a code detection circuit CDDT and a division circuit FD are supplied to each part of the transmission / reception macrocell TRMC. Further, the frequency dividing circuit FD divides the frequency of the received clock signal RXC supplied from the receiving PLL circuit PLLR by one tenth, and substantially adds the frequency to the non-inverted output signal F49Q of the flip-flop FF49 supplied from the code detecting circuit CDDT. It forms a synchronized inverted receive byte align signal RAB and receive byte clock signals RBC0 and RBC1. Among them, the inverted reception byte alignment signal RAB is supplied to the serial / parallel conversion circuit S / P and the code detection circuit CDDT as described above.
And receive byte clock signals RBC0 and RB
C1 is supplied to the protocol device PD. Needless to say, the center frequency of the inverted reception byte alignment signal RAB and the reception byte clock signals RBC0 and RBC1 is 0.10625 GHz, that is, 106.25 MHz.
(Megahertz).

On the other hand, the serial / parallel conversion circuit S / P includes a shift register which operates according to the reception clock signal RXC, as described later, and converts the reception serial data RSD supplied from the input buffer IB into 10-bit parallel data, that is, reception data. The data is converted into data RXD0 to RXD9 and transmitted to the protocol device PD. Further, the code detection circuit CDDT includes inverted output signals F1QB-F1 of the flip-flops FF1 to FF3 supplied from the serial / parallel conversion circuit S / P.
Based on the F3QB, a COMMA code included in the received serial data RSD, for example, as a header byte code is identified, and the code detection signal COMD is selectively set to a valid level, that is, a high level at a predetermined timing. The code detection signal COMD is supplied to the protocol device PD,
It is provided for the protocol processing. The specific configuration and operation of the serial / parallel conversion circuit S / P and the code detection circuit CDDT will be described later in detail.

Next, the parallel / serial conversion circuit P / S of the transmission / reception macro cell TRMC includes 10
Bit parallel data, that is, transmission data TXD0-T
XD9 is supplied and the transmission PLL circuit PLLT
Supplies a transmission clock signal TXC. Transmission PLL
The circuit PLLT includes a crystal oscillation circuit XOSC (not shown).
From the transmission byte clock signal TB of 106.25 MHz
C is supplied. This transmission byte clock signal TBC
Is also supplied to the protocol device PD. The output signal of the parallel / serial conversion circuit P / S is the transmission serial data TSD
Is supplied to the output buffer OB, and its output signal is
Non-inverted output data + DOUT and inverted output data -DO
It is supplied as a UT to the transmission circuit TM.

The transmission PLL circuit PLLT is provided with a transmission byte clock signal TBC supplied from the crystal oscillation circuit XOSC.
Is multiplied by a factor of 10 to generate a transmission clock signal TXC, which is supplied to the parallel / serial conversion circuit P / S. Further, the parallel / serial conversion circuit P / S converts transmission data TXD0 to TXD9 supplied in parallel from the protocol device PD in synchronization with the transmission byte clock signal TBC into transmission serial data of 1.0625 Gbps synchronized with the transmission clock signal TXC. Convert to TSD and supply to output buffer OB. The output buffer OB includes non-inverted output data + DOUT and inverted output data -D, which are complementary signals, based on the transmission serial data TSD supplied from the parallel / serial conversion circuit P / S.
OUT is formed and transmitted to the transmission circuit TM.

FIG. 2 shows the transmission / reception macro cell TRM of FIG.
3 is a circuit diagram of one embodiment of a serial-parallel conversion circuit S / P included in C. The specific configuration and operation of the serial-parallel conversion circuit S / P constituting the transmission / reception macrocell TRMC of this embodiment will be described with reference to FIG. In the following circuit diagram, flip-flops constituting each circuit including the serial / parallel conversion circuit S / P of the transmission / reception macro cell TRMC are as follows:
A non-inverted data input terminal D and a non-inverted data output terminal Q are provided, respectively, but in the following description, they are simply referred to as the data input terminal D and the data output terminal Q. Each flip-flop is a so-called edge-triggered flip-flop having a clock input terminal CK. The logic level of the non-inverted output signal Q is synchronized with the rising edge of the clock signal input to the clock input terminal CK. And change.

In FIG. 2, the serial-parallel conversion circuit S / P of this embodiment is not particularly limited, but a flip-flop FF1 receiving a reception serial data RSD at a data input terminal D thereof and two serially-formed flip-flops FF1. Flip-flops FF2 and F connected in series to flip-flop FF1 via inverters V1 and V2 or V3 and V4
F3. Also, two inverters V5 and V6, V7 and V8, V9 and V10, V1 which are in a series form
1 and V12, V13 and V14, V15 and V16,
V17 and V18, V19 and V20, V21 and V2
2 or 10 flip-flops FF10 to FF19 which are serially coupled to the flip-flop FF3 via V23 and V24 to form a shift register for serial-parallel conversion together with the FF1 to FF3, and these flip-flops FF10 to FF19 The output register is constituted by receiving the non-inverted output signal Q of
It includes zero flip-flops FF20 to FF29.
Among these, the reception clock signal RXC is commonly supplied to the clock input terminals CK of the flip-flops FF1 to FF3 and FF10 to FF19 forming the shift register, and the flip-flop FF forming the output register is provided.
The inverted reception byte alignment signal RAB is commonly supplied to the clock input terminals CK of the FFs 20 to FF29.

Flip-flops FF1 to FF3 and FF constituting a shift register of the serial / parallel conversion circuit S / P
The 10-FF 19 performs a shift operation according to the reception clock signal RXC, and sequentially shifts and transmits the reception serial data RSD supplied from the input buffer IB. Also, flip-flops FF20 to FF constituting an output register
29 fetches and holds the non-inverted output signals F10Q to F19Q of the flip-flops FF10 to FF19 in parallel in accordance with the inverted receive byte alignment signal RAB supplied from the frequency divider FD, and holds the received data RXD0.
RXD9 to the protocol device PD.
Flip-flops FF1 to F forming a shift register
The non-inverted output signal Q of F3 is output from the corresponding inverter V1,
After being inverted by V3 or V5, respectively, the inverted output signals F1QB to F1QB of the flip-flops FF1 to FF3 are output.
F3QB (hereinafter, the inverted signal of the inverter immediately after the corresponding non-inverted output signal Q of each flip-flop by the inverter is referred to as the inverted output signal QB) and the code detection circuit CDD
T is used for the code detection process. The non-inverted output signals Q of the flip-flops FF20 to FF29 are supplied to the protocol device PD as received data RXD0 to RXD9.

FIG. 3 shows the transmission / reception macro cell TRM of FIG.
A circuit diagram of an embodiment of the code detection circuit CDDT included in C is shown. FIG. 4 is a signal waveform diagram of one embodiment of the code detection circuit CDDT of FIG. 3, and FIG. 5 is a signal waveform diagram of one embodiment of the transmission / reception macrocell TRMC of FIG. . With reference to these figures, the specific configuration and operation of the code detection circuit CDDT constituting the transmission / reception macrocell TRMC of this embodiment and the features thereof will be described. In the following signal waveform diagram, each cycle of the reception clock signal RXC is composed of ten cycles A0 to A9, B0 to B9,
Exemplified as C0 to C9 and D0 to D9. Also, the received serial data RSD processed by the transmission / reception macro cell TRMC is one frame with four bytes, and the first byte, that is, cycles A0 to A9,
This is a header byte code for identifying the start of each frame, that is, a COMMA code of logic “00111111010”.

In FIG. 3, a code detection circuit CDDT of this embodiment has an inverted output signal F1Q of a flip-flop FF1 of a serial / parallel conversion circuit S / P connected to a data input terminal D thereof.
The two flip-flops FF31 and FF32 receiving the inverted signal from the inverter V25 or V26 of B, and the inverted output signals F1QB and F1 of the flip-flops FF1 and FF2 of the serial / parallel conversion circuit S / P are connected to a pair of input terminals.
It includes a 2-input substantial AND circuit receiving 2QB, that is, a NAND gate NA1. The data input terminal D
A flip-flop FF41 receiving an inverted signal of the output signal of the NAND gate NA1 by the inverter V31, and NAND gates NA2 to NA9 and flip-flops FF42 to FF49 alternately serially connected to the subsequent stage of the flip-flop FF41. And two flip-flops FF50 and FF51 provided at the subsequent stage. Flip-flop FF
The receiving clock signal RXC is commonly supplied to clock input terminals CK of the flip-flops 31 and FF32 and FF41 to FF50, and the inverted receiving byte-aligned signal RAB is supplied to the clock input terminal CK of the flip-flop FF51.

As described above, the flip-flops FF1 to FF3 of the serial / parallel conversion circuit S / P are in a serial form in which the non-inverting output terminal Q and the data input terminal D are sequentially connected, and both receive clock signals. It operates according to RXC. Therefore, the non-inverted output signal Q of the flip-flop FF31 corresponds to the non-inverted output signal Q of the flip-flop FF2, and the inverted signal of the non-inverted output signal Q of the flip-flop FF32 by the inverter V29 corresponds to the inverted output signal F2QB. Will do. The flip-flops FF31 and FF32 are provided with serial / parallel conversion circuits S / P, as can be easily analogized to engineers engaged in related fields.
To compensate for the output fan-out of the flip-flop FF2, and to reduce the transmission delay time of the output signal.

One input terminal of the NAND gate NA2 corresponding to the flip-flop FF42 of the code detection circuit CDDT is supplied with the non-inverted output signal Q of the preceding flip-flop FF41, and the other input terminal is supplied with the serial-parallel conversion signal. An inverted signal of the inverted output signal F2QB of the flip-flop FF2 of the circuit S / P by the inverter V27, that is, a non-inverted output signal F2Q is supplied. The non-inverted output signal Q of the preceding flip-flop FF42 is supplied to one input terminal of the NAND gate NA3 corresponding to the flip-flop FF43, and the other input terminal is connected to the flip-flop of the serial / parallel conversion circuit S / P. An inverted signal of the inverted output signal F2QB of the flip-flop FF2 by the inverter V28, that is, a non-inverted output signal F2Q is supplied.

Similarly, the non-inverted output signal Q of the preceding flip-flop FF43 is supplied to one input terminal of the NAND gate NA4 corresponding to the flip-flop FF44, and the code detection circuit CDDT is supplied to the other input terminal.
, That is, the non-inverted output signal F2Q of the flip-flop FF2 of the serial-parallel conversion circuit S / P. The non-inverted output signal Q of the preceding flip-flop FF44 is supplied to one input terminal of the NAND gate NA5 corresponding to the flip-flop FF45, and the non-inverted output signal Q of the flip-flop FF31 is supplied to the other input terminal. That is, the non-inverted output signal F2Q of the flip-flop FF2 of the serial-parallel conversion circuit S / P is supplied. Furthermore, flip-flop FF
The non-inverted output signal Q of the preceding flip-flop FF45 is supplied to one input terminal of the NAND gate NA6 corresponding to 46, and the non-inverted output signal Q of the flip-flop FF31, that is, serial-parallel conversion, is supplied to the other input terminal. Non-inverted output signal F2 of flip-flop FF2 of circuit S / P
Q is supplied.

On the other hand, the non-inverted output signal Q of the preceding flip-flop FF46 is supplied to one input terminal of the NAND gate NA7 corresponding to the flip-flop FF47, and the code detection circuit CDDT is supplied to the other input terminal.
Of the non-inverted output signal Q of the flip-flop FF32 by the inverter V29, that is, the serial / parallel conversion circuit S /
The inverted output signal F2QB of the P flip-flop FF2 is supplied. The non-inverted output signal Q of the preceding flip-flop FF47 is supplied to one input terminal of the NAND gate NA8 corresponding to the flip-flop FF48, and the other input terminal is connected to the inverter V30 of the output signal of the inverter V29. , Ie, the non-inverted output signal F2Q of the flip-flop FF2 of the serial-parallel conversion circuit S / P. Further, the non-inverted output signal Q of the preceding flip-flop FF48 is supplied to one input terminal of the NAND gate NA9 corresponding to the flip-flop FF49, and the non-inverted output signal Q of the flip-flop FF32 is supplied to the other input terminal. Inverter V2
9, the inverted output signal F2QB of the flip-flop FF2 of the serial / parallel conversion circuit S / P is supplied.

Here, flip-flops FF31 to FF32 and FF41 to FF of the code detection circuit CDDT are used.
The received clock signal RXC supplied to the 50 clock input terminals CK is, as shown in FIG.
And a pulse signal having a frequency of 50 Hz and a duty of 50%, for example, and supplied to the clock input terminal CK of the flip-flop FF51.
B is set to a low level in a cycle B3 three cycles after the cycle A9 corresponding to the last bit of the COMMA code, and then set to a low level again in a cycle C3 ten cycles after the cycle A9. Further, the inverted output signal F1QB of the flip-flop FF1 of the serial / parallel conversion circuit S / P is the reception serial data RSD supplied to the data input terminal D thereof.
Are delayed by one cycle of the reception clock signal RXC, and the inverted output signals F2QB and F3QB of the flip-flops FF2 and FF3 are signals obtained by delaying the reception serial data RSD by one bit each.

From these facts, the inverted signal of the output signal of the NAND gate NA1 by the inverter V31, that is, the output signal V31out of the inverter V31 is the same as the inverted output signals F2QB and F3QB of the flip-flops FF2 and FF3 of the serial / parallel conversion circuit S / P. When set to the high level, in other words, the corresponding two bits of the received serial data RSD in the process of shift transmission via the flip-flops FF2 and FF3 are the code detection circuit CD.
When the logic value is coincident with the corresponding two bits of the COMMA code to be detected by the DT and both are set to logic "0", the logic level is selectively set to a high level.
The 41 non-inverted output signal F41Q is selectively set to a valid level, that is, a high level in the next cycle.

On the other hand, an inverted signal of the output signal of the NAND gate NA2 by the inverter V32, that is, the inverter V32
The output signal V32out of the flip-flop FF41
Is high, and the non-inverted output signal F2Q of the flip-flop FF2 of the serial-parallel conversion circuit S / P is high, in other words, the two bits immediately before the received serial data RSD. Is logical "00" and the next bit of the received serial data RSD in the process of shift transmission via the flip-flop FF2 is the same as the corresponding one bit of the COMMA code to be detected by the code detection circuit CDDT. When the logic "1" is set, the level is selectively set to a high level. In response to this, the non-inverted output signal F4 of the flip-flop FF42 is received.
2Q is selectively set to the high level in the next cycle of the reception clock signal RXC.

Similarly, inverted signals of the output signals of the NAND gates NA3 to NA9 by the inverters V33 to V39, that is, the output signals V33out to V33out of the inverters V33 to V39.
V39out is a flip-flop FF of the preceding stage, respectively.
In other words, when the non-inverted output signals F42Q to F48Q of 42 to FF38 are set to the high level and the non-inverted output signal F2Q or the inverted output signal F2QB of the flip-flop FF2 of the serial-parallel conversion circuit S / P is set to the high level, in other words, For example, the received 3 bits to 9 bits immediately before the received serial data RSD coincide with the corresponding 3 bits to 9 bits of the COMMA code to be detected, and the received serial data is in the shift transmission process via the flip-flop FF2. When the next bit of the RSD coincides with the corresponding bit of the COMMA code, the bit is selectively set to a high level.
The non-inverted output signals F43Q to F49Q of F49 are selectively set to the high level in the next cycle of the reception clock signal RXC.

As a result, the non-inverted output signal F49Q of the flip-flop FF49 of the code detection circuit CDDT is obtained.
Is selectively set to a high level in a cycle B2 two cycles after the cycle A9 corresponding to the last bit of the COMMA code, and in response to this, the non-inverted output signal F50Q of the flip-flop FF50 becomes the next cycle of the reception clock signal RXC. Is selectively set to a high level. As described above, the non-inverted output signal F49 of the flip-flop FF49
Q is also supplied to the frequency dividing circuit FD, and upon receiving the high level of the non-inverted output signal F49Q, the inverted received byte alignment signal RAB is changed to the next cycle of the received clock signal RXC.
That is, after being selectively made low level in cycle B3,
Further, in the cycle ten cycles after that, that is, in cycle C3, the level is set to the low level again. Further, the frequency dividing circuit FD
Is a flip-flop FF49 as shown in FIG.
Receiving the high level of the non-inverted output signal F49Q, the received byte clock signal RBC having a predetermined setup time tbef and hold time taft with respect to its falling, that is, the rising of the code detection signal COMD.
0 and RBC1 are formed and supplied to the protocol device PD.

In the code detection circuit CDDT, the flip-flop FF51 is set in response to the rise of the inverted reception byte alignment signal RAB, and the non-inversion output signal F51Q, that is, the code detection signal COMD is set in the next cycle of the reception clock signal RXC. It goes high in synchronization with cycle B4. This code detection signal COMD
Is returned to the low level after 10 cycles, that is, in response to the second rising of the inverted reception byte alignment signal RAB in the cycle C3.

As described above, the code detection signal COMD formed by the code detection circuit CDDT is supplied to the protocol device PD.
It is determined that the MMA code has been detected, and the subsequent 3 bytes, that is, 30 bits, are identified as substantial communication data included in the frame. These communication data are taken into the protocol device PD in accordance with the received byte clock signals RBC0 and RBC1 output from the frequency divider FD of the code detection circuit CDDT, and are subjected to reception processing.

As described above, the code detection circuit CDDT included in the transmission / reception macro cell TRMC of this embodiment operates in accordance with the reception clock signal RXC and synchronizes with the input data, ie, immediately before the reception serial data RSD. FF41 to FF49 whose output signals are selectively set to an effective level, that is, a high level, when the predetermined bit of the received serial data coincides with the corresponding bit of, for example, a COMMA code to be detected. For example, 2 bits are COMM
When the bit coincides with the corresponding bit of the A code, or the output signals of the flip-flops FF41 to FF48 of the preceding stage are set to the high level, and for example, the next one bit of the reception serial data RSD coincides with the corresponding bit of the COMMA code. And the flip-flop F
For example, two-input logic gates transmitted to F42 to FF49, that is, NAND gates NA1 to NA9 are sequentially and alternately connected in series. Therefore, the logic gate provided for the code detection processing of the code detection circuit CDDT has at most two inputs, and its transmission delay time is as shown in FIG.
This is sufficiently smaller than the conventional code detection circuit illustrated in FIG. As a result, the operation of determining the code such as the COMMA code by the code detection circuit CDDT can be speeded up so as to be completed within one cycle.
It is possible to increase the speed of the MC, the LSI for high-speed communication including the same, and the communication system including the same.

The operation and effect obtained from the above embodiment are as follows. (1) A code detection circuit constituting a transmission / reception macro cell of a communication LSI conforming to the Fiber Channel standard operates in accordance with a reception clock signal, and detects a predetermined bit immediately before input data serially input in synchronization with the reception clock signal. A flip-flop whose output signal is selectively set to a valid level when the bit matches the corresponding bit of the target code; and a predetermined bit at the beginning of the input data matches the corresponding bit of the code, or And a two-input logic gate for identifying that the output signal of the flip-flop has a valid level and that the next predetermined bit of the input data matches the corresponding bit of the code, and transmitting the same to the subsequent flip-flop. Are serially and alternately connected in series, so that input data serially input at a high rate can be input. The data is compared with the corresponding bits of the code to be detected bit by bit, and the result is held by a flip-flop, sequentially transmitted, and it can be determined within one cycle that the code matches the code. can get.

(2) According to the above item (1), an effect is obtained that the operation of determining a code such as a header byte code by the code detection circuit can be sped up. (3) According to the above items (1) and (2), there is an effect that the transmission / reception macro cell including the code detection circuit, the high-speed communication LSI including the same, and the communication system including the same can be speeded up. can get.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is. For example, in FIG. 1, the block configuration of the transmission / reception macro cell TRMC can adopt various embodiments, and the same applies to the interface conditions between the transmission system circuit TM and the protocol device PD. The clock generation circuit for generating the transmission byte clock signal TBC is not particularly required to be a crystal oscillation circuit, and the reception clock signal RXC, the transmission clock signal TXC, the reception byte clock signals RBC0 and RBC1, and the transmission byte. The frequency of the clock signal TBC can also be set arbitrarily.

In FIG. 2, the specific circuit configuration of the serial-parallel conversion circuit S / P is not restricted by this embodiment. In FIG. 3, the logic gate constituting the code detection circuit CDDT does not need to be a two-input NAND gate.
For example, three inputs may be used as long as the transmission delay time allows. In this case, each flip-flop constituting the code detection circuit CDDT needs to operate according to a clock signal obtained by dividing the received clock signal RXC by １ ／. Further, for example, a NAND gate provided at the preceding stage of the first flip-flop determines that the leading 3 bits of the received serial data RSD and the corresponding 3 bits of the COMMA code match, and a NAND gate provided at the subsequent stage determines Is determined to be at a high level, and that the next two bits of the received serial data RSD coincide with the corresponding two bits of the COMMA code. The specific configuration of the code detection circuit CDDT is not restricted by the present embodiment, and the types of flip-flops and logic gates constituting the code detection circuit CDDT can be arbitrarily selected.

In FIGS. 4 and 5, the frequency and waveform of the received serial data RSD and each clock signal and their absolute levels and time relationships do not affect the gist of the present invention. Further, in this embodiment, the code detection signal COMD is set to the valid level, that is, the high level in the cycle B4 four cycles after the cycle A9 corresponding to the last bit of the COMMA code. Cycle C0
It may be set to a high level for example.

In the above description, mainly the case where the invention made by the present inventor is applied to a code detection circuit constituting a transmission / reception macrocell, which is a field of application, and a high-speed communication LSI and a communication system including the same is described. Although explained, it is not limited to it,
For example, the present invention can be applied to a single code detection circuit or various communication systems including a similar code detection circuit. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a code detection circuit for detecting a specific code from a received signal transmitted at least at a high rate, and an apparatus or system including the same.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a code detection circuit constituting a transmission / reception macro cell or the like of a communication LSI conforming to the Fiber Channel standard operates in accordance with a reception clock signal, and a predetermined bit immediately before input data serially input in synchronization with the reception clock signal is detected. A flip-flop whose output signal is selectively set to a valid level when it matches the corresponding bit of the code, and a flip-flop in which a predetermined bit at the head of the input data matches the corresponding bit of the code, or Of the input data is set to a valid level and, for example, a two-input logic gate for transmitting to a subsequent flip-flop by identifying that the next one bit of the input data coincides with the corresponding bit of the code, for example. The input data that is serially input at a high rate can be configured by alternately coupling in series. Is compared one bit at a time with the corresponding bit of the code to be detected, and the result is held by a flip-flop and sequentially transmitted to determine within one cycle that the input data matches the code. Can be. As a result, it is possible to speed up the operation of determining a code such as a header bytecode by the code detection circuit, and thereby, a transmission / reception macrocell including the code detection circuit and a high-speed communication LSI including the same are provided.
And the speed of a communication system and the like including the same can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a transmission / reception macro cell including a code detection circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of a serial-parallel conversion circuit included in the transmission / reception macrocell of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a code detection circuit included in the transmission / reception macro cell of FIG. 1;

FIG. 4 is a signal waveform diagram showing one embodiment of the code detection circuit of FIG. 3;

FIG. 5 is a signal waveform diagram showing one embodiment of the transmission / reception macro cell of FIG. 1;

FIG. 6 is a circuit diagram showing an example of a code detection circuit developed by the present inventors prior to the present invention.

[Explanation of symbols]

TRMC: Transmission / reception macro cell, PD: Protocol device, TM: Transmission circuit, XOSC: Crystal oscillation circuit, IB: Input buffer, PLLR: Receiving PLL
(Phase-locked loop) circuit, FD ... frequency divider circuit,
CDDT code detection circuit, S / P serial-parallel conversion circuit, PLLT transmission PLL circuit, P / S parallel-serial conversion circuit, OB output buffer. + DIN, -DIN ...
... input data, RXC ... receive clock signal, RSD ...
... Received serial data, RAB ... Reversed receive byte alignment signal, COMD ... Code detection signal, RXD0-R
XD9: reception data, RBC0 to RBC1, reception byte clock signal, TBC: transmission byte clock signal, TXD0 to TXD9: transmission data, TXC: transmission clock signal, TSD: transmission serial data, + D
OUT, -DOUT... Output data. FF1 to FF71
... flip-flops, V1 to V58 ... inverters,
NA1 to NA11 NAND gate, NO1 NOR gate.

Claims (5)

[Claims] The present invention operates in accordance with a clock signal or a frequency-divided signal thereof, and a predetermined bit immediately before input data serially input in synchronization with the clock signal coincides with a corresponding bit of a code to be detected. When the output signal of the flip-flop is selectively set to a valid level, the first predetermined bit of the input data matches the corresponding bit of the code, or the output signal of the preceding flip-flop is set to a valid level. And a logic gate for identifying that the next predetermined bit of the input data matches the corresponding bit of the code and transmitting the same to the subsequent flip-flop is sequentially and alternately connected in series. Code detection circuit. 2. The flip-flop according to claim 1, wherein each of the flip-flops operates in accordance with the clock signal, and each of the logic gates is configured around a two-input substantial AND circuit. A code detection circuit characterized by the following. 3. The code detection circuit according to claim 1, wherein the code detection circuit constitutes a transmission / reception macrocell of a communication LSI compliant with a Fiber Channel standard. 4. The transmission / reception macrocell according to claim 3, wherein the input data constitutes a byte by using a predetermined bit thereof, and the transmission / reception macrocell includes a serial / parallel conversion circuit for performing a serial / parallel conversion of the input data in the byte unit. Wherein the code includes a header byte code for byte alignment. 5. The code detection circuit according to claim 1, wherein the communication LSI is configured by using a CMOS circuit as a basic element.