JPH11162874A - Ohmic joint electrode and semiconductor device using the same - Google Patents
Ohmic joint electrode and semiconductor device using the sameInfo
- Publication number
- JPH11162874A JPH11162874A JP34716297A JP34716297A JPH11162874A JP H11162874 A JPH11162874 A JP H11162874A JP 34716297 A JP34716297 A JP 34716297A JP 34716297 A JP34716297 A JP 34716297A JP H11162874 A JPH11162874 A JP H11162874A
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- Prior art keywords
- oxide film
- silicon
- silicon substrate
- sub
- thickness
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はオーム性接合電極及びこ
れを用いた半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ohmic junction electrode and a semiconductor device using the same.
【０００２】[0002]
【従来の技術】シリコン電子デバイスを作る上で金属半
導体接合は重要な要素である。この接合には、整流性を
示すショットキー接合、他は整流性のないオーム性接合
の２つがある。ｎ型シリコン基板と金属を接触させて良
好な低接触抵抗を示すオーム性接合電極を形成するに
は、理論上、シリコン基板の不純物濃度を１０20ｃｍ-3
以上にする必要がある。実用的には、シリコン基板の不
純物濃度が１０19から１０20ｃｍ-3でオーム性接合を作
っている。シリコンに不純物を多量に導入するために、
イオン注入・熱処理法や不純物デポジション・熱拡散法
などの方法が使われてきた。2. Description of the Related Art Metal-semiconductor junctions are an important factor in making silicon electronic devices. This junction includes a Schottky junction exhibiting rectification and an ohmic junction having no rectification otherwise. In order to form an ohmic junction electrode exhibiting good low contact resistance by bringing a metal into contact with an n-type silicon substrate, theoretically, the impurity concentration of the silicon substrate should be 10 20 cm −3.
It is necessary to do above. Practically, an ohmic junction is formed when the impurity concentration of the silicon substrate is 10 19 to 10 20 cm -3 . In order to introduce a large amount of impurities into silicon,
Methods such as ion implantation and heat treatment, and impurity deposition and thermal diffusion have been used.
【０００３】最近のシリコンウェーハの大口径化に伴
い、ウェーハの厚さは厚くなっている。縦型構造のパワ
ーデバイスにおいては、ウェーハの厚さが厚くなること
は、オ （２） ン抵抗の上昇を引き起こすことになるので、このオン抵
抗の上昇を抑えるためにウェーハ表側のデバイスを作製
した後、組み立て前にウェーハを裏側から削って薄くす
る。この裏側を薄くした後、裏側にオーム性接合電極を
作製する。しかしながら、このときシリコン基板の不純
物濃度は、１０20ｃｍ-3よりも低いことが多い。表側に
デバイスがすでにできており、Ａ１などの金属配線がな
されているため、高温熱処理が困難であり、イオン注入
・熱処理法や不純物デポジション・熱拡散法を使って意
識的に不純物をシリコン基板に導入することはできな
い。又、特開平７−３０７３０６号に示すように半導体
基板表面に電荷を内存する薄膜を設けてオーム性電極を
形成することも提案されている。[0003] With the recent increase in diameter of silicon wafers, the thickness of the wafers is increasing. In a power device with a vertical structure, an increase in the thickness of the wafer causes an increase in the on-resistance. Therefore, a device on the front side of the wafer was manufactured to suppress the increase in the on-resistance. Thereafter, the wafer is shaved from the back side to reduce the thickness before assembling. After thinning the back side, an ohmic junction electrode is formed on the back side. However, at this time, the impurity concentration of the silicon substrate is often lower than 10 20 cm −3 . The device has already been formed on the front side, and metal wiring such as A1 has been made, so high-temperature heat treatment is difficult, and impurities are intentionally added to the silicon substrate by ion implantation / heat treatment or impurity deposition / thermal diffusion. Can not be introduced. It has also been proposed to form an ohmic electrode by providing a thin film containing electric charges on the surface of a semiconductor substrate as shown in Japanese Patent Application Laid-Open No. 7-307306.
【０００４】[0004]
【発明が解決しようとする課題】本発明はこのような問
題に対して、たとえシリコン基板の不純物濃度が１０20
ｃｍ-3よりも低くても良好な低接触抵抗を示すオーム性
接合を提供するものである。通常、シリコン基板の不純
物濃度が低いとき、その上に金属膜を堆積させると、金
属とシリコン基板の間でショットキー接触となる。この
ような場合でも、金属とシリコン基板の間にシリコン酸
化膜を介することで、良好な低接触抵抗を示すオーム性
接合を得る。The present invention solves such a problem even if the impurity concentration of the silicon substrate is 10 20
It provides an ohmic junction exhibiting good low contact resistance even if it is lower than cm −3 . Usually, when the impurity concentration of the silicon substrate is low, when a metal film is deposited thereon, Schottky contact occurs between the metal and the silicon substrate. Even in such a case, an ohmic junction exhibiting good low contact resistance can be obtained by interposing a silicon oxide film between the metal and the silicon substrate.
【０００５】[0005]
【課題を解決するための手段】本発明は、シリコン基板
とオーム接合用金属との間にシリコンサブ酸化膜［Ｓｉ
Ｏｘ（ｘ＝０．５，１．０，１．５）］を介在せしめ且
つ前記酸化膜の厚さを０．３ｎｍ〜２．２５ｎｍとした
ことを特徴とする。According to the present invention, a silicon sub-oxide film [Si] is formed between a silicon substrate and an ohmic metal.
Ox (x = 0.5, 1.0, 1.5)] and the oxide film has a thickness of 0.3 nm to 2.25 nm.
【０００６】シリコン基板を熱酸化法やプラズマ酸化法
で酸化させると、２酸化シリコン（ＳｉＯ2）がシリコ
ン基板上には生成される。この２酸化シリコンとシリコ
ン基板の界面には、２酸化シリコン（ＳｉＯ2）ではな
く、サブシリコン酸化膜［ＳｉＯｘ（ｘ＝０．５，１．
０，１．５）］が形成される。このサブシリコン酸化膜
の厚さは界面から２ｎｍ程度である。本発明の電極構造
のシリコン酸化膜とは （３） このサブ酸化膜［ＳｉＯｘ（ｘ＝０．５，１．０，１．
５）］のことである。金属膜とサブシリコン酸化膜とを
接触させることによって、良好で低接触抵抗を示すオー
ム性接合が得られる。サブシリコン酸化膜の化学的な活
性さによって、本発明の効果が得られるものと思われる
が、詳細な理由は明確ではない。２酸化シリコン層と金
属膜を接触させると、効果はまったくなくなる。When a silicon substrate is oxidized by a thermal oxidation method or a plasma oxidation method, silicon dioxide (SiO 2) is generated on the silicon substrate. At the interface between the silicon dioxide and the silicon substrate, not a silicon dioxide (SiO2) but a sub-silicon oxide film [SiOx (x = 0.5, 1..
0, 1.5)] is formed. The thickness of this sub silicon oxide film is about 2 nm from the interface. What is the silicon oxide film having the electrode structure of the present invention? (3) This sub-oxide film [SiOx (x = 0.5, 1.0, 1..
5)]. By contacting the metal film with the sub-silicon oxide film, an ohmic junction exhibiting good and low contact resistance can be obtained. It is considered that the effect of the present invention can be obtained by the chemical activity of the sub-silicon oxide film, but the detailed reason is not clear. When the silicon dioxide layer is brought into contact with the metal film, the effect is completely lost.
【０００７】[0007]
【実施例】図１は本発明の一実施例を示す断面図で図中
１はシリコン基板、２はシリコンサブ酸化膜、３は電極
金属である。図２は本発明の酸化膜の厚さの有効性を調
べるためのデバイス構造を示す。使用したシリコン基板
は、抵抗率が２ｍΩｃｍ（不純物濃度：８×１０19ｃｍ
-3）のｎ+シリコン基板６に、抵抗率が０．５Ωｃｍ
（不純物濃度：１０16ｃｍ-3）のシリコンエピタクシャ
ル層５を５μｍ成長させたものを使用した。このエピタ
クシャル面はミラーポリッシュ加工されており、表面の
ひずみは小さい。1 is a sectional view showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a silicon substrate, 2 denotes a silicon sub-oxide film, and 3 denotes an electrode metal. FIG. 2 shows a device structure for examining the effectiveness of the oxide film thickness of the present invention. The silicon substrate used has a resistivity of 2 mΩcm (impurity concentration: 8 × 10 19 cm)
-3 ) The resistivity of the n + silicon substrate 6 is 0.5 Ωcm.
The silicon epitaxial layer 5 (impurity concentration: 10 16 cm −3 ) grown to 5 μm was used. This epitaxial surface is mirror polished, and the surface distortion is small.
【０００８】図２の構造を作製するための製造プロセス
は、まず、シリコン基板を希沸酸で１分間洗浄した後、
ドライ酸化法を用いて８００℃、３０分間酸化させた。
酸化膜厚は約３ｎｍである。次に、その酸化膜の厚さを
変えるために希沸酸（ＨＦ：Ｈ2Ｏ＝１：１００）液中
に一定の時間だけ浸漬させた。この希沸酸で上記３ｎｍ
の酸化膜を完全にエッチングするには、１００秒の時間
がかかった。さらに、上部電極４を形成するために、シ
リコンエピタクシャル層５の上にチタン膜をスパッタ法
で５００ｎｍの厚さに堆積した後、ホトリソグラフィ技
術を使って図２に示すように０．９ｍｍ角にパターン化
した。チタンの化学エッチングには希沸酸を使用した。
エッチング時間は２．５分間である。ホトレジストは、
沸騰硝酸を用いて除去した。最後に、シリコン基板の裏
側にチタンを１００ｎｍ、ニッケルを５００ｎｍ、銀を
１００ｎｍ真空蒸着し、下部電極７を形成した。下部電
極７はオーム性接合電極である。The manufacturing process for fabricating the structure of FIG. 2 is as follows.
Oxidation was performed at 800 ° C. for 30 minutes using a dry oxidation method.
The oxide film thickness is about 3 nm. Next, in order to change the thickness of the oxide film, it was immersed in a dilute hydrofluoric acid (HF: H 2 O = 1: 100) solution for a certain period of time. The above-mentioned 3 nm
It took 100 seconds to completely etch the oxide film. Further, in order to form the upper electrode 4, a titanium film is deposited on the silicon epitaxial layer 5 to a thickness of 500 nm by a sputtering method, and then, as shown in FIG. Patterned. Dilute hydrofluoric acid was used for chemical etching of titanium.
The etching time is 2.5 minutes. Photoresist
Removed using boiling nitric acid. Finally, 100 nm of titanium, 500 nm of nickel, and 100 nm of silver were vacuum-deposited on the back side of the silicon substrate to form the lower electrode 7. The lower electrode 7 is an ohmic junction electrode.
【０００９】（４） 図３は各ＨＦ浸漬時間に対する評価デバイス（図２）の
電流−電圧特性を示すもので、図２において電極４をプ
ラス（＋）、電極７をマイナス（−）にした時を第一象
限に示し（順方向特性）、又極性を逆にした時を第３象
限に示した（逆方向特性）ものである。ＨＦ浸漬しない
時（酸化膜の厚さ３ｎｍ）図中特性Ａに示すように順方
向、逆方向共、電流は全く流れない。ＨＦ浸漬時間を増
加するのに伴って電流は両方向共流れ始め酸化膜が厚さ
１．５ｎｍで（浸漬時間５０秒）で特性Ｂに示すオーミ
ック特性が得られている。更に浸漬時間を増し約１００
秒で酸化膜はなくなり特性Ｃに示す整流特性（ショット
キー特性）になった。(4) FIG. 3 shows the current-voltage characteristics of the evaluation device (FIG. 2) with respect to each HF immersion time. In FIG. 2, the electrode 4 is plus (+) and the electrode 7 is minus (-). The time is shown in the first quadrant (forward characteristic), and the time when the polarity is reversed is shown in the third quadrant (reverse characteristic). When HF is not immersed (the thickness of the oxide film is 3 nm), no current flows at all in the forward and reverse directions as shown by the characteristic A in the figure. As the HF immersion time increases, the current starts to flow in both directions, and the oxide film has a thickness of 1.5 nm (the immersion time is 50 seconds), and the ohmic characteristics shown in the characteristic B are obtained. Further increase the immersion time to about 100
In seconds, the oxide film disappeared, and the rectification characteristics (Schottky characteristics) shown in Characteristic C were obtained.
【００１０】図４は図３の電流−電圧特性から抵触抵抗
の変化を示す値（ΔＲ）のＨＦ浸漬時間依存性を示す特
性図で横軸は浸漬時間Ｓ（秒）、縦軸に変化値ΔＲ（ｍ
Ωｃｍ2）を示す。なお、ΔＲは酸化膜を介さない従来
デバイスの抵抗値（図３Ｃ）を基準に算出した。又、こ
の時の抵抗値は第１象限の特性から求めた。この方法に
より接触抵抗以外の抵抗成分は相殺され、接触抵抗の変
化分のみ得られる。ΔＲの値がマイナス（負）であるこ
とは従来デバイスより接触抵抗が減少していることを意
味する。このマイナス領域は図４から明らかなように浸
漬時間で２５秒〜９０秒の範囲即ち残余の酸化膜の厚さ
２．２５ｎｍ〜０．３ｎｍに相当する。FIG. 4 is a characteristic diagram showing the HF immersion time dependency of the value (ΔR) indicating the change in the contact resistance from the current-voltage characteristics in FIG. 3, where the horizontal axis indicates the immersion time S (second) and the vertical axis indicates the change value. ΔR (m
Ωcm 2 ). Note that ΔR was calculated based on the resistance value of a conventional device without an oxide film (FIG. 3C). The resistance value at this time was obtained from the characteristics of the first quadrant. With this method, the resistance components other than the contact resistance are canceled, and only the change in the contact resistance is obtained. If the value of ΔR is minus (negative), it means that the contact resistance is smaller than that of the conventional device. As is apparent from FIG. 4, this minus region corresponds to a dipping time in the range of 25 seconds to 90 seconds, that is, the remaining oxide film thickness of 2.25 nm to 0.3 nm.
【００１１】図５は酸化法をＯ2プラズマ照射法および
基板を２ｍΩｃｍにしたとき、接触抵抗が改善されるか
どうかを調べるためのデバイス構造を示す。使用したシ
リコン基板は、抵抗率が２ｍΩｃｍ（不純物濃度：８×
１０19ｃｍ-3）のｎ+シリコン基板６を使用した。この
構造を作製するため、まず、シリコン基板を希沸酸で１
分間洗浄した後、マイクロ波プラズマ照射装置で酸素プ
ラズマをシリコンに照射させた。すなわち、シリコン基
板の表側のみに酸素プラズマを照射させ、酸化させた。
プラズマパワーを１０００Ｗ、酸素圧を０．５Ｔｏｒ
ｒ、照射時間を２分とした。このときの酸化膜の厚さは
２．５ｎｍであった。次に、その酸化膜の厚さを変える
ために希沸酸（ＨＦ：Ｈ2Ｏ＝１：１００）液中に一定
時間だけ浸漬させ、さらに、上部電極４を形成するため
に、シリコンの上にチタン膜をスパ （５） ッタ法で５００ｎｍの厚さに堆積した後、ホトリソグラ
フィ技術を使って０．９ｍｍ角にパターン化した。チタ
ンの化学エッチングには希沸酸を使用した。エッチング
時間は２．５分間である。ホトレジストは、沸騰硝酸を
用いて除去した。最後にシリコン基板の裏側にチタンを
１００ｎｍ、ニッケルを５００ｎｍ、銀を１００ｎｍ真
空蒸着し、下部電極７を形成した。下部電極７はオーム
性接合電極である。FIG. 5 shows a device structure for examining whether the contact resistance is improved when the oxidation method is O 2 plasma irradiation and the substrate is 2 mΩcm. The silicon substrate used had a resistivity of 2 mΩcm (impurity concentration: 8 ×
An n + silicon substrate 6 of 10 19 cm −3 ) was used. To fabricate this structure, a silicon substrate is first diluted with dilute hydrofluoric acid.
After washing for 1 minute, the silicon was irradiated with oxygen plasma using a microwave plasma irradiation apparatus. That is, only the front side of the silicon substrate was irradiated with oxygen plasma to be oxidized.
Plasma power 1000 W, oxygen pressure 0.5 Torr
r, the irradiation time was 2 minutes. At this time, the thickness of the oxide film was 2.5 nm. Next, it is immersed in a dilute hydrofluoric acid (HF: H 2 O = 1: 100) solution for a certain period of time to change the thickness of the oxide film. After a titanium film was deposited to a thickness of 500 nm by a spatula method, a pattern of 0.9 mm square was formed by photolithography. Dilute hydrofluoric acid was used for chemical etching of titanium. The etching time is 2.5 minutes. The photoresist was removed using boiling nitric acid. Finally, 100 nm of titanium, 500 nm of nickel, and 100 nm of silver were vacuum-deposited on the back side of the silicon substrate to form a lower electrode 7. The lower electrode 7 is an ohmic junction electrode.
【００１２】図６は酸化膜厚に対するデバイスの（図
５）電流−電圧特性を示したものである。この特性は、
図５において上部電極４をプラス、下部電極７をマイナ
スにしたときと第１象限に描き、逆の場合を第３象限に
描いている。ＨＦ浸漬をしないとき（酸化膜厚：２．５
ｎｍ）、電流は順、逆の両方向とも流れていない
（Ａ）。ＨＦ浸漬を３０秒行って、酸化膜の厚さを、
１．６ｎｍとしたとき、電流−電圧特性Ｂが得られた。
さらに、浸漬時間を９０秒行って酸化膜を完全にエッチ
ングすると電流−電圧特性はＣになった。図６から明ら
かなように、酸化膜を１．６ｎｍ残したときに得られた
特性Ｂは酸化膜のないときの特性Ｃよりも抵抗は低減し
ている。特性Ｃにおいてもオーミック特性が得られてい
るのは抵抗率が２ｍΩｃｍの基板を使用したためであ
る。結果として、酸化膜を介した電極構造とすることで
より低い接触抵抗を持ったオーミック特性が得られるこ
とがわかった。この実施例では、上部電極４の金属膜を
チタンとしたが、チタン以外の金属膜たとえばクロムに
対しても同様に本発明の効果を確認した。FIG. 6 shows the current-voltage characteristics (FIG. 5) of the device with respect to the oxide film thickness. This property is
In FIG. 5, when the upper electrode 4 is plus and the lower electrode 7 is minus, it is drawn in the first quadrant, and the opposite case is drawn in the third quadrant. When not immersing in HF (oxide film thickness: 2.5
nm), and no current flows in both the forward and reverse directions (A). Perform HF immersion for 30 seconds to reduce the thickness of the oxide film.
When the thickness was set to 1.6 nm, current-voltage characteristics B were obtained.
Further, when the immersion time was 90 seconds and the oxide film was completely etched, the current-voltage characteristics became C. As is clear from FIG. 6, the resistance of the characteristic B obtained when the oxide film remains 1.6 nm is lower than that of the characteristic C without the oxide film. In the characteristic C, the ohmic characteristic is also obtained because a substrate having a resistivity of 2 mΩcm was used. As a result, it was found that ohmic characteristics with lower contact resistance can be obtained by using an electrode structure with an oxide film interposed. In this example, the metal film of the upper electrode 4 was titanium, but the effect of the present invention was similarly confirmed for a metal film other than titanium, for example, chromium.
【００１３】図７は本発明の電極構造にパワーＭＯＳＦ
ＥＴ（６０Ｖ、４０Ａ級）のドレイン電極に適用したＭ
ＯＳＦＥＴの出力特性図で図中特性Ｂは従来例（酸化膜
なし）特性Ａは実施例を示す。従来例のドレイン電極構
造の出力特性Ｂのオン抵抗は、１９．０４ｍΩであるの
に対して、酸化膜を介したドレイン電極構造の出力特性
Ａのオン抵抗は、１６．３１ｍΩとなり、酸化膜を介さ
ない電極構造の出力特性のオン抵抗よりも約１４．３％
低下した。なお、ＭＯＳＦＥＴはアンチモン添加した抵
抗率が１７ｍΩｃｍ（不純物濃度約１０18ｃｍ-3）シリ
コン基板にソー （６） ス領域、ドレイン領域、ゲート等の能動領域を形成した
後、ウェーハの裏側を削って薄くし、その表面に厚さ
１．２ｎｍのシリコン酸化膜をシリコン基板の裏側に形
成した。その後、チタンを１００ｎｍの厚さだけ真空蒸
着し、さらに引き続きニッケルを５００ｎｍ、銀を１０
０ｎｍの厚さだけ真空蒸着しドレイン電極とした。FIG. 7 shows a power MOSF in an electrode structure according to the present invention.
M applied to the drain electrode of ET (60V, 40A class)
In the output characteristic diagram of the OSFET, the characteristic B in the figure is a conventional example (without an oxide film), and the characteristic A is an example. The on-resistance of the output characteristic B of the conventional drain electrode structure is 19.04 mΩ, whereas the on-resistance of the output characteristic A of the drain electrode structure via the oxide film is 16.31 mΩ. Approximately 14.3% of the ON resistance of the output characteristics of the electrode structure that does not pass through
Dropped. In addition, after forming an active region such as a source region, a drain region, and a gate on a silicon substrate having a resistivity of 17 mΩcm (impurity concentration of about 10 18 cm −3 ) doped with antimony, the back side of the wafer is shaved. A thin silicon oxide film having a thickness of 1.2 nm was formed on the back surface of the silicon substrate. Thereafter, titanium is vacuum-deposited to a thickness of 100 nm, nickel is further deposited at 500 nm, and silver is deposited at 10 nm.
Vacuum evaporation was performed to a thickness of 0 nm to form a drain electrode.
【００１４】[0014]
【発明の効果】本発明によれば、０．３〜２．２５ｎｍ
のシリコンサブ酸化膜を金属膜とシリコン基板の間には
さむことにより、良好なオーミック接触電極が得られ、
高性能デバイスの開発に極めて有効である。According to the present invention, 0.3 to 2.25 nm
By sandwiching the silicon sub-oxide film between the metal film and the silicon substrate, a good ohmic contact electrode is obtained,
It is extremely effective for developing high performance devices.
【図１】本発明の実施例を示す断面図FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本発明の有効性を評価するデバイスの構造図FIG. 2 is a structural diagram of a device for evaluating the effectiveness of the present invention.
【図３】評価デバイスの電圧−電流特性図FIG. 3 is a voltage-current characteristic diagram of an evaluation device.
【図４】ＨＦ浸漬時間依存性を示す特性図FIG. 4 is a characteristic diagram showing HF immersion time dependency.
【図５】他の評価デバイスの電流−電圧特性図FIG. 5 is a current-voltage characteristic diagram of another evaluation device.
【図６】評価デバイスの電流−電圧特性図FIG. 6 is a current-voltage characteristic diagram of an evaluation device.
【図７】本発明をＭＯＳＦＥＴに適用した出力特性図FIG. 7 is an output characteristic diagram in which the present invention is applied to a MOSFET.
【符号の説明】 １，６ シリコン基板 ２ シリコンサブ酸化膜 （７） ３ 電極金属 ４，７ 電極 ５ エビタキシアル層[Description of Signs] 1,6 Silicon substrate 2 Silicon sub-oxide film (7) 3 Electrode metal 4,7 Electrode 5 Epitaxial layer
Claims (3)
にシリコンサブ酸化膜［ＳｉＯｘ（ｘ＝０．５，１．
０，１．５）］を介在せしめ且つ前記酸化膜の厚さを
０．３ｎｍ〜２．２５ｎｍとしたことを特徴とするオー
ム性接合電極。1. A silicon sub-oxide film [SiOx (x = 0.5, 1....) Between a silicon substrate and an ohmic bonding metal.
0,1.5)], and the thickness of the oxide film is 0.3 nm to 2.25 nm.
不純物濃度を１０16ｃｍ-3乃至１０20ｃｍ-3としたこと
を特徴とする請求項１のオーム性接合電極。2. The ohmic junction electrode according to claim 1, wherein an n-type silicon substrate is used and the impurity concentration of said substrate is set to 10 16 cm −3 to 10 20 cm −3 .
シリコン基板の表面もしくは裏面にシリコンサブ酸化膜
［ＳｉＯｘ（ｘ＝０．５，１．０，１．５）］を介して
電極金属を接合したことを特徴とする半導体装置。3. An active region is formed on a silicon substrate, and an electrode metal is formed on the front or back surface of the silicon substrate via a silicon sub-oxide film [SiOx (x = 0.5, 1.0, 1.5)]. A semiconductor device characterized by being joined.
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