JPH11161778A - Digital picture processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by controlling power supply so that the power is not supplied to a memory element which is discriminated to be not used. SOLUTION: A picture data area arithmetic circuit 5 calculates a valid picture area based on a parameter value which is set in respective registers 7, 9 and 11. The picture data area arithmetic circuit 5 transmits which bank 1 is not used to a memory control circuit 3. The memory control circuit 3 receiving the transmission of the non-use of the memory bank 1 controls to stop a memory refresh operation on the memory bank 1. The picture data area arithmetic circuit 5 discriminates the memory bank 1 which is not used at all based on a decided data holding memory area and transmits the discriminated result to a power control circuit 13. For controlling power, power supply to the memory element of the memory bank which is not used at all is stopped by the power control circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing system for storing various kinds of image processing by storing image data in a frame memory composed of a plurality of memory elements, and more particularly to sufficiently reducing power consumption. The present invention relates to a digital image processing system capable of performing the following.

[0002]

2. Description of the Related Art Generally, in a digital image processing system for storing image data in a frame memory composed of a plurality of memory elements and performing various image processing, a required frame is required in accordance with an improvement in resolution, full color, and the like. The memory capacity is increasing more and more. For this reason, a technique for reducing power consumption is increasingly required. As one means for coping with this, there is a method of selecting a memory element that performs a refresh operation for retaining data according to the size of an image stored in a frame memory (Japanese Patent Laid-Open No. 4-153).
No. 984).

[0003]

However, when a large amount of memory is mounted, there is a problem that the power consumption cannot be sufficiently reduced only by performing the refresh control according to the image size. In addition, the above prior art (Japanese Unexamined Patent Application Publication No.
Japanese Patent Application Publication No. -153984) is intended only to reduce the power consumption of the memory, and does not consider the power consumption of the memory control circuit, so that a sufficient reduction in power consumption cannot be achieved. The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a digital image processing system capable of sufficiently reducing power consumption.

[0004]

According to one aspect of the present invention, there is provided a digital image processing apparatus for storing image data in a frame memory comprising a plurality of memory elements and performing various image processing. In the processing system, a memory size for storing the image data is calculated, and an image data area calculation unit for determining an unused memory element, and a power supply control unit for controlling power supply to the memory element Wherein the power supply control means performs control so as to stop power supply to the memory element determined not to be used by the image data area calculation means. According to a second aspect of the present invention, the power supply control means controls a supply of power and a power supply control circuit connected to the power supply control circuit for selecting whether to perform power supply control of the memory element. And a register. According to the first and second aspects of the present invention, it is possible to control power supply to unused memory elements, thereby reducing power consumption. According to a third aspect of the present invention, the digital image processing system supplies a plurality of memory control circuits for performing memory control on each of the plurality of memory elements, and individually supplies a clock to the memory control circuit. A clock control circuit, wherein the clock control circuit performs control so as to stop clock output to a memory control circuit that performs memory control of a memory element determined not to be used by the image data area calculation unit. It is characterized by performing. According to the third aspect of the invention, in addition to controlling the power supply to the unused memory elements, the clock supply to the memory control circuit of the unused memory elements is controlled, so that further power consumption is achieved. Can be reduced. According to a fourth aspect of the present invention, the digital image processing system supplies a plurality of memory control circuits for performing memory control on each of the plurality of memory elements, and individually supplies a clock to the memory control circuit. A clock control circuit, wherein the power supply control means stops power supply to the memory element determined not to be used by the image data area calculation means, and controls the memory element determined to be unused. It is characterized in that control is performed such that power supply to a memory control circuit that performs memory control is also stopped. According to the fourth aspect of the present invention, not only the unused memory elements but also the power supply to the memory control circuit are controlled, so that the power consumption is further reduced.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a digital image processing system embodying the present invention. As shown in FIG. 1, this digital image processing system has first to fourth memory banks (frame memories) 1a to 1d, and the first to fourth memory banks 1a to 1d First to fourth memory control circuits 3a to 3d for performing memory control are connected to the respective circuits. That is, one bank is composed of, for example, 16 elements of 16 Mbit DRAM, and a memory control circuit is prepared for each memory bank, and RAS (RAS0-RAS3), CAS (CAS0)
To CAS3) are connected in units of memory banks.
Further, an image data area operation circuit 5 for calculating a memory size for storing an image is connected to each of the memory control circuits 3a to 3d. , Y size register 9 and pixel format register 11 are connected. The X size register 7 stores the number of pixels of the image area in the main scanning direction, the Y size register 9 stores the number of pixels of the image area in the sub scanning direction, and the pixel format register 11 stores Pixel information (gradation, monochrome / color, etc.) is stored. A power control circuit 13 for controlling power supply is provided in each of the memory banks 1a to 1d, each of the memory control circuits 3a to 3d, and the image data area arithmetic circuit 5. Is connected to a power control register 15 for selecting whether to perform power control of the memory by software.

Next, the operation of the digital image processing system will be described with reference to FIG. FIG.
4 is an operation flowchart of the digital image processing system shown in FIG. First, in step 101 of FIG. 2, each parameter value (the number of pixels in the main scanning direction in the image area, the number of pixels in the sub-scanning direction in the image area, Pixel information (gradation, monochrome / color, etc.) is set, and in step 103, each of the registers 7, 9,
The effective image area is calculated by the image data area calculation circuit 5 based on the parameter value set to “11”. That is, the image data area calculation circuit 5 calculates a memory size necessary for developing an image from the respective parameter values, and sets a data holding memory area (first to fourth memory banks 1a to 1d) to be used. Is determined, and the determination result is transmitted to the first to fourth memory control circuits 3a to 3d, and based on the determination, the first to fourth memory control circuits 3a to 3d are determined.
Performs memory control. Here, the image data area operation circuit 5 transmits to the memory control circuit 3 which memory bank 1 is unused. Therefore,
The memory control circuit 3 receiving the unused transmission of the memory bank 1 performs control so as to stop the memory refresh operation for the memory bank 1.

Next, in step 105, the image data area calculation circuit 5 determines a memory bank 1 that is not used at all based on the determined data holding memory area, and sends the determination result to the power supply control circuit 13. introduce. Then, in step 107, it is determined whether or not to perform power control.
7; YES), the power supply control circuit 13 stops the power supply to the memory elements of the memory banks that are not used at all (step 109). That is, the power supply control circuit 13 can control the power supply to the memory element for each memory bank. In this case, for example, the image size is relatively small, and the result calculated by the image data area calculation circuit 5 is used. , Third and fourth memory banks 1c, 1d
When these memory elements become unused, the power supply to these memory elements 1c and 1d is stopped according to the setting of the power control register 15. Here, when a memory bank is constituted by 16 memory elements, power supply to 32 memory elements is stopped. As described above, according to the first embodiment, power consumption can be reduced by enabling control of power supply to unused memory elements.

Next, a second embodiment of the digital image processing system according to the present invention will be described. FIG. 3 is a schematic configuration diagram of a digital image processing system according to a second embodiment of the present invention. The second embodiment not only stops the power supply to the unused memory elements to realize low power consumption, but also stops the clock output to the memory control circuit, thereby further reducing the current consumption. It is something to do. For this reason, in the second embodiment, as shown in FIG. 3, the first embodiment in the first embodiment shown in FIG.
To the fourth memory control circuits 3a to 3d, the image data area calculation circuit 5, and the power supply control circuit 13,
A clock control circuit 17 for individually supplying a clock to the fourth to fourth memory control circuits 3a to 3d is provided. The other configuration operation is the same as that of the first embodiment shown in FIG.

Next, the operation of the second embodiment will be described with reference to FIG. In step 201 of FIG. 4, each parameter value (the number of pixels in the main scanning direction of the image area, the number of pixels in the sub-scanning direction of the image area, the pixel information) is stored in the X size register 7, the Y size register 9, and the pixel format register 11. (Gradation, monochrome / color, etc.) are set, and in step 203, the effective image area is calculated by the image data area calculation circuit 5 based on the parameter values set in the registers 7, 9, and 11. The image data area calculation circuit 5 calculates a memory size required for developing an image from the parameter values and uses the data holding memory areas (first to first).
The fourth memory banks 1a to 1d) are determined, the determination results are transmitted to the first to fourth memory control circuits 3a to 3d, and the first to fourth memory control circuits 3
Memory control is performed by a to 3d. Also, where
The image data area calculation circuit 5 determines which memory bank 1
Is transmitted to the memory control circuit 3 as to whether or not is unused.
Therefore, the memory control circuit 3 receiving the unused transmission of the memory bank 1 performs control so as to stop the memory refresh operation for the memory bank 1.

Next, in step 205, the image data area calculation circuit 5 determines a memory bank 1 that is not used at all based on the determined data holding memory area, and determines the result of the determination by the power control circuit 13, And the clock control circuit 17. And step 2
At 07, the supply of the clock from the clock control circuit 17 to the memory control circuit 3 of the memory bank 1 determined not to be used at all is stopped. Next, in step 209, it is determined whether or not to perform power control.
When the power control is performed (YES in step 209), the power supply to the memory element of the memory bank 1 that is not used at all is stopped by the power control circuit 13 (step 211). That is, the power supply control circuit 13 can control the power supply to the memory element for each memory bank. Here, for example, the image size is relatively small,
If the memory elements of the third and fourth memory banks 1c and 1d are not used as a result of the calculation by the image data area arithmetic circuit 5, power is supplied to these memory elements according to the setting of the power control register 15. Stop. Here, when a memory bank is constituted by 16 memory elements, power supply to 32 memory elements is stopped. As described above, according to the second embodiment, in addition to controlling the power supply to the unused memory, the clock supply to the memory control circuit of the unused memory is controlled. Can be reduced.

Next, a third embodiment of the digital image processing system according to the present invention will be described. FIG. 5 is a schematic configuration diagram of a third embodiment of the digital image processing system according to the present invention. In the third embodiment, not only the unused memory elements are stopped in order to realize low power consumption, but also the power supply of the unused memory control circuit is stopped to further reduce power consumption. It is intended to be realized. Therefore, in the third embodiment,
As shown in FIG. 5, the configuration is such that the memory control circuit 3 and the power supply control circuit 13 in the second embodiment shown in FIG. 3 are connected.

Next, the operation of the third embodiment will be described with reference to FIG. In step 301 of FIG. 6, each parameter value (the number of pixels in the main scanning direction of the image area, the number of pixels in the sub scanning direction of the image area, (Gradation, monochrome / color, etc.) are set, and in step 303, the effective image area is calculated by the image data area calculation circuit 5 based on the parameter values set in the registers 7, 9, and 11. The image data area calculation circuit 5 calculates a memory size required for developing an image from the parameter values and uses the data holding memory areas (first to first).
The fourth memory banks 1a to 1d) are determined, the determination results are transmitted to the first to fourth memory control circuits 3a to 3d, and the first to fourth memory control circuits 3
Memory control is performed by a to 3d. Also, where
The image data area calculation circuit 5 determines which memory bank 1
Is transmitted to the memory control circuit 3 as to whether or not is unused.
Therefore, the memory control circuit 3 receiving the unused transmission of the memory bank 1 performs control so as to stop the memory refresh operation for the memory bank 1.

Next, in step 305, the image data area calculation circuit 5 determines a memory bank 1 that is not used at all based on the determined data holding memory area, and determines the result of the determination by using the power supply control circuit 13 and The signal is transmitted to the clock control circuit 17. And step 30
In 7, it is determined whether or not to perform the power control. If the power control is to be performed (YES in step 307), the power control circuit 13 supplies the memory element 1 of the memory bank that is not used at all and the memory control circuit 3 The power supply is stopped (step 309). That is, the power supply control circuit 13 can control the power supply to the memory element 1 and the memory control circuit 3 for each memory bank. Here, for example, if the image size is relatively small and the memory elements of the third and fourth memory banks 1c and 1d are not used as a result of calculation by the image data area arithmetic circuit 5, the power control register 15 Of the memory banks 1c and 1d and the control circuit 3
c, stop the power supply to 3d. When a memory bank is composed of 16 memory elements, 32
Power supply to the memory elements and the memory control circuits 3c and 3d is stopped. As described above, according to the third embodiment, not only the unused memory but also the power supply to the memory control circuit is controlled, so that the power consumption is further reduced.

[0014]

According to the present invention, by controlling the power supply to the unused memory elements,
Power consumption can be reduced. Further, in addition to controlling the power supply to the unused memory elements, the clock supply to the memory control circuit of the unused memory elements is controlled, so that the power consumption can be further reduced. In addition, since the power supply to the memory control circuit as well as to the unused memory element is controlled, the power consumption is further reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a digital image processing system embodying the present invention.

FIG. 2 is an operation flowchart of the digital image processing system shown in FIG. 1;

FIG. 3 shows a second embodiment of the digital image processing system according to the present invention.
It is a schematic structure figure of an embodiment.

FIG. 4 is an operation flowchart of the digital image processing system shown in FIG. 3;

FIG. 5 is a third view of the digital image processing system according to the present invention;
It is a schematic structure figure of an embodiment.

FIG. 6 is an operation flowchart of the digital image processing system shown in FIG. 5;

[Explanation of symbols]

1 ... memory bank, 3 ... memory control circuit, 5 ... image data area calculation circuit,
7, 9, 11 ... register, 13 ... power supply control circuit,
15 ... power control register, 17 ... clock control circuit,

Claims (4)

[Claims] 1. A digital image processing system for storing image data in a frame memory composed of a plurality of memory elements and performing various image processings, wherein the digital image processing system calculates a memory size for storing the image data. Image data area calculating means for determining a memory element not used, and power control means for controlling power supply to the memory element, wherein the power control means is controlled by the image data area calculating means. A digital image processing system which performs control so as to stop power supply to a memory element determined to be unused. 2. The power supply control means comprises a power supply control circuit for controlling power supply, and a power supply control register connected to the power supply control circuit for selecting whether or not to perform power supply control of the memory element. 2. The method according to claim 1, wherein
A digital image processing system according to claim 1. 3. A digital image processing system, comprising: a plurality of memory control circuits for performing memory control on each of the plurality of memory elements; and a clock control circuit for individually supplying a clock to the memory control circuit. Wherein the clock control circuit performs control so as to stop clock output to a memory control circuit that performs memory control of a memory element determined not to be used by the image data area calculation unit. The digital image processing system according to claim 1. A plurality of memory control circuits for controlling the memory of each of the plurality of memory elements, a clock control circuit for individually supplying a clock to the memory control circuit, Wherein the power supply control means stops power supply to the memory element determined not to be used by the image data area calculation means and performs memory control of the memory element determined to be unused. 2. The digital image processing system according to claim 1, wherein control is performed so as to stop power supply to the memory control circuit.