JPH1115794A - Parallel data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously input the data and to attain the real-time processing for a parallel data processor by using a processor unit output control means which temporarily stores the processing result of a block unit by switching plural buffer memories for each processing frequency of processor units. SOLUTION: A processor unit output control part 5 processes once the data inputted from every PU(processor unit) 4 and transfers the processing result to every BM(buffer memory). The part 5 notifies a buffer memory output control part 7 of the processing result by a PU status signal. The part 7 recognizes that every PU 4 proceeded to the next input data processing by the PU status signal and then switches the BMs connected to both parts 5 and 7 with no overlapping of them by a BM switching signal. Thus, a parallel processor can perform its processing with its real-time performance maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data processing apparatus, and more particularly to a parallel data processing apparatus for image signals and the like suitable for an apparatus for automatically inspecting for foreign matter and defects.

[0002]

2. Description of the Related Art A processing apparatus according to the prior art is, for example, as disclosed in Japanese Patent Application No. 63-206086 shown in FIG. It outputs a bus acquisition request to the 921 bus controller connected to the bus.

The 921 bus controller receiving this request gives the bus acquisition permission to only one CPU. The CPU to which the bus acquisition permission has been given makes read access to the main memory unit via the memory read bus.

Next, when the CPU performs write access to the main memory unit, the CPU outputs a bus acquisition request to the 922 bus controller connected to the 915 memory write bus. Upon receiving this request, the 922 bus controller gives the bus acquisition permission to only one of the CPUs that output the bus acquisition request. The permitted CPU performs access via the memory write bus. As a result, the usage rate of each bus is reduced, and the usage rate of the CPU is improved.

[0005]

However, in the processing device according to the prior art, there is no mechanism for checking the priority of a bus acquisition request from each CPU. When it is required to perform processing in real time at the same processing speed as that of the above, if the processing is performed with the number of CPUs having a small margin with respect to the required minimum number of CPUs satisfying the real-time property, each CP
Due to differences in the amount of data input to U and the content of the processing, the CPU that has started the processing later may end the processing first.

In such a case, if the data was output in the order in which the processing was completed, the CPU that took a long time
Before the output of the processing result, input data to be processed next arrives, and there is a risk that the data may be missed.

Further, if the number of CPUs is increased to avoid this, the capacity is improved more than necessary, and the economic efficiency is deteriorated. An object of the present invention is to provide a parallel data processing method and a parallel data processing method capable of realizing real-time processing for continuously inputting and processing data.

[0008]

According to the present invention, in order to achieve the above, when a transfer result of a processing result is sent from each processor unit to a buffer memory, the order of arrival of the transfer request and the processor which has issued the transfer request are determined. Parallel data processing that determines the processing result of which processor unit should be transferred to the buffer memory based on the priority of the unit and the number of times of processing, and gives transfer permission to the relevant processor unit, thereby maintaining the real-time processing and performing parallel data processing. In the device.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS For example, using a linear sensor,
When a signal detected by scanning of a stage on which a sample to be detected is scanned is processed in real time, a parallel processing CPU that performs data processing immediately reads the detected data and performs processing in parallel. At this time, each CPU cannot maintain the real-time processing unless the processing is completed before the next processing data is input.

Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing one embodiment of the present invention. As shown in FIG. 1, the parallel data processing device according to the present embodiment includes a control CPU 1 connected to 9 local buses 1 (9), and a data input that is also connected to the local bus 1 (9) and inputs a digital signal. A data storage unit 3 for storing input data, a plurality of processor units 4 connected to the local bus 1 like the control CPU for processing data,
A processing result storage unit 8 connected to the local bus 1 (9) and the local bus 2 (10) and storing a processing result;
Further, a processor unit output control unit 5 for controlling the timing of the result output of the processor unit, a plurality of buffer memories 6 for temporarily storing the processing results of the processor unit, and control of the processing result output from the buffer memory 6 to the processing result storage unit 8 And a buffer memory output control unit 7 for performing

The buffer memory output control section 7 is connected to the processing result storage section 8 by the local bus 2 (10). The processor unit output control unit 5 and the buffer memory output control unit 7 are connected to different buffer memories, respectively, and while writing the processing result from the processor unit 4 to one buffer memory, The buffer memory output control unit 7 controls so that the processing result stored in the memory can be read.

For example, as shown in FIG. 2, when each processor unit (PU) is transferring the processing result to the buffer memory 1 (BM1) via the processor unit output control unit 5, the buffer memory output control unit Reference numeral 7 is connected to the buffer memory 2 (BM2). If there is a processing result temporarily stored in the BM2, the BM is stored in the processing result storage unit 8 in parallel with the transfer of the processing result from the PU to the BM1.
Transfer the processing result of 2.

Further, the processor unit output control unit 5 processes the data inputted by all the PUs once, and transfers the processing result to the buffer memory (BM) once.
The buffer memory output control unit 7 is notified by the 1PU status signal. When the buffer memory output control unit 7 recognizes from the PU status signal that each PU has shifted to the processing of the next input data, the buffer memory output control unit 7 is connected to the processor unit output control unit 5 and the buffer memory output control unit 7 by the 12BM switching signal. The buffer memories are switched so that they do not overlap. That is, the BM1 is connected to the processor unit output control unit until each PU performs the first processing and transfers the processing result to the BM.
The BM 2 is connected to the buffer memory output control unit 7.

Next, when each PU starts the second processing,
BM2 is connected to the processor unit output control unit 5,
The BM 1 is connected to the buffer memory output control unit 7.

The flow of the buffer memory switching control will be described with reference to FIG. The buffer memory output control unit 7 monitors the PU status signal output from the processor unit output control unit 5 to check whether the results of all 301 PUs have been output. If all the PUs have finished outputting the processing results, the BM that switches the processing results temporarily and then temporarily stores the processing results checks whether the transfer of the processing results to the 302 processing result storage unit has been completed. 303BM if you have
Is switched, and if the connection has not been completed, the process waits until the transfer is completed.

When the BM is switched, the transfer of the 304 processing result from the BM connected to the buffer memory output control unit 7 is performed in parallel with the transfer of the processing result from each PU to the BM. As a result, while processing new processing data and transferring it to the BM, the processing result of the previous processing can be simultaneously transferred.

The control CPU controls which processor unit (PU) takes in and processes data input by the data input unit. Each PU starts processing when data to be processed is input, and outputs a processing result to a buffer memory for temporary storage. At this time, output arbitration is performed by the processor unit output control unit.

FIG. 4 shows the flow of the processor unit output control.
This will be described with reference to FIG. When there is a 401 transfer request of the processing result from the PU, the processor unit output control unit 5 checks the 402th processing result of the PU 4 that has made the transfer request and wants to transfer it. That is, the transfer request P
U checks whether the BM has been switched and is about to transfer the first processing result, and if it is the first processing result, it is determined that the data is to be transferred this time, and if it is the second processing result, For example, it is determined that the data is to be transferred to a different BM next time.

For example, as shown in FIG. 5, a PU status register 13 corresponding to each PU is prepared, and the initial state is set to "0".

Next, when there is a transfer request from the PU,
The value of the PU status register is ANDed, and if "1", the determination result is determined as the first processing result by the 15 determination circuit and recognized as data to be transferred. After the processing result is transferred to the BM, the value of the PU status register is rewritten to “1” by the 16 transfer inhibit signal, and when there is a second transfer request of the processing result, it is determined that the data is to be transferred next time. I do.

The buffer memory output control unit determines whether all the PUs have finished transferring the first processing result to the BM by monitoring the PU status signal 11 and switches the BM. If the PU status register is reset ("0") by the register reset signal 14 in synchronization with the switching timing, the same determination can be made from the next time.

If the processing result of the PU requested to be transferred is the data to be transferred to the BM this time,
Check whether another PU has transferred the processing result to the BM. If the other PU is not transferring, then 404 checks whether there is a transfer request from another PU, and if there is a transfer request from another PU, performs 406 priority check, 405 transfer permission is given to the PU with the highest number. This is to prevent the input data from being missed by transferring the processing result from the PU with the higher priority first.

As shown in FIG. 6, when the control CPU 1 determines which processor unit 4 should input data input by the data input unit 2 and in what order, as shown in FIG. The priorities of the PUs can be determined by assigning priorities to the PUs in the order in which the PUs are started, and by notifying in advance to the 15 determination circuits in the processor unit output control unit 5 with the priority notification signal 17.

Here, the priorities of PUs are assigned in the order of data input in order to prevent the next processing data from being missed. When all the PUs finish transferring the first processing result to the BM, the BM is switched and the transfer of the next processing result is started. The buffer memory output control unit reads the processing result from the BM in which the first processing result is written during this time, and transfers the processing result via the local bus 2 to the processing result storage unit.

In this embodiment, a dedicated transfer inhibit signal is input to the PU status register to control the transfer of the processing result of each PU, but as shown in FIG.
The transfer permission signal may be shared. In this embodiment,
Although a data storage unit that stores data input from the data input unit is provided, when processing data that is continuously input from the linear sensor is processed in real time, the data input unit does not need to pass through the data storage unit. May be transmitted directly to the PU.

Further, in this embodiment, the processing results of all PUs are transferred to a plurality of BMs for each processing count. However, as shown in FIG. 8, the processor unit output control unit 5 and the buffer memory output control unit 7 May be provided, and the processing result may be transferred to the BM 6 corresponding to each PU for each several PUs for each processing count. In this case, when the contents of each BM are transferred to the processing result storage unit 8, transfer arbitration is performed by the buffer memory selection unit 19. Here, in the arbitration in the buffer memory selection unit, similarly to the processor unit output control unit, it is determined how many times the processing result stored in each BM is the processing result, and the processing result storage unit is determined from the priority of each PU. May be selected and the processing result may be transferred.

[0027]

According to the present invention, it is possible to provide an image signal processing apparatus suitable for an apparatus for automatically inspecting for foreign matter or defects.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of a buffer memory switching control method according to the present invention.

FIG. 3 is a diagram showing an embodiment of a flow of buffer memory switching control according to the present invention.

FIG. 4 is a diagram showing an embodiment of a flow of a processor unit output control according to the present invention.

FIG. 5 is a diagram showing one embodiment of a processor unit output control method according to the present invention.

FIG. 6 is a diagram showing an embodiment of a priority determination method according to the present invention.

FIG. 7 is a diagram showing another embodiment of the present invention.

FIG. 8 is a diagram showing another embodiment of the present invention.

FIG. 9 is a diagram showing an embodiment of a processing apparatus according to the prior art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control CPU, 2 ... Data input part, 3 ... Data storage part, 4 ... Processor unit, 5 ... Processor unit output control part, 6 ... Buffer memory, 7 ... Buffer memory output control part, 8 ... Processing result storage part, 9 local bus 1, 10 local bus 2, 11 PU status signal, 12 BM switching signal, 13 PU status register, 14 register reset signal, 15 determination circuit, 16 transfer inhibition signal, 17 priority Ranking notification signal,
18: transfer permission signal, 19: buffer memory selection unit,
301 ... output the results of all PUs, 302 ... end the transfer from the BM to the processing result storage unit, 303 ... switch the BM connection, 304 ... B
M: processing result transfer start, 401: transfer request, 402: number of processing times, 403: transfer is currently in progress, 404: transfer request from another PU, 405: transfer permission, 406: high priority
911 ... CPU, 912 ... Main memory unit, 914 ... Memory
Read bus, 915 ... Memory / write bus, 916,91
7,918,919 ... Bus interface, 920 ... Cache memory, 921,922 ... Bus controller, 923 ... I / O
unit.

Claims (5)

[Claims] 1. A data input unit for inputting digital signal data in time series, a data storage unit for storing input data, a plurality of processor units for processing data in the data storage unit in parallel, and the processor unit Data processing unit, a data transmission bus, and a CPU that controls the whole, and distributes and processes the input data to each processor unit a plurality of times. A processor that has a plurality of buffer memories between the plurality of processor units and the processing result storage unit, and temporarily stores the processing results of the processor unit by switching the plurality of buffer memories for each number of times of processing of the processor unit A parallel data processing device comprising unit output control means. 2. A processor according to claim 1, wherein priorities are assigned to said plurality of processor units, and when there is a transfer request for a processing result from said plurality of processor units, a priority order of said processor unit which has issued said transfer request is determined. A priority determining unit for receiving a transfer request of a processor unit having a higher priority, and a register corresponding to the plurality of processor units for storing the number of transfers of a processing result; Recognize by the value of, and has a processing number determination unit that determines whether to transfer data from the processing number, when writing processing results from the plurality of processor units to the buffer memory, the priority determination unit Processor unit output control means for judging write permission from the judgment result of the number of processing judgment unit Parallel data processing apparatus that. 3. The parallel data processing device according to claim 2, wherein the priorities are assigned in the order of starting data processing. 4. A parallel processing system according to claim 1, further comprising a buffer memory output control means for transferring data to a processing result storage unit for a buffer memory not selected by said processor unit output control means. Data processing device. 5. The data processing device according to claim 1, wherein the data input unit is connected to the CPU, a data input unit, a data storage unit, a processor unit, and a processing result storage unit. A parallel data processing device having a local bus connected to a local bus, a processing result storage unit, and a buffer memory output control means for transmitting a processing result in the processor unit.