JPS6220041A - Asynchronous data transfer circuit for data processor - Google Patents

Abstract

PURPOSE:To minimize a required time in a memory circuit related to transfer operation and a data processing circuit by transferring data between the memory circuit and the data processing circuit through a buffer memory. CONSTITUTION:Data existing before processing stored in a memory circuit 2 is transferred first to a buffer memory 5 by the control of a DMA control circuit 3. The write address is given by the counter value of a write address counter 6. A signal WACLK is given to the write address counter 6 for every write operation, and the number of these signals is counted. The value of the write address counter 6 is inputted to an address coincidence detecting circuit 9 and is compared with the valve of a read address counter 7. If this comparison becomes dissident reception of transfer data is requested to a processing circuit 4 through a transfer end decision circuit 10. The processing circuit 4 starts the transfer operation for reception. The read address counter 7 receives a signal RACLK for every read operation from the buffer memory 5 and counts this signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device, and particularly to a data transfer device configured to transfer data between a memory circuit and a processing circuit thereof via a buffer memory circuit. Regarding circuits.

(Prior Art) Conventionally, in this type of data transfer circuit, a microprocessor that controls all operations of a data processing device directly transfers a program between a memory circuit and a processing circuit, or a DMA control circuit directly transfers a program. , data was transferred by DMA between the memory circuit and the processing circuit.

(Problems to be Solved by the Invention) In the conventional data transfer circuit described above, data is transferred directly between the memory circuit and the processing circuit, so the access time to the memory circuit and the processing time of the processing circuit are The transfer must be performed while synchronizing with the data. Therefore, during data transfer, for example, instruction fetching from the microprocessor's memory circuit is limited, or data processing operations in the processing circuit are limited, resulting in a longer overall data processing time. .

An object of the present invention is to provide a buffer memory for temporarily storing transfer data between a memory circuit and a processing circuit, to separately manage write addresses to the buffer memory and read addresses from the buffer memory, and to write data to the buffer memory first. It is an object of the present invention to provide an asynchronous data transfer circuit configured to eliminate the above drawbacks and shorten data processing time by performing in-first-out (FIFO) operation.

(Means for Solving the Problems) The asynchronous data transfer circuit of the data processing device according to the present invention is configured to read data stored in the memory circuit, process it in the processing circuit, and transfer it to the memory circuit. A DMA control circuit, a buffer memory circuit,
The device is configured to include a write/read address counter means, a selector circuit, a data direction control/gate means, and a transfer end determination circuit.

The DMA control circuit is for controlling data transfer between the memory circuit and the processing circuit.

The buffer memory circuit temporarily stores data transferred between the memory circuit and the processing circuit, and performs first-in first-out operation.

The write/read address counter means is for setting all write addresses and read addresses to the buffer memory.

The selector circuit is for inputting either a write address or a read address to an address address of the buffer memory.

The data direction control/gate means is for controlling the transfer direction of data transferred via the buffer memory.

The transfer end determination circuit detects a match between a write address and a read address and determines the end of data transfer.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an asynchronous data transfer circuit according to the present invention. In FIG. 1, 1 is a microprocessor, 2 is a memory circuit, 3 is a DMA control circuit,
4 is a processing circuit, 5 is a buffer memory, 6 is a write address counter, 7 is a read address counter, 8 is a selector circuit, 9 is an address-number configuration circuit, 10 is a transfer end determination circuit, 11 is a data direction control circuit, 12 and 13 are gate circuits, respectively.

In FIG. 1, a microprocessor 1 is a processor that controls the operation of the entire data processing device, and first transfers unprocessed data stored in a memory circuit 2 to a buffer memory 5 under the control of an iDMA control circuit 3. At this time, the DMA control circuit 3 is instructed to start the transfer after setting the necessary data such as the DMA address and the number of transfer bytes to transfer data from the memory circuit 2 to the buffer memory 5 as specified by the microprocessor. is giving.

The write address of the transfer data to the buffer memory 5 is given by the count value of the write address counter 6, and this counter value is added to the buffer memory 5 via the selector circuit 8. In order to count the number of commit operations for transfer data to the buffer memory 5, a WAOLK signal is given to the write address counter 6 for each write operation, and the scan address counter 6 receives the WAOLK signal.
Count the number of signals. The count value of the write address counter 6 is simultaneously input to the address-number construction circuit 6 and compared with the count value of the read address counter. As a result of the comparison, if the count value of the write address counter 6 and the count value of the read address counter 7 do not match, this fact is output to the transfer end determination circuit 10.

Therefore, the transfer completion determination circuit 10 requests the processing circuit 4 to receive the transfer data, ! Request lll. The processing circuit 4 is
A data transfer operation is started to receive the transfer data from the buffer memory 5. At this time, the read address of the buffer memory 5 is given to the buffer memory 5 via the selector circuit 8 as the count value of the read address carantuff. As in the case of the write address counter 6, the read address counter 7 is given the FLAOLK signal for each read operation from the buffer memory 5, and the read address counter 7 counts the number of EtAOLK signals.

Next, the data processed by the processing circuit 4 is transferred to the memory circuit 2 via the buffer memory 5 in a reverse operation to the method described above. Note that the direction of transfer data in these data transfers is determined by the data direction control circuit 11 controlling the gate circuits 12, 13'i.

Furthermore, when the data transfer is completed, the count value of the write address counter 6 and the count value of the read address count coincide again. This is detected by the address/number configuration circuit 9, and the transfer end determination circuit 10 is notified of the end of the data transfer.The transfer end determination circuit 10 notifies the processing circuit 4 and the DMA control circuit 3 of the end of the data transfer. A series of transfer operations is completed.

(Effects of the Invention) As explained above, the present invention transfers data between a memory circuit and a data processing circuit via a buffer memory, thereby asynchronously transferring data between the memory circuit and the data processing circuit. This has the advantage that the time required for the memory circuit and data processing circuit involved in the transfer operation can be minimized, and that an efficient data processing operation can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an asynchronous data transfer circuit according to the present invention. 1...Microprocessor 2...Memory circuit 3.
DMA control circuit 4 Processing circuit 5 Buffer memory 6 Write address counter 7 Read address counter 8 Selector circuit 9 Address-number configuration circuit 10...・Transfer completion determination circuit 11...Data direction control circuit 12.13...Gate circuit Patent applicant NEC Corporation Representative Patent attorney Hisashi Inoro Figure 1

Claims (1)

[Claims] In an asynchronous data transfer circuit of a data processing device configured to read data stored in a memory circuit, process it in a processing circuit, and write it into the memory circuit, data is transferred between the memory circuit and the processing circuit. a DMA control circuit for controlling transfer; a buffer memory circuit for temporarily storing data transferred between the memory circuit and the processing circuit and performing a first-in-first-out operation; write/read address counter means for setting a write address and a read address of the buffer memory; a selector circuit for inputting either the write address or the read address to an address address of the buffer memory; data direction control/gate means for controlling the transfer direction of data transferred via the buffer memory, detecting a match between the write address and the read address, and determining the end of the data transfer; 1. An asynchronous data transfer circuit for a data processing device, characterized in that the asynchronous data transfer circuit includes a transfer completion determination circuit for determining the completion of transfer.