JPH11154988A - Digital signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To have an optimum reception state maintained without being affected by the level fluctuation of signals inputted to an A/D converter when digital signals are received by the digital signal receiver of a digital transmission system under various S/N environment and the like. SOLUTION: An output of a carrier recovery circuit 9 is given to an S/N detection circuit 12, where a level ratio of a signal to a noise, that is, the S/N is detected. The detected S/N is read by a micro processor 16 via a CPU interface 21. The micro processor 16 calculates a setting condition for a reference setting circuit 14 based on the S/N and gives it to the reference setting circuit 14. Thus, gain control by which characteristics of both an orthogonal detection circuit 5 and an A/D converter 6 are not deteriorated is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal receiving device used for digital transmission equipment.

[0002]

2. Description of the Related Art A conventional digital signal receiving apparatus will be described below. As an example of a conventional digital signal receiving apparatus, there is a digital signal receiving apparatus that receives a QPSK modulated signal transmitted through a satellite. FIG. 6 is a block diagram of the digital signal receiving apparatus, and FIG. 7 is an explanatory diagram. Hereinafter, the operation will be described with reference to the drawings.

[0003] In FIG. 6, a parabolic antenna has 12G.
The received signal frequency-converted from the Hz band to the 1 GHz band is
The signal is input to the input terminal 1 and the frequency conversion circuit 2 outputs, for example, 4
The frequency is converted to an intermediate frequency centered at 79.5 MHz, band-limited by an intermediate frequency filter 4, converted to orthogonal I and Q signals by a quadrature detection circuit 5,
Is converted to a digital signal, the frequency error is absorbed by the AFC 7, the frequency band is limited by the roll-off filter 8 so as not to cause intersymbol interference, and the carrier is reproduced by the carrier reproducing circuit 9. After the data is detected by the error correction circuit 11 and the error is corrected by the error correction circuit 11, the clock is output from the output terminal 19 and the data is output from the output terminal 20 as data. AD converter 6, AFC
7, roll-off filter 8, carrier reproduction circuit 9, data detection circuit 10, error correction circuit 11, amplitude detection circuit 1
3, reference circuit 14, DA converter 15, CP
The U interface 21 is generally composed of an LSI, as shown in FIG.
In the drawing, reference numeral 18 is used. Now, when the level at which the performance of the AD converter 6 is maximally improved is 1 Vpp and the maximum level at which the quadrature detection circuit 5 can output without deteriorating the characteristics is 1 Vpp or more, the S / N of 3 dB to 6 dB is received. The operation will be described with an example where it is necessary. FIG. 7 shows the relationship between the signal and noise at the input of the AD converter 6 in this case.

In order for the maximum level not to exceed 1 Vpp, it is necessary to determine the signal level at 3 dB which is noisy, and the signal level becomes 0.59 Vpp as shown at 31 in FIG. Therefore, the amplitude detection circuit 1
3, reference setting circuit 14, DA converter 15,
In the gain control circuit 17 constituted by the gain variable circuit 3, the reference value 0.59 Vpp is supplied to the reference setting circuit 14 by the microprocessor 16 from the CPU.
When the input signal to the AD converter 6 is greater than 0.59 Vpp, the control is performed via the DA converter 15 so as to reduce the gain of the gain variable circuit 3. When it is smaller than 0.59 Vpp, control is performed via the DA converter 15 so as to increase the gain of the variable gain circuit 3. The gain control is performed so that the input of the AD converter becomes 1 Vpp or less as indicated by 33, including the noise 32 (0.41 Vpp) and the signal 31.

[0005] Similar techniques include, for example, the Technical Report of the Institute of Television Engineers of Japan, ITEJ Technical Report V
ol.16, No52.pp19-24.CE'92-48, BSC'92-31, BFO'92-2
4 (Aug. 1992).

[0006]

However, in such a conventional configuration, since the signal level input to the AD converter 6 is constant, the optimum reception state when receiving in an environment having a different S / N ratio. There was a problem that it could not be set. That is, in the above example, when the S / N is 3 dB, the optimal signal level 31 is input to the AD converter 6, but when the S / N is 6 dB, the signal 3
Level 3 combining 1 and noise 35 (0.29 Vpp)
7 is as low as 0.88 Vpp as shown in FIG. 7A, and the performance of the AD converter 6 is not fully utilized.

An object of the present invention is to solve such a problem and to provide a digital signal receiving apparatus capable of performing optimal reception in reception environments having different SNs.

[0008]

In order to achieve the above object, a gain control circuit of a digital signal receiving apparatus according to the present invention comprises:
The input level of the AD converter is controlled based on the amplitude ratio between the received signal and the noise.

Thus, it is possible to obtain a digital signal receiver capable of performing optimal reception in a reception environment having different S / N.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a frequency conversion circuit for frequency-converting a digitally modulated received signal to an intermediate frequency, and an intermediate frequency band for limiting the band of the signal converted to the intermediate frequency. Frequency filter, a quadrature detection circuit for quadrature detection of the output of the intermediate frequency filter, an AD converter to which the output of the quadrature detection circuit is input, and a gain control circuit for controlling the level of a received signal input to the AD converter And an S / N detection circuit for detecting an amplitude ratio between the received signal and the noise, wherein the gain control circuit controls an input level to the AD converter based on the amplitude ratio between the received signal and the noise. This is a digital signal receiving device, and the optimum level of the received signal input to the AD converter and the amplitude value of the noise in the receiving environment with different S / N are optimized. Good gain control characteristic is exhibited improves the error rate characteristic.

According to a second aspect of the present invention, there is provided the digital signal receiving apparatus according to the first aspect, wherein the gain control circuit makes a sum of a received signal and a noise amplitude value constant. Since the level obtained by combining the amplitude of the received signal and the noise input to the AD converter is constant, good gain control characteristics are exhibited and the error rate characteristics are improved.

According to a third aspect of the present invention, there is provided a frequency conversion circuit for converting a received signal which is digitally modulated and whose transmission rate value changes to an intermediate frequency, An intermediate frequency filter that performs band limiting, a quadrature detection circuit that performs quadrature detection on the output of the intermediate frequency filter, an AD converter that receives the output of the quadrature detection circuit, and a gain that controls the amplitude that is input to the AD converter A digital circuit comprising: a control circuit; and a microprocessor for controlling the gain control circuit, wherein the microprocessor controls an input level of an AD converter based on values of a pass band width and a transmission rate of an intermediate frequency filter. Even if it is a signal receiving device and receives a received signal in which the value of the transmission rate changes,
Since the level combining the amplitude of the received signal with the input signal to the AD converter is optimized, optimal reception is possible in a reception environment where the pass bandwidth of the intermediate frequency filter and the bandwidth of the received signal are different, and excellent error rate characteristics are achieved. It will be realized.

According to a fourth aspect of the present invention, in the digital signal receiving apparatus according to the third aspect, the gain control circuit makes a sum of a received signal and a noise amplitude value constant. Even if a received signal with a variable transmission rate is received, the level combining the amplitude of the received signal and the noise input to the AD converter is constant, resulting in good gain control characteristics and improved error rate characteristics. I do.

According to a fifth aspect of the present invention, when a digitally modulated reception signal is frequency-converted to an intermediate frequency, the reception signal including an undesired wave in the intermediate frequency is converted to an intermediate frequency. A frequency conversion circuit that converts the frequency to an intermediate frequency, an intermediate frequency filter that limits the band of the signal converted to the intermediate frequency, a quadrature detection circuit that performs quadrature detection on the output of the intermediate frequency filter, and an output of the quadrature detection circuit An input A / D converter, a gain control circuit for controlling a gain input to the A / D converter, and a microprocessor for controlling the gain control circuit, wherein the microprocessor includes A digital signal receiving apparatus for controlling an input level of an AD converter based on the number of desired waves. When the digitally modulated received signal is converted to an intermediate frequency, the level input to the AD converter is optimized even if the intermediate frequency includes an undesired wave. Even if an undesired wave exists in the band, optimal reception is possible, and excellent error rate characteristics are realized.

According to a sixth aspect of the present invention, in the digital signal receiving apparatus according to the fifth aspect, the gain control circuit makes the sum of the amplitude values of the received signal, noise, and the undesired wave constant. When the digitally modulated received signal is converted to an intermediate frequency, even if the intermediate frequency contains an undesired wave, the received signal input to the AD converter, the noise, and the amplitude value of the undesired wave Is constant, optimal reception is possible even when an undesired wave exists in the pass band of the intermediate frequency filter, and excellent error rate characteristics are realized.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a block diagram of a digital signal receiving apparatus according to an embodiment of the present invention.

In FIG. 1, a digital signal receiving apparatus according to the present embodiment includes an input terminal 1 to which a digitally modulated signal is input, a frequency conversion circuit 2 connected to the input terminal 1, and a frequency conversion circuit 2 , An intermediate frequency filter 4 connected to the output of the gain variable circuit 3, a quadrature detection circuit 5 connected to the output of the intermediate frequency filter 4, and a quadrature detection circuit A / D converter 6 connected to the output of
An AFC circuit 7 connected to the output of the D converter 6; a roll-off filter 8 connected to the output of the AFC circuit 7; a carrier regeneration circuit 9 connected to the output of the roll-off filter 8; A data detection circuit 10 connected to the output of the circuit 9, an error correction circuit 11 connected to the output of the data detection circuit 10, and a clock output terminal 19 connected to the output of the error correction circuit 11
And the data output terminal 20 and the roll-off filter 8
, An amplitude detection circuit 13 connected to the output of the CPU, and a reference setting in which an output of the amplitude detection circuit 13 is connected to one input and an output of the CPU interface 21 is connected to the other input to set a reference value. Circuit 1
4, a DA converter 15 connected between the output of the reference setting circuit 14 and the gain control terminal of the gain variable circuit 3, and the output of the carrier reproducing circuit 9 and the C
An S / N detection circuit 12 connected between the CPU interface 21 and the PU interface 21;
And a microprocessor 16 for setting a reference value of a reference setting circuit 14 based on the output of the S / N detection circuit 12.

In the digital signal receiving apparatus thus configured, the output of the carrier recovery circuit 9 is input to the S / N detection circuit 12, and the amplitude ratio between the signal and the noise, that is, S / N.
N is detected. This detected value is stored in CPU interface 2
1 is read by the microprocessor 16. V
s (V) is the amplitude of the signal input to the AD converter 6 (hereinafter referred to as Vs), and Vn (V) is the
S / N (dB) is represented by (Equation 1), where the amplitude of the noise input to the input signal (hereinafter referred to as Vn) is expressed as

[0019]

(Equation 1)

The level at which the performance of the AD converter 6 is maximized is 1 Vpp, and the maximum level that the quadrature detection circuit 5 can output without deteriorating the characteristic is 1 Vpp.
In the above case, a condition that does not deteriorate both the characteristics of the quadrature detection circuit 5 and the AD converter 6 is given by (Equation 2).

[0021]

(Equation 2)

The microprocessor 16 obtains (Equation 3) from (Equation 1) and (Equation 2).

[0023]

(Equation 3)

As described above, the optimum Vs (V) is calculated and given to the reference setting circuit 14 via the CPU interface 21. The reference setting circuit 14 compares the detection value detected by the amplitude detection circuit 13 with the result. If the detection value is larger than the optimum Vs value, the control is performed via the DA converter 15 so that the gain of the gain variable circuit 3 is reduced. Do. When the detected value is smaller than the optimum Vs value, control is performed via the DA converter 15 so as to increase the gain of the gain variable circuit 3, and gain control is performed so that the characteristics of the AD converter 6 and the quadrature detection circuit 5 do not deteriorate. . As a result, A
As shown in FIG. 2A, when the S / N is 6 dB, the noise amplitude 36 is 0.33 Vp.
p, the signal amplitude 37 is 0.67 Vpp, and the sum of the noise amplitude 36 and the signal amplitude 37 is 1.000 V
pp. When the S / N is 3 dB, the noise amplitude 39 is 0.41 Vpp and the signal amplitude is 4 as shown in FIG.
0 becomes 0.59 Vpp, and the amplitude 41 obtained by adding the noise amplitude 39 and the signal amplitude 40 also becomes 1.000 Vpp.

As described above, the sum of the noise amplitude and the signal amplitude of the AD converter 6 is 1 V regardless of the S / N value.
pp, the quadrature detection circuit 5 and the AD converter 6
The gain control can be performed under the optimum condition that does not deteriorate both the characteristics of the above. As a result, as shown at 55 in FIG.
Is constant, and Vs shown at 54 in FIG.
When the S / N is large, the signal input to the AD converter 6 can be set large, and excellent error rate characteristics can be realized as compared with the conventional example.

As described above, according to the embodiment of the present invention, it is possible to improve the error rate characteristics when the S / N is higher than in the conventional case.

Next, assuming that the roll-off rate is α and the transmission rate is T, the bandwidth B of the received signal is expressed by (Equation 4).

[0028]

(Equation 4)

For example, when the roll-off rate α is 0.35 and the transmission rate is 40 Mbps, the band B is 27 MHz, the roll-off rate α is 0.35, and the transmission rate is 20M.
In the case of bps, the band B is 13.5 Mbps. now,
Roll-off rate α is 0.35 and transmission rate is 40Mbps
Assuming that the transmission rate of the received signal changes from 20 Mbps to 20 Mbps, the bandwidth of the received signal is 27 MHz to 13.5 M
Hz. Therefore, when receiving from 40 Mbps to 20 Mbps with one digital signal receiving device, the pass bandwidth of the intermediate frequency filter 4 is 40 Mbps.
The frequency must be 27 MHz or higher in order to pass the received signal of s.

Now, when receiving a 20 Mbps signal,
The S / N (dB) is represented by (Equation 5) similarly to (Equation 1).

[0031]

(Equation 5)

When the level at which the performance of the AD converter 6 is maximized is 1 Vpp, and the maximum level at which the quadrature detection circuit 5 can output the signal without deteriorating the characteristics is 1 Vpp or more, the characteristics of the quadrature detection circuit 5 and the AD converter 6 are changed. The condition that neither of them is deteriorated is given by (Equation 6) since the pass bandwidth of the intermediate frequency filter 4 becomes twice the bandwidth of the received signal.

[0033]

(Equation 6)

The microprocessor 16 transforms (Equation 5) and (Equation 6) to become (Equation 7).

[0035]

(Equation 7)

As described above, the optimum Vs (V) is calculated and given to the reference setting circuit 14 via the CPU interface 21.

The reference setting circuit 14 compares the detection value detected by the amplitude detection circuit 13 with the result. If the detection value is larger than the optimum Vs value, the reference setting circuit 14 uses the DA converter 15 to reduce the gain of the gain variable circuit 3. Control
If the detected value is smaller than the optimum Vs value, the gain variable circuit 3
Is controlled via the DA converter 15 so that the gain of the AD converter 6 is increased, and the gain control is performed so that the characteristics of the AD converter 6 and the quadrature detection circuit 5 do not deteriorate. As a result, the input level of the AD converter 6 becomes S / S as shown in FIG.
When N is 6 dB and the pass bandwidth of the intermediate frequency filter is twice the bandwidth of the received signal, the noise amplitude 42 is 0.50 Vp
p, the signal amplitude 43 becomes 0.50 Vpp, and the sum of the noise amplitude 42 and the signal amplitude 43 becomes 1.000 V.
pp. Further, as shown in FIG. 4B, the S / N is 3d.
B, When the pass bandwidth of the intermediate frequency filter is twice the bandwidth of the received signal, the noise amplitude 45 is 0.59 Vpp and the signal amplitude 46 is 0.41 Vpp, and the amplitude 47 obtained by combining the noise amplitude 45 and the signal amplitude 46 Becomes 1.000 Vpp.

As described above, regardless of the ratio between the reception bandwidth of the intermediate frequency filter and the reception signal, or the S / N value,
The sum of the noise amplitude and signal amplitude of converter 6 is 1
Vpp is constant, and gain control can be performed under optimum conditions that do not deteriorate both the characteristics of the quadrature detection circuit 5 and the AD converter 6. As a result, even when the transmission rate is low and the bandwidth of the received signal is smaller than the pass bandwidth of the intermediate frequency filter, the signal input to the AD converter 6 and the noise amplitude can be set to be constant, and excellent error rate characteristics can be realized. . As described above, according to the embodiment of the present invention, the transmission rate and S /
Good error rate characteristics can be obtained regardless of N.

Now, if the received signal and the undesired signal of the same level exist in the band of the intermediate frequency filter 4, AD
The level at which the performance of the converter 6 is maximized is 1 Vpp
When the maximum level that the quadrature detection circuit 5 can output without deteriorating the characteristics is 1 Vpp or more, the conditions for not deteriorating the characteristics of both the quadrature detection circuit 5 and the AD converter 6 are (Equation 8) and (Equation 9) Given by

[0040]

(Equation 8)

[0041]

(Equation 9)

The microprocessor 16 transforms (Equation 8) and (Equation 9) to obtain (Equation 10).

[0043]

(Equation 10)

As described above, the optimum Vs (V) is calculated and given to the reference setting circuit 14 via the CPU interface 21. The reference setting circuit 14 compares the detection value detected by the amplitude detection circuit 13 with the result. If the detection value is larger than the optimum Vs value, control is performed via the DA converter 15 so as to reduce the gain of the gain variable circuit 3. When the detected value is smaller than the optimum Vs value, control is performed via the DA converter 15 so as to increase the gain of the gain variable circuit 3, and the gain control is performed so that the characteristics of the AD converter 6 and the quadrature detection circuit 5 do not deteriorate. Done. As a result, A
As shown in FIG. 5 (a), the input level of the D converter 6 has an S / N of 6 dB, and the noise amplitude and the noise amplitude when the received signal and the undesired wave of the same level exist in the pass band width of the intermediate frequency filter. The sum of the undesired wave amplitudes is 0.67 Vpp,
The received signal amplitude 49 is 0.33 Vpp, and the sum 50 of the noise amplitude and the undesired wave amplitude 48 and the received signal amplitude 49 is 1.000 Vpp. FIG.
As shown in (b), when the S / N is 3 dB and the received signal and the undesired wave have the same level in the pass band width of the intermediate frequency filter, the total of the noise amplitude and the undesired wave amplitude is 51.
Is 0.71 Vpp and the received signal amplitude 52 is 0.29 Vpp
The amplitude 53, which is the sum of the noise amplitude and the undesired wave amplitude 51 and the received signal amplitude 52, is 1.000 Vpp.

As described above, even when the received signal and the undesired wave having the same level exist in the pass band width of the intermediate frequency filter 4, the noise amplitude of the AD converter 6 and the signal amplitude do not depend on the S / N value. The value obtained by combining the amplitudes becomes constant at 1 Vpp, and the gain control can be performed under the optimum condition that does not deteriorate the characteristics of both the quadrature detection circuit 5 and the AD converter 6. As a result, even when a reception signal and an undesired wave of the same level exist in the pass band width of the intermediate frequency filter 4, the signal input to the AD converter 6 and the noise amplitude can be set to be constant, and the excellent error rate characteristic can be obtained. Can be realized.

As described above, even when a received signal and an undesired wave of the same level exist in the pass band width of the intermediate frequency filter 4, a good error rate characteristic can be obtained regardless of the S / N. .

The case where the maximum level that the quadrature detection circuit 5 can output without deteriorating the characteristics is larger than the level at which the performance of the AD converter 6 is maximized. If the maximum level that the quadrature detection circuit 5 can output without deteriorating the characteristics is smaller than the level that improves, the quadrature detection circuit 5 determines the right side of (Equation 2), (Equation 5), and (Equation 8). Similarly, excellent error rate characteristics can be obtained by setting the maximum level that can be output without deteriorating the error rate.

[0048]

As described above, according to the present invention, the gain of the input level of the AD converter is controlled to an optimum value by the amplitude ratio of the received signal and the noise. The level can be set optimally.

In a reception environment having different S / N, A
Since the input level of D can be set optimally, there is an effect that the error rate can be improved in a reception environment with different S / N.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital signal receiving apparatus according to an embodiment of the present invention.

FIG. 2 (a) is a diagram showing a relationship between a signal having an S / N of 6 dB and noise in the digital signal receiving device, and FIG. 2 (b) is a diagram showing a relationship between a signal having an S / N of 3 dB in the digital signal receiving device. Noise relation diagram

FIG. 3 is a characteristic diagram of a bit error rate with respect to S / N.

FIG. 4 (a) is a diagram showing the relationship between noise and a signal whose intermediate frequency filter has a pass bandwidth of twice the received signal bandwidth and an S / N of 6 dB. FIG. 4 (b) shows the same pass band of the intermediate frequency filter. Diagram of the relationship between noise and a signal whose width is twice the received signal bandwidth and whose S / N is 3 dB

FIG. 5 (a) is a diagram showing the relationship between a signal having an S / N of 6 dB and noise in the same case where a reception signal and an undesired wave having the same level exist in the pass band width of the intermediate frequency filter. ) Shows the case where the received signal and the undesired wave of the same level exist in the pass band width of the intermediate frequency filter.
Diagram of the relationship between signal and noise when N is 3 dB

FIG. 6 is a block diagram of a conventional digital signal receiving device.

FIGS. 7A and 7B are diagrams showing the relationship between signal and noise of a conventional digital signal receiving apparatus, respectively.

[Explanation of symbols]

 4 Intermediate frequency filter 5 Quadrature detection circuit 6 AD converter 12 S / N detection circuit

Claims (6)

[Claims] A frequency conversion circuit for converting the frequency of a digitally modulated received signal to an intermediate frequency; an intermediate frequency filter for limiting the band of the signal converted to the intermediate frequency;
A quadrature detection circuit that performs quadrature detection on the output of the intermediate frequency filter, an AD converter to which the output of the quadrature detection circuit is input, a gain control circuit that controls the level of a reception signal input to the AD converter, And an S / N detection circuit for detecting a noise amplitude ratio. The gain control circuit controls an input level to an AD converter based on a received signal and noise amplitude ratio. . 2. The digital signal receiving apparatus according to claim 1, wherein the gain control circuit makes a sum of a received signal and a noise amplitude value constant. 3. A frequency conversion circuit for frequency-converting a digitally modulated received signal whose transmission rate value changes to an intermediate frequency, an intermediate frequency filter for band-limiting the signal converted to the intermediate frequency, and A quadrature detection circuit that performs quadrature detection on the output of the intermediate frequency filter, an AD converter to which the output of the quadrature detection circuit is input,
A gain control circuit for controlling a gain input to the converter; and a microprocessor for controlling the gain control circuit, wherein the microprocessor controls an input of the AD converter based on a value of a pass bandwidth and a transmission rate of the intermediate frequency filter. A digital signal receiving device for controlling a level. 4. The digital signal receiving device according to claim 3, wherein the gain control circuit makes the sum of the amplitude values of the received signal and the noise constant. 5. A frequency conversion circuit which digitally modulates the received signal and converts the frequency of the digitally modulated received signal to an intermediate frequency when the received signal includes an undesired wave. , An intermediate frequency filter that limits the band of the signal converted to the intermediate frequency, a quadrature detection circuit that performs quadrature detection on the output of the intermediate frequency filter, an AD converter to which the output of the quadrature detection circuit is input, and this AD converter And a microprocessor for controlling the gain control circuit. The microprocessor controls the gain of the AD converter based on the number of undesired waves present in the band of the intermediate frequency filter. A digital signal receiving device for controlling an input level. 6. The digital signal receiving apparatus according to claim 5, wherein the gain control circuit makes a sum of amplitude values of the received signal, noise, and the undesired wave constant.