JPH11150150A - Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip - Google Patents

Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip

Info

Publication number
JPH11150150A
JPH11150150A JP31672697A JP31672697A JPH11150150A JP H11150150 A JPH11150150 A JP H11150150A JP 31672697 A JP31672697 A JP 31672697A JP 31672697 A JP31672697 A JP 31672697A JP H11150150 A JPH11150150 A JP H11150150A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
mounting
insulating resin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31672697A
Other languages
Japanese (ja)
Inventor
Masaaki Kato
正明 加藤
Yoshitaka Okugawa
良隆 奥川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP31672697A priority Critical patent/JPH11150150A/en
Publication of JPH11150150A publication Critical patent/JPH11150150A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method, in which a board for semiconductor mounting mounted with an electrical connection mechanism and with a mechanical connection mechanism is manufactured at low cost in the board for semiconductor mounting, onto which a semiconductor chip is flip-chip mounted, and to provide its mounting method. SOLUTION: In a board for semiconductor mounting, an adhesive insulating resin 16, which is softened by heating and which reveals adhesive property is formed on the surface of a wiring board 11, and conductor terminals 18 for electrical connection are formed on the surface of the adhesive insulating resin 16 by copper etching or conductive-paste printing. A semiconductor chip is heated and pressurized by being pressed to the board for semiconductor mounting. The adhesive insulating resin 16 is softened. The conductor terminals 18 are embedded and passed through so as to be connected electrically. The semiconductor chip is fixed and bonded to the board for semiconductor mounting by the adhesive insulating resin 16, so as to achieve mechanical connection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップをフ
リップチップ接続により搭載する半導体搭載用基板及び
その製造方法、さらには半導体チップの実装方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate for mounting a semiconductor chip by flip-chip connection, a method of manufacturing the same, and a method of mounting a semiconductor chip.

【0002】[0002]

【従来の技術】近年の電子機器の高機能化並びに軽薄短
小化の要求に伴い、電子部品の高密度集積化さらには高
密度実装化が進んできており、これらの電子機器に使用
される半導体パッケージは従来にも増して益々小型化か
つ多ピン化が進んできている。
2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been advanced, and semiconductors used in these electronic devices have been developed. Packages are becoming smaller and more multi-pin than ever before.

【0003】半導体パッケージはその小型化に伴って、
従来のようなリードフレームを使用した形態のパッケー
ジでは小型化に限界がきているため、最近では回路基板
上にチップを実装したものとしてBGA(Ball G
rid Array)やCSP(Chip Scale
Package)といったエリア実装型の新しいパッ
ケージ方式が提案されている。これらの半導体パッケー
ジにおいて、半導体チップの電極と従来型半導体パッケ
ージのリードフレームの機能を有する半導体搭載用基板
と呼ばれるプラスチックやセラミックス等各種絶縁材料
と導体配線で構成される基板の端子との電気的接続方法
として、ワイヤーボンディング方式やTAB(Tape
Automated Bonding)方式、さらに
はFC(Frip Chip)方式などが知られている
が、最近では半導体パッケージの小型化に有利なFC接
続方式を用いたBGAやCSPの構造が盛んに提案され
ている。このFC接続方式は、一般に、半導体チップの
電極にあらかじめ電気メッキ法により接続用バンプを形
成しておき、このバンプと基板上の端子を位置合わせし
て熱圧着により接続するが、半導体チップの電極にバン
プを形成する工程が複雑でバンプ製造コストが掛かり、
また、バンプ接続部分の耐湿信頼性を得るためチップと
基板との間隙に、アンダーフィルと呼ばれる絶縁樹脂を
充填してバンプ接続部分を封止する必要があり、このア
ンダーフィルを充填し硬化させる工程が必要となるため
製造工程が複雑で製造コストが高くなる問題がある。
[0003] With the miniaturization of semiconductor packages,
Since the miniaturization of a package using a conventional lead frame has reached its limit, it has recently been proposed to mount a chip on a circuit board and use a BGA (Ball G
Rid Array) and CSP (Chip Scale)
A new package method of area mounting type such as “Package” has been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate made of various insulating materials such as plastics and ceramics called a semiconductor mounting substrate having the function of a lead frame of a conventional semiconductor package and conductive wiring. As a method, a wire bonding method or TAB (Tape)
Automated Bonding (FC) systems and FC (Flip Chip) systems are known. Recently, BGA and CSP structures using FC connection systems that are advantageous for miniaturization of semiconductor packages have been actively proposed. In this FC connection method, generally, connection bumps are formed in advance on the electrodes of a semiconductor chip by electroplating, and the bumps and the terminals on the substrate are aligned and connected by thermocompression bonding. The process of forming bumps is complicated, and bump manufacturing costs are incurred.
In addition, in order to obtain the moisture resistance reliability of the bump connection part, it is necessary to fill the gap between the chip and the substrate with an insulating resin called underfill to seal the bump connection part, and to fill and cure this underfill. Therefore, there is a problem that the manufacturing process is complicated and the manufacturing cost is increased.

【0004】そこで、半導体チップにバンプを形成する
ことなく半導体チップと基板を電気的に接続しかつ機械
的に接着する接続材料として異方導電シートを使用する
方法が着目され検討されている。この異方導電シートに
は接着性が付与されており、通常では、先に基板上に異
方導電シートを貼り合わせてから半導体チップを搭載し
電気的接続と機械的接続を同時に行う。このような異方
導電シート方式は半導体パッケージの小型化や低コスト
化に有効な手段として益々注目されてきており、以下の
ような異方導電シートが提案されている。
Therefore, attention has been paid to a method of using an anisotropic conductive sheet as a connection material for electrically connecting and mechanically bonding a semiconductor chip and a substrate without forming a bump on the semiconductor chip. The anisotropic conductive sheet is provided with an adhesive property. Normally, an anisotropic conductive sheet is first attached to a substrate, and then a semiconductor chip is mounted, and electrical connection and mechanical connection are simultaneously performed. Such an anisotropic conductive sheet method has been increasingly attracting attention as an effective means for reducing the size and cost of semiconductor packages, and the following anisotropic conductive sheet has been proposed.

【0005】従来より、熱可塑性や熱硬化性の樹脂中に
導電性の微粒子を分散させ、熱圧着時に樹脂が流動して
接続端子間に挟まれた導電性の微粒子によって厚さ方向
の電気的接続を得る異方導電シート(図4)がよく知ら
れており、液晶ディスプレイパネルとTCP(Tape
Carrier Package)の電気的接続など
に使用されている。前記構造の異方導電シートは樹脂に
導電性微粒子を分散させるといった比較的簡単な工程で
製造できることと、基板に貼り合わせる際の位置合わせ
が比較的ラフに行えることを特徴としている。しかしな
がら、電気的接続を半導体チップの電極と基板の端子と
の間に確率的に存在する導電性微粒子によって得ている
ため、狭ピッチになるに従い導電性微粒子をより微小に
より多く分散させる必要があり、これにより、微粒子密
度が高まり微粒子間距離が狭まるため電気的絶縁性が低
下する問題と、微粒子と電極及び端子との接続面積が小
さくなるため接続抵抗が上昇する問題、さらには微粒子
コストの上昇の問題がある。また最近では、樹脂フィル
ムにドリルやレーザによって微小な貫通穴を明け、その
後メッキや導電性ペースト印刷などの方法により、貫通
穴内部を導電体で充填し、さらに樹脂フィルムの表面に
接着層を形成した構造であって、熱圧着時に接着層が流
動し導電体が露出して接続端子間に挟まれた導電体によ
って電気的接続を得る異方導電シート(図5)が提案さ
れている。前記構造の異方導電シートは半導体チップの
電極および基板の端子と導電体が相対して配列されるの
で電気的接続性に優れかつ隣接する導電体においての電
気的絶縁性にも優れることを特徴としている。しかしな
がら、高位置精度での微小な穴あけ加工が要求されるた
めレーザによる穴明け加工が必要となり、レーザの欠点
である低生産性及び高ランニングコストにより製造コス
トが高くなる問題がある。また、微小穴への導電体形成
は、通常メッキで行われるが、穴径が小さくなるほど均
一なメッキが難しく、導電体の高さにバラツキを生じ易
く、接続時に電気的接続が出来ないといった品質低下の
問題がある。さらには、前記異方導電シートはこれに貼
り合わせる基板及び半導体チップの両方に対し高精度で
位置合わせしなければならず、位置合わせ工程が複雑に
なり実装歩留まりが悪いといった問題もある。
[0005] Conventionally, conductive fine particles are dispersed in a thermoplastic or thermosetting resin, and the resin flows during thermocompression bonding, so that the conductive fine particles sandwiched between the connection terminals make the electrical conduction in the thickness direction possible. Anisotropic conductive sheets (FIG. 4) for obtaining connections are well known, and include a liquid crystal display panel and a TCP (Tape).
Carrier Package). The anisotropic conductive sheet having the above structure is characterized in that it can be manufactured by a relatively simple process such as dispersing conductive fine particles in a resin, and that the alignment at the time of bonding to a substrate can be performed relatively roughly. However, since the electrical connection is obtained by the conductive fine particles that are stochastically present between the electrode of the semiconductor chip and the terminal of the substrate, it is necessary to disperse the conductive fine particles more finely as the pitch becomes narrower. As a result, the density of fine particles is increased and the distance between the fine particles is reduced, so that the electrical insulation property is reduced. Further, the connection area between the fine particles and the electrode and the terminal is reduced, so that the connection resistance is increased. There is a problem. Recently, a small through hole was drilled in a resin film using a drill or laser, and then the inside of the through hole was filled with a conductor by plating or conductive paste printing, and an adhesive layer was formed on the surface of the resin film. An anisotropic conductive sheet (FIG. 5) has been proposed, in which an adhesive layer flows at the time of thermocompression bonding, a conductor is exposed, and an electrical connection is obtained by a conductor sandwiched between connection terminals. The anisotropic conductive sheet having the structure described above is characterized in that since the conductors are arranged opposite to the electrodes of the semiconductor chip and the terminals of the substrate, the electrical conductivity is excellent and the electrical insulation between adjacent conductors is also excellent. And However, since fine drilling with high positional accuracy is required, drilling with laser is required, and there is a problem that the manufacturing cost is increased due to the low productivity and high running cost, which are the drawbacks of laser. In addition, the formation of a conductor in a minute hole is usually performed by plating. However, as the hole diameter decreases, uniform plating becomes more difficult, the height of the conductor tends to vary, and electrical connection cannot be performed at the time of connection. There is a problem of decline. Further, the anisotropic conductive sheet must be positioned with high precision on both the substrate and the semiconductor chip to be bonded thereto, and there is a problem that the positioning process is complicated and the mounting yield is poor.

【0006】[0006]

【発明が解決しようとする課題】そこで本発明は、従来
のメッキバンプや異方導電シートにより半導体チップと
基板とを電気的かつ機械的に接続する方法が有する上記
の種々の問題を鑑みて、鋭意研究をした結果なされたも
のであり、半導体チップとの電気的及び機械的接続の機
能を有する半導体搭載用基板を低コストで製造提供する
ことができ、さらに、容易で生産性に優れた半導体チッ
プの実装方法を提供することを目的とする。
SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned various problems of a conventional method for electrically and mechanically connecting a semiconductor chip and a substrate by plating bumps or anisotropic conductive sheets. It has been made as a result of earnest research, and it is possible to manufacture and provide a semiconductor mounting substrate having a function of electrical and mechanical connection with a semiconductor chip at a low cost. An object of the present invention is to provide a chip mounting method.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体搭載用基板の構成は、配線基板の
半導体チップを搭載する側の面に、加熱で軟化性及び接
着性を発現する接着性絶縁樹脂が形成されているととも
に、前記接着性絶縁樹脂上の半導体チップの電極と配線
基板の導体配線とを接続する位置に独立した導体端子を
形成した構成となっている。
In order to achieve the above object, a semiconductor mounting substrate according to the present invention has a structure in which a surface of a wiring board on which a semiconductor chip is mounted has a softening property and an adhesive property by heating. An adhesive insulating resin that is developed is formed, and independent conductor terminals are formed at positions on the adhesive insulating resin that connect the electrodes of the semiconductor chip and the conductor wiring of the wiring board.

【0008】また本発明の半導体搭載用基板の製造方法
は、導体配線を形成した配線基板の半導体チップを搭載
する側の面に、銅箔と加熱で軟化性及び接着性を発現す
る接着性絶縁樹脂から成る2層シートを加熱加圧して貼
り合わせる工程と、前記2層シートの銅箔を選択的にエ
ッチングして導体端子を形成する工程を有している。
Further, according to the method of manufacturing a semiconductor mounting substrate of the present invention, an adhesive insulating material which exhibits softness and adhesiveness when heated with a copper foil is provided on a surface of a wiring substrate on which a semiconductor chip is mounted, on which a conductive wiring is formed. The method includes a step of bonding a two-layer sheet made of resin by heating and pressing, and a step of selectively etching the copper foil of the two-layer sheet to form a conductor terminal.

【0009】また本発明の半導体搭載用基板の製造方法
は、導体配線を形成した配線基板の半導体チップを搭載
する側の面に、銅箔と加熱で軟化性及び接着性を発現す
る接着性絶縁樹脂を塗布し乾燥する工程と、前記接着性
絶縁樹脂上に導電性ペーストを印刷し硬化して導体端子
を形成する工程を有している。
Further, according to the present invention, there is provided a method of manufacturing a substrate for mounting a semiconductor device, comprising the steps of: providing an adhesive insulating material which exhibits softness and adhesiveness by heating with a copper foil on a surface of a wiring substrate on which a semiconductor chip is mounted; A step of applying and drying a resin; and a step of printing and curing a conductive paste on the adhesive insulating resin to form conductor terminals.

【0010】さらに、本発明の半導体搭載用基板に半導
体チップを実装する方法にあっては、半導体搭載用基板
の導体端子と半導体チップの電極とを対向させ位置合わ
せする工程と、半導体チップを裏面から加熱しながら半
導体搭載用基板に平行に押し付け導体端子を接着性絶縁
樹脂層に垂直に埋没貫通させ前記半導体搭載用基板の接
続端子に接続するとともに半導体チップも同時に接着す
る工程からなっている。
Further, in the method of mounting a semiconductor chip on a semiconductor mounting substrate according to the present invention, there is provided a step of aligning a conductor terminal of the semiconductor mounting substrate with an electrode of the semiconductor chip so as to face each other; And a step of pressing the semiconductor terminal parallel to the semiconductor mounting substrate while heating the semiconductor terminal vertically through the adhesive insulating resin layer so as to be connected to the connection terminal of the semiconductor mounting substrate and to simultaneously bond the semiconductor chip.

【0011】[0011]

【発明の実施の形態】以下に本発明を図面に基づき説明
する。図1の(a)から(d)は本発明の半導体搭載用
基板を得るための製造方法の第1の実施例である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIGS. 1A to 1D show a first embodiment of a manufacturing method for obtaining a substrate for mounting a semiconductor according to the present invention.

【0012】まず、配線基板11と2層シート17を用
意する(図1(a))。配線基板11は、少なくとも絶
縁樹脂13と半導体チップの電極と接続するための接続
端子と、実装用基板の端子と接続するための接続端子を
含む導体配線12から成り、必要に応じて本実施例のよ
うに表面にソルダーレジスト14を形成してしてあって
も良いし、また導体配線12の表面にAu、Ni、P
d、In、Pb、Snなどの金属及びこれらの合金を無
電解メッキもしくは電解メッキで施してあっても良く、
ポリイミド樹脂やポリエステル樹脂等を絶縁層としたフ
レキシブル配線基板や、エポキシ樹脂やフェノール樹脂
等を絶縁層としたリジット配線基板や、さらにはAl2
O3やAlN等のセラミックスを絶縁層としたセラミッ
クス配線基板を用いることができる。2層シート17
は、銅箔15の表面に液状の接着性絶縁樹脂を、後述の
導体端子18と導体配線12とに挟まれる部位の接着性
絶縁樹脂16の厚さが導体端子18の厚さに後述の表面
処理の厚さを加えた厚さの0.7〜1.5倍の範囲に入
るように塗布量を調整し、均一に塗布して後乾燥して得
ることができる。上記の導体端子18と導体配線12と
に挟まれる部位の接着性絶縁樹脂16の厚さが導体端子
18の厚さに表面処理19の厚さを加えた厚さの0.7
倍より小さいと後述の半導体チップの実装において導体
端子18が柱となって半導体チップと接着性絶縁樹脂1
6に間隙ができ半導体チップを接着することができず電
気的信頼性が落ち易く、また1.5倍より大きいと導体
端子18が接着性絶縁樹脂16を貫通できず導通が得ら
れないといった問題を生じ易くなる。接着性絶縁樹脂1
6は熱可塑性樹脂、熱硬化性樹脂またはこれらを混合し
た樹脂のいずれかから成り、加熱により軟化性及び接着
性を発現する樹脂を用いる。具体的にはエポキシ系樹
脂、ポリアミド系樹脂、ポリエステル系樹脂、ポリイミ
ド系樹脂、マレイミド系樹脂、フッ素系樹脂、ウレタン
系樹脂、ポレスチレン系樹脂、アクリル系樹脂、シリコ
ーン系樹脂、合成ゴム系樹脂などの樹脂を1種または複
数種混合したものに、硬化剤や無機充填剤、各種カップ
リング剤などを添加して成る。
First, a wiring board 11 and a two-layer sheet 17 are prepared (FIG. 1A). The wiring board 11 includes at least a connection terminal for connecting the insulating resin 13 to the electrode of the semiconductor chip and a conductor wiring 12 including a connection terminal for connecting to the terminal of the mounting board. The solder resist 14 may be formed on the surface as shown in FIG.
Metals such as d, In, Pb, Sn and alloys thereof may be applied by electroless plating or electrolytic plating,
Flexible wiring boards with an insulating layer of polyimide resin or polyester resin, rigid wiring boards with an insulating layer of epoxy resin or phenolic resin, or even Al2
A ceramic wiring board using a ceramic such as O3 or AlN as an insulating layer can be used. Two-layer sheet 17
The thickness of the adhesive insulating resin 16 at the portion sandwiched between the conductor terminals 18 and the conductor wirings 12 described later is changed to the thickness of the conductor terminals 18 by applying a liquid adhesive insulating resin on the surface of the copper foil 15. It can be obtained by adjusting the coating amount so as to fall within a range of 0.7 to 1.5 times the thickness including the thickness of the treatment, applying uniformly, and then drying. The thickness of the adhesive insulating resin 16 at the portion sandwiched between the conductor terminal 18 and the conductor wiring 12 is 0.7 of the thickness of the conductor terminal 18 plus the thickness of the surface treatment 19.
If it is smaller than twice, the conductive terminal 18 becomes a pillar in mounting of the semiconductor chip described later, and the semiconductor chip and the adhesive insulating resin 1 are used.
6, there is a problem that the semiconductor chip cannot be bonded and the electrical reliability is easily lowered, and if it is more than 1.5 times, the conductive terminal 18 cannot penetrate the adhesive insulating resin 16 and the conduction cannot be obtained. Tends to occur. Adhesive insulating resin 1
Numeral 6 is made of a thermoplastic resin, a thermosetting resin, or a resin obtained by mixing them, and uses a resin that exhibits softening properties and adhesiveness when heated. Specifically, epoxy resin, polyamide resin, polyester resin, polyimide resin, maleimide resin, fluorine resin, urethane resin, polystyrene resin, acrylic resin, silicone resin, synthetic rubber resin, etc. It is formed by adding a curing agent, an inorganic filler, various coupling agents, and the like to one or a mixture of a plurality of resins.

【0013】次いで配線基板11の半導体チップを搭載
する側の面に2層シート17を加熱加圧してラミネート
する(図1(b))。
Next, the two-layer sheet 17 is laminated on the surface of the wiring substrate 11 on the side on which the semiconductor chip is mounted by heating and pressing (FIG. 1B).

【0014】次いで銅箔15及びソルダーレジスト14
の両面に感光性レジスト膜を形成し、パターン露光、レ
ジスト現像、銅エッチング及び感光性レジスト剥離の各
工程を経て導体端子18を形成する(図1(c))。こ
こで、ソルダーレジスト14の面に形成する感光性レジ
ストは導体配線12をエッチング液から保護する目的で
施されるものである。
Next, copper foil 15 and solder resist 14
A photosensitive resist film is formed on both sides of the substrate, and conductor terminals 18 are formed through the steps of pattern exposure, resist development, copper etching, and photosensitive resist peeling (FIG. 1C). Here, the photosensitive resist formed on the surface of the solder resist 14 is provided for the purpose of protecting the conductor wiring 12 from an etchant.

【0015】次いで導体端子18に表面処理19を施す
(図1(d))。これは銅酸化を防止し電気的接続性能
を高めるために成されるもので、Au、Ni、Pd、P
b、Sn、Inなどの金属及び合金を無電解メッキする
方法や、Pb−Sn合金であればフローソルダー法で行
うこともできる。以上のようにして、本発明の半導体搭
載用基板を得ることができる。
Next, a surface treatment 19 is applied to the conductor terminal 18 (FIG. 1D). This is done to prevent copper oxidation and to improve the electrical connection performance. Au, Ni, Pd, P
A method of electroless plating a metal or alloy such as b, Sn, In, or the like, or a Pb-Sn alloy by a flow solder method can be used. As described above, the semiconductor mounting substrate of the present invention can be obtained.

【0016】図2の(a)から(d)は本発明の半導体
搭載用基板を得るための製造方法の第2の実施例であ
る。
FIGS. 2A to 2D show a second embodiment of the manufacturing method for obtaining the semiconductor mounting substrate of the present invention.

【0017】まず、配線基板21を用意する(図2
(a))。配線基板21は第1の実施例に記載の構成か
ら成るフレキシブル配線基板、リジット配線基板及びセ
ラミックス配線基板を用いることができる。
First, a wiring board 21 is prepared (FIG. 2).
(A)). As the wiring board 21, a flexible wiring board, a rigid wiring board, and a ceramic wiring board having the configuration described in the first embodiment can be used.

【0018】次いで配線基板21の半導体チップを搭載
する側の表面に液状の接着性絶縁樹脂を、後で形成する
導体端子28と導体配線22とに挟まれる部位の接着性
絶縁樹脂26の厚さが導体端子28の厚さに後述の表面
処理29の厚さを加えた厚さの0.7〜1.5倍の範囲
に入るように塗布量を調整し、凹凸が発生しないように
塗布した後乾燥する(図2(b))。接着性絶縁樹脂2
6は第1の実施例に記載の樹脂を用いることができる。
また、接着性絶縁樹脂26の厚さが上記の範囲から外れ
た場合は第1の実施例に記載の問題を生じる。
Next, a liquid adhesive insulating resin is applied to the surface of the wiring substrate 21 on the side where the semiconductor chip is mounted, and the thickness of the adhesive insulating resin 26 at a portion sandwiched between the conductor terminals 28 and the conductor wiring 22 to be formed later. Was adjusted so that the thickness was in the range of 0.7 to 1.5 times the thickness of the conductor terminal 28 plus the thickness of the surface treatment 29 described later, and the coating was performed so that no unevenness was generated. After drying (FIG. 2 (b)). Adhesive insulating resin 2
6 can use the resin described in the first embodiment.
If the thickness of the adhesive insulating resin 26 is out of the above range, the problem described in the first embodiment occurs.

【0019】次いで前記接着性絶縁樹脂26の表面に、
スクリーン印刷により導電性ペーストを端子形状に印刷
し硬化して導体端子28を形成する(図2(c))。導
電性ペーストに配合される金属はCu、Ag、Au、S
n、Pb−Sn,In等の微粒が用いられる。以上のよ
うにして、本発明の半導体搭載用基板を得ることができ
る。
Next, on the surface of the adhesive insulating resin 26,
The conductive paste is printed in a terminal shape by screen printing and cured to form the conductor terminal 28 (FIG. 2C). Metals mixed in the conductive paste are Cu, Ag, Au, S
Fine particles such as n, Pb-Sn, and In are used. As described above, the semiconductor mounting substrate of the present invention can be obtained.

【0020】図3の(a)、(b)は本発明の半導体搭
載用基板に半導体チップを実装する方法の一実施例であ
る。
FIGS. 3A and 3B show an embodiment of a method for mounting a semiconductor chip on a semiconductor mounting substrate according to the present invention.

【0021】まず本発明による半導体搭載用基板32を
ボンディング装置の基板受け台34の所定の位置に置
く。次いでチップ吸着機構を有した加熱加圧ツール33
に半導体チップ31を吸着し、半導体搭載用基板32と
半導体チップ31に予め形成されてある位置決めマーク
を画像認識装置により読み取り導体端子35と電極36
を対向させ正確に位置合わせする。前記位置合わせと同
時に半導体チップ31を加熱加圧ツールを介し所定の温
度に加熱する(図3(a))。必要であれば基板受け台
34にヒーターを内蔵させ半導体搭載用基板も加熱して
おいて接着性絶縁樹脂37を予め軟化させておいてもよ
い。さらに、導体端子35と電極36の接合金属材料の
組み合わせによっては超音波を併用しより高い接続性を
得ることも可能である。
First, the semiconductor mounting substrate 32 according to the present invention is placed at a predetermined position on the substrate receiving base 34 of the bonding apparatus. Next, a heating and pressing tool 33 having a chip suction mechanism
The semiconductor chip 31 is adsorbed onto the semiconductor chip 31 and the positioning mark formed in advance on the semiconductor mounting substrate 32 and the semiconductor chip 31 is read by an image recognition device using a conductor terminal 35 and an electrode 36
Face each other for accurate positioning. Simultaneously with the alignment, the semiconductor chip 31 is heated to a predetermined temperature via a heating and pressing tool (FIG. 3A). If necessary, a heater may be incorporated in the substrate receiving base 34 to heat the semiconductor mounting substrate, and the adhesive insulating resin 37 may be softened in advance. Further, depending on the combination of the joining metal material of the conductor terminal 35 and the electrode 36, it is also possible to obtain higher connectivity by using ultrasonic waves together.

【0022】次いで加熱加圧ツール33を降下させ半導
体チップ31を半導体搭載用基板32に所定の圧力で平
行に押し付ける。導体端子35と電極36が接触した時
点で半導体チップ31の熱が導体端子35を介し接着性
絶縁樹脂37に伝達しこれを軟化すると同時に、導体端
子35は接着性絶縁樹脂37を貫通し、その底部が半導
体搭載用基板32の接続端子に接続される。さらに所定
の時間だけ加熱加圧を維持することで半導体チップ31
と半導体搭載用基板32は接着性絶縁樹脂37によって
固着される(図3(b))。以上のようにして、半導体
チップ31は半導体搭載用基板32に電気的かつ機械的
に実装される(図3(c))。
Next, the heating / pressing tool 33 is lowered, and the semiconductor chip 31 is pressed against the semiconductor mounting substrate 32 in parallel with a predetermined pressure. When the conductor terminals 35 and the electrodes 36 come into contact with each other, the heat of the semiconductor chip 31 is transmitted to the adhesive insulating resin 37 via the conductor terminals 35 and softened, and at the same time, the conductor terminals 35 penetrate the adhesive insulating resin 37 and The bottom is connected to the connection terminal of the semiconductor mounting substrate 32. Further, by maintaining the heating and pressurizing for a predetermined time, the semiconductor chip 31
And the semiconductor mounting substrate 32 are fixed by an adhesive insulating resin 37 (FIG. 3B). As described above, the semiconductor chip 31 is electrically and mechanically mounted on the semiconductor mounting substrate 32 (FIG. 3C).

【0023】[0023]

【発明の効果】以上詳述したように、本発明によれば半
導体チップとの電気的及び機械的接続の機能を有する半
導体搭載用基板を低コストで製造提供することができ、
さらに、容易で生産性に優れた実装方法をも提供するこ
とができる。
As described above in detail, according to the present invention, a semiconductor mounting substrate having an electrical and mechanical connection function with a semiconductor chip can be manufactured and provided at low cost.
Furthermore, an easy and highly productive mounting method can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による半導体搭載用基板の製造方法の
第1の実施例
FIG. 1 shows a first embodiment of a method for manufacturing a semiconductor mounting substrate according to the present invention.

【図2】本発明による半導体搭載用基板の製造方法の第
2の実施例
FIG. 2 is a second embodiment of the method for manufacturing a semiconductor mounting substrate according to the present invention;

【図3】本発明による半導体搭載用基板を用いた実装方
法の一実施例
FIG. 3 shows an embodiment of a mounting method using a semiconductor mounting substrate according to the present invention.

【図4】従来の導電性微粒子を分散した異方導電シート
を用いた半導体チップの一実装例
FIG. 4 shows a mounting example of a conventional semiconductor chip using an anisotropic conductive sheet in which conductive fine particles are dispersed.

【図5】従来の貫通穴に導電体を充填した異方導電シー
トを用いた半導体チップの一実装例
FIG. 5 is a mounting example of a conventional semiconductor chip using an anisotropic conductive sheet in which a conductor is filled in a through hole.

【符号の説明】[Explanation of symbols]

11、21:配線基板 12、22:導体配線 13、23:絶縁樹脂 14、24:ソルダーレジスト 15:銅箔 16、26、37:接着性絶縁樹脂 17:2層シート 18、28、35:導体端子 19、29:表面処理 31、41、51:半導体チップ 32、42、52:半導体搭載用基板 33:加熱加圧ツール 34:基板受け台 36、44、54:電極 43:導電性微粒子を分散した異方導電シート 45:導電性微粒子 53:貫通穴を導電体で充填した異方導電シート 55:導電体 11, 21: Wiring board 12, 22: Conductor wiring 13, 23: Insulating resin 14, 24: Solder resist 15: Copper foil 16, 26, 37: Adhesive insulating resin 17: Two-layer sheet 18, 28, 35: Conductor Terminals 19, 29: Surface treatment 31, 41, 51: Semiconductor chip 32, 42, 52: Semiconductor mounting substrate 33: Heating / pressing tool 34: Substrate receiving base 36, 44, 54: Electrode 43: Disperse conductive fine particles Anisotropic conductive sheet 45: Conductive fine particles 53: Anisotropic conductive sheet having through holes filled with a conductor 55: Conductor

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップをフリップチップ接続で搭
載する半導体搭載用基板において、配線基板の半導体チ
ップを搭載する側の面に、加熱で軟化し接着性を発現す
る接着性絶縁樹脂が形成されているとともに、前記接着
性絶縁樹脂上の半導体チップの電極と配線基板の導体配
線とを接続する位置に独立した導体端子が形成されてい
ることを特徴とする半導体搭載用基板。
1. A semiconductor mounting substrate on which a semiconductor chip is mounted by flip-chip connection, wherein an adhesive insulating resin which is softened by heating and exhibits adhesiveness is formed on a surface of the wiring substrate on a side on which the semiconductor chip is mounted. A semiconductor mounting substrate, wherein independent conductive terminals are formed at positions connecting the electrodes of the semiconductor chip on the adhesive insulating resin and the conductive wiring of the wiring substrate.
【請求項2】 導体端子の厚さが、その直下に形成され
る加熱で軟化性及び接着性を発現する接着性絶縁樹脂の
厚さの0.7〜1.5倍の範囲であることを特徴とする
請求項1記載の半導体搭載用基板。
2. The method according to claim 1, wherein the thickness of the conductor terminal is in the range of 0.7 to 1.5 times the thickness of the adhesive insulating resin which develops softness and adhesiveness by heating formed immediately below. The substrate for mounting a semiconductor according to claim 1, wherein:
【請求項3】 導体配線を形成した配線基板の半導体チ
ップを搭載する側の面に、銅箔と加熱で軟化性及び接着
性を発現する接着性絶縁樹脂から成る2層シートを加熱
加圧して貼り合わせる工程と、前記2層シートの銅箔を
選択的にエッチングして導体端子を形成する工程を有す
ることを特徴とする半導体搭載用基板の製造方法。
3. A two-layer sheet made of a copper foil and an adhesive insulating resin exhibiting softness and adhesiveness by heating is heated and pressed on the surface of the wiring board on which the semiconductor chip is mounted, on which the conductive wiring is formed. A method of manufacturing a substrate for mounting a semiconductor, comprising a step of bonding and a step of forming conductive terminals by selectively etching the copper foil of the two-layer sheet.
【請求項4】 導体配線を形成した配線基板の半導体チ
ップを搭載する側の面に、加熱で軟化性及び接着性を発
現する接着性絶縁樹脂を塗布し乾燥する工程と、前記接
着性絶縁樹脂上に導電性ペーストを印刷し硬化して導体
端子を形成する工程を有することを特徴とする半導体搭
載用基板の製造方法。
4. A step of applying an adhesive insulating resin exhibiting softness and adhesiveness by heating to a surface of the wiring board on which the semiconductor chip is mounted on which the conductor wiring is formed, and drying the applied adhesive insulating resin. A method of manufacturing a substrate for mounting a semiconductor, comprising a step of printing a conductive paste thereon and curing the same to form a conductor terminal.
【請求項5】 請求項1記載の半導体搭載用基板の導体
端子とこれに搭載する半導体チップの電極とを対向させ
位置合わせする工程と、半導体チップを裏面から加熱し
ながら前記半導体搭載用基板に平行に押し付け導体端子
を接着性絶縁樹脂に垂直に埋没貫通させ前記半導体搭載
用基板の接続端子に接続させるとともに半導体チップも
同時に接着する工程を有する半導体チップの実装方法。
5. A step of positioning the conductor terminals of the semiconductor mounting substrate according to claim 1 so as to face the electrodes of the semiconductor chip mounted thereon, and positioning the conductor terminals on the semiconductor mounting substrate while heating the semiconductor chip from the back surface. A method of mounting a semiconductor chip, comprising the steps of: pressing a conductor terminal in parallel, vertically penetrating and penetrating an adhesive insulating resin, connecting the terminal to the connection terminal of the semiconductor mounting substrate, and simultaneously bonding the semiconductor chip.
JP31672697A 1997-11-18 1997-11-18 Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip Pending JPH11150150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31672697A JPH11150150A (en) 1997-11-18 1997-11-18 Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31672697A JPH11150150A (en) 1997-11-18 1997-11-18 Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH11150150A true JPH11150150A (en) 1999-06-02

Family

ID=18080227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31672697A Pending JPH11150150A (en) 1997-11-18 1997-11-18 Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH11150150A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11330161A (en) * 1998-05-18 1999-11-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP2006121042A (en) * 2004-09-21 2006-05-11 Seiko Instruments Inc Manufacturing method of semiconductor device
KR20210006436A (en) 2018-05-25 2021-01-18 미쓰비시 세이시 가부시키가이샤 Manufacturing method of pattern transfer material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11330161A (en) * 1998-05-18 1999-11-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP2006121042A (en) * 2004-09-21 2006-05-11 Seiko Instruments Inc Manufacturing method of semiconductor device
KR20210006436A (en) 2018-05-25 2021-01-18 미쓰비시 세이시 가부시키가이샤 Manufacturing method of pattern transfer material

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