JPH11134892A - Internal potential generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal potential generating circuit which can output a plurality of internal potentials while the increase of a circuit area is suppressed. SOLUTION: In an internal potential generating circuit 200, in the initial stage of its operation, a high voltage switching circuit 218 is in a continuity state to keep the common potential level between the output node NH1 of a 1st step-up circuit 202 and the output node NH2 of a 2nd step-up circuit for operation. After an output potential level from the 2nd step-up circuit 204 reaches a predetermined potential level, the high voltage switching circuit 218 is in a cut-off state and the 1st step-up circuit 202 and the 2nd step-up circuit 204 drive potential levels corresponding to the respective output nodes independently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal potential generating circuit mounted on a semiconductor integrated circuit device and receiving an external power supply potential and generating an internal potential. More specifically, the present invention relates to an internal potential generation circuit that generates an internal potential required for data writing and erasing operations to a nonvolatile memory element upon receiving an external power supply potential in a nonvolatile semiconductor memory device or the like.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, particularly in a nonvolatile semiconductor memory device such as a flash memory, storage data is written to a memory cell transistor having a floating gate by a tunnel current or the like. Therefore, generally, an external power supply voltage (for example, Vcc =
It is necessary to generate a voltage higher than 3.3 V) on the chip.

[0003] In addition to the nonvolatile semiconductor memory device,
For example, a dynamic semiconductor memory device (hereinafter, DRA)
M), when the sense amplifier is shared by the left and right bit line pairs, the gate voltage of the bit line isolation transistor that opens and closes the connection between the sense amplifier and the left and right bit line pairs is sufficient. It is necessary to apply a boosted potential. That is, when the boosted voltage is not applied, the data is written to the memory cell even when the bit line isolation transistor is turned on in the data writing operation to the memory cell or the data rewriting operation in the refresh operation. The potential level of the "H" level data is reduced by the threshold voltage of the data line isolation transistor.

In a data output circuit, for example,
Since a large current flows through the output transistor, an N-channel MOS transistor is generally used to avoid CMOS latch-up. In this case, it is necessary to avoid a decrease in the charging speed for a load due to a decrease in the potential of the output transistor by the threshold voltage. Therefore, the gate potential of the N-channel MOS output transistor also needs to be driven at the boosted potential.

In a nonvolatile semiconductor memory device such as a flash memory, as described later, in a writing operation or an erasing operation, a negative potential is applied to a control gate, a source line, and a substrate in accordance with an operation mode. Must be applied.

In general, DRAMs and the like also require C
Improve the latch-up resistance of MOS circuits,
In general, a negative potential is applied to the substrate side in order to suppress a variation in the threshold value of the transistor.

In this case, it is necessary to generate a negative potential from a single power supply potential (for example, Vcc = 3.3 V) supplied from the outside.

When an internal potential higher than the external power supply potential or a negative internal potential is generated as described above, a charge pump circuit is generally used.

FIG. 19 is a circuit diagram showing a main part of a conventional charge pump circuit 2000 for generating a positive internal high potential.

Charge pump circuit 2000 includes an output node N _{H to} which a positive internal high potential is to be output, and a power supply potential V _H.
cc and N-channel MOS transistors Q1-Q7, each of which is connected in series with each other and diode-connected.
And capacitors C1 to C6 each having one end connected to the gate of each of the transistors Q2 to Q7. A clock signal PH is applied to the other ends of the capacitors C1, C3 and C5, and a signal / PH of a clock signal complementary (non-overlapping) to the clock signal PH is applied to the other ends of the capacitors C2, C4 and C6. The configuration is given.

FIG. 20 shows the transistor Q shown in FIG.
It is a schematic diagram which shows the cross-section of 1-Q7. Since the gate electrode and the source are commonly connected, the configuration is equivalent to a diode having a forward direction from the source side to the drain side.

FIG. 21 is a diagram showing an equivalent circuit of the circuit shown in FIG. FIG. 22 is a timing chart showing a time change of clock signals PH and / PH.

Referring to FIGS. 21 and 22, the operation of charge pump circuit 2000 will be briefly described.

The potential of a node to which the signal PH and the signal / PH are coupled via a capacitor rises and falls in synchronization with the signal PH and the signal / PH.

Therefore, referring to FIG. 22, at time t1
When signal PH attains "H" level (Vcc level) and signal / PH changes to "L" level (GND level), the potential levels of nodes N1, N3 and N5 rise, and nodes N2, N4 and The potential of N6 is a signal /
Try to decrease according to PH.

However, the nodes N1 and N
2, a diode is connected between the nodes N3 and N4 and between the nodes N5 and N6, so that a forward current flows from the node N1 to the node N2 via the diode Q2. Similarly, a diode Q4 is connected from node N3 to node N4.
Through a diode Q from node N5 to node N6.
6, forward currents respectively flow. For this reason,
In the period from time t1 to time t2, nodes N2 and N4
And N6 do not drop significantly.

Next, at time t2, signal PH changes to "L" level and signal / PH changes to "H" level. As in the case of the time t1 to the time t2, the node N
1 is from the power supply potential Vcc to the diode Q1.
Does not decrease as much as the decrease in the signal PH due to the current flowing through. Similarly, the nodes N3 and N5
Does not decrease as much as the decrease in signal PH due to currents flowing from nodes N2 and N4 via diodes Q3 and Q5, respectively.

By repeating such an operation,
A potential level sufficiently higher than internal power supply potential Vcc is output to output node Nh.

[0019]

The diode of the charge pump circuit 2000 shown in FIG. 19 is constituted by connecting the source and the gate of a MOS transistor. In this case, the potential difference at which the voltage can be boosted is represented by the following equation.

(Amplitude of signal given as pulse−threshold of MOS transistor) × number of stages (1) On the other hand, in a steady state, charge pump circuit 200
The supply current I _OUT output from 0 is represented by the following equation.

I _OUT = f × (C + Cs) × V ₁ (2) where f is the frequency of the clock signal supplied to the charge pump circuit, and C is the capacitance value of the coupling capacitors C1 to C6. Cs is a parasitic capacitance, and _VL represents a voltage amplitude when the coupling capacitor is charged and discharged.

According to the equation (2), it is understood that the output current increases as the sum C of the capacitances of the coupling capacitors C1 to C6 increases.

In the transient state, the larger the output current, the faster the load capacity can be charged.

Next, the operation of a nonvolatile semiconductor memory device, such as a flash memory, which operates using the above-described internal potential generating circuit will be described.

FIG. 23 is a schematic cross-sectional view for explaining the configuration of a floating gate type transistor constituting a memory cell of a conventional nonvolatile semiconductor memory device and the potential of each part in writing and erasing operations on the transistor.
(A) shows the case of the writing operation, and (b) shows the case of the erasing operation.

Referring to FIG. 23, the memory cell transistor includes, for example, an n-type drain region 1502 and an n-type source region 1 formed on the surface of p-type semiconductor substrate 1500.
A floating gate 1506 formed on a channel region between the drain region 1502 and the source region 1504 via a thin tunnel oxide film (for example, film thickness = 10 nm);
The control gate 15 stacked on the insulating film 506 via an insulating film
08.

The drain region 1502 has a bit line BL
Is connected to the source region 1504 and the source line SL
A predetermined potential is selectively supplied via a not shown (not shown), or a floating state is provided.

The conductivity (conductance) between the source and the drain is applied according to the potential applied to the control gate. In the above configuration, the channel conductance increases as the potential applied to the control gate increases. That is, when the potential of the control gate is increased while a predetermined voltage is applied between the drain and the source, the current Ids flowing between the source and the drain also increases.

Here, the control gate potential at which the current Ids starts to flow between the source and the drain by increasing the potential of the control gate is called a cell threshold.

This cell threshold value increases as electrons accumulate in floating gate 1506 from an electrically neutral state of floating gate 1506.

In other words, the floating gate 150
As the electrons are accumulated in 6, the current does not flow between the source and the drain unless a higher voltage is applied to the control gate.

Since the floating gate is literally electrically isolated from the outside by an insulating film, information is stored in a nonvolatile manner by the stored electrons. Therefore, in a state where data is written in the memory cell, when a predetermined potential difference, for example, 1 V, is applied between the sort drains and a constant potential, for example, 3 V is applied to control gate 1508, the potential between the source and drain is reduced. The data written in the memory cell is determined based on whether or not the current flows.

FIG. 24 shows a case where data is applied to bit line BL, control gate 1508, source line SL and substrate 1500 when data is written to the memory cell, when data is erased, and when data is read. FIG. 4 is a diagram illustrating an example of potentials to be applied.

[Write Operation] Referring to FIG. 23A and FIG. 13, the write operation will be briefly described first.

Writing of data to the memory cell is performed by extracting accumulated electrons from floating gate 1506.

That is, assuming that power supply voltage Vcc is applied to control gate 1508 at the time of data reading, the cell threshold value in the written state is set to 0 V or more.
c is set to be less than or equal to c.

In general, the potential level of control gate 1508 of a non-selected memory cell is maintained at 0 V, and control gate 1508 of a selected memory cell has power supply potential Vcc.
Is held. Therefore, when the cell threshold value is set as described above, when data is written in the selected memory cell, the floating gate transistor constituting the memory cell has a current between the source and the drain. Will flow.

In writing data, for example, a potential of 5 V is applied to the bit line, a potential of -8 V is applied to the control gate,
A potential of 0 V is applied to the substrate, and the source line SL is set in a floating state.

When the potential is thus set, electrons are extracted from the floating gate 1506 to the drain region 1502. That is, the cell threshold value decreases.

[Erase Operation] Next, FIG. 12B and FIG.
The erase operation will be described with reference to FIGS.

In the erasing operation, as an example, the bit line BL is set in a floating state, the potential of the control gate 1508 is set to 10 V, the potential of the source line SL is set to -8 V, and the potential of the substrate 1500 is set to -8 V.

In this case, electrons are injected from the substrate 1500 side, that is, the channel region to the floating gate 1506 toward the control gate 1508 which is biased to the positive side.

That is, electrons are accumulated in the floating gate 1506, and the cell threshold value increases.

Therefore, as described above, in the read operation, the potential of the bit line BL is set to 1 V and the control gate 15
08 to 3 V, source line SL and substrate 1500
Is 0 V, no current flows between the source and drain when an erased memory cell is selected.

As described above, the cell threshold value can be changed by injecting or extracting electrons into or from floating gate 1506, and it is determined whether or not a current flows through a selected memory cell in a read operation. Then, the stored data can be read.

In writing, erasing and reading data to and from the memory cells of the flash memory as described above, a plurality of different levels of high voltages are required. That is, with respect to the external power supply potential of 3 V, 5 V is applied to the bit line at the time of writing, and 10 V is applied to the control gate at the time of erasing.
V is applied.

If a charge pump circuit corresponding to each of these voltages is mounted on a chip of a nonvolatile semiconductor memory device, the circuit area increases.
As a result, the chip area is increased.

Exactly the same applies to the case where a negative potential is generated. That is, in the example shown in FIG. 24, only one kind of potential level of -8 V is required as the negative potential. However, in order to optimize the circuit operation and the like, the negative potential level is also plural. May need to be generated.

Also in this case, if the charge pump circuits are respectively mounted in the chip to generate the respective negative potentials, the chip area increases.

Further, as disclosed in Japanese Patent Application Laid-Open No. 5-182481, for example, in order to narrow the threshold distribution range of memory cells in an erase operation mode and to rewrite memory cell data easily and in a short time. In some cases, after the erase pulse is applied, an erase operation in which the amount of change in the threshold value of a memory cell equal to or less than a predetermined threshold value becomes small is performed. That is, by setting the voltage (for example, 10 V) applied to the control gate of the memory cell transistor at the time of writing after erasing to be smaller than the voltage (for example, 12 V) applied at the time of normal writing, By gradually changing the threshold voltage, the controllability of the threshold voltage can be improved.

Also in such a case, at least two types of high voltages higher than the external power supply voltage are required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the circuit area and to generate an internal potential capable of generating a plurality of necessary internal potentials. It is to provide a generating circuit.

Another object of the present invention is to provide an internal potential generating circuit capable of rapidly charging a load capacitance corresponding to a plurality of internal potentials.

[0054]

An internal potential generating circuit according to claim 1 receives an external power supply potential and receives a first predetermined internal potential and a second predetermined potential which is smaller in absolute value than the first predetermined internal potential. An internal potential generating circuit for generating a predetermined internal potential, a clock generating means for outputting clock signals complementary to each other, and a first internal potential for outputting a first predetermined internal potential.
Output node, and the first node is provided in response to a complementary clock signal.
Driving the potential of the first output node with the current supply amount of
And a second output node to which a second predetermined internal potential is to be output, and a second current supply amount smaller than the first current supply amount according to a complementary clock signal. A second charge pump means for driving the potential of the second output node, a switch means for setting the connection between the first output node and the second output node to one of a conductive state and a cut-off state, Control means for controlling supply of complementary clock signals to the first charge pump means and the second charge pump means in accordance with the potential level of the output node and the potential level of the second output node, respectively. The means changes the switch means from the conductive state to the cut-off state in response to the potentials of the first and second output nodes reaching the second predetermined potential.

According to a second aspect of the present invention, in the internal potential generating circuit of the first aspect, the first predetermined internal potential and the second predetermined internal potential are both positive potentials. The control means supplies the complementary clock signal to the first charge pump means so that the potential level of the first output node becomes the first predetermined internal potential after the switch means is turned off. And the supply of a complementary clock signal to the second charge pump means is controlled such that the potential level of the second output node becomes the second predetermined internal potential.

According to a third aspect of the present invention, in the configuration of the first aspect, the first predetermined internal potential and the second predetermined internal potential are both positive potentials. The control means supplies the complementary clock signal to the first charge pump means so that the potential level of the first output node becomes the first predetermined internal potential after the switch means is turned off. After the first internal control means for controlling the voltage and the switch means are turned off, the second charge pump means is controlled so that the potential level of the second output node becomes the second predetermined internal potential. Second internal control means for controlling supply of a complementary clock signal.

According to a fourth aspect of the present invention, in the configuration of the internal potential generating circuit of the second aspect, the control means includes a first charge pump means and a second charge pump means in response to the start of the operation of the internal potential generating circuit. The supply of complementary clock signals to both of the two charge pump means is started.

According to a fifth aspect of the present invention, in the configuration of the internal potential generating circuit according to the third aspect, the second internal control means controls that the potential level of the second output node is the second predetermined internal level. When the potential becomes equal to or higher than the potential, the internal control signal is deactivated, the switch means is set in response to the deactivation of the internal control signal, and is reset in response to the stop of the operation of the internal potential generating circuit. Means for connecting the first output node to the second output node when the latch means is set to the set state.

According to a sixth aspect of the present invention, in the internal potential generating circuit of the second aspect, the control means is complementary to the first charge pump means in response to the start of the operation of the internal potential generating circuit. Supply of a complementary clock signal to the second charge pump means after the switching means is turned off.

According to a seventh aspect of the present invention, in the configuration of the internal potential generating circuit of the third aspect, the second internal control means controls that the potential level of the second output node is the second predetermined internal level. Switch means including potential level detection means for inactivating an internal control signal in response to the potential or more, and clock supply control means for controlling supply of a complementary clock signal to the second charge pump means A latch means which is set in response to the inactivation of the internal control signal and which is reset in response to the stoppage of the operation of the internal potential generating circuit; and
A connection unit that disconnects a connection between the first output node and the second output node, wherein the clock supply control unit includes:
In response to the internal control signal being active and the latch being in the set state, the supply of the complementary clock signal is started.

According to an eighth aspect of the present invention, in the configuration of the first aspect, the first predetermined internal potential and the second predetermined internal potential are both negative potentials. The control means supplies the complementary clock signal to the first charge pump means so that the potential level of the first output node becomes the first predetermined internal potential after the switch means is turned off. And the supply of a complementary clock signal to the second charge pump means is controlled such that the potential level of the second output node becomes the second predetermined internal potential.

According to a ninth aspect of the present invention, in the configuration of the internal potential generating circuit of the first aspect, the first predetermined internal potential and the second predetermined internal potential are both negative potentials. The control means supplies the complementary clock signal to the first charge pump means so that the potential level of the first output node becomes the first predetermined internal potential after the switch means is turned off. After the first internal control means for controlling the voltage and the switch means are turned off, the second charge pump means is controlled so that the potential level of the second output node becomes the second predetermined internal potential. Second internal control means for controlling supply of a complementary clock signal.

According to a tenth aspect of the present invention, in the configuration of the internal potential generating circuit of the eighth aspect, the control means includes a first charge pump means and a second charge pump means in response to the start of the operation of the internal potential generating circuit. The supply of complementary clock signals to both of the two charge pump means is started.

According to an eleventh aspect of the present invention, in the configuration of the internal potential generating circuit of the ninth aspect, the second internal control means includes a second internal control means for setting the potential level of the second output node to the second level.
The internal control signal is deactivated when the internal potential becomes equal to or lower than the predetermined internal potential, the switch means is set in response to the inactivation of the internal control signal, and reset in response to the stop of the operation of the internal potential generating circuit. And a connection unit that disconnects the connection between the first output node and the second output node when the latch unit is set.

According to a twelfth aspect of the present invention, in the configuration of the internal potential generating circuit of the eighth aspect, the control means is complementary to the first charge pump means in response to the start of the operation of the internal potential generating circuit. Supply of a complementary clock signal to the second charge pump means after the switching means is turned off.

According to a thirteenth aspect of the present invention, in the configuration of the internal potential generating circuit of the ninth aspect, the second internal control means includes a second internal control means for setting the potential level of the second output node to the second level.
A potential level detecting means for inactivating the internal control signal in response to the internal potential being equal to or less than a predetermined internal potential, and a clock supply controlling means for controlling supply of a complementary clock signal to the second charge pump means. The switch means is set in response to the inactivation of the internal control signal, and is set to a reset state in response to the stoppage of the operation of the internal potential generating circuit. Connection means for disconnecting the connection between the first output node and the second output node, wherein the clock supply control means determines that the internal control signal is in an active state and the latch means is in a set state. Accordingly, the supply of the complementary clock signal is started.

[0067]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a schematic block diagram showing a configuration of a nonvolatile semiconductor memory device 1000 according to a first embodiment of the present invention.

Referring to FIG. 1, nonvolatile semiconductor memory device 1000 receives external address signals A0 to Ai, and receives a corresponding internal row address signal Ax, a corresponding internal column address signal Ay, and a source address Asl. And an address buffer 102 that outputs a select gate address signal Asg, a memory cell array 104 in which memory cells are arranged in a matrix, and an internal row address signal Ax from the address buffer 102, and the corresponding memory cell array 104 X decoder 1 for selecting a row (word line)
06, and a Y decoder 108 which receives an internal column address signal Ay from the address buffer 102 and selects a corresponding column of the memory cell array 104.

Here, memory cell array 104 includes two memory cell array blocks BLK0 and BLK1. In the example shown in FIG. 1, for the sake of simplicity, one memory cell array block BLK0 or BLK1 includes four memory cell transistors, and each memory cell array block BLK0 has a memory cell whose drain is connected to sub-bit line SBL1. Transistors MC1a and MC1b and memory cell transistors MC2a and MC2b each having a drain connected to sub-bit line SBL2
And a selection gate SG1 for opening and closing the connection between the main bit line BL1 and the sub-bit line SBL1, and a selection gate SG2 for opening and closing the connection between the main bit line BL2 and the sub-bit line SBL2.

Memory cell transistors MC1a and M
The control gates of C2a are both connected to word line WL1,
The control gates of the memory cell transistors MC1b and MC2b are connected to the word line WL2.

Similarly, in memory cell array block BLK1, memory cell transistors MC3a and MC3b each having a drain connected to sub-bit line SBL3,
Sub bit line SBL4 and memory cell transistors MC4a and MC4b each connected to a drain are included.

The memory cell array block BLK1 further includes a selection gate SG3 for opening and closing the connection between the main bit line BL1 and the sub bit line SBL3, and a selection gate SG4 for opening and closing the connection between the main bit line BL2 and the sub bit line SBL4.
And

Memory cell transistors MC3a and MC4
The control gate a is connected to the word line WL3, and the control gates of the memory cell transistors MC3b and MC4b are connected to the word line WL4.

The X decoder 106 has the address buffer 1
02 according to the internal row address signal Ax given from
One of the corresponding word lines WL1 to WL4 is selected.

Non-volatile semiconductor memory device 1000 further includes a high voltage generating circuit 110 which receives an external power supply voltage and generates a high voltage required for data writing or erasing operation to a memory cell, and an external power supply voltage Vcc. Receiving the outputs of the negative voltage generating circuit 112 and the high voltage generating circuit 110 and the negative voltage generating circuit 112 for generating a negative voltage necessary for a write or erase operation to the memory cell array, Corresponding select gates SG1 to SG4
Select gate decoder 114 for selectively connecting the sub-bit line and the main bit line, and receiving the output of negative voltage generating circuit 112 and receiving the output of negative voltage generation circuit 112 to select the source of the memory cell transistor. A source decoder for selectively supplying a predetermined source potential; and a well potential drive circuit for receiving an output of the negative voltage generation circuit and controlling a well potential on a semiconductor substrate surface on which a memory cell transistor is formed. .

The X decoder 106 is connected to the high voltage generation circuit 11
In response to 0 and the output of the negative voltage generation circuit 112, a predetermined negative voltage is supplied to a selected word line in a writing operation, and a high voltage is supplied to a selected word line in an erasing operation.

Nonvolatile semiconductor memory device 1000 further includes a write / erase control circuit 122 for controlling a write operation and an erase operation for a memory cell, and an internal circuit for receiving data from the inside, or for a memory cell. Data input / output buffer 124 for receiving read data and outputting it to outside
And a data driver 126 for receiving write data input to data input / output buffer 124 and driving a corresponding bit line potential, and a bit line BL for reading data.
1 or BL2, according to the storage information of the selected memory cell, according to the storage information of the selected memory cell, and receives and holds the write data from data driver 126 according to the storage data of high voltage generation circuit 110 Circuit to supply a high voltage from bit line to a corresponding bit line, and verify potential V to X decoder 106 during a verify operation.
And a verify voltage generating circuit 100 for supplying PVRF.

Here, the verify operation means that when writing is performed on a memory cell, the threshold value of the memory cell is
This means an operation for confirming whether or not the potential level has reached a predetermined level.

The data driver 126 and the sense amplifier 128 are connected to the column selection gate SL for the bit line BL1.
The bit line BL2 is connected to the bit line BL2 through a column selection gate SLG2 via G1, and the selection gates SLG1 and S
The gate potential of LG2 is controlled by Y decoder 108. Therefore, the selected bit line is connected to the sense amplifier 128 or the data driver 126 according to the internal column address signal Ay from the address buffer 102.

In the above configuration, the bit lines have a hierarchical structure composed of main bit lines and sub-bit lines for the following reason.

That is, the memory cell transistors MC1a and MC1b in the memory cell array block BLK0 and the memory cell array block BL are connected to one bit line BL1.
When the memory cell transistors MC3a and MC3b of K1 are connected at the same time, for example, when writing data only to the memory cells in memory cell array block BLK0, the memory in memory cell array block BLK1 can be used. High voltage is also applied to the drain of the cell transistor. Therefore, the amount of charge in the floating gate of the memory cell transistor in the memory cell array block BLK1 changes during data writing to the adjacent memory cell array block BLK0, and in the worst case, the written data changes. Problem.

As a countermeasure against the above problem, a bit line may be separately provided for each memory cell array block to which data is written. That is, the main bit lines BL1, BL2
The main bit line connects all the memory cell array blocks, and the sub-bit lines SBL1 to SBL4 connect the memory cell transistors in each memory cell array block.

The main bit lines BL1 and BL2 and the sub bit line S
BL1 to SBL4, select gates SG1 to SG
4, and in a write operation, an unselected memory cell array block is electrically disconnected from the main bit line by this select gate.

By doing so, it is possible to prevent the influence on the memory cell transistors of another memory cell array block during rewriting of one memory cell array block.

Hereinafter, of the configuration of the nonvolatile semiconductor memory device 1000 shown in FIG. 1, the configuration of the high voltage generating circuit 200 or the negative voltage generating circuit 400 will be described in more detail.

FIG. 2 is a circuit diagram of the high voltage generating circuit 20 shown in FIG.
FIG. 4 is a schematic block diagram showing the configuration of the ０0 ’in more detail.

The high voltage generation circuit 200 is controlled by the control circuit 122 shown in FIG. 1 to output the boosted potential Vpp1 to the output node N _H1 , and the control circuit 122 The second booster circuit 204 that outputs the second boosted voltage Vpp2 to the second output node N _H2 , and is controlled by the control circuit 122 and the second booster circuit 204 to output the first output node N _H1 and the second Output node N of
A high-voltage switch circuit 218 for turning on or off the connection to _H2 and a clock generator for outputting complementary clock signal CLK and clock signal / CLK in response to the start of operation of high-voltage generating circuit 200 Circuit 22
0 is included.

The first booster circuit 202 includes the control circuit 12
2 starts the operation in response to the first detection circuit activation signal DE1 from the first detection node activation signal DE1, and the first clock activation signal PE in response to the potential level Vpp1 output to the first output node N _H1.
1 in an active state or an inactive state, and a clock signal CLK and / or
CLK, which is controlled by signal PE1, outputs first drive clock signals PH1 and / PH1 complementary to each other, and clock gate circuit 210 driven by signals PH1 and / PH1 to apply potential Vpp1 to output node N. _And a first charge pump circuit 214 for outputting to _H1 . Second booster circuit 204 is controlled by the second detection circuit activation signal DE2 output from the control circuit 122 starts operating in response to the potential Vpp2 output to the output node N _H2, complementary to each other High voltage level detection circuit 208 for outputting second clock activation signal PE2 and signal / PE2, and clock signals CLK and / CLK
In response to this, clock gate circuit 212 controlled by signal PE2 to output second driving clock signals PH2 and / PH2 complementary to each other, and signals PH2 and / P
Driven by _H2 , the potential Vpp2 is applied to the output node N _H2.
And a second charge pump circuit 216 for outputting the same.

The high voltage switch circuit 218 outputs the signal DE2
When the high voltage generation circuit 200 starts operating under the control of the signal / DE2 which is a signal complementary to the above and the signal / PE2 output from the high voltage level detection circuit 208,
The connection between the output node N _H1 and the output node N _H2 is made conductive, and as the potential level of the second output node N _H2 becomes a predetermined potential level, the first output node N _H1 and the second The connection to the output node N _H2 is cut off.

Here, the first charge pump circuit 214
Is a conventional charge pump circuit 2000 shown in FIG.
The second charge pump circuit 216 has a smaller number of diode-connected transistors connected in series than the first charge pump circuit 214, as described later. Shall be.

That is, the second charge pump circuit 21
6, the current supply amount is smaller than the supply current amount of the first charge pump circuit 214 in accordance with Expression (2).

The clock generation circuit 220 outputs the signal D
In response to activation of either E1 or signal DE2, the operation is started and clock signal CLK and clock signal / C
LK is output.

FIG. 3 is a schematic block diagram showing a configuration of high voltage level detection circuit 206 shown in FIG.

The configuration of the high voltage level detection circuit 208 is basically the same as the configuration of the high voltage level detection circuit 206 except that the input signal is different. Therefore, only the configuration of the high voltage detection circuit 206 will be described in detail below.

The high voltage level detection circuit 206 detects the potential Vp
It includes resistors R1 and R2 connected in series with each other between p1 and the ground potential. From the connection node n1 of the resistors R1 and R2, a potential level Vmon obtained by dividing the potential Vpp1 by these resistance ratios is output.

The high voltage level detection circuit 206 further includes
A current mirror type differential amplifier circuit 2062, which is activated in response to activation of signal DE1 (change to “H” level) and receives a predetermined reference potential Vref and potential Vmon to amplify the potential difference, and a current mirror Between the output node n2 of the differential amplifier and the power supply potential Vcc.
A p-channel MOS transistor Q16 which is turned on in response to inactivation of E1 (change to "L" level), p connected in series between power supply potential Vcc and ground potential.
Channel MOS transistor Q17, n-channel MOS
It includes a transistor Q18 and an n-channel MOS transistor Q19.

It is assumed that the gates of transistors Q17 and Q18 are both connected to node n2, and the gate of transistor Q19 receives potential Vref.

The high voltage level detection circuit 206 further includes
An n-channel MOS transistor Q20 connected between a connection node n3 between the transistors Q17 and Q18 and the ground potential, and rendered conductive in response to the inactivation of the signal / DE1 (change to "H"level); Node n3
And an input node, and an inverter 2064 that outputs signal PE1.

When the potential level of node N3 is at signal / PE1
Is output as Next, the high voltage level detection circuit 206
The operation of will be briefly described.

Signal DE1 is inactive ("L" level)
, The transistor Q15 in the differential amplifier circuit 2062 is in a cut-off state.
Is inactive. On the other hand, transistor Q20 is rendered conductive in response to signal / DE1 being inactive ("H" level), and node n3 attains "L" level. In response, signal PE1 output from inverter 2064 attains an "H" level, and signal / PE1 attains an "L" level.

Next, when signal DE1 is activated ("H" level), differential amplifier circuit 2062 is activated. Accordingly, the reference potential Vref and the potential Vmon
In accordance with the comparison result, the potential levels of signals PE1 and / PE1 output from high voltage level detection circuit 206 change as follows.

I) The potential Vmo is higher than the reference potential Vref
When n is large Since the signal DE1 is in the active state (“H” level),
Transistor Q16 is off. Therefore, the potential level of the output node n2 of the differential amplifier circuit 2062 is
It changes to the “L” level. In response, transistor Q17 is turned on and transistor Q18 is turned off, so that the potential level of node n3 attains "H" level. In response, the level of signal PE1 output from inverter 2064 attains an "L" level and signal / P
E1 becomes "H" level.

Ii) The potential Vmo is higher than the reference potential Vref.
In the case where n is low In this case, the potential level of output node n2 of differential amplifier 2062 attains "H" level. In response, transistor Q17 is turned off and transistor Q18 is turned on. Since the gate of the transistor Q19 receives the reference potential Vref, it is in a conductive state,
Thereby, the potential level of node n3 changes to "L" level.

Therefore, signal PE1 of the output signal of inverter 2064 changes to "H" level, and signal / PE1 changes to "L" level.

[0105] That is, from the high voltage level detecting circuit 206, when the potential level of the potential level Vpp1 output from the output node N _H1 of the step-up circuit 202, becomes equal to or less than a predetermined value, active CLK activity signal PE1 will be output.

FIG. 4 is a schematic block diagram showing a configuration of high voltage switch circuit 218 shown in FIG.

The high voltage switch circuit 218 outputs the signal / PE
2 as a set signal, a flip-flop circuit 2182 receiving a signal / DE2 as a reset signal, an inverter 2184 receiving an output signal / TGX of the flip-flop circuit 2182 and outputting an inverted signal TGX, and a first booster circuit 202 P-channel MOS transistor 2188 that sets the connection between output node N _H1 of the second _stage and output node N _H2 of second booster circuit 204 to a conductive state or a cut-off state.
And a level conversion circuit 2186 controlled by signals TGX and / TGX to control the gate potential level of p-channel MOS transistor 2188.

The back gate of p channel MOS transistor 2188 is connected to output node N _H1 .

On the other hand, level conversion circuit 2186 outputs signal T
When GX is at "L" level and signal / TGX is at "H" level, p-channel MOS transistor 21
A potential level of "L" level (ground potential) is applied to the gate of 88, and during the period when signal TGX is at "H" level (signal / TGX is at "L" level), the gate of p-channel MOS transistor 2188 has: The potential level of the node N _H1 is supplied.

The operation of the high voltage switch circuit 218 will be briefly described below. i) When the signal DE2 is at the “L” level and the signal PE2 is at the “H” level As described with reference to FIG.
At 08, while the level of the signal DE2 is in the inactive state (“L” level), the level of the signal PE2 is at “H” level.

In this case, flip-flop circuit 218
2 is at "L" level, and signal / DE2 is at "H" level. Therefore, signal / TGH output from flip-flop circuit 2182 is at “H” level, and p-channel MOS transistor 2188 controlled by level shift circuit 2186 is conductive.

That is, the output node N _{H1 of} the first booster circuit 202 and the output node N _{H2 of} the second booster circuit 204 are kept conductive.

Ii) When the signal DE2 goes to "H" level In this case, the high voltage level detection circuit 2 shown in FIG.
06, the level of the potential Vmon is changed to the reference potential Vr
It should initially be lower than ef. Therefore, the signal DE
2 becomes “H” level and the high voltage level detection circuit 20
At the time when 8 is activated, signal PE2 is at "H" level.

Therefore, flip-flop circuit 218
2, the signal / TGH maintains the "H" level without changing its state.

That is, the transistor 2188 remains conductive. Further, when signal PE2 changes to "L" level and signal / PE2 attains "H" level, the potential level applied from level conversion circuit 2186 to the gate of p-channel MOS transistor 2188 becomes the potential of node _NH1 . Level, and the transistor p-channel MOS transistor 2188 is turned off.

Thereafter, as long as signal DE2 maintains the "H" level, the potential level output from flip-flop circuit 2182 does not change, regardless of the potential level of signal PE2, and p-channel MOS transistor 2188 remains cut off. maintain.

FIG. 5 shows the CLK gate circuit 2 shown in FIG.
It is a schematic block diagram which shows the structure of No.10.

The configuration of CLK gate circuit 212 is basically the same as that of CLK gate circuit 210, except that the received signal and the output signal are different.

CLK gate circuit 210 receives signal CLK and signal PE1, and outputs a first AND circuit 2102 for outputting drive clock signal PH1, and receives signal / CLK and signal PE1 to generate drive clock signal / PH1. And a second AND circuit 2104 for outputting.

Therefore, CLK gate circuit 210
Only during the period when signal PE1 is in the active state (“H” level), input clock signals CLK and / CLK are
They are output as drive clock signals PH1 and / PH1, respectively.

While signal PE1 is inactive, drive clock signals PH1 and / PH1 maintain the "L" level.

FIG. 6 is a schematic block diagram showing the structure of charge pump circuit 212 shown in FIG.

As described with reference to FIG. 2, the first charge pump circuit 214 is
000.

The first charge pump circuit 214 is configured by connecting seven stages of diode-connected transistors driven by drive clock signals PH1 and / PH1 via coupling capacitors C1 to C6. , The second charge pump circuit 216 has a configuration in which diode-connected transistors are connected in three stages.

Therefore, according to equation (2), the amount of supply current of the second charge pump circuit 216 has a smaller value than the amount of supply current of the first charge pump circuit 214.

FIG. 7 is a circuit diagram of the high voltage generating circuit 20 shown in FIG.
6 is a timing chart for explaining the operation of the "0".

First, at time t0, detection circuit activation signals DE1 and DE2 output from control circuit 122 are both at "L" level. In this case, both CLK activation signals PE1 and PE2 output from high voltage level detection circuits 206 and 208 are at "H" level.

As described with reference to FIG. 4, at such a signal level, p-channel MOS transistor 2188 in high voltage switch circuit 218 is conductive.

Subsequently, at time t1, both signal DE1 and signal DE2 change to the active state ("H" level).

In response, clock generation circuit 220
Starts outputting the clock signal CLK and the clock signal / CLK.

The first charge pump circuit 214 and the second charge pump circuit 216 include the CLK gate circuit 2
In response to drive clock signals PH1 / PH1 and PH2 / PH2 provided from 10 and 212, respectively,
The potential levels of corresponding output nodes N _H1 and N _H2 are raised. However, since the high voltage switch circuit 218 is in a conductive state, the output voltage N _H1 and the output node N _H2
Are kept equal.

In other words, at this stage, the first charge pump circuit 214 having a larger supply current amount drives the potential levels of the output nodes N _H1 and N _H2 more dominantly. .

At time t3, the potential level of output node N _H1 (that is, the potential level of output node N _H2 ) becomes
When the high voltage level detection circuit 208 detects that a predetermined potential level has been reached, the signal / PE2 changes to "H" level.

In response, high voltage switch circuit 218
The signal / TGX output from the middle flip-flop circuit 2182 changes to “L” level, and the signal TGX of the output signal of the inverter 2184 changes to “H” level.

Under the control of these signals TGX and / TGX, high voltage switch circuit 218 is turned off.

Therefore, after time t3, the output node
N_H1Potential level and output node N _H2The potential level of
A first booster circuit 202 and a second booster circuit 2
04 is controlled independently.

[0137] That is, the output node potential level of the potential Vpp2 output from N _H2 of the second booster circuit 204, because it reaches a predetermined potential level in already time t3, the subsequent high voltage level detecting circuit 208 controls the CLK gate circuit 212 according to whether or not the potential level Vpp2 is equal to or higher than a predetermined lower limit potential level.

[0138] That is, for example, at time t4, when the potential Vpp2 has a lower than a predetermined lower limit voltage level V _s2 high voltage level detecting circuit 208 detects, CL
The K activation signal PE2 changes from “L” level to “H” level, in other words, the high voltage level detection circuit 208
Activates the CLK activation signal PE2,
From the gate circuit 212 to the second charge pump circuit 216
Output the drive clock signals PH2 and / PH2.

As a result, the potential Vpp2 starts rising again, and at time t5, when the high voltage level detecting circuit 208 detects that the potential Vpp2 has risen to a predetermined potential level or higher, the signal PE2 becomes inactive. The supply of the drive clock signal to the second charge pump circuit 216 is stopped.

Thereafter, similarly, second booster circuit 204 is controlled such that potential Vpp2 maintains a predetermined potential level.

On the other hand, the potential level Vpp1 of the output node N _H1 of the first booster circuit 202 is at the stage of time t3.
Since the potential has not reached the predetermined potential level, CLK activation signal PE1 output from high voltage level detection circuit 206
Maintains the active state after time t3.

At time t6, when high voltage level detection circuit 206 detects that potential Vpp1 has reached a predetermined potential level, it deactivates CLK activation signal PE1.

In response, the operation of first charge pump circuit 214 stops. Level potential Vpp1 is detected gradually began to decline by the first charge pump circuit 214 is stopped, at time t7, the high voltage level detecting circuit 206, the potential Vpp1 is equal to or less than a predetermined lower limit level V _s1 Then, the CLK activation signal PE1 is activated.

In response, first charge pump circuit 214 operates again, and rises until potential Vpp1 becomes higher than a predetermined potential level. Thereafter, similarly, the first booster circuit 2 is controlled by the high voltage level detection circuit 206.
02 is kept at a predetermined value.

In the high voltage generating circuit of the first embodiment, the above operation is performed. Therefore, when the amount of current supplied to second charge pump circuit 216 is small, in other words, second charge pump circuit 216 Even when the circuit area is small, it is possible to make the rising of the potential level Vpp2 output from the second boosting circuit 204 equal to the rising speed of the first boosting circuit 202.

The second charge pump circuit 216 only needs to have a current supply amount enough to maintain the level of potential Vpp2 at a predetermined potential level.
00 outputs the first high voltage output Vpp1 and the second high voltage output Vpp2,
It is possible to suppress an increase in circuit area as compared with a case where p1 and Vpp2 are generated by completely independent boosting circuits.

In the above description, the case where the high voltage output from the high voltage generating circuit 200 is of two types has been described. However, the present invention is not limited to such a case, and even more high voltages can be output. It is also possible to apply when outputting.

[Second Embodiment] FIG. 9 is a schematic block diagram showing a configuration of a high voltage generating circuit 300 according to a second embodiment of the present invention.

The difference from the configuration of the high voltage generation circuit 200 of the first embodiment is that both the signal TGX generated in the high voltage switch 218 and the CLK activation signal PE2 are controlled and the second booster circuit CLK gate circuit 31 in 204
2 operates.

Other points are the same as those of the first embodiment shown in FIG.
Is the same as that of high voltage generating circuit 200, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 8 shows the CLK gate circuit 3 shown in FIG.
FIG. 12 is a circuit diagram illustrating a configuration of a twelfth embodiment. CLK gate circuit 31
2 is a clock signal CLK, a signal TGX and a signal PE.
2 that outputs the first drive clock signal PH
ND circuit 3122, clock signal / CLK, signal TG
And an AND circuit 3124 receiving X and signal PE2 and outputting a second drive clock signal / PH2.

Therefore, CLK gate circuit 312 outputs clock signals CLK and / C only while signal TGX and PE2 are both active means ("H" level).
LK, the first and second drive clock signals PH
And / PH are output.

FIG. 10 is a circuit diagram of the high voltage generating circuit 3 shown in FIG.
10 is a timing chart for explaining the operation of the control unit 00.

At time t0, detection circuit activation signals DE1 and DE2 output from control circuit 122 are both inactive, and at time t1, signals DE1 and DE2 change to the active state ("H" level). Change.
On the other hand, at time t0, signal PE2 is in the active state, and signal / PE2 is at "L" level. on the other hand,
Since signal / DE2 is at "H" level, high voltage switch 218 shown in FIG. 9 is conductive.

At time t1, even when signal DE2 attains "H" level, that is, signal / DE2 attains "L" level, high voltage switch 218 maintains a conductive state.

That is, signal TGX output from high voltage switch 218 is at "L" level. Therefore, C
The LK gate circuit 312 outputs an active drive clock signal P
H2 and / PH2 are not output. Therefore, the operation of the second charge pump circuit 216 remains stopped.

Therefore, only the first charge pump circuit 214 operates during the period from time t1 to t3,
The potential levels of the output node N _{H1 of} the first booster circuit 202 and the output node N _H2 of the second booster circuit 204 are driven only by the first charge pump circuit 214.

At time t3, when the potential level of node _NH2 reaches a predetermined potential level, high voltage level detection circuit 208 changes the potential level of signal PE2 to "L" level. Accordingly, the high voltage switch circuit 21
8, the signal / PE2 changes to "H" level,
The high voltage switch circuit 218 is turned off. further,
In response to the change of the signal / PE2 to the “H” level, the signal T
GX also changes to “H” level.

That is, in CLK gate circuit 312, although signal TGX is at "H" level, signal PE
Since 2 is at the “L” level, drive clock signals PH2 and / PH2 are not yet supplied to second charge pump circuit 216.

[0160] At time t4, the high voltage level detecting circuit 208, the node N _H2 potential level, i.e. the potential Vp
Upon detecting that the potential level of p2 is equal to or lower than the predetermined lower limit potential level _Vs2 , the high voltage level detection circuit 208
The signal PE2 is changed to the active state. At this point, since both signal PE2 and signal TGX attain an "H" level, active drive clock signals PH2 and / PH2 are supplied from CLK gate circuit 312 to second charge pump circuit 216.

As a result, the potential Vpp2 is independently driven by the second charge pump circuit 216 and is boosted until it reaches a predetermined potential level again. At time t5, when high voltage level detection circuit 208 detects that potential Vpp2 has become equal to or higher than the predetermined potential level, signal PE2 is inactivated, and accordingly, the driving clock to second charge pump circuit 216 is driven. The supply of the signal is also stopped.

Thereafter, similarly, the second booster circuit 20
4 independently controls the potential Vpp2.

On the other hand, at time t3, when the high voltage switch circuit 218 is turned off, the potential Vpp1 output from the first booster circuit 202 becomes the potential Vpp1.
Does not reach a predetermined potential level. Therefore, the high voltage level detection circuit 206
Signal PE1 is maintained in an active state ("H" level). Therefore, the first charge pump circuit 214 outputs the potential Vp
The boosting operation is continued by controlling p1 independently.

At time t6, high voltage level detection circuit 2 detects that potential Vpp1 has reached a predetermined potential level.
When 06 is detected, the signal PE1 changes to the inactive state.

In response, supply of drive clock signals PH1 and / PH1 to first charge pump circuit 214 is stopped. At time t7, the potential Vpp1 again
Charge potential level, that lower than the first predetermined lower potential level V _s1, the high voltage level detecting circuit 206 detects again the signal PE1 is the active state ( "H" level), the first Potential Vp by pump circuit 214
A boost operation of p1 is performed.

As described above, in boosting circuit 300 of the second embodiment, the potential levels of output node N _H1 supplied with potential Vpp1 and output node N _H2 supplied with potential Vpp2 are set at the initial stage of the boosting operation. In
Both are driven by the first charge pump circuit 214.

The second charge pump circuit 216 has the second
Only the operation of maintaining the potential Vpp2 raised to the predetermined potential level at the second predetermined potential level may be performed. For this reason, even when the supply current amount of the second charge pump circuit is suppressed to be smaller than the supply current amount of the first charge pump circuit, in other words, the circuit area of the second charge pump circuit 216 is reduced. Even when the charge pump circuit 214 has a smaller circuit area, the potential level of the node N _H2 can rise in the initial stage of the boosting operation, similarly to the potential level of the node N _H1. .

[Third Embodiment] FIG. 11 is a schematic block diagram showing a configuration of negative voltage generating circuit 400 shown in FIG.

The difference from the configuration of high voltage generating circuit 200 of the first embodiment shown in FIG. 2 is as follows.

That is, the negative voltage generating circuit 400 includes a first negative potential driving circuit 402, a second negative potential driving circuit 404, a negative high voltage switch 418, and a clock generating circuit 220.

Here, the first negative potential driving circuit 402
The potential level of the output node Nn1 is determined by the control circuit 122
, And is driven to a negative high voltage (for example, −10 V). Second negative potential driving circuit 404 drives the potential level of output node Nn1 to a negative high potential. Here, the amount of supply current of the second negative potential drive circuit 404 is equal to the first supply current.
Is smaller than the supply current amount of the negative potential drive circuit 402. The high voltage switch 418 is controlled according to the potential levels of the control circuit 122 and the output node Nn1 to open and close the connection between the node Nn1 and the node Nn2, as described later.

That is, the point that both the first negative potential drive circuit 402 and the second negative potential drive circuit 404 drive the potential level of the output node to be negative, and that the high voltage switch circuit 418 has the negative potential level Negative voltage generation circuit 400 is different from high voltage generation circuit 200 in that the connection between two output nodes Nn1 and Nn2 is opened and closed.

The first negative potential drive circuit 402 is activated in response to the detection circuit activation signal DE1 from the control circuit 122, and detects that the potential level of the output node Nn1 is equal to or higher than a predetermined potential level. CLK activation signal PE
1 is activated in response to signal PE1 and receives clock signals CLK and / CLK, and receives drive clock signals PH1 and / CLK.
It includes a CLK gate circuit 410 that outputs PH1, and a charge pump circuit 414 that drives the potential level of output node Nn1 to a negative potential with a first current supply amount according to drive clock signals PH1 and / PH1.

Second negative potential drive circuit 404 is also activated in response to detection circuit activation signal DE2 from control circuit 122, and the potential level of output node Nn2 is higher than a second predetermined potential level. Includes the CLK activation signal PE
2 is activated in response to signal PE2, receives clock signals CLK and / CLK, and receives drive clock signals PH2 and / CLK.
A CLK gate circuit 412 that outputs PH2;
2 and a second charge pump circuit 416 driven according to / PH2 and driving the potential level of output node Nn2 with a second predetermined supply current amount.

From the negative high voltage level detection circuit, the signal P
The inverted signal / PE2 of E2 is output, and the high voltage switch circuit 418 is controlled by the signal / DE2 and the signal / PE2 which are inverted signals of the detection circuit activation signal DE2,
The state is switched to the conduction state or the interruption state.

FIG. 12 is a circuit diagram showing a configuration of negative high voltage level detection circuit 406 shown in FIG. 11, and is a diagram to be compared with FIG.

The configuration of high voltage level detection circuit 408 is also different only in the level of the input signal, output signal and reference potential, and the basic configuration is the same as that of high voltage level detection circuit 406 shown in FIG. Is the same as

The configuration of the high voltage level detection circuit 406 shown in FIG. 12 is different from the configuration of the high voltage level detection circuit 206 shown in FIG. 3 in the following two points.

That is, first, the differential amplifier circuit 4
Node n1 that outputs Vmon which is an input signal of 062
Corresponds to a connection node between resistors R1 and R2 connected in series between power supply potential Vcc and potential Vnn1.

Second, with respect to the potential Vmon input to the differential amplifier circuit 4062 and the first reference potential Vref1,
The point is that the potential level of the output node N2 of the differential amplifier circuit 4062 is driven as follows.

That is, the potential level Vmon changes to the potential Vr
When it is higher than ef1, the potential level of node N1 is driven to "H" level. On the other hand, when the potential level of potential Vmon is lower than potential Vref1, node N
2 is driven to the “L” level.

Therefore, the potential Vmon changes to the potential Vref.
If it is higher than 1, the signal PE1 goes high and the signal / PE1 goes low.

On the other hand, when the potential level of potential Vmon is lower than potential Vref1, signal PE1 is at "L" level and signal / PE1 is at "H" level.

Since the other points are the same as those of high voltage level detecting circuit 206 shown in FIG. 3, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 13 is a circuit diagram showing a configuration of high voltage switch circuit 418 shown in FIG. 11, and is a diagram compared with FIG.

High voltage switch circuit 418 shown in FIG.
Is different from the configuration of the high-voltage switch circuit 218 in FIG. 4 in the following point.

First, the high voltage switch circuit 418
A potential level lower than the ground potential is transmitted to the output side of inverter 2184 between an output node of inverter 2184, which receives and inverts and outputs a signal output from flip-flop circuit 2182, and a level shift circuit 4186. This is a configuration including a p-channel MOS transistor 4190 for preventing the operation.

P-channel MOS transistor 4190
Is connected between the input node of the level shift circuit 4186 and the output node of the inverter 2184, the gate receives the ground potential, and the back gate receives the output level of the inverter 2184.

Second, the level shift circuit 4186 includes:
Depending on the signal output from the inverter 2184, and a state for outputting a power supply potential Vcc, it is that switches to a state of outputting the potential level of the node N _H2.

Third, the connection between the node N _H1 and the node N _H2 is switched by the n-channel MOS transistor 41.
88.

N channel MOS transistor 4188
Is connected between the nodes N _H1 and N _H2 , the gate receives the output of the level shift circuit 4186, and the back gate receives the potential level of the node N _H2 .

That is, the high voltage switch circuit 418
When the signal TE2 is at the "L" level, the signal / DE2 is at the "H" level, and the signal / PE2 is at the "L" level, the connection between the nodes N _H1 and N _H2 is made conductive.

This state is maintained even after signal / PE2 is at "L" level and signal / DE2 is at "L" level (signal DE2 is at "H" level).

When signal / DE2 is at "L" level (signal DE2
Is at "H" level), and the transistor 4188 is turned off in response to the signal / PE2 attaining "H" level.

FIG. 14 shows the first charge pump circuit 4 of the components of the negative voltage generation circuit 400 shown in FIG.
FIG. 20 is a diagram showing a configuration of No. 14 and is a diagram to be compared with FIG. 19.

The difference from the structure of FIG. 19 is that both the gate and the source of transistor Q1 receive the ground potential.

The other points are the same as the configuration of charge pump circuit 2000 shown in FIG.

FIG. 15 shows the second charge pump circuit 4 of the components of the negative voltage generation circuit 400 shown in FIG.
FIG. 16 is a circuit diagram showing a configuration of No. 16;

The difference from the structure of the first charge pump circuit 414 shown in FIG. 14 is that the number of stages of diode-connected transistors connected in series to each other is seven in the first charge pump circuit 414. On the other hand, the second charge pump circuit 416 has a three-stage configuration.

Therefore, in the charge pump circuit shown in FIG. 14, coupling transistors C1 to C6
Whereas, in the second charge pump circuit 416 shown in FIG. 15, only two of C1 'and C2' are present. Therefore, according to Expression (2), the amount of current supplied to the second charge pump circuit 416 has a smaller value than that of the first charge pump circuit 414.

FIG. 16 is a timing chart for explaining the operation of negative voltage generating circuit 400 shown in FIG.

First, at time t0, detection circuit activation signals DE1 and DE2 output from control circuit 122 are both at "L" level. In this case, both CLK activation signals PE1 and PE2 output from high voltage level detection circuits 406 and 408 are at "H" level.

As described with reference to FIG. 13, at such a signal level, n-channel MOS transistor 4188 in high voltage switch circuit 418 is conductive.

Subsequently, at time t1, both signal DE1 and signal DE2 change to the active state ("H" level).

The first charge pump circuit 414 and the second charge pump circuit 416
10 and 412, respectively, according to drive clock signals PH1 / PH1 and PH2 / PH2,
The potential levels of corresponding output nodes Nn1 and Nn2 are raised. However, since high voltage switch circuit 418 is conductive, the potential levels of the output, Nn1 and output node Nn2 are kept equal.

In other words, at this stage, first charge pump circuit 414 having a larger supply current amount drives the potential levels of output nodes Nn1 and Nn2 more dominantly.

At time t3, the potential level of output node Nn1 (that is, the potential level of output node Nn2)
However, when the high voltage level detection circuit 408 detects that the signal has reached the predetermined potential level, the signal / PE2 changes to the “H” level.

In response, high voltage switch circuit 418
Signal TGX of the output signal of inverter 2184 receiving the signal output from middle flip-flop circuit 2182 changes to “H” level.

Under the control of signal TGX, high voltage switch circuit 418 is cut off. Therefore, after time t3, the potential level of output node Nn1 and output node Nn
The potential level of n2 is the first negative potential drive circuit 4
02 and the second negative potential drive circuit 404 are controlled independently.

That is, since the potential level of potential Vnn2 output from output node Nn2 of second negative potential drive circuit 404 has already reached the predetermined potential level at time t3, high voltage level detection is performed thereafter. The circuit 408 is
The potential level Vnn2 in response to or less than a predetermined upper limit voltage level V _R2, will control the CLK gate circuit 412.

Generally, the potential level of node Nn2 is
After the charge pump circuit 416 is inactivated due to a minute leakage current, the voltage gradually rises.

[0212] That is, for example, at time t4, when the potential Vnn2 is, that rises above a predetermined upper limit voltage level V _R2 high voltage level detecting circuit 408 detects, CL
The K activation signal PE2 changes from “L” level to “H”. In other words, the high voltage level detection circuit 408
The LK activation signal PE2 is activated, and the drive clock signals PH2 and / PH2 are output from the CLK gate circuit 412 to the second charge pump circuit 416.

As a result, the potential Vnn2 starts falling again. At time t5, when the high voltage level detection circuit 408 detects that the potential has dropped below the predetermined potential level, the signal PE2 becomes inactive. The supply of the drive clock signal to the second charge pump circuit 416 is stopped.

Thereafter, similarly, the second negative potential driving circuit 20 is set so that potential Vnn2 maintains a predetermined potential level.
4 will be controlled.

On the other hand, the potential level Vnn1 of the output node Nn1 of the first negative potential drive circuit 202 has not reached the predetermined potential level at the stage of time t3, and is thus output from the high voltage level detection circuit 406. CLK activation signal PE1 maintains an active state after time t3. Time t
In 6, when the high voltage level detection circuit 406 detects that the potential Vnn1 has reached a predetermined potential level, it deactivates the CLK activation signal PE1.

In response, the operation of first charge pump circuit 414 stops. Level potential Vnn1 is detected gradually begins to rise by the first charge pump circuit 414 is stopped, at time t7, the high voltage level detecting circuit 406, the potential Vnn1 exceeds a predetermined upper limit level V _R1 Then, the CLK activation signal PE1 is activated.

In response, first charge pump circuit 414 operates again, and lowers potential Vnn1 until it falls below a predetermined potential level. Thereafter, similarly, the level of the potential Vnn1 output from the first negative potential drive circuit 402 is maintained at a predetermined value under the control of the high voltage level detection circuit 406.

In the high voltage generating circuit according to the third embodiment, the above operation is performed. Therefore, when the amount of current supplied to second charge pump circuit 416 is small, in other words, second charge pump circuit 416 Of the potential level Vnn2 output from the second negative potential drive circuit 404,
Can be made equal to the falling speed of the negative potential driving circuit 402.

Second charge pump circuit 416 only needs to have a current supply amount for maintaining the level of potential Vnn2 at a predetermined potential level.
00 outputs the first high voltage output Vnn1 and the second high voltage output Vnn2,
Compared to the case where n1 and Vnn2 are generated by completely independent negative potential drive circuits, it is possible to suppress an increase in circuit area.

In the above description, a case has been described where there are two types of high voltages output from negative voltage generating circuit 400. However, the present invention is not limited to such a case, and even more high voltages can be output. It is also possible to apply when outputting.

[Fourth Embodiment] FIG. 17 is a schematic block diagram showing a configuration of a negative voltage generating circuit 500 according to a fourth embodiment of the present invention.

The difference from the configuration of the negative voltage generating circuit of the third embodiment shown in FIG. 11 is as follows.

That is, in the negative voltage generating circuit according to the fourth embodiment, CLK gate circuit 512 in second negative potential driving circuit 404 is connected to CLK activating signal PE2 from high voltage level detecting circuit 408 and high voltage switch. 418 is controlled by both signals TGX from 418.

That is, similarly to the configuration of CLK gate circuit 312 of the second embodiment shown in FIG. 8, CLK gate circuit 512 has both signal TGX and signal PE2 in an active state ("H" level). Clocks CLK and / CLK received from clock generation circuit 220 only during the period
Are output as drive clock signals PH2 and / PH2.

Therefore, in the initial stage of operation of negative voltage generating circuit 500, high voltage switch 418 is conductive and CLK gate circuit 512 does not output active drive clock signals PH2 and / PH2. It has become.

Therefore, second charge pump circuit 416 does not operate until the potential level of output node Nn2 attains a desired voltage.

Since the other points are the same as those of the configuration of negative voltage generating circuit 400 of the third embodiment shown in FIG. 11, the same portions are denoted by the same reference characters and description thereof will not be repeated. FIG. 18 is a timing chart for explaining the operation of negative voltage generation circuit 500 shown in FIG.

At time t0, detection circuit activation signals DE1 and DE2 output from control circuit 122 are both inactive, and at time t1, signals DE1 and DE2 change to the active state ("H" level). Change.
On the other hand, at time t0, signal PE2 is in the active state, and signal / PE2 is at "L" level. signal/
Since DE2 is at the “H” level, the high-voltage switch 418 shown in FIG. 17 is conductive.

At time t1, even when signal DE2 attains "H" level, that is, signal / DE2 attains "L" level, high voltage switch 418 maintains a conductive state.

That is, signal TGX output from high voltage switch 418 is at "L" level. Therefore, C
The LK gate circuit 412 outputs an active drive clock signal P
H2 and / PH2 are not output. For this reason, the operation of the second charge pump circuit 416 remains stopped.

Therefore, during the period from time t1 to time t3, only first charge pump circuit 414 operates,
The potential levels of the output node N _{H1 of} the first negative potential drive circuit 402 and the output node Nn2 of the second negative potential drive circuit 404 are driven only by the first charge pump circuit 414.

At time t3, when the potential level of node Nn2 attains a predetermined potential level, high voltage level detection circuit 408 changes the potential level of signal PE2 to "L" level. In response, the high-voltage switch circuit 4
The signal / PE2 input to 18 changes to "H" level, and the high voltage switch circuit 418 is cut off. Further, signal TGX also changes to "H" level in response to change of signal / PE2 to "H" level.

That is, in the CLK gate circuit 512, although the signal TGX is at the “H” level, the signal PE
Since 2 is at the “L” level, drive clock signals PH2 and / PH2 are not yet supplied to second charge pump circuit 416.

At time t4, high voltage level detection circuit 408 detects the potential level of node Nn2, that is, potential V
When nn2 potential level detects that the predetermined upper limit potential level V _R2 above, the high voltage level detecting circuit 408
Changes the signal PE2 to the active state. At this point, both the signal PE2 and the signal TGX become “H” level, so that the CLK gate circuit 512 sends the active drive clock signal P to the second charge pump circuit 416.
H2 and / PH2 are supplied.

As a result, the potential Vnn2 is independently driven by the second charge pump circuit 416, and is lowered until it reaches a predetermined potential level again. At time t5, when high voltage level detection circuit 408 detects that potential Vnn2 has become equal to or lower than the predetermined potential level, signal PE2 is inactivated, and accordingly, the driving clock to second charge pump circuit 416 is driven. The supply of the signal is also stopped.

Thereafter, similarly, the potential Vnn2 is independently controlled by the second negative potential drive circuit 404.

On the other hand, at time t3, when the high voltage switch circuit 418 is turned off, the potential Vnn1 output from the first negative potential drive circuit 402 becomes the potential Vnn.
nn1 has not reached a predetermined potential level. Therefore, the high voltage level detection circuit 40
6 maintains the signal PE1 in an active state ("H" level). For this reason, the first charge pump circuit 414 independently controls the potential Vnn1, and further continues the step-down operation.

At time t6, the high voltage level detection circuit 4 detects that the potential Vnn1 has reached the predetermined potential level.
When 06 is detected, the signal PE1 changes to the inactive state.

In response, supply of drive clock signals PH1 and / PH1 to first charge pump circuit 414 is stopped. At time t7, the potential Vnn1 again
When the high voltage level detection circuit 406 detects that the potential level has risen above the first predetermined upper limit potential level V _R1 , the signal PE1 is activated again, and the potential Vnn1 is applied by the first charge pump circuit 414. Is performed.

As described above, in negative potential drive circuit 500 of the fourth embodiment, the potential levels of output node Nn1 supplied with potential Vnn1 and output node Nn2 supplied with potential Vnn2 are set at the initial stage of the step-down operation. Are driven by the first charge pump circuit 414.

[0241] The second charge pump circuit 416
Only the operation of maintaining the potential Vnn2 lowered to the predetermined potential level at the second predetermined potential level may be performed. For this reason, even when the supply current amount of the second charge pump circuit is suppressed smaller than the supply current amount of the first charge pump circuit, in other words, the circuit area of the second charge pump circuit 416 is reduced. Even when the charge pump circuit 414 is kept small compared to the circuit area of the single charge pump circuit 414, the potential level of the node Nn2 can rise in the initial stage of the step-down operation, similarly to the potential level of the node Nn1.

[0242]

In the internal potential generating circuit according to the first aspect, the output nodes of the first and second charge pump means are kept until the potentials of the first and second output nodes reach the second predetermined potential. Are maintained in common. Therefore, even when the current supply amounts of the first charge pump unit and the second charge pump unit are different, the speed at which the potential levels of the first output node and the second output node rise can be made common. . Therefore, even when the internal potential generation circuit needs to generate the first predetermined internal potential and the second predetermined internal potential, it is possible to suppress an increase in circuit area.

The internal potential generating circuit according to the second aspect has a second
After the potential of the output node attains the second predetermined potential and the switch is turned off, the potential levels of the first output node and the second output node are controlled independently of each other. The first current supply amount output from the second charge pump means is sufficient to maintain the second predetermined internal potential. For this reason, the circuit area of the second charge pump means can be reduced, and the increase in the circuit area of the internal potential generating circuit itself can be suppressed.

The internal potential generating circuit according to claim 3 is characterized in that:
After the potential of the output node becomes the second predetermined potential and the switch means is turned off, the potential levels of the first output node and the second output node are controlled independently of each other. The first current supply amount output from the second charge pump means is sufficient to maintain the second predetermined internal potential. For this reason, the circuit area of the second charge pump means can be reduced, and the increase in the circuit area of the internal potential generating circuit itself can be suppressed.

The internal potential generating circuit according to claim 4 is characterized in that the internal potential generating circuit starts outputting the first predetermined internal potential and the second predetermined internal potential in the initial stage, and Because both pump means operate
It is possible to reduce the time required for the potential levels of the first and second output nodes to reach the predetermined potential levels, respectively.

According to a fifth aspect of the present invention, in the initial stage in which the internal potential generating circuit starts outputting the first predetermined internal potential and the second predetermined internal potential, the first and second charge circuits are provided. Because both pump means operate
It is possible to reduce the time required for the potential levels of the first and second output nodes to reach the predetermined potential levels, respectively.

The internal potential generating circuit according to claim 6 is characterized in that:
Until the potential level of the second output node reaches the second predetermined potential level, only the first charge pump means operates, so that power consumption can be suppressed.

An internal potential generating circuit according to claim 7 is characterized in that:
Until the potential level of the second output node reaches the second predetermined potential level, only the first charge pump means operates, so that power consumption can be suppressed.

The internal potential generating circuit according to claim 8 is characterized in that:
After the potential of the output node becomes the second predetermined potential and the switch means is turned off, the potential levels of the first output node and the second output node are controlled independently of each other. The first current supply amount output from the second charge pump means is sufficient to maintain the second predetermined internal potential. For this reason, the circuit area of the second charge pump means can be reduced, and the increase in the circuit area of the internal potential generating circuit itself can be suppressed.

The internal potential generating circuit according to claim 9 is characterized in that
After the potential of the output node becomes the second predetermined potential and the switch means is turned off, the potential levels of the first output node and the second output node are controlled independently of each other. The first current supply amount output from the second charge pump means is sufficient to maintain the second predetermined internal potential. For this reason, the circuit area of the second charge pump means can be reduced, and the increase in the circuit area of the internal potential generating circuit itself can be suppressed.

According to a tenth aspect of the present invention, in the initial stage where the internal potential generating circuit starts outputting the first predetermined internal potential and the second predetermined internal potential,
Since both the first and second charge pumps operate, it is possible to reduce the time required for the potential levels of the first and second output nodes to reach the predetermined potential levels, respectively.

According to an eleventh aspect of the present invention, in the initial stage in which the internal potential generating circuit starts outputting the first predetermined internal potential and the second predetermined internal potential,
Since both the first and second charge pumps operate, it is possible to reduce the time required for the potential levels of the first and second output nodes to reach the predetermined potential levels, respectively.

In the internal potential generating circuit according to the twelfth aspect, only the first charge pump means operates until the potential levels of the first and second output nodes reach the second predetermined potential level. Thus, power consumption can be reduced.

In the internal potential generating circuit according to the thirteenth aspect, only the first charge pump means operates until the potential levels of the first and second output nodes reach the second predetermined potential level. Thus, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a nonvolatile semiconductor memory device 1000 according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating a configuration of a high voltage generation circuit 200 according to the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a high voltage level detection circuit 206.

FIG. 4 is a schematic block diagram illustrating a configuration of a high-voltage switch circuit 218.

FIG. 5 is a schematic block diagram showing a configuration of a CLK gate circuit 210.

FIG. 6 is a circuit diagram showing a configuration of a second charge pump circuit 216.

FIG. 7 is a timing chart illustrating an operation of the high voltage generation circuit 200 according to the first embodiment.

FIG. 8 is a schematic block diagram illustrating a configuration of a CLK gate circuit 312 according to the second embodiment.

FIG. 9 is a schematic block diagram illustrating a configuration of a high-voltage generation circuit 300 according to a second embodiment.

FIG. 10 is a timing chart for explaining an operation of the high voltage generation circuit 300 according to the second embodiment.

FIG. 11 is a schematic block diagram showing a configuration of a negative voltage generation circuit 400 according to a third embodiment.

FIG. 12 is a circuit diagram showing a configuration of a high voltage level detection circuit 406.

FIG. 13 is a circuit diagram showing a configuration of a high voltage switch 418.

FIG. 14 is a circuit diagram showing a configuration of a first charge pump circuit 414.

FIG. 15 is a circuit diagram showing a configuration of a second charge pump circuit 416.

FIG. 16 is a timing chart illustrating an operation of negative voltage generation circuit 400 according to the third embodiment.

FIG. 17 is a schematic block diagram illustrating a configuration of a negative voltage generation circuit 500 according to a fourth embodiment.

FIG. 18 is a timing chart for explaining an operation of the negative voltage generation circuit 500.

FIG. 19 is a circuit diagram showing a configuration of a conventional charge pump circuit 2000.

FIG. 20 is a schematic cross-sectional view showing a structure of a transistor in a conventional charge pump circuit 2000.

FIG. 21 is a circuit diagram showing an equivalent circuit of a conventional charge pump circuit 2000.

FIG. 22 is a timing chart showing temporal changes of drive clock signals PH and / PH.

23A and 23B are schematic cross-sectional views illustrating the configuration and operation of a memory cell transistor of a conventional nonvolatile semiconductor memory device. FIG. 23A shows the potential of each part in a write operation, and FIG. Shows the potential of each part in.

FIG. 24 is a diagram showing potential levels in a write operation, an erase operation, and a read operation for a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

100 verify voltage generating circuit, 102 address buffer, 104 memory cell array, 106 X decoder, 108 Y decoder, 114 select gate decoder, 116, 118 source decoder, 120 well potential drive circuit, 122 control circuit, 124 data input / output buffer, 126 Data driver, 128 sense amplifier, 130 writing circuit, 200, 300 high voltage generating circuit, 400, 500 negative voltage generating circuit, 1000
Non-volatile semiconductor storage device.

Claims (13)

[Claims] 1. An internal potential generating circuit for receiving an external power supply potential and generating a first predetermined internal potential and a second predetermined internal potential having an absolute value smaller than the first predetermined internal potential. Clock generating means for outputting mutually complementary clock signals; and a first output node to which the first predetermined internal potential is to be output, wherein a first current supply is performed in accordance with the complementary clock signals. A first charge pump means for driving the potential of the first output node by an amount, and a second output node to which the second predetermined internal potential is to be output, and the second output node is responsive to the complementary clock signal. A second charge pump means for driving the potential of the second output node with a second current supply amount smaller than the first current supply amount; the first output node and the second output Make the connection with the node conductive. Switch means for setting the first charge pump means and the second charge pump means in accordance with a potential level of the first output node and a potential level of the second output node. And control means for controlling the supply of the complementary clock signal to the first and second output nodes.
An internal potential generating circuit for switching the switch means from a conductive state to a cut-off state in response to a predetermined potential. 2. The method according to claim 1, wherein the first predetermined internal potential and the second predetermined internal potential are both positive potentials. To control the supply of the complementary clock signal to the first charge pump means, so that the potential level of the output node of the second node becomes the first predetermined internal potential, and the potential of the second output node 2. The internal potential generating circuit according to claim 1, wherein the supply of said complementary clock signal to said second charge pump means is controlled so that a level becomes said second predetermined internal potential. 3. The first predetermined internal potential and the second predetermined internal potential are both positive potentials, and the control unit sets the first predetermined internal potential to the first predetermined internal potential after the switch unit is turned off. First internal control means for controlling the supply of the complementary clock signal to the first charge pump means, so that the potential level of the output node of the first node becomes the first predetermined internal potential; and the switch means After turning off the second clock signal, the supply of the complementary clock signal to the second charge pump means is controlled so that the potential level of the second output node becomes the second predetermined internal potential. 2. The internal potential generation circuit according to claim 1, further comprising a second internal control means. 4. The control means starts supply of the complementary clock signal to both the first charge pump means and the second charge pump means in response to the start of operation of the internal potential generation circuit. 3. The internal potential generating circuit according to claim 2. 5. The internal control signal according to claim 2, wherein said second internal control means inactivates an internal control signal in response to a potential level of said second output node being equal to or higher than said second predetermined internal potential. A latch unit that is set in response to the deactivation of the internal control signal and is reset in response to the stoppage of the operation of the internal potential generation circuit; and 4. The internal potential generating circuit according to claim 3, further comprising: connection means for disconnecting a connection between said first output node and said second output node. 6. The control means causes the first charge pump means to start supplying the complementary clock signal in response to the start of the operation of the internal potential generating circuit, and the switch means is turned off. later,
3. The internal potential generating circuit according to claim 2, wherein said second charge pump means starts supplying said complementary clock signal. 7. A potential level for inactivating an internal control signal in response to a potential level of said second output node being equal to or higher than said second predetermined internal potential. Detecting means; and clock supply control means for controlling supply of the complementary clock signal to the second charge pump means, wherein the switch means is set in response to inactivation of the internal control signal. A latch unit that is reset when the operation of the internal potential generating circuit is stopped, and a connection between the first output node and the second output node when the latch unit is set. Connection means for setting a cut-off state, wherein the clock supply control means is configured to perform the complementary operation in response to the internal control signal being in an active state and the latch means being in a set state. It starts supplying the clock signal, the internal potential generation circuit of claim 3, wherein. 8. The first predetermined internal potential and the second predetermined internal potential are both negative potentials, and the control unit sets the first predetermined internal potential to the first predetermined internal potential after setting the switch unit to a cutoff state. To control the supply of the complementary clock signal to the first charge pump means, so that the potential level of the output node of the second node becomes the first predetermined internal potential, and the potential of the second output node 2. The internal potential generating circuit according to claim 1, wherein the supply of said complementary clock signal to said second charge pump means is controlled so that a level becomes said second predetermined internal potential. 9. The control circuit according to claim 1, wherein the first predetermined internal potential and the second predetermined internal potential are both negative potentials. First internal control means for controlling the supply of the complementary clock signal to the first charge pump means, so that the potential level of the output node of the first node becomes the first predetermined internal potential; and the switch means After turning off the second clock signal, the supply of the complementary clock signal to the second charge pump means is controlled so that the potential level of the second output node becomes the second predetermined internal potential. 2. The internal potential generation circuit according to claim 1, further comprising a second internal control means. 10. The control means causes both the first charge pump means and the second charge pump means to start supplying the complementary clock signal in response to the start of the operation of the internal potential generation circuit. The internal potential generating circuit according to claim 8, wherein 11. The second internal control means, when the potential level of the second output node becomes lower than or equal to the second predetermined internal potential, deactivates an internal control signal. A latch unit that is set in response to the deactivation of the internal control signal and is reset in response to the stoppage of the operation of the internal potential generation circuit; and 10. The internal potential generating circuit according to claim 9, further comprising: connection means for disconnecting a connection between said first output node and said second output node. 12. The control means causes the first charge pump means to start supplying the complementary clock signal in response to the start of the operation of the internal potential generating circuit, and the switch means is turned off. later,
9. The internal potential generating circuit according to claim 8, wherein said second charge pump means starts supplying said complementary clock signal. 13. A potential level for inactivating an internal control signal in response to a potential level of the second output node falling below the second predetermined internal potential. Detecting means; and clock supply control means for controlling supply of the complementary clock signal to the second charge pump means, wherein the switch means is set in response to inactivation of the internal control signal. A latch unit that is reset when the operation of the internal potential generating circuit is stopped, and a connection between the first output node and the second output node when the latch unit is set. Connection means for setting a cutoff state, wherein the clock supply control means sets the phase in response to the internal control signal being active and the latch means being set. It starts supplying a clock signal, the internal potential generation circuit of claim 9, wherein.