JPH04229655A - Erasure system at nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To stably erase the title memory device without erasing it excessively. CONSTITUTION:The title memory device is erased in the following manner: a memory array is formed inside a P-well 112 which is separated from a peripheral circuit; a drain 3 and a source 4 for a memory transistor are kept floating at an erasure operation; a high voltage is applied to the P-well 112; and a control gate 1 is grounded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erasing method in an electrically writable and erasable nonvolatile semiconductor memory device.

0002

2. Description of the Related Art FIG. 11 is a diagram showing the memory cell structure of a flash EEPROM as a conventional nonvolatile semiconductor memory device, and FIG. 12 is a block diagram of the conventional flash EEPROM. FIG. 13 is an equivalent circuit diagram of a conventional memory transistor. In FIGS. 10 and 11, 1 is a control gate, 2 is a floating gate, 3 is a drain,
4 is a source, 5 is a memory array, 6 is a bit line, 7 is a word line, 8 is a Y gate, 9 is a row decoder, 10 is a column decoder, 11 is a source line switch, 12 is a write circuit, 13 is a sense amplifier, 14 is a control circuit, 15 is an address buffer, 16 is an input/output buffer, 17 is a source line, and 18 is a memory cell. The memory cell 18 is composed of a memory transistor consisting of two gate layers, a control gate 1 and a floating gate 2.

The memory array 5 has the memory cells shown in FIG. 11 arranged in the row and column directions, and the drain 3 of the memory cell 18 is connected to the bit line 6, the control gate 1 is connected to the word line 7, and the source is connected to the bit line 6. 4 is connected to the source line 17. Word line 7 is the output of row decoder 9. Bit line 6 is connected to Y gate 8. Source line 17 is connected to source line switch 11 . Y gate 8 is controlled by column decoder 10 and controls the connection between bit line 6, sense amplifier 13, and write circuit 12. Row decoder 9 and column decoder 10 are address buffer 1
5 and selects one word line and one set of Y gates 8. Data written to the memory array 5 and data read from the memory array 5 are input and output via the input/output buffer 16. The control circuit 14 controls the operation of each circuit block according to a control signal applied from the outside.

Next, the operation will be explained. Data stored in the memory array 5 is erased all at once. A source line switch 11 is connected to the source 4 of all memory cells 18.
A high voltage is applied to the control gate 1, and the control gate 1 is grounded. Since a high electric field is applied to the oxide film between the floating gate 2 and the source 4, a tunnel current flows, and the electrons accumulated in the floating gate 2 are removed. This lowers the threshold value of the memory transistor as seen from the control gate 1. That is, the state is the same as that of an EPROM erased by ultraviolet rays. The writing is
It is carried out in the same manner as in EPROM, and a high voltage pulse is applied to the drain 3 and control gate 1 of the memory transistor, and the source 4 is grounded. Electrons generated by aparanche collapse near the drain 3 are injected into the floating gate 2, and the threshold value of the memory transistor as seen from the control gate 1 becomes high. The high voltage necessary for erasing and writing is supplied externally. This is because the current flowing through the bit line 6 during writing is 1 mA to 5 mA, so a high voltage generating circuit such as a charge pump has insufficient current supply ability.

Reading is performed by sensing whether current flows through the selected memory cell. At this time, if a high potential is applied to the bit line 6, a high electric field will be applied to the oxide film between the floating gate 2 and the drain 3, causing a problem that electrons stored in the floating gate 2 will escape. Therefore, drain 3
The potential of must be suppressed to 1 to 2V. drain 3
The sense amplifier 13 is used to sense the current flowing through the memory cell 18 while suppressing the potential of the memory cell 18.

FIG. 14 shows voltage application conditions for selected memory cells such as erasing, writing, and reading. Here, the write voltage is 6 to 8V, and the read voltage is 1 to 2V. The memory array is formed on a P substrate as shown in FIG. Now, FIG. 16 shows a specific circuit diagram of a row decoder that selects one word line during reading and writing. NAND gate 2 to which address signal Xi etc. is input
4. N-channel MOS transistor 18 to which address signals A1, /A1 (/ indicates a bar) are input to the gate;
19, it is composed of P channel MOS transistors 21 and 22 and an N channel transistor 23 whose sources are input with high voltage VPP or power supply voltage VCC. That is, the transistors 21 to 23 form a latch circuit. Next, the operation will be explained. When all the address signals input to the NAND gate 24 become "H", the NAND gate 24 becomes selected and the output becomes "L". One of the address signals A1 to A4 becomes "H" and the other address signals are kept "L". At this time, only one corresponding address signal among the complementary address signals /A1 to /A4 becomes "L" and the other address signals become "H". For example, if address signal A2 becomes "H", address signals A1, A3, A4 are "L", address signal /A2 is "L", address signals /A1, /A3, /A4
becomes “H”. As a result, only the node N2 becomes "L", and the nodes N1, N3, and N4 become "H". Therefore,
When a high voltage is applied to the sources of P-channel MOS transistors 21 and 22, only word line WL2 is boosted, and the other word lines are grounded. When a power supply voltage of 5V is applied to the sources of P-channel MOS transistors 21 and 22, only word line WL2 becomes 5V.

[0007]

[Problems to be Solved by the Invention] Since the conventional nonvolatile semiconductor memory device is configured as described above, the high voltage applied to the external input pin is directly applied to the source of the memory transistor during erasing, and therefore the source Approximately 12V was applied to it. Also, before erasing, the memory transistor is in a written state and electrons are injected into the floating gate, so even if the voltage applied to the source is, for example, 12V, the oxide film between the floating gate and the source is A large electric field is induced. For this reason, even with a short pulse of about 10 ms, electrons are excessively extracted, the floating gate is positively charged, and the threshold value of the memory transistor becomes negative, resulting in overerasure. This will be explained in more detail below.

FIG. 13 shows an equivalent circuit of a memory transistor. Control gate 1 and floating gate 2
The capacitance between floating gate 2 and drain 3 is CCF, the capacitance between floating gate 2 and drain 3 is CD, floating gate 2 and substrate 1
CC is the capacitance between floating gate 2 and source 4, Cs is the capacitance between floating gate 2 and source 4, QFG is the amount of charge accumulated in floating gate 2, and control gate 1 is
If the potential applied to VG is VG, and the potentials of the drain, channel, and source are VD, VC, and Vs, respectively, then the floating gate potential VFG is VFG=(VG VCF+VD CD +VC CC
+Vs Cs +QFG)/CTOTAL. However, CTOTAL=CCF+CD
+CC +Cs. The coupling ratio is expressed as KC and KC = CCF/CTOTAL. Further, the amount of threshold shift seen from the control gate 1 is ΔVTH=-QFG/CCF. During erasing, VG = VC = VD = 0V, Vpp, so the potential difference between the floating gate and source is (1-
Cs /CTOTAL )Vs +KCΔVTH. The oxide film thickness A between the floating gate 2 and the substrate 111 is 100 angstroms, the threshold shift amount ΔVTH during writing is 5V, and the coupling ratio KC is 0.
．． 6. If Cs /CTOTAL is 0.1, if the source potential Vs is 12V, the oxide film will have a voltage of 13.8MV/
An electric field of cm is induced.

Furthermore, as described above, conventional nonvolatile semiconductor memory devices were constructed to erase data by applying a high voltage to the source and grounding the gate, so they were of the batch erasing type.

The present invention has been made to solve the above-mentioned problems, and its object is to provide an erasing method for a nonvolatile semiconductor memory device that allows stable erasing without overerasing. Another object of the present invention is to obtain an erasing method in a nonvolatile semiconductor memory device that allows erasing in units of word lines.

[0011]

[Means for Solving the Problems] In the erasing method in a nonvolatile semiconductor memory device according to the invention of claims 1 and 2, the memory array is formed in a P-well separate from the peripheral circuit, and the drain of the memory transistor is 3 and source 4 are kept floating, and P where the memory array is formed.
A high voltage is applied to the well 112 and the control gate 1 is grounded. In the erasing method in the nonvolatile semiconductor memory device according to the invention of claim 6, the memory transistor is formed on the P well 112, and for erasing, a high voltage is applied to the P well 112, the selected word line is grounded, and the unselected word line is A high voltage is applied to the wire.

0012

[Operation] In the invention of claims 1 and 2, the memory array is formed in the P well 112 separate from the peripheral circuit, and the drain 3 and source 4 of the memory transistor are kept floating during erasing. Erasing is performed by applying a high voltage and grounding the control gate 1. In the sixth aspect of the invention, the control gate 1 of the selected memory cell is grounded, and erasing is performed in units of word lines.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings. First, an embodiment according to the invention of claim 1 will be described. FIG. 1 is a block diagram of the memory array of this embodiment. Note that the memory cell structure is the same as that shown in FIG. In FIG. 1, 6, 7, 9, 10, 12, 13, and 17 are the same as those shown in the conventional example of FIG. 12, so their explanation will be omitted. A memory array is formed in a P-well 112 separate from the P-well in which peripheral circuits are formed. The potential of the P well 112 is supplied by the well voltage application circuit 21. source line 17
is grounded via a MOS transistor 22 whose gate receives the signal CLK.

Next, the operation will be explained. During writing and reading, the P well 112 is connected to the well voltage generation circuit 2.
Grounded by 1. In addition, the signal CLK becomes “H”,
Source line 17 is grounded. This makes the operation equivalent to the conventional example. During erasing, a high voltage applied from the outside is applied to the P well 112 by the well voltage application circuit 21. The outputs of row decoder 9 and column decoder 10 and signal CLK are set to "L". That is, the drain 3 and source 4 of the memory transistor are kept floating, the control gate 1 is grounded, and a high voltage is applied to the channel. The capacitance between the floating gate 2 and the channel is larger than the capacitance between the floating gate 2 and the source 4, so the capacitance between the floating gate 2 and the substrate (
The electric field applied to the oxide film between the P-wells 112) is 10M.
It is relaxed to about V/cm and over-erasing does not occur.

FIG. 2 is a diagram showing a memory cell structure of an embodiment according to the second aspect of the invention. This memory cell has a control gate 1 extending to the source 4 side. The rest of the structure is the same as the memory cell structure shown in FIG. In this embodiment, since the control gate 1 serves as a selection transistor, over-erasing does not occur.

FIG. 3 is a diagram showing a memory cell structure of an embodiment according to the third aspect of the invention. In this example,
Using a P substrate 111, a memory array is formed in a P well 112 provided in an N well 113, and erasing is performed using P, N
This is done by applying a high voltage to the wells 112 and 113 and grounding the control gate 1.

FIG. 4 is a diagram showing a memory cell structure of an embodiment according to the invention. In this embodiment, a negative high voltage is applied to the control gate 1.

FIG. 5 is a diagram showing a memory cell structure of an embodiment according to the fifth aspect of the invention. In this embodiment, a positive voltage VCC is applied to the P and N wells 112 and 113, and a negative voltage is applied to the control gate 1.

It goes without saying that the embodiments shown in FIGS. 3, 4 and 5 can also be applied to the memory structure shown in FIG.

FIG. 6 shows an embodiment according to the invention of claim 6,
The voltage application conditions during erasing are shown. The memory array consists of a P well 112 provided in an N well 113 as shown in FIG.
formed within. During erasing, a high voltage is applied to the P well 112 and the N well 113. Then, the selected word line is grounded. The same high voltage as that applied to the well is applied to unselected word lines. In the memory cell connected to the selected word line, the potential difference between the control gate 1 and the P well 112 is VPP, so a tunnel current flows through the oxide film between the floating gate 2 and the P well 112 and is accumulated in the floating gate 2. electrons are extracted. This lowers the threshold. For unselected word lines, control gate 1 and P well 112
Since no potential difference occurs between them, no tunnel current flows, and the amount of charge accumulated in the floating gate 2 remains unchanged. That is, there is no change in the threshold voltage of the memory transistor, and the threshold voltage is maintained at a high level.

Next, FIG. 8 shows a circuit diagram of a row decoder that switches the word line voltage as described above. Compared to the conventional row decoder, an inverter 31 and a transfer gate 32 are added. The voltage application conditions are shown in FIG. Another embodiment of the row decoder is shown in FIG. The sources of N-channel MOS transistors 33 and 34 are connected to the word line. N-channel MOS transistor 35
, 36 and the capacitor 37 form a booster circuit. The voltage at the drains of transistors 33 and 34 is read/
There are differences between writing and erasing as shown in the figure. During writing, the selected word line is approximately at VCC (power supply voltage), and the unselected word line is grounded (GND). Then the signal φ
is input and the selected word line is boosted. A charge pump (boosting circuit) or a high voltage applied from the outside is applied to the drain of the transistor 35 during writing/erasing, and VCC is applied during reading. Note that the signal φ is the output of the oscillator.

[0022]

As described above, according to the inventions of claims 1 and 2, the memory array is formed in a P-well separate from the peripheral circuit, and a high voltage is applied to the P-well in which the memory array is formed during erasing. Since the voltage is applied, the problem of over-erasing does not occur and stable erasing is possible. Further, according to the invention of claim 6, the electrons injected into the floating gate are removed by applying a high voltage to the P-well, grounding the selected word line, and applying a high voltage to unselected word lines. Since only the memory transistors connected to the selected word line are selectively erased by applying the voltage, it is possible to erase the word line by word line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory array of an embodiment of a nonvolatile semiconductor memory device according to a first aspect of the invention.

FIG. 2 is a diagram showing a memory cell structure of an embodiment of a nonvolatile semiconductor memory device according to a second aspect of the invention.

FIG. 3 is a diagram showing a memory cell structure of an embodiment of a nonvolatile semiconductor memory device according to a third aspect of the invention.

FIG. 4 is a diagram showing a memory cell structure of an embodiment of a nonvolatile semiconductor memory device according to a fourth aspect of the invention.

FIG. 5 is a diagram showing a memory cell structure of an embodiment of a nonvolatile semiconductor memory device according to a fifth aspect of the invention.

FIG. 6 is a diagram showing a memory cell structure of an embodiment of a nonvolatile semiconductor memory device according to a sixth aspect of the invention.

FIG. 7 is a diagram showing the structure of a memory array according to the embodiment of FIG. 6;

FIG. 8 is a circuit diagram of a row decoder according to the embodiment of FIG. 7;

9 is a diagram showing voltage application conditions in the circuit of FIG. 8. FIG.

FIG. 10 is a circuit diagram of another embodiment of the row decoder.

FIG. 11 is a diagram showing a memory cell structure of a conventional nonvolatile semiconductor memory device.

FIG. 12 is a block diagram of a conventional nonvolatile semiconductor memory device.

FIG. 13 is an equivalent circuit diagram of a conventional memory transistor.

FIG. 14 is a diagram for explaining voltage application conditions for selected memory cells during erasing, writing, and reading in a conventional example.

FIG. 15 is a diagram showing the structure of a conventional memory array.

FIG. 16 is a circuit diagram of a conventional row decoder.

[Explanation of symbols]

1 Control gate 2 Floating gate 3 Drain 4. Sauce 111 P board 112 P well 113 N-well

Claims (6)

[Claims] 1. Memory transistors each having a floating gate and a control gate are arranged in an array in the row and column directions, and the drain of the memory cell is connected to a bit line.
The gate line is connected to the word line, and the source is connected to the source line.The memory array is formed in a P well separate from the peripheral circuit, and during erasing, the memory array is connected to the P well where the memory array is formed. An erasing method for a nonvolatile semiconductor memory device characterized by applying a high voltage. 2. Memory transistors each having a floating gate and a control gate extending to the source side are arranged in an array in the row and column directions, the drains of the memory cells are connected to bit lines, the gate lines are connected to word lines,
The source is connected to the source line, the memory array is formed in a P-well separate from the peripheral circuitry, and a high voltage is applied to the P-well in which the memory array is formed during erasing. An erasing method in a nonvolatile semiconductor memory device characterized by: 3. A P substrate is used, a memory array is formed in a P well provided in an N well, and erasing is performed by applying a high voltage to the P and N wells and grounding the control gate. Claim 1 or Claim 2
erasing method in nonvolatile semiconductor memory devices. 4. An erasing method in a nonvolatile semiconductor memory device according to claim 1 or claim 2, characterized in that a negative high voltage is applied to the control gate. 5. The erasing method in a nonvolatile semiconductor memory device according to claim 1 or 2, characterized in that a positive voltage is applied to the P and N wells and a negative voltage is applied to the control gate. 6. A structure in which memory transistors are arranged in an array in row and column directions, each memory transistor has a floating gate and a control gate, and each memory transistor is formed on the same or divided P well. In order to remove the electrons injected into the floating gate, a high voltage is applied to the P-well, the selected word line is grounded, and a high voltage is also applied to the unselected word lines, and the selected word line is removed. An erasing method in a nonvolatile semiconductor memory device characterized by selectively erasing only memory transistors connected to a line.