JPH11134174A - Arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplication result at high speed in a synchronism circuit. SOLUTION: A partial product gate 10 finds a partial product by multiplying multiplicand data A [m-1:0] of m-bits by data B0 of the lowest order in the multiplier B [n-1:0]. Respective partial product gates 20-x ((x) is 1<=x<=n-1) obtain the partial products by multiplying multiplicand data A [m-1:0] of m-bits by data Bx of x-th bit from the lowest order in the multiplicand B [n-1:0] of n-bits. The partial products found by the respective partial product gates 10 and 20-x are summed up by an addition means 30 and the multiplication result Σ[m+n-1:0] of multiplicand data A [m-1:0] of m-bits and the multiplier B [n-1:0] of n-bits is found.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit incorporated in a synchronous circuit or the like to perform multiplication or division.

[0002]

2. Description of the Related Art A conventional synchronous circuit comprises m bits of data from a _0th bit data _A0 to a (m-1) th (m is a positive integer) bit data _Am-1. Multiplicand data A [m-1: 0] (where [m-1: 0]
Indicates the range of bit data), and multiplier data B composed of _n- bit data from the _0th bit data _B0 to the (n-1) th (n is a positive integer) bit data _Bn-1. Some include an arithmetic circuit that performs multiplication with [n-1: 0]. Further, in the conventional synchronous circuit, the dividend data C [m composed of _m- bit data from the _0th bit data _C0 to the (m-1) th bit data _{Cm-1 is provided.}
−1: 0] and the 0th bit data D ₀ to (n−
Some include an arithmetic circuit for performing division with divisor data D [n-1: 0] composed of _n- bit data up to the 1) th bit data D _n−1 . The arithmetic circuit that performs these multiplications or divisions operates in synchronization with a clock, and obtains a product as a final multiplication result and a quotient and a remainder as division results. FIG. 2 is a time chart showing a multiplication state of a conventional arithmetic circuit.

An arithmetic circuit that performs multiplication in synchronization with the clock Clk performs the following operations (a1) to (a6) to obtain a multiplication result. (A1) Clear all stored data such as flip-flops for storing data. (A2) For the data of data A [m-1: 0],
The data B ₀ is multiplied in synchronization with the clock Clk, and the multiplication result S ₀ is stored. (A3) data A [m-1: 0] it multiplies the bit data B ₁ data up one bit digit of the result of the multiplication S ₀ cumulatively adding the multiplication results, obtained in the cumulatively added obtained addition result storing S _1. (A4) Carry data A [m-1: 0] data by two bits, multiply it by bit data B ₂ , accumulatively add the addition result S ₁ to the multiplication result, and obtain this accumulative addition. cumulatively result storing S ₂ which is. (A5) Carry data A [m-1: 0] by three bits, multiply it by bit data B ₃ , add the result of the cumulative addition S ₂ to the result of the multiplication, and obtain the result by the cumulative addition. cumulative addition results stored S ₃ that is. (A6) Processing similar to the above (3) or (4) is continued. That is, the data of the data A [m−1: 0] is x
(X is a natural number) carry by bits and multiply by the bit data B _x , add the cumulative addition result S _x−1 obtained immediately before to the multiplication result, and obtain the cumulative result S obtained by this cumulative addition.
_The process of storing x is repeated until x becomes n-1. Finally, the cumulative result _Sx is obtained and the multiplicand data A [m-1:
0] and the multiplier data B [n-1: 0].

FIG. 3 is a time chart showing a division state of a conventional arithmetic circuit. The arithmetic circuit that performs the division performs the following operations (b1) to (b5) to obtain the division result. (B1) Clear all stored data such as flip-flops for storing data. (B2) The divisor data D [n] in synchronization with the clock Clk
-1: 0], the two's complement D _* of the next clock Clk is obtained.
In synchronization with the uppermost n-bit data C [m
−1: m−n], the two's complement D _* of the divisor data D [n−1: 0] is added, and the remainder E and the quotient F are obtained from the addition result.
Get. The quotient is "1" when the addition result is positive or zero,
When the addition result is negative, it becomes "0". (B3) The divisor data D [n] in synchronization with the clock Clk
-1: 0], the two's complement D _* of the next clock Clk is obtained.
The 2's complement D _* of the divisor data D [n−1: 0] is added to the upper n bits of the remainder in synchronization with
A remainder E and a quotient F are obtained from the addition result. The quotient becomes "1" when the addition result is positive or zero, and becomes "0" when the addition result is negative. (B4) The divisor data D [n] in synchronization with the clock Clk
-1: 0], the two's complement D _* of the next clock Clk is obtained.
In synchronism with the upper n of the remainder obtained in the process of (b3).
The 2's complement D _* of the divisor data D [n-1: 0] is added to the bit data, and the remainder E and the quotient F are obtained from the addition result.
Get. The quotient is "1" when the addition result is positive or zero,
When the addition result is negative, it becomes "0". (B5) Thereafter, the processes of (b3) and (b4) are sequentially repeated, and the calculation is stopped when the addition result becomes smaller than the data B. Then, the quotient F obtained so far is output in parallel as a final quotient, and the finally obtained E is output as a remainder.

[0005]

However, the conventional arithmetic circuit has the following problems. In the arithmetic circuit that performs multiplication, as shown in FIG. 2, the operations (a2) to (a6) are performed in synchronization with the clock CK. Therefore, the state change of the division in the arithmetic circuit is at most one per clock. ,
Until the final multiplication result is obtained by multiplication with many state changes,
There was a problem that it took time. Also in the arithmetic circuit for performing the division, as shown in FIG. 3, the operations (b2) to (b5) are performed in synchronization with the clock Clk. There is a problem that it takes time to obtain a proper division result.

[0006]

In order to solve the above-mentioned problems, the first and second inventions of the present invention provide an arithmetic circuit for multiplying an m-bit multiplicand by an n-bit multiplier. , A (n-1) second partial product gate, and an adding means. The first partial product gate is a circuit that calculates a partial product by multiplying the multiplicand by the value of the least significant bit of the multiplier.
Each of the second partial product gates inputs the multiplicand in parallel, and outputs x-th (x is a natural number of 1 ≦ x ≦ n−1) bit from the least significant bit of the multiplicand and the multiplier. To obtain partial products, respectively, and output the partial products in a state where they are carried up by x digits. The adding means is means for calculating the first partial product gate and the respective second partial product gates and summing up the zero partial products.

The third and fourth inventions are directed to an arithmetic circuit for dividing an m-bit dividend and an n-bit divisor, wherein the following complement means, a first divisor block, and (m-
n) stage of second division block. The complement means is means for calculating the two's complement of the divisor. The first division block adds the two's complement to the upper n bits of the dividend and outputs "1" as a quotient when the result of the addition indicates a positive or zero value. Then, the lower (mn) bits of the dividend are added and output as a remainder, and when the addition result indicates a negative value, "0" is output as a quotient and the dividend is output as the remainder as it is. It has a configuration. (M-
Each second division block of the n) stage is cascade-connected to the first division block, and adds the two's complement to the data of the upper (n + 1) bits of the remainder number given from the previous stage, and this addition result Indicates a positive or zero value, "1" is output as a quotient, and the lower (m-n-y) bits (y is 1) of the remainder given from the preceding stage to the effective bit of the addition result. ≤ y ≤ mn) and output them as remainders of the own stage. When the addition result indicates a negative value, "0" is output as a quotient and the remainder number given from the preceding stage Are output as the remainders of the stage. Then, each quotient output from the first division block and each of the second division blocks is output in parallel as a quotient obtained by dividing the dividend by the divisor, and the quotient is output from the last stage of the second division block. The remainder is obtained by dividing the dividend by the divisor.

According to the first and second inventions, since the arithmetic circuit is configured as described above, the first partial product gate,
By providing a multiplicand and a multiplier to the (n-1) second partial product gates, a partial product required for multiplication can be obtained independently of a clock. By adding these partial products, the result of multiplication of the multiplicand and the multiplier is immediately obtained.
According to the third and fourth aspects of the present invention, by giving a divisor to the complement means, the two's complement of the divisor is obtained. When the two's complement is given to the first division block, the quotient and the remainder are obtained by the first division block. (M
-N) Each second division block of the stage performs addition of the remainder number given from the previous stage and a two's complement, obtains a quotient according to the addition result, and obtains the remainder number, respectively, to the subsequent stage. Give each. These operations are performed without synchronization with the clock. The quotients obtained in the first division block and the respective second division blocks in the (mn) stages are output in parallel, so that the final quotient obtained by dividing the dividend by the divisor is output. Then, the remainder corresponding to the quotient is output from the second division block in the final stage. Therefore, the above problem can be solved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of an arithmetic circuit according to a first embodiment of the present invention. This arithmetic circuit is provided in a synchronizing circuit or the like, and provided multiplicand data A [m−1: 0] and multiplier data B
This is a circuit that performs multiplication with [n-1: 0], a first partial product gate 10 to which parallel multiplicand data A [m-1: 0] is input, and a parallel multiplicand data A [m-1]. :
0] are input to each of the (n-1) second partial product gates 20-1 to 20- (n-1). Adder means 30 is connected to the output side of the partial product gates 10, 20-1 to 20- (n-1). 4A and 4B are circuit diagrams showing examples of the configuration of the partial product gate in FIG. 1. FIG. 4A shows the partial product gate 10, and FIG. 4B shows each partial product gate. A gate 20-x (x is a natural number of 1 ≦ x ≦ n−1) is shown. The partial product gate 10 outputs the multiplicand data A [m
-1: 0], the multiplier data B [n-1: 0] is intended to obtain the first partial product S10 by multiplying the data B ₀ of, each data A ₀ to A _m-1 an input terminal sequence input, and having an input terminal to which data B ₀ is input, the data a ₀ ~A _m-1 is input to one input terminal, the data B ₀ to the other input terminal common to the m input 2 input aND gate 11 ₀ to 11 _m-1 to have respectively provided. Each AND gate 11 ₀ to 11 _m-1, the
The product of the data A ₀ -A _m-1 and the data B ₀ is obtained, and the output data of the AND gates 11 ₀ -11 _m-1 is a partial product S10.

[0010] Each partial product gate 20-x is multiplicand data A [m-1: 0] and, multiplier data B [n-1: 0] Data B _x and the multiply partial products S20-x of the are those respectively obtained, and the input terminal rows each data a ₀ ~A _m-1 is input, and having an input terminal to which data B _x is input, each data a ₀ ~A _m-1 one M input 2-input AND gates 21 _{0 to} 21 to which data B _x is commonly input to the other input terminals.
_m-1 . Each AND gate 21 ₀ to 2
1 _m-1 is for obtaining the product of the data A ₀ to A _m-1 and the data B _x, respectively, these AND gates 21 ₀ ~
The output data of 21 _m-1 is configured to be a partial product S20-x. Note that each partial product S20-1 is a partial product S1.
0 is carried by x digits each, and the adding means 3
The multiplicand data A [m-1: 0] input to each of the partial product gates 20-x is input while shifting the bus so that the input is 0.

FIG. 5 is a time chart showing the multiplication state of FIG. 1. The operation of FIG. 1 will be described with reference to FIG. When the multiplicand data A [m−1: 0] and the multiplier B [n−1: 0] are given to the arithmetic circuit of FIG. 1 in synchronization with the clock Clk, the partial product gate 10 causes the multiplicand data A
The product of [m−1: 0] and data B ₀ is obtained to obtain a partial product S1
Output as 0. Each partial product gate 20-x obtains a product of the multiplicand data A [m-1: 0] and the data _Bx and outputs the product as a partial product S20-x. Partial product S10,
20-x is given to the adding means 30 in a state where the digits are adjusted, and the adding means 30 makes these partial products S10 and 20-x
Σ [m + n−1: 0]. The sum Σ [m + n−1: 0] output from the adding means 30 is a multiplication result of the multiplicand data A [m−1: 0] and the multiplier B [n−1: 0]. As described above, in the first embodiment, the arithmetic circuit that performs the multiplication of the multiplicand data A [m−1: 0] and the multiplier B [n−1: 0] includes the partial product gate 10 and (n −
Since 1) partial product gates 20-x and the adding means 30 are used, the operation is executed asynchronously, and as shown in FIG.
Conventionally, the operation time required for multiplication by the clock time for n bits (n × 1 time) can be completed only by the gate delay generated in the operation circuit.

Second Embodiment FIG. 6 is a configuration diagram of an arithmetic circuit according to a second embodiment of the present invention. This arithmetic circuit is provided in a synchronous circuit or the like, and is provided with dividend data C [m−1: 0] and divisor data D
A circuit for performing division with [n-1: 0], a complement means 40 for obtaining a two's complement D _* [n-1: 0] of the divisor data D [n-1: 0], A division block 50 and second division blocks 60-1, 60-2, ..., 60- of (mn) stages cascade-connected to the output side of the division block 50.
(Mn). Each division 50, 60-1 to 60
− (Mn) is the two's complement D obtained by the complement means 40
_* [N-1: 0] is input via the bus b. FIGS. 7A and 7B are block diagrams showing the division block in FIG. 6, wherein FIG. 7A shows the division block 50 and FIG. 7B shows the division block 60- (mny). ing. Here, y is a natural number satisfying 1 ≦ y ≦ mn. The division block 50 has an adder 51 and a two-input selector 52 connected to the adder 51. The adder 51 is composed of, for example, a two-input adder in which a general half adder circuit is the least significant bit and the upper side is a full adder circuit. The adder 51 adds 2 bits to the upper n bits of the dividend data C [m−1: 0].
In order to add the complement D _* [n-1: 0], the two's complement D [n-1:
0] is input with the bus position shifted. Adder 5
The output side of the addition result s50 of 1 is connected to one input side of the selector 52, and the carry signal c of the adder 51
a ₅₀ is a connection input to the selection terminal of the selector 52. The other input side of the selector 52 is connected to receive the dividend data C [m−1: 0], and the remainder number data H [m−
1: 0] is output to the subsequent stage.

Each of the division blocks 60- (mny) has the same configuration, and includes an adder 61 and a 2 connected to the adder 61.
And an input selector 62. Adder 61
Are each configured by, for example, a two-input adder in which a half adder circuit is the least significant bit and the upper side is a full adder circuit. In each adder 61, the data of the higher (n + 1) bits of the remainder data H [my: 0] given from the preceding stage is added to the two's complement D
_* To add [n-1: 0], the dividend data C
Two's complement D _* [n-1: 0] for [m-1: 0]
Are input while shifting the bus position. The output side of the addition result s61 of the respective adders 61 is connected to one input of the selector 62 and the carry signal ca _y of each of the adders 61 are in connected inputted to the selection terminal of the selector 62. The other input side of the selector 62 is connected to input data H [my: 0],
Data H [my-1: 0] output from the selector 62
Are output to the subsequent stages, respectively. Then, the second division block 60 of the (mn) -th stage of the last stage
The configuration is such that the final remainder number data H [n−1: 0] is output from the output side of the selector 62 in − (mn).

FIG. 8 is a time chart showing the division state of the arithmetic circuit of FIG. 6. The operation of FIG. 6 will be described with reference to FIG. In synchronization with the clock Clk, the dividend data C [m−1: 0] and the divisor data D
When [n-1: 0] is given, the complement means 40 outputs the two's complement D _* [n-1: 0] of the divisor data D [n-1: 0].
And the two's complement D _* [n-1: 0] is given to the adders 51 and 61 of each of the division blocks 50 and 60- (mny). Adder 51 in division block 50
Adds a 2's complement D _* [n-1: 0] to the upper n bits of data of the dividend data C [m-1: 0], and provides an addition result s50 to one input side of the selector 52. At the same time, the adder 51, two's complement _{D * [n-1: 0} ] is the dividend data C [m-1: 0] is greater than, and outputs a carry signal ca ₅₀ of "0" as the quotient , Two's complement D
_* [N-1: 0] is the dividend data C: smaller than or equal to [m-1 0], and outputs a carry signal ca ₅₀ "1" as the quotient. When the carry signal ca ₅₀ is “0”, the selector 52 receiving the carry signal ca ₅₀ outputs
Dividend data C [m-1: 0] data H as it is selected and the number of remainder [m-1: 0] outputs, in the case of the carry signal ca ₅₀ is "1", selects the addition result s51 On the lower side of the dividend data C [m-1: 0].
n) bits are added, and this is set as a remainder, and the data H [m
-1: 0] is output.

The adder 61 in each of the division blocks 60- (mny) has a remainder number data H [m-
y: 0], the 2's complement D _* [n
−1: 0], and the addition result s61 is provided to one input side of the selector 62. At the same time, each adder 61 converts the two's complement D _* [n-1: 0] to the data H [m
-Y: larger than 0, and outputs a carry signal ca _y "0" as the quotient, 2's complement D _* [n-1: Data 0] is given from the preceding stage H [m-y: 0 smaller or equal to, and outputs the carry signal ca _y "1" as the quotient. Each selector 62 inputs the carry signal ca _y is the carry signal ca _y is a residue number data H in the case of "0" [m-y: 0] Valid data H of the
[M-y-1: 0 ] selects and outputs the dividend, in the case of the carry signal ca _y is "1", the addition result s61
To the lower side of the data H [my: 0] (m
-N-1) bits, and the remainder is represented by the remainder data H [m
-Y-1: 0]. Each block 5
Carry signal c determined between 0 and 60- (mny)
a _50, ca _y is the dividend C [m-1: 0] of the divisor D [n
-1: 0] and output in parallel as a quotient divided by [-1: 0].
In this case, carry signal ca ₅₀ becomes the uppermost bit,
ca _mn becomes the data of the least significant bit. From the output side of the last division block 60- (mn), the remaining data H [n-1: 0] is output.

As described above, in the second embodiment,
The arithmetic circuit for performing the division is a complement means 40, a first division block 50, and a second division block 60 of (mn) stages.
, 60- (mn), each of the division blocks 50, 60-1 to 60- (mn) is added to an adder 51,
61 and selectors 52 and 62. Therefore, the dividend data C [m-1: 0] and the divisor data D [n
-1: 0], the division state is conventionally changed in a time of two clocks, and as a whole 2 × (m−
n) Although the time required for the clock is required, in the configuration of FIG. 6, the dividend data C [m−
1: 0] and the divisor data D [n-1: 0], the quotient and remainder are automatically obtained. That is,
The process ends in one clock time. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(1) In the first embodiment, multiplicand data A [m-1: input to each partial product gate 20-x:
[0] is input while shifting the bus position. However, even if a configuration in which the bus position is fixed and a value of “0” is input as appropriate is adopted, each of the partial products S10 by x digits may be used. You can set the carry state. (2) In the second embodiment, each division block 60-
(Mny), the residual data H given from the previous stage
In order to add the two's complement D _* [n-1: 0] to the data of the upper (n + 1) bits of [my: 0], 2 is added to the dividend data C [m-1: 0]. The complement D _* [n−
1: 0] are input while shifting the bus position, but the same operation is possible even if a configuration is adopted in which the bus position is fixed and a value of “0” is input as appropriate. Has the effect of

[0018]

As described above in detail, according to the first and second aspects, the first partial product gate for multiplying the multiplicand by the value of the least significant bit of the multiplier, A plurality of second partial product gates for performing multiplication with the data of the x-th bit from the least significant bit;
And the addition means for summing the partial products obtained by the partial product gates of (1) and (2) form an arithmetic circuit, so that the multiplication of the m-bit multiplicand and the n-bit multiplier can be obtained irrespective of the clock time, and the operation time is greatly Can be shortened to According to the third and fourth aspects of the present invention, the complement means for obtaining the 2's complement of the divisor, the first division for adding the 2's complement to the upper n bits of the dividend, and obtaining the quotient and the remainder based on the addition result Block and a first division block, cascade-connected to each other, add a two's complement to the data of the upper (n + 1) bits of the remainder number given from the previous stage, and calculate a quotient and a remainder number based on the addition result. 2 divided blocks are output in parallel as quotients obtained by dividing the dividend by the divisor. The quotients output from the first division block and the respective second division blocks are output in parallel from the last stage of the second division block. Since the remainder obtained by dividing the dividend by the divisor is output, the division of the m-bit dividend and the n-bit divisor is obtained irrespective of the clock time, and the operation time can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an arithmetic circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing a multiplication state of a conventional arithmetic circuit.

FIG. 3 is a time chart showing a division state of a conventional arithmetic circuit.

FIG. 4 is a circuit diagram showing a configuration example of a partial product gate in FIG. 1;

FIG. 5 is a time chart showing a multiplication state in FIG. 1;

FIG. 6 is a configuration diagram of an arithmetic circuit according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a division block in FIG. 6;

FIG. 8 is a time chart showing a division state of FIG. 6;

[Explanation of symbols]

10 First partial product gate 20-1 to 20- (n-1) Second partial product gate 30 Addition means 40 Complement means 50 First division block 60-1 to 60- (mn) Second division block A [m-1: 0] Multiplicand B [n-1: 0] Multiplier S10, S20-x Partial product C [m-1: 0] dividend D [n-1: 0] divisor H [n-1: 0] ], H [m-y- 1: 0] dividend ca _50, ca _y carry signal (quotient)

Claims (4)

[Claims] An arithmetic circuit for multiplying a multiplicand of m bits (m is a positive integer) by a multiplier of n bits (n is a positive integer), wherein a least significant bit of the multiplicand and the multiplier is And a first partial product gate for obtaining a partial product by multiplying the multiplicand with the value of the multiplicand. The multiplicand is input in parallel, and x (x is 1 ≦ x) from the least significant bit of the multiplicand and the multiplier. ≤
(n-1) second partial product gates are obtained by multiplying the data by the (n-1) th bit to obtain partial products, and outputting the partial products in a state where they are carried up by x digits. And an adding means for summing partial products obtained by the first partial product gate and each of the second partial product gates. 2. It is incorporated in a synchronous circuit and has m bits (m is
An arithmetic circuit for multiplying a multiplicand of (positive integer) by an n-bit (n is a positive integer) multiplier, multiplying the multiplicand by the value of the least significant bit of the multiplier to obtain a partial product The first partial product gate to be obtained and the multiplicand are input in parallel respectively, and x (x is 1 ≦ x ≦ 1) from the least significant bit of the multiplicand and the multiplier
(n-1) second partial product gates are obtained by multiplying the data by the (n-1) th bit to obtain partial products, and outputting the partial products in a state where they are carried up by x digits. And an adding means for summing partial products obtained by the first partial product gate and each of the second partial product gates. 3. An arithmetic circuit for dividing a dividend of m bits (m is a positive integer) and a divisor of n bits (n is a positive integer of m ≧ n), wherein a two's complement of the divisor is The complement means to be obtained; and adding the two's complement to the upper n bits of the dividend, and outputting a "1" as a quotient when the addition result indicates a positive or zero value. The lower (mn) bits of the dividend are added and output as a remainder, and when the addition result indicates a negative value, "0" is output as a quotient and the dividend is output as the remainder as it is. 1 division block and the first division block are cascaded, and the data of the higher (n + 1) bits of the remainder number given from the previous stage is added to the 2
When the result of the addition indicates a positive or zero value, "1" is output as a quotient, and the lower bits (m-n) of the remainder given from the preceding stage to the effective bits of the addition result are added. −y) bits (y is a natural number of 1 ≦ y ≦ mn) are added and output as the remainder of the own stage, and when the addition result indicates a negative value, “0” is output as a quotient. And (m-n) second division blocks each of which outputs a significant bit of the remainder number given from the previous stage as the remainder number of the own stage, wherein the divide by the dividend is divided by the divisor. Each quotient output from the first division block and each of the second division blocks is outputted in parallel, and the remainder obtained by dividing the dividend by the divisor is outputted from the last stage of the second division block. An arithmetic circuit characterized by the above. 4. An arithmetic circuit incorporated in a synchronous circuit for performing a division of an m-bit (m is a natural number) dividend and an n-bit (n is a natural number of m ≧ n) divisor, wherein a 2's complement of the divisor is provided. And the two's complement is added to the upper n bits of the dividend, and when the addition result indicates a positive or zero value, “1” is output as a quotient and the effective bit of the addition result is Then, the lower (mn) bits of the dividend are added and output as a remainder, and when the addition result indicates a negative value, "0" is output as a quotient and the dividend is output as the remainder as it is. A first division block, cascade-connected to the first division block, and the upper (n + 1) -bit data of the remainder number given from the previous stage
When the result of the addition indicates a positive or zero value, "1" is output as a quotient, and the lower bits (m-n) of the remainder given from the preceding stage to the effective bits of the addition result are added. −y) bits (y is a natural number of 1 ≦ y ≦ mn) are added and output as the remainder of the own stage, and when the addition result indicates a negative value, “0” is output as a quotient. And (m-n) second division blocks each of which outputs a significant bit of the remainder number given from the previous stage as the remainder number of the own stage, wherein the divide by the dividend is divided by the divisor. Each quotient output from the first division block and each of the second division blocks is outputted in parallel, and the remainder obtained by dividing the dividend by the divisor is outputted from the last stage of the second division block. An arithmetic circuit characterized by the above.