CN102591615A - Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device - Google Patents
Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device Download PDFInfo
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Abstract
The invention discloses a structured mixed bit-width multiplying method and a structured mixed bit-width multiplying device. The method includes the steps: 1) inputting a multiplier, a multiplicand and a computing control signal; 2) splitting the multiplier and the multiplicand and performing sign bit expansion for the multiplier and the multiplicand; 3) importing the multiplier and the multiplicand to two MXN multiplying units for Booth decoding and generating partial products, and compressing the partial products; 4) generating a corrected value; and 5) compressing a compressed output result and the corrected value to obtain a multiplying result. The device comprises an operand selection and expansion unit, the first MXN multiplying unit, the second MXN multiplying unit, a correcting unit and a final product arithmetic element, wherein the operand selection and expansion unit is connected with the final product arithmetic element through the MXN multiplying unit, the second MXN multiplying unit and the correcting unit. The structured mixed bit-width multiplying device has the advantages of high hardware use ratio and area use ratio, high arithmetic speed, low hardware expenditure, simple structure and orderliness in obtained territory.
Description
Technical field
The present invention relates to processor and relate to the field, be specifically related to the method and the device of a kind of implementation structure mixing bit wide multiplying.
Background technology
Multiplier is the key operation parts of Modern microprocessor, and the multiplying number of times of accomplishing in the unit interval is an important indicator weighing microprocessor performance.Different arithmetic types has different demands to the bit wide of multiplier.In science was calculated, 32 and 64 was basic requirement, and therefore directly 32 of supports or 64 s' multiply operation of specialised hardware generally all is set in high-performance microprocessor.In multimedia and communication class application, most of arithmetic type is 8 and 16.In order to improve the ability of little bit wide data processing, many processors have all increased the SIMD instruction.The SIMD instruction once can be done same operation to a plurality of data, has improved the processing power of little bit wide computing greatly.SIMD has dual mode on hardware is realized, a kind of is that special SIMD parts are set, and these parts only can be carried out the SIMD operation, like the MMX parts among the PentumII; Another kind is that original arithmetic unit is improved, and makes it both keep original arithmetic capability, possesses the ability of new execution SIMD operation again, like Intel XScale.A kind of implementation method in back; Need not carry out big change to architecture; Its multi-medium data processing power is doubled; Therefore in the design of embedded microprocessors such as DSP, obtained using widely, all adopted this method like the design of the up-to-date DSP multiplier of TI company and AD company.
In order to realize mixing the bit wide multiplying, prior art comprises two kinds of methods: a kind of direct implementation method is that a plurality of multipliers are set, and the shortcoming of this method is that hardware spending is big; Another kind method is to adopt the flowing water technology, and like Intel XScale, its shortcoming is to have improved CPI, the instruction number of accomplishing in promptly single the bat.Therefore, high-performance, low-power consumption microprocessor Design press for a kind of bit wide Multiplier Design technology of mixing efficiently.And multiplier now commonly used generally comprises, and this decoding of cloth, partial product produce, partial product is compressed three parts.Bu Si decoding is at first deciphered multiplier, produces control signal control multiplicand and produces partial product, then partial product is sent into the compression array addition and produces last product.The partial product compression array generally adopts the Wallace tree structure; In order to shorten line; The compression module of when layout, usually coordination being weighed is placed on same row, and the domain that obtains at last generally is the shape of parallelogram, and therefore certain waste is arranged on area; When the multiplier bit wide was very big, the area waste was even more serious.In order to improve the area utilization of multiplier domain, need carry out new design to multiplier.When full customization multiplier domain was realized, the corresponding a kind of partial product compression array structure of a kind of operand of bit wide when the bit wide of input changes, need be adjusted even design again compression array, and the reusability of domain is not high.Full custom design can well improve design performance, but the process that realizes is quite consuming time, in order to improve the design efficiency of multiplier, also need explore the implementation algorithm of multiplier.
Summary of the invention
The technical matters that the present invention will solve provide a kind of hardware utilization factor and area utilization height, fast operation, hardware spending little, obtain domain structuring regular, simple in structure and mix bit wide multiplying method and device.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopts is:
A kind of structuring mixes bit wide multiplying method, and implementation step is following:
1) the s operation control signal of importing multiplier, multiplicand and comprising arithmetic type, sign bit;
2) according to said arithmetic type multiplier, multiplicand are split, the multiplicand after splitting is carried out the sign bit expansion according to said sign bit;
3) will split with sign bit expansion after multiplier, multiplicand send into respectively that two M * N multiplier carries out this decoding of cloth, partial product generates, and the partial product that all M * N multiplier generates is compressed respectively;
4) generate modified value according to arithmetic type in the said s operation control signal and sign bit;
5) modified value that all output results that the compression of said step 3) obtained and said step 4) obtain is compressed and is obtained multiplication result.
Mix bit wide multiplying further improvements in methods as structuring of the present invention:
Arithmetic type in the said step 1) comprises 1 M * 2N multiplying and 2 (M/2) * N multiplying.
Said step 2) according to arithmetic type the detailed step that multiplier, multiplicand split is comprised in: if arithmetic type is 1 M * 2N multiplying, then multiplier is split as high-order multiplier part and low level multiplier part, multiplicand remains unchanged; If arithmetic type is 2 (M/2) * N multiplying, then multiplier is split as high-order multiplier part and low level multiplier part, and M position multiplicand is split as high-order multiplicand part and the low level multiplicand part that is the M/2 position.
Said step 2) according to said sign bit the detailed step that the multiplicand after splitting carries out the sign bit expansion is comprised in: if said arithmetic type is 1 M * 2N multiplying of realization, then multiplicand remains unchanged; If said arithmetic type for realizing 2 (M/2) * N multiplying, then with the low level expansion 0 of high-order multiplicand part, is partly done sign extended with the low level multiplier.
To split in the said step 3) with sign bit expansion after multiplier, multiplicand send into two M * N multiplier respectively and specifically be meant: if said arithmetic type is for realizing 1 M * 2N multiplying; Then high-order multiplier part and multiplicand are sent into a M * N multiplier, low level multiplier part and multiplicand are sent into another M * N multiplier; If said arithmetic type is for realizing 2 (M/2) * N multiplying, then high-order multiplicand part and the multiplicand after the low level expansion 0 sent into a M * N multiplier, and part of the low level multiplier after the sign extended and multiplicand are sent into another M * N multiplier.
Detailed step according to arithmetic type in the said s operation control signal and sign bit generation modified value in the said step 4) comprises: if said arithmetic type is 1 M * 2N multiplying of realization, then generating modified value is 0; If said arithmetic type is for realizing 2 (M/2) * N multiplying, and the operation result of part of the low level multiplier after the said sign extended and multiplicand is negative, and (the M/2)+N position that then generates modified value is 1, and all the other are 0.
The concrete steps that the partial product that in the said step 3) all M * N multiplier is generated is compressed comprise: the partial product that at first all M * N multiplier is generated is according to array or tree-like arrangement, then a plurality of partial products on each in the said arrangement compressed the result who obtains the mode of representing with redundancy.
The present invention comprises that also a kind of structuring mixes bit wide multiplying device; Comprise be used for according to the s operation control signal multiplier, the multiplicand of input split and the operand of sign bit expansion select expanding element, the one M * N multiplier, the 2nd M * N multiplier, be used to revise multiplication result low level multiplication symbol position amending unit, be used for the modified value of amending unit output is compressed the finant product arithmetic element that obtains multiplication result with the result of multiplying, said operand is selected expanding element to pass through the one M * N multiplier, the 2nd M * N multiplier, amending unit respectively to link to each other with said finant product arithmetic element.
Mix the further improvement of bit wide multiplying device as structuring of the present invention:
Said the one M * N multiplier is the identical multiplication module of structure with the 2nd M * N multiplier; Said multiplication module comprises this decoding module of cloth, partial product generation module, the partial product compression module of series connection successively; The input end of said this decoding module of cloth selects expanding element to link to each other with operand, and the output terminal of said partial product compression module links to each other with the finant product arithmetic element.
Said partial product compression module comprises the processed compressed logic that is used for storing long-pending partial product storage organization of said partial product generation module output and the partial product processed compressed that is used for the partial product storage organization is stored; The input end of said partial product storage organization links to each other with said partial product generation module; The output terminal of said partial product storage organization links to each other through the said finant product arithmetic element of processed compressed logical and, and said partial product storage organization is tree structure or array structure.
Structuring of the present invention mixes bit wide multiplying method and has following advantage:
1, the present invention is through splitting operand according to arithmetic type and sign bit expansion, generating modified value according to arithmetic type in the s operation control signal and sign bit; And the result of M * N multiplier output and modified value compressed obtain multiplication result; Can realize the multiplying of 2 (M/2) * N or two kinds of bit wides of 1 M * 2N through same set of hardware, the utilization factor of hardware resource is high, hardware spending is little.
2, agent structure of the present invention is 2 M * N multiplier; The design complexity of M * N multiplier is than much lower with M * 2N multiplier; The present invention can make up M * 2N multiplier through 2 M * N multiplier, have simple in structure, obtain the advantage that domain is regular, area utilization is higher.
3, the compression first time can only be carried out to partial product in the single M of the present invention * N multiplier inside, and the output resume as a result after will compressing then carries out the compression second time, can effectively promote the multiplying speed of multiplier.
Structuring of the present invention mixes bit wide multiplying device and mixes the corresponding structure of bit wide multiplying method owing to have structuring, therefore also has the utilization factor height, fast operation of hardware resource, the advantage that hardware spending is little, simple in structure, area utilization is higher; Partial product compression module of the present invention further comprises the processed compressed logic that is used for storing long-pending partial product storage organization of said partial product generation module output and the partial product processed compressed that is used for the partial product storage organization is stored; And the partial product storage organization is tree structure or array structure, and the domain that obtains is more regular.
Description of drawings
Fig. 1 mixes the schematic flow sheet of bit wide multiplying method for embodiment of the invention structuring.
Fig. 2 is the contraction principle synoptic diagram of embodiment of the invention M * N multiplier partial product.
Fig. 3 mixes the framed structure synoptic diagram of bit wide multiplying device for embodiment of the invention structuring.
Fig. 4 is the schematic flow sheet that the embodiment of the invention realizes 1 M * 2N multiplication.
Fig. 5 is the schematic flow sheet that the embodiment of the invention realizes 2 (M/2) * N multiplication.
Marginal data: 1, operand is selected expanding element; 21, the one M * N multiplier; 22, the 2nd M * N multiplier; 23, this decoding module of cloth; 24, partial product generation module; 25, partial product compression module; 3, amending unit; 4, finant product arithmetic element.
Embodiment
As shown in Figure 1, the implementation step that the present embodiment structuring mixes bit wide multiplying method is following:
1) the s operation control signal of importing multiplier, multiplicand and comprising arithmetic type, sign bit;
2) according to arithmetic type multiplier, multiplicand are split, the multiplicand after splitting is carried out the sign bit expansion according to sign bit;
3) will split with sign bit expansion after multiplier, multiplicand send into respectively that two M * N multiplier carries out this decoding of cloth, partial product generates, and the partial product that all M * N multiplier generates is compressed respectively;
4) generate modified value according to arithmetic type in the s operation control signal and sign bit;
5) modified value that all output results that step 3) compression obtained and step 4) obtain is compressed and is obtained multiplication result.
Comprise twice compression process in the present embodiment altogether, compression is for the first time accomplished in step 3), and its compressed object is a partial product; Compression is for the second time accomplished in step 5), and its compressed object is that all compress the result of output and the modified value that step 4) produces, the multiplication result of the result of its output for finally obtaining for the first time.
Arithmetic type in the step 1) comprises 1 M * 2N multiplying and 2 (M/2) * N multiplying.
Step 2) according to arithmetic type the detailed step that multiplier, multiplicand split is comprised in: if arithmetic type is 1 M * 2N multiplying, then multiplier is split as high-order multiplier part and low level multiplier part, multiplicand remains unchanged; If arithmetic type is 2 (M/2) * N multiplying, then multiplier is split as high-order multiplier part and low level multiplier part, and M position multiplicand is split as high-order multiplicand part and the low level multiplicand part that is the M/2 position.Step 2) according to sign bit the detailed step that the multiplicand after splitting carries out the sign bit expansion is comprised in: if arithmetic type is 1 M * 2N multiplying of realization, then multiplicand remains unchanged; If arithmetic type for realizing 2 (M/2) * N multiplying, then with the low level expansion 0 of high-order multiplicand part, is partly done sign extended with the low level multiplier.
To split in the step 3) with sign bit expansion after multiplier, multiplicand send into two M * N multiplier respectively and specifically be meant: if arithmetic type is for realizing 1 M * 2N multiplying; Then high-order multiplier part and multiplicand are sent into a M * N multiplier, low level multiplier part and multiplicand are sent into another M * N multiplier; If arithmetic type is for realizing 2 (M/2) * N multiplying, then high-order multiplicand part and the multiplicand after the low level expansion 0 sent into a M * N multiplier, and part of the low level multiplier after the sign extended and multiplicand are sent into another M * N multiplier.The concrete steps that the partial product that in the present embodiment step 3) all M * N multiplier is generated is compressed comprise: the partial product that at first all M * N multiplier is generated is according to array or tree-like arrangement, and a plurality of partial products in will arranging then on each are compressed the result who obtains the mode of representing with redundancy.As shown in Figure 2; This deciphers the control signal of available partial product to 21B through cloth for the multiplier after splitting; Can produce PPA partial product array 21C by this control signal, when compression adopt the method for 3-2 compression or 4-2 compression will arrange in a plurality of partial products on each compress the 21D as a result that obtains the mode of representing with redundancy.Wherein S is the redundant digit of identifier, when partial product is S=0 in correct time, as partial product S=1 when negative.E is a sign-extension bit, when multiplicand and partial product symbol contrary sign or partial product E=0 when being-0 * multiplicand, when multiplicand and partial product jack per line or partial product E=1 when being+0 * multiplicand.Can know that by this compression array shape can the partial product compression module on both sides be put together when the layout design constitutes row, make compression array more regular with this, thereby the domain that obtains is more regular.In addition, partial product equally also can reach according to tree-like arrangement and make the more regular technique effect of compression array domain more regular, that obtain.
Detailed step according to arithmetic type in the s operation control signal and sign bit generation modified value in the step 4) comprises: if arithmetic type is 1 M * 2N multiplying of realization, then generating modified value is 0; If arithmetic type is for realizing 2 (M/2) * N multiplying, and the operation result of part of the low level multiplier after the sign extended and multiplicand is negative, and (the M/2)+N position that then generates modified value is 1, and all the other are 0.
As shown in Figure 3; The present embodiment structuring mix bit wide multiplying device comprise be used for according to the s operation control signal multiplier, the multiplicand of input split and the operand of sign bit expansion select expanding element 1, the one M * N multiplier 21, the 2nd M * N multiplier 22, be used to revise multiplication result low level multiplication symbol position amending unit 3, be used for the modified value of amending unit 3 outputs is compressed the finant product arithmetic element 4 that obtains multiplication result with the result of multiplying, operand is selected expanding element 1 to pass through the one M * N multiplier 21, the 2nd M * N multiplier 22, amending unit 3 respectively to link to each other with finant product arithmetic element 4.
The one M of present embodiment * N multiplier 21 is the identical multiplication module of structure with the 2nd M * N multiplier 22; This multiplication module comprises this decoding module 23 of cloth, partial product generation module 24, the partial product compression module 25 of series connection successively; The input end of this decoding module 23 of cloth selects expanding element 1 to link to each other with operand, and the output terminal of partial product compression module 25 links to each other with finant product arithmetic element 4.The compression first time of present embodiment is accomplished in step 3) by partial product compression module 25, and compression is for the second time accomplished in step 5) by finant product arithmetic element 4.In the present embodiment; Partial product compression module 25 comprises the processed compressed logic that is used for long-pending partial product storage organization of long-pending generation module 24 outputs of storage area and the partial product processed compressed that is used for the partial product storage organization is stored; The input end of partial product storage organization links to each other with partial product generation module 24; The output terminal of partial product storage organization links to each other through processed compressed logical and finant product arithmetic element 4, and the partial product storage organization is tree structure or array structure.In the present embodiment, the partial product storage organization is an array structure, and finant product arithmetic element 4 also is an array structure.With reference to Fig. 2, partly accumulating storage structure in the present embodiment is that array structure can make the more regular technique effect of compression array domain more regular, that obtain; In addition, the partial product storage organization is that tree structure equally also can reach and makes the more regular technique effect of compression array domain more regular, that obtain.
As shown in figures 1 and 3, arithmetic type control signal 10C is used to indicate common multiplication or the SIMD multiplication of 2 (M/2) * N that current multiplication is 1 M * 2N, indicate current multiplication simultaneously has sign multiplication or no sign multiplication; The bit wide of multiplicand 10A and multiplier 10B is respectively M and 2N.Operand is selected expanding element 1 at first multiplicand 10A and multiplier 10B to be broken and is obtained 11A, 11B, 11C, 11D; Multiplicand 11A after the fractionation, 11C send into the one M * N multiplier 21 with multiplier 11B, 11D combination respectively and the 2nd M * N multiplier 22 carries out this decoding of cloth, partial product produces and the squeeze operation of one-level partial product.The one M * N multiplier 21 and the 2nd M * N multiplier 22 common properties give birth to two groups of 21A as a result, 22A after the compression, and amending unit 3 produces a modified value 3A simultaneously, send into finant product arithmetic element 4 in the lump and continue compression and obtain multiplication result.Operand selects module according to the arithmetic type control signal; When carrying out the common multiplication of a M * 2N, be the multiplier 10C of 2N multiplier 11B, 11D that to be divided into two bit wides be N with bit wide, if current be that sign multiplication is arranged; Multiplier after the partition is done sign extended, otherwise expand 0; When carrying out the SIMD multiplication of two (M/2) * N; Because hardware multiplexing; The multiplicand input position still is a number that bit wide is M; Will be that the multiplicand of M extracts height (M/2) position and low (M/2) position respectively this moment with bit wide, and high (M/2) multiplicand forms the multiplicand 11A that new bit wide is M to low level expansion (M/2) position 0, and whether low (M/2) position multiplicand is to have sign multiplication to do sign extended or the new bit wide of 0 expansion formation is the multiplicand 11C of M to a high position according to current multiplication.
As shown in Figure 4, realize that Src1 and Src2 are respectively multiplicand and the multiplier that bit wide is M and 2N in 1 M * 2N multiplication (common multiplication) calculating process, do not need in this case to revise, so the modified value of amending unit 3 outputs is 0.Step 2) in, multiplier Src1 remains unchanged, and the multiplicand Src2 of 2N position is split as high-order multiplicand part (Src2_H) and the low level multiplicand part (Src2_L) that is the N position.In the step 3); Src1 sends into the one M * N multiplier 21 (high-order M * N multiplier) with Src2_H and obtains the long-pending 21A of high-order portion; Src1 and Src2_L send into the 2nd M * N multiplier 22 (low level M * N multiplier) and obtain the long-pending 22A of low portion; If it is current for sign multiplication is arranged; The long-pending 22A of low portion needs obtain 22B to a high position expansion N position sign bit, otherwise 22A directly expansion 0 obtain 22B, 22B and high-order portion amass 21A and send into finant product arithmetic element 4 and continue to compress and obtain multiplication result 4A then.
As shown in Figure 5, realize that Src1 is a multiplicand in 2 (M/2) * N multiplication (SIMD multiplication) calculating process, Src2 is a multiplier.Step 2) in, multiplier Src1 is split as high-order multiplier part (Src1_H) and low level multiplier part (Src1_L), and multiplicand Src2 is split as high-order multiplicand part (Src2_H) and the low level multiplicand part (Src2_L) that is the M/2 position; Src1_H is to low level expansion 0 then, and Src1_L does sign extended, to high-order escape character position or 0.In the step 3); Src1_H after the low level expansion 0 sends into the one M * N multiplier 21 (high-order M * N multiplier) with Src2_H; Src1_L and Src2_L send into the 2nd M * N multiplier 22 (low level M * N multiplier) after the sign extended; The one M * N multiplier 21 computings obtain the long-pending 21A of high-order portion, and the 2nd M * N multiplier 22 computings obtain the long-pending 22A of low portion.Because SIMD multiplication and common multiplication are shared this multiplier architecture is so whether the long-pending 22A of low portion can will influence high-order SIMD multiplication and obtain correct result according to current for there being sign multiplication to do the sign bit expansion equally like this.When 22A is negative, that is when Src1_L and Src2_L opposite in sign, need be to this situation correction.(M/2)+N position of the modified value of amending unit 3 generations is 1 in such cases, and all the other positions are 0.If it is current for sign multiplication is arranged; The long-pending 22A of low portion needs to obtain 22B to a high position expansion N position sign bit; Otherwise 22A directly expansion 0 obtains 22B; Long-pending 22B of low portion after long-pending 21A of high-order portion and the expansion and modified value 3A send into the last product of finant product arithmetic element 4 completion together and calculate (the compression second time) like this, finally obtain the multiplication result 4A of two (M/2) * N multiplication.
The above only is a preferred implementation of the present invention, and protection scope of the present invention also not only is confined to the foregoing description, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art in the some improvement and the retouching that do not break away under the principle of the invention prerequisite, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (10)
1. a structuring mixes bit wide multiplying method, it is characterized in that implementation step is following:
1) the s operation control signal of importing multiplier, multiplicand and comprising arithmetic type, sign bit;
2) according to said arithmetic type multiplier, multiplicand are split, the multiplicand after splitting is carried out the sign bit expansion according to said sign bit;
3) will split with sign bit expansion after multiplier, multiplicand send into respectively that two M * N multiplier carries out this decoding of cloth, partial product generates, and the partial product that all M * N multiplier generates is compressed respectively;
4) generate modified value according to arithmetic type in the said s operation control signal and sign bit;
5) modified value that all output results that the compression of said step 3) obtained and said step 4) obtain is compressed and is obtained multiplication result.
2. structuring according to claim 1 mixes bit wide multiplying method, and it is characterized in that: the arithmetic type in the said step 1) comprises 1 M * 2N multiplying and 2 (M/2) * N multiplying.
3. structuring according to claim 2 mixes bit wide multiplying method; It is characterized in that; Said step 2) according to arithmetic type the detailed step that multiplier, multiplicand split is comprised in: if said arithmetic type is 1 M * 2N multiplying; Then multiplier is split as high-order multiplier part and low level multiplier part, multiplicand remains unchanged; If said arithmetic type is 2 (M/2) * N multiplying, then multiplier is split as high-order multiplier part and low level multiplier part, and M position multiplicand is split as high-order multiplicand part and the low level multiplicand part that is the M/2 position.
4. structuring according to claim 3 mixes bit wide multiplying method; It is characterized in that; Said step 2) according to said sign bit the detailed step that the multiplicand after splitting carries out the sign bit expansion is comprised in: if said arithmetic type is 1 M * 2N multiplying of realization, then multiplicand remains unchanged; If said arithmetic type for realizing 2 (M/2) * N multiplying, then with the low level expansion 0 of high-order multiplicand part, is partly done sign extended with the low level multiplier.
5. structuring according to claim 4 mixes bit wide multiplying method; It is characterized in that; To split in the said step 3) with sign bit expansion after multiplier, multiplicand send into two M * N multiplier respectively and specifically be meant: if said arithmetic type is for realizing 1 M * 2N multiplying; Then high-order multiplier part and multiplicand are sent into a M * N multiplier, low level multiplier part and multiplicand are sent into another M * N multiplier; If said arithmetic type is for realizing 2 (M/2) * N multiplying, then high-order multiplicand part and the multiplicand after the low level expansion 0 sent into a M * N multiplier, and part of the low level multiplier after the sign extended and multiplicand are sent into another M * N multiplier.
6. structuring according to claim 5 mixes bit wide multiplying method; It is characterized in that: the detailed step according to arithmetic type in the said s operation control signal and sign bit generation modified value in the said step 4) comprises: if said arithmetic type is 1 M * 2N multiplying of realization, then generating modified value is 0; If said arithmetic type is for realizing 2 (M/2) * N multiplying, and the operation result of part of the low level multiplier after the said sign extended and multiplicand is negative, and (the M/2)+N position that then generates modified value is 1, and all the other are 0.
7. mix bit wide multiplying method according to any described structuring in the claim 1～6; It is characterized in that; The concrete steps that the partial product that in the said step 3) all M * N multiplier is generated is compressed comprise: the partial product that at first all M * N multiplier is generated is according to array or tree-like arrangement, then a plurality of partial products on each in the said arrangement compressed the result who obtains the mode of representing with redundancy.
8. a structuring mixes bit wide multiplying device; It is characterized in that: comprise be used for according to the s operation control signal multiplier, the multiplicand of input split and the operand of sign bit expansion select expanding element (1), the one M * N multiplier (21), the 2nd M * N multiplier (22), be used to revise multiplication result low level multiplication symbol position amending unit (3), be used for the modified value of amending unit (3) output is compressed the finant product arithmetic element (4) that obtains multiplication result with the result of multiplying, said operand is selected expanding element (1) to pass through the one M * N multiplier (21), the 2nd M * N multiplier (22), amending unit (3) respectively to link to each other with said finant product arithmetic element (4).
9. structuring according to claim 8 mixes bit wide multiplying device; It is characterized in that: said the one M * N multiplier (21) is the identical multiplication module of structure with the 2nd M * N multiplier (22); Said multiplication module comprises this decoding module of cloth (23), partial product generation module (24), the partial product compression module (25) of series connection successively; The input end of this decoding module of said cloth (23) selects expanding element (1) to link to each other with operand, and the output terminal of said partial product compression module (25) links to each other with finant product arithmetic element (4).
10. structuring according to claim 9 mixes bit wide multiplying device; It is characterized in that: said partial product compression module (25) comprises the processed compressed logic that is used for storing long-pending partial product storage organization of said partial product generation module (24) output and the partial product processed compressed that is used for the partial product storage organization is stored; The input end of said partial product storage organization links to each other with said partial product generation module (24); The output terminal of said partial product storage organization links to each other through the said finant product arithmetic element of processed compressed logical and (4), and said partial product storage organization is tree structure or array structure.
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