JPH11121328A - Scanning reduction projection exposure system - Google Patents
Scanning reduction projection exposure systemInfo
- Publication number
- JPH11121328A JPH11121328A JP9277526A JP27752697A JPH11121328A JP H11121328 A JPH11121328 A JP H11121328A JP 9277526 A JP9277526 A JP 9277526A JP 27752697 A JP27752697 A JP 27752697A JP H11121328 A JPH11121328 A JP H11121328A
- Authority
- JP
- Japan
- Prior art keywords
- scanning
- semiconductor substrate
- exposure
- reduction projection
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70216—Mask projection systems
- G03F7/70358—Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、走査型縮小投影露
光装置に関し、特に紫外線および遠紫外線を用いた走査
型縮小投影露光装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning reduction projection exposure apparatus, and more particularly to a scanning reduction projection exposure apparatus using ultraviolet rays and far ultraviolet rays.
【０００２】[0002]
【従来の技術】半導体集積回路においては、半導体基板
（以下ウェハとする）上のパターン形成に露光装置が使
用される。2. Description of the Related Art In a semiconductor integrated circuit, an exposure apparatus is used to form a pattern on a semiconductor substrate (hereinafter, referred to as a wafer).
【０００３】近年、広面積を有する半導体集積回路で
は、ウェハ上のパターン形成において走査型縮小投影露
光装置が使用されている。In recent years, in a semiconductor integrated circuit having a large area, a scanning reduction projection exposure apparatus has been used for forming a pattern on a wafer.
【０００４】図１に走査型縮小投影露光装置の一例の概
略を示す。図において、露光光１０１は、光源１０２か
ら反射鏡１０３、フライアイレンズ１０４、アパーチャ
ー絞り１０５、レチクルブラインド１０６、反射鏡１０
７、コンデンサレンズ１０８、レチクル１０９、投影レ
ンズ１１０を順次通って、ウェハステージ１１１上のウ
ェハ１１２に所望の露光量だけ照射される。このときの
露光視野は２５×８ｍｍ程度のスリット形状であり、レ
チクルブラインド１０６、レチクルステージ１１３およ
びウェハステージ１１１を同期走査することで、最大２
５×３０ｍｍ程度の領域のウェハ１１１上にレチクル１
０９上のパターンを形成する。これをウェハステージ１
１１を移動し、図２中、矢印で示すように、ウェハ２０
１上を繰り返し走査させることにより、ウェハ１１２全
面にレチクル１０９上のパターンが繰り返し露光され
る。FIG. 1 schematically shows an example of a scanning reduction projection exposure apparatus. In the figure, an exposure light 101 is transmitted from a light source 102 to a reflecting mirror 103, a fly-eye lens 104, an aperture stop 105, a reticle blind 106, and a reflecting mirror 10.
7. The wafer 112 on the wafer stage 111 is irradiated with a desired exposure amount through the condenser lens 108, the reticle 109, and the projection lens 110 in this order. At this time, the exposure visual field has a slit shape of about 25 × 8 mm, and a maximum of 2 is obtained by synchronously scanning the reticle blind 106, the reticle stage 113 and the wafer stage 111.
The reticle 1 is placed on the wafer 111 in an area of about 5 × 30 mm.
09 is formed. This is the wafer stage 1
11 to move the wafer 20 as shown by the arrow in FIG.
By repeatedly scanning over the wafer 1, the pattern on the reticle 109 is repeatedly exposed on the entire surface of the wafer 112.
【０００５】以上のように同期走査露光を行う際の同期
制御精度は、結像性能に大きな影響を与える。同期制御
はレチクルステージ１１３、ウェハステージ１１１にそ
れぞれ設けられているレーザー干渉計１１５、１１７に
よりレチクルステージ１１３、ウェハステージ１１１の
位置を検出し、制御部１１８によりレチクルステージ移
動機構１１４およびウェハステージ移動機構１１６を制
御することにより行っている。As described above, the accuracy of the synchronous control when performing the synchronous scanning exposure has a great influence on the imaging performance. Synchronous control detects the positions of the reticle stage 113 and the wafer stage 111 using laser interferometers 115 and 117 provided on the reticle stage 113 and the wafer stage 111, respectively, and the control unit 118 controls the reticle stage moving mechanism 114 and the wafer stage moving mechanism. 116 is controlled.
【０００６】例えば、ウェハステージの走査速度が８０
ｍｍ／ｓｅｃ、レチクルステージ１１３の走査速度が３
２０ｍｍ／ｓｅｃの場合、８ｍｍのスリットがウェハ１
１２上の１点を通過する時間は０．１ｓｅｃである。こ
の０．１ｓｅｃの間、各々のステージに設置されたレー
ザー干渉計１１５、１１７により計測されるレチクルス
テージ１１３、ウェハステージ１１１の位置から算出さ
れる差分がウェハステージ１１１とレチクルステージ１
１３の同期制御精度である。０．１ｓｅｃの間の差分の
内、平均値はパターンの結像位置を決定する。また、差
分の振幅は、パターンの結像のぼけ、つまり解像力の低
下や焦点深度の低下につながる。この差分、つまり同期
制御精度は、走査速度にほぼ比例する。図４にウェハス
テージ走査速度と差分の最大振幅の関係を示す。最大振
幅の許容値は、露光波長、投影レンズのＮＡ、パターン
の種類や線幅により異なる。例えば、ＫｒＦエキシマ露
光により、ＮＡ＝０．６の投影レンズを用い、０．２０
μｍＬ／Ｓを形成する場合の最大振幅の許容値は３０ｎ
ｍ程度である。ウェハステージ１１１の走査最大速度
は、最大振幅が最大許容振幅を上回らないように決定さ
れる。露光装置の機械的特性等により最大振幅は、ウェ
ハステージ１１１の走査位置により異なるが、従来はウ
ェハ全面にわたって同一の走査速度で露光する機能しか
有していないため、最大振幅が許容値以下であることを
満たすように走査最大速度が決定されている。図５のよ
うなチップをウェハ面内に形成するような場合において
は、ウェハ内領域Ａ、Ｂ、Ｃ、Ｄ、Ｅのチッブで最大振
幅が３０ｎｍ以下にできるようなウェハステージ走査最
大速度は、それぞれ６０、４０、１００、１２０、８０
ｎｍ／ｓｅｃであるため、ウェハ全面にわたり、ウェハ
ステージの走査最大速度は４０ｍｍ／ｓｅｃに設定され
る。For example, when the scanning speed of the wafer stage is 80
mm / sec, the scanning speed of the reticle stage 113 is 3
In the case of 20 mm / sec, the 8 mm slit
The time for passing through one point on 12 is 0.1 sec. During this 0.1 second, the difference calculated from the positions of the reticle stage 113 and the wafer stage 111 measured by the laser interferometers 115 and 117 installed on each stage is the difference between the wafer stage 111 and the reticle stage 1.
13 is the synchronization control accuracy. The average value of the differences between 0.1 sec determines the imaging position of the pattern. Further, the amplitude of the difference leads to blurring of image formation of the pattern, that is, a reduction in resolution and a reduction in the depth of focus. This difference, that is, the synchronization control accuracy is almost proportional to the scanning speed. FIG. 4 shows the relationship between the wafer stage scanning speed and the maximum amplitude of the difference. The allowable value of the maximum amplitude differs depending on the exposure wavelength, the NA of the projection lens, the type of pattern, and the line width. For example, by KrF excimer exposure, using a projection lens with NA = 0.6, 0.20
The maximum allowable amplitude for forming μmL / S is 30n
m. The maximum scanning speed of the wafer stage 111 is determined so that the maximum amplitude does not exceed the maximum allowable amplitude. Although the maximum amplitude varies depending on the scanning position of the wafer stage 111 due to the mechanical characteristics of the exposure apparatus, the maximum amplitude is less than an allowable value because conventionally, only the function of exposing the entire wafer at the same scanning speed is provided. The maximum scanning speed is determined so as to satisfy the above. In the case where a chip as shown in FIG. 5 is formed on the wafer surface, the wafer stage scanning maximum speed at which the maximum amplitude can be reduced to 30 nm or less in the in-wafer regions A, B, C, D, and E is as follows: 60, 40, 100, 120, 80 respectively
nm / sec, the maximum scanning speed of the wafer stage is set to 40 mm / sec over the entire surface of the wafer.
【０００７】[0007]
【発明が解決しようとする課題】ところが、このような
従来の走査型縮小投影露光装置によるときには、処理能
力が低いという問題点があった。However, such a conventional scanning-type reduction projection exposure apparatus has a problem in that the processing capability is low.
【０００８】その理由は、走査最大速度は、ウェハ全面
にわたり同期制御精度の最大振幅が許容値を越えない値
に設定されているからである。The reason is that the maximum scanning speed is set to a value such that the maximum amplitude of the synchronization control accuracy does not exceed an allowable value over the entire surface of the wafer.
【０００９】本発明の目的は、上記課題に鑑み、処理能
力が高い走査型縮小投影露光装置を提供することにあ
る。An object of the present invention is to provide a scanning reduction projection exposure apparatus having a high processing capability in view of the above-mentioned problems.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、本発明による走査型縮小投影露光装置においては、
半導体基板およびマスクを往復同期走査することにより
半導体基板に露光を行う走査型縮小投影露光装置であっ
て、半導体基板内の位置に応じ、走査最大速度を変化さ
せて露光を行うものである。In order to achieve the above object, a scanning reduction projection exposure apparatus according to the present invention comprises:
A scanning type reduced projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein the exposure is performed by changing a maximum scanning speed according to a position in the semiconductor substrate.
【００１１】また、半導体基板およびマスクを往復同期
走査することにより半導体基板に露光を行う走査型縮小
投影露光装置であって、半導体基板内の走査露光位置毎
に走査最大速度を決定するものである。A scanning reduction projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein a maximum scanning speed is determined for each scanning exposure position in the semiconductor substrate. .
【００１２】また、半導体基板の位置に応じ、走査最大
速度を変化させて露光を行う際に、自動的に同期制御精
度を検知し、同期制御精度を確保できる走査最大速度に
設定して露光を行うものである。Further, when performing the exposure by changing the maximum scanning speed according to the position of the semiconductor substrate, the synchronization control accuracy is automatically detected, and the exposure is set by setting the maximum scanning speed at which the synchronization control accuracy can be ensured. Is what you do.
【００１３】また、半導体基板およびマスクを往復同期
走査することにより半導体基板に露光を行う走査型縮小
投影露光装置であって、半導体基板の面内での同期制御
精度を設定し、半導体基板の面内のチップ毎の走査最大
速度を設定するものである。Further, the present invention is a scanning reduction projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein synchronization control accuracy within the surface of the semiconductor substrate is set, and The maximum scanning speed is set for each of the chips.
【００１４】また、半導体基板の各位置のチップ露光時
に、第ｎチップ（但し、ｎ＝１，２，…）で同期制御精
度が許容値をはずれたときには、次の第ｎ＋１チップ露
光時に走査最大速度を下げて露光を行うものである。When the synchronization control precision of the n-th chip (where n = 1, 2,...) Deviates from the allowable value during the chip exposure at each position of the semiconductor substrate, the maximum scanning is performed at the next (n + 1) -th chip exposure. Exposure is performed at a reduced speed.
【００１５】本発明においては、ウェハ内走査露光位置
毎に同期制御精度により走査最大速度を決定するため、
同期制御精度を確保した状態でかつ最大のスループット
でのウェハ露光処理が可能となる。In the present invention, the maximum scanning speed is determined by the synchronization control accuracy for each scanning exposure position in the wafer.
The wafer exposure process can be performed with the maximum throughput while the synchronization control accuracy is secured.
【００１６】[0016]
【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１７】図１に示す走査型縮小投影露光装置におい
て、露光光１０１は、光源１０２から反射鏡１０３、フ
ライアイレンズ１０４、アパーチャー絞り１０５、レチ
クルブラインド１０６、反射鏡１０７、コンデンサレン
ズ１０８、レチクル１０９、投影レンズ１１０を順に通
ってウェハステージ１１１上のウェハ１１２に所望の露
光量だけ照射される。このとき、露光視野としては２５
×８ｍｍ程度のスリット形状であり、レチクルブライン
ド１０６、レチクルステージ１１３およびウェハステー
ジ１１１を同期走査することで、最大２５×３０ｍｍ程
度の領域のウェハ１１２上にレチクル１０９上のパター
ンを形成する。これをウェハステージ１１１を移動し、
図２のように繰り返し走査させることにより、ウェハ１
１２全面にレチクル１０９上のパターンが繰り返し露光
される点は従来と同じである。In the scanning type reduction projection exposure apparatus shown in FIG. 1, exposure light 101 is transmitted from a light source 102 to a reflecting mirror 103, a fly-eye lens 104, an aperture stop 105, a reticle blind 106, a reflecting mirror 107, a condenser lens 108, and a reticle 109. The wafer 112 on the wafer stage 111 is irradiated with a desired exposure amount through the projection lens 110 in order. At this time, the exposure field of view is 25
The slit has a shape of about 8 mm, and a pattern on the reticle 109 is formed on the wafer 112 in a region of up to about 25 × 30 mm by synchronously scanning the reticle blind 106, the reticle stage 113, and the wafer stage 111. This is moved to the wafer stage 111,
By repeatedly scanning the wafer 1 as shown in FIG.
The point that the pattern on the reticle 109 is repeatedly exposed on the entire surface 12 is the same as the conventional case.
【００１８】また、同期制御は従来と同様にレチクルス
テージ１１３、ウェハステージ１１１にそれぞれ設けら
れているレーザー干渉計１１５、１１７によりレチクル
ステージ１１３、ウェハステージ１１１の位置を検出
し、制御部１１８によりレチクルステージ移動機構１１
４およびウェハステージ移動機構１１６を制御すること
により行っている。In the synchronous control, the positions of the reticle stage 113 and the wafer stage 111 are detected by the laser interferometers 115 and 117 provided on the reticle stage 113 and the wafer stage 111, respectively. Stage moving mechanism 11
4 and the wafer stage moving mechanism 116 are controlled.
【００１９】本発明においては、ウェハ内走査位置毎の
同期制御精度から走査最大速度を決定する。あらかじ
め、図３に示すような手順でウェハ面内での同期制御精
度を測定し、ウェハ面内の各チップ毎の走査最大速度を
決めておく。すなわち、本発明においては、図３に示す
ように、（１）ウェハ内の露光条件設定入力を行う、
（２）ウェハを露光装置のウェハステージにセットす
る。（３）ウェハ全面にわたり露光動作を行い、同時に
同期制御精度の測定を行う。（４）各工程毎に所望の同
期精度からウェハ内の各チップでの走査最大速度を決定
する。（５）露光装置へ各チップの最大走査速度を保存
する。（６）ウェハ露光のステップの順でウェハの露光
を行うものである。In the present invention, the maximum scanning speed is determined from the synchronization control accuracy for each scanning position in the wafer. The synchronization control accuracy in the wafer plane is measured in advance by the procedure shown in FIG. 3, and the maximum scanning speed for each chip in the wafer plane is determined. That is, in the present invention, as shown in FIG. 3, (1) exposure condition setting input in the wafer is performed.
(2) Set the wafer on the wafer stage of the exposure apparatus. (3) The exposure operation is performed over the entire surface of the wafer, and simultaneously the synchronization control accuracy is measured. (4) For each step, the maximum scanning speed of each chip in the wafer is determined from the desired synchronization accuracy. (5) Store the maximum scanning speed of each chip in the exposure apparatus. (6) The wafer is exposed in the order of the wafer exposure steps.
【００２０】なお、ウェハステージ走査速度とウェハス
テージとレチクルステージ間の位置の差分の最大振幅と
の関係を示す図４において、ウェハ内領域は図５に示し
てある。ウェハ内領域Ａ、Ｂ、Ｃ、Ｄ、Ｅのチッブで最
大振幅を３０ｎｍ以下にできるようなウェハステージ走
査最大速度は、それぞれ６０、４０、１００、１２０、
８０ｎｍ／ｓｅｃであるため、各チップに対しては、図
６に示すようなそれぞれの走査最大速度で走査露光を行
う。FIG. 4 shows the relationship between the scanning speed of the wafer stage and the maximum amplitude of the difference between the position of the wafer stage and the position of the reticle stage. The maximum wafer stage scanning speed at which the maximum amplitude can be reduced to 30 nm or less in the chips of the in-wafer regions A, B, C, D, and E is 60, 40, 100, 120,
Since it is 80 nm / sec, scanning exposure is performed on each chip at the maximum scanning speed as shown in FIG.
【００２１】本発明によれば、従来技術に比べ、走査露
光時間が約５０％短縮できる。これをアライメントやウ
ェハ交換時間をも含めて考えれば、１枚のウェハでは約
３０％の処理能力の向上が可能である。According to the present invention, the scanning exposure time can be reduced by about 50% as compared with the prior art. Considering this, including the alignment and the wafer exchange time, it is possible to improve the processing capacity by about 30% with one wafer.
【００２２】もっとも、走査型縮小投影露光装置の設置
環境、特に振動環境が変化した場合、同期制御精度も変
化する場合がある。そのような場合に備え、常に制御部
１１８において同期制御精度の変化を認識し、同期制御
精度が許容値にはいるように走査最大速度を走査露光位
置（チップ）毎に自動的に調整する。その動作を図７に
示す。位置の各チップ露光時には同期制御精度も監視し
ている。図７において、第ｎチップ（但しｎ＝１，２，
…）で同期制御精度が許容値をはずれた場合には、次の
第（ｎ＋１）チップ露光時に最大走査速度を例えば１０
％下げて露光を行う。このことにより、次のチップでは
同期制御精度の低下を防ぐことができる。従って、本実
施例の場合、装置の設置環境が変化した場合にも対応可
能であるという利点がある。However, when the installation environment of the scanning reduction projection exposure apparatus, particularly the vibration environment, changes, the synchronization control accuracy may change. In preparation for such a case, the control unit 118 always recognizes a change in the synchronization control accuracy, and automatically adjusts the maximum scanning speed for each scanning exposure position (chip) so that the synchronization control accuracy falls within an allowable value. The operation is shown in FIG. At the time of each chip exposure at the position, the synchronization control accuracy is also monitored. In FIG. 7, the n-th chip (where n = 1, 2, 2)
..), The synchronization control accuracy deviates from the allowable value, the maximum scanning speed is set to, for example, 10 at the next (n + 1) th chip exposure.
Exposure is performed with the percentage lowered. As a result, it is possible to prevent the synchronization control accuracy from being reduced in the next chip. Therefore, in the case of the present embodiment, there is an advantage that it is possible to cope with a change in the installation environment of the apparatus.
【００２３】[0023]
【発明の効果】以上説明したように、本発明の走査型縮
小投影露光装置においては、走査露光位置毎に走査最大
速度を変化させることにより、スループットの向上が可
能である。As described above, in the scanning type reduced projection exposure apparatus of the present invention, the throughput can be improved by changing the maximum scanning speed for each scanning exposure position.
【図１】本発明および従来技術の走査型縮小投影露光装
置の概略図である。FIG. 1 is a schematic view of a scanning type reduction projection exposure apparatus of the present invention and a conventional technique.
【図２】ウェハの走査露光例である。FIG. 2 is an example of scanning exposure of a wafer.
【図３】本発明の一実施形態の動作図である。FIG. 3 is an operation diagram of one embodiment of the present invention.
【図４】本発明のウェハステージ走査速度と最大振幅の
関係図である。FIG. 4 is a relationship diagram between a wafer stage scanning speed and a maximum amplitude according to the present invention.
【図５】本発明のウェハ内領域を示す図である。FIG. 5 is a diagram showing an area in a wafer according to the present invention.
【図６】本発明のウェハ内領域と最大走査速度を示す図
である。FIG. 6 is a diagram showing an in-wafer area and a maximum scanning speed according to the present invention.
【図７】本発明の他の実施の形態の動作図である。FIG. 7 is an operation diagram of another embodiment of the present invention.
【符号の説明】 １０１ 露光光 １０２ 光源 １０３、１０７ 反射鏡 １０４ フライアレイレンズ １０５ アパーチャ絞り １０６ レチクルブラインド １０８ コンダンサーレンズ １０９ レチクル １１０ 縮小投影レンズ １１１ ウェハステージ １１２ ウェハ １１３ レチクルステージ １１４ レチクルステージ移動機構 １１５ レーザー干渉計 １１６ ウェハステージ移動機構 １１７ レーザー干渉計 １１８ 制御部 ２０１ ウェハDESCRIPTION OF SYMBOLS 101 Exposure light 102 Light source 103, 107 Reflector 104 Fly array lens 105 Aperture stop 106 Reticle blind 108 Conductor lens 109 Reticle 110 Reduction projection lens 111 Wafer stage 112 Wafer 113 Reticle stage 114 Reticle stage moving mechanism 115 Laser Interferometer 116 Wafer stage moving mechanism 117 Laser interferometer 118 Control unit 201 Wafer
Claims (5)
することにより半導体基板に露光を行う走査型縮小投影
露光装置であって、 半導体基板内の位置に応じ、走査最大速度を変化させて
露光を行うものであることを特徴とする走査型縮小投影
露光装置。1. A scanning reduction projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein the exposure is performed by changing a maximum scanning speed according to a position in the semiconductor substrate. A scanning type reduction projection exposure apparatus characterized in that:
することにより半導体基板に露光を行う走査型縮小投影
露光装置であって、 半導体基板内の走査露光位置毎に走査最大速度を決定す
るものであることを特徴とする走査型縮小投影露光装
置。2. A scanning reduction projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein a maximum scanning speed is determined for each scanning exposure position in the semiconductor substrate. A scanning-type reduction projection exposure apparatus, characterized in that:
を変化させて露光を行う際に、自動的に同期制御精度を
検知し、同期制御精度を確保できる走査最大速度に設定
して露光を行うものであることを特徴とする請求項１又
は２に記載の走査型縮小投影露光装置。3. When exposure is performed by changing the maximum scanning speed in accordance with the position of the semiconductor substrate, the synchronization control accuracy is automatically detected, and the exposure is set by setting the maximum scanning speed to ensure the synchronization control accuracy. 3. The scanning-type reduction projection exposure apparatus according to claim 1, wherein the scanning-type reduction projection exposure apparatus is used.
することにより半導体基板に露光を行う走査型縮小投影
露光装置であって、 半導体基板の面内での同期制御精度を設定し、半導体基
板の面内のチップ毎の走査最大速度を設定することを特
徴とする走査型縮小投影露光装置。4. A scanning reduction projection exposure apparatus for exposing a semiconductor substrate by reciprocating synchronous scanning of a semiconductor substrate and a mask, wherein a synchronization control precision within a surface of the semiconductor substrate is set, and the surface of the semiconductor substrate is set. A scanning-type reduction projection exposure apparatus, wherein a maximum scanning speed is set for each chip in the apparatus.
第ｎチップ（但し、ｎ＝１，２，…）で同期制御精度が
許容値をはずれたときには、次の第ｎ＋１チップ露光時
に走査最大速度を下げて露光を行うものであることを特
徴とする請求項３又は４に記載の走査型縮小投影露光装
置。5. When exposing a chip at each position of a semiconductor substrate,
When the synchronization control accuracy deviates from the allowable value in the n-th chip (where n = 1, 2,...), The exposure is performed at a lower scanning maximum speed during the next (n + 1) -th chip exposure. A scanning reduction projection exposure apparatus according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09277526A JP3097620B2 (en) | 1997-10-09 | 1997-10-09 | Scanning reduction projection exposure equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09277526A JP3097620B2 (en) | 1997-10-09 | 1997-10-09 | Scanning reduction projection exposure equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11121328A true JPH11121328A (en) | 1999-04-30 |
| JP3097620B2 JP3097620B2 (en) | 2000-10-10 |
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ID=17584815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09277526A Expired - Fee Related JP3097620B2 (en) | 1997-10-09 | 1997-10-09 | Scanning reduction projection exposure equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3097620B2 (en) |
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