JPH1083174A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To judge a display mode from cycles of synchrinizing signals by a software processing. SOLUTION: This display device is contituted of a synchronizing circuit part 1 separating a horizontal synchronizing signal and a vertical synchronizing signal from an inputted video signal, a clock generating part 2, the gate part 3 for example, of an AND gate or the like performing the gate control of the horizontal synchronizing signal, an H counter part 4 counting the horizontal synchronizing signal, an H cycle count part 5 measuring the cycle of the horizontal synchronizing signal while counting a clock signal, a vertical cycle counter part 6 measuring the cycle of the vertical synchronizing signal, a storage part 7 storing the measured cycles, a judgement part 8 judging a mode based on the cycles of the synchronizing signals, an arithmetic part 9 calculating mean cycles and a control part controlling respective parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device,
More specifically, the present invention relates to a method for determining a display mode based on a synchronization signal of an input video signal.

[0002]

2. Description of the Related Art Conventionally, in a display device, for example, a liquid crystal projector or the like, each image can be displayed corresponding to a plurality of kinds of video signals. As an example, in the case of a video signal generated by a personal computer, a VGA (Video Grahics
Array), SVGA (Super Video Grahics Array), etc., and appropriately display images.

For this reason, for example, a display mode of an input video signal is determined based on a method of separating a synchronization signal from an input video signal and detecting a period of the synchronization signal.
More specifically, a synchronization circuit that separates a horizontal synchronization signal and a vertical synchronization signal from an input video signal, a plurality of counter circuits that measure the period of the horizontal synchronization signal and the vertical synchronization signal, and a plurality of decoding circuits that decode the counter value Using a decoder and a logic circuit that determines the display mode based on the output of the decoder, the counter circuit measures the period of the synchronization signal separated from the video signal, decodes it based on the measured value, and displays the decoded value. The mode is determined so as to correspond to the input video signal.

[0004] As described above, the method of determining a display mode using a hardware circuit not only causes an increase in the number of components to be realized and an increase in the circuit scale, but also increases the substrate size and the cost. There was a problem.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a display device which measures a period of a synchronization signal and determines a display mode by software processing. I do.

[0006]

In order to achieve the above object, a display mode of a video signal is determined based on a synchronization signal,
In a display device for selectively displaying, a synchronization circuit section for separating a synchronization signal from an input video signal, a clock generation section for generating a required clock signal, a gate section for gate-controlling the synchronization signal, and a cycle of the horizontal synchronization signal. An H cycle counter for measuring, a V cycle counter for measuring the cycle of the vertical synchronization signal, a storage for storing the measured cycle, and a determination unit for determining the display mode based on the cycle of the synchronization signal are provided.

In addition, the H cycle counter section and the V cycle counter section are reset at the fall (rise) of the synchronization signal, and count the clock signal from the fall (rise) to the next fall (rise). did.

The H counter is reset at the falling edge (rising edge) of the vertical synchronizing signal to count the number of horizontal synchronizing signals.

The gate section controls the passage of the horizontal synchronizing signal by the number of horizontal synchronizing signals.

Further, the determination unit is configured to determine the display mode from a relationship table between the combination of the cycle of the horizontal synchronization signal and the cycle of the vertical synchronization signal and the display mode.

[0011] Further, an arithmetic unit for calculating an average period of the synchronization signal is provided.

Further, an H counter for counting the horizontal synchronizing signals is provided, and the arithmetic unit calculates the horizontal average cycle based on the horizontal cycle after the horizontal synchronizing signal having a predetermined count.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With the above configuration, FIG.
This will be described with reference to FIG. The H cycle counter section and the V cycle counter section, for example, start counting the clock at the falling point of the synchronization signal and stop counting at the next falling point, and count the cycle of the synchronization signal to the number of clocks. It measures by doing. The determination unit determines the display mode from the cycle of the horizontal synchronization signal and the cycle of the vertical synchronization signal.

The determination section determines the display mode from a table showing the relationship between the combination of the cycle of the horizontal synchronization signal and the cycle of the vertical synchronization signal and the display mode.

Further, the arithmetic unit calculates the average period based on the horizontal period after the tenth horizontal synchronization signal.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a main block diagram showing an embodiment of a display device according to the present invention. Reference numeral 1 denotes a synchronization circuit for separating a horizontal synchronization signal and a vertical synchronization signal from an input video signal. Reference numeral 2 denotes a clock generator for generating a clock signal of a required frequency. Reference numeral 3 denotes a gate unit such as an AND gate that performs gate control so as to pass or block a horizontal synchronization signal by a control signal. Reference numeral 4 denotes an H counter unit that resets with a vertical synchronization signal and counts a horizontal synchronization signal. Reference numeral 5 denotes an H cycle counter that resets with the horizontal synchronization signal, counts the clock signal, and measures the cycle of the horizontal synchronization signal. Reference numeral 6 denotes a V cycle counter unit that resets with the vertical synchronization signal, counts the clock signal, and measures the period of the vertical synchronization signal. Reference numeral 7 denotes a storage unit that stores the measured cycle.
Reference numeral 8 denotes a determination unit that determines the display mode based on the cycle of the synchronization signal. Reference numeral 9 denotes a calculation unit that calculates an average period based on a plurality of periods. Reference numeral 10 denotes a control unit that controls each unit.

The display mode determining operation of the display device according to the present invention will be described with reference to FIGS. FIG. 2 is a time chart for explaining the measurement of the period of the synchronization signal of the display device according to the present invention. FIG. 3 is a diagram showing the combination of the horizontal synchronization signal period and the vertical synchronization signal period of the display device according to the present invention, and the display mode. It is a figure showing an example of a relation table with. Externally, for example, an XGA (eXtended Grade)
hics Array). Synchronous circuit section 1
Performs processing such as separation from the video signal to extract a horizontal synchronization signal and a vertical synchronization signal. H cycle counter 5
Resets, for example, at the falling edge of each horizontal synchronization signal gate-controlled by the gate unit 3 based on the number of horizontal synchronization signals measured by the H counter unit 4, and counts the clock signal from the clock generation unit 2. Thus, the number of clocks corresponding to the cycle of the horizontal synchronization signal is obtained. V cycle counter 6
Resets at the falling edge of each vertical synchronization signal, for example, and counts clock signals to obtain the number of clocks corresponding to the period of the vertical synchronization signal. The same clock number is stored in the storage unit 7. The calculation unit 9 calculates the number of horizontal average clocks from, for example, 10 sets of horizontal periods, and the determination unit 8 determines the display mode based on a combination of the number of horizontal average clocks and the number of vertical average clocks. Note that the period of the synchronization signal =
Since the relationship is one cycle of the clock signal × the number of clocks,
The operation unit 9 may calculate the period of the synchronization signal and store the same in the storage unit 7.

As shown in FIG. 2A, the horizontal (H) synchronization signal includes first, second,..., N-th,.
And the number of horizontal (H) synchronization signals is
Is counted as a count number. The control unit 10 is a gate unit 3
Is controlled so that, for example, the tenth horizontal (H) synchronization signal passes through the twentieth horizontal (H) synchronization signal, and 1 for each of the ten sets of horizontal (H) synchronization signals.
0 sets of clock numbers are obtained. The calculation unit 9 calculates an average clock number based on the clock numbers of the ten sets of horizontal (H) synchronization signals. Also, as shown in FIG. 2B, the vertical (V) synchronization signal calculates, for example, the average number of clocks from the first cycle to the tenth cycle.

The determination section 8 stores in advance a combination of the horizontal cycle and the vertical cycle and the corresponding display mode in a relation table. Alternatively, the combination of the number of horizontal average clocks and the number of vertical average clocks and the corresponding display mode are stored in a relation table. For example, as shown in FIG.
Using the period, the combination of the horizontal period: 63.57 [μs] and the vertical period: 16.67 [ms] is the 15k mode, as can be seen from the above relation table, and is also 26.40 [μs]
In addition, it can be seen that the combination of 16.58 [ms] is the SVGA 37k mode. Therefore, from the combination of the cycles from the calculation unit 9 based on the input video signal, the determination unit 8
SVGA 37k mode etc. can be determined reliably.

In an actual relation table, for example, the horizontal period is ±
By giving an allowable value of 1 [μs] and a vertical cycle of ± 0.2 [ms], erroneous determination is reduced. In addition, it is also possible to create a relation table similar to the above using the number of clocks other than the above-described period and determine the display mode. The operation of each section from the gate section 3 to the control section 10 of each section described above can be easily realized by software processing using a built-in counter and storage section of the microcomputer, for example, by using a one-chip microcomputer. it can.

[0021]

As described above, the present invention provides a display device in which the period of a synchronization signal is measured and the display mode is determined by software processing. Therefore, in the conventional method of determining the display mode using a hardware circuit,
(A) In addition to the increase in the number of components to be realized and the increase in the circuit scale, (b) the size of the substrate is increased, and there is an advantage of solving the problem of cost increase. Further, the software processing method of the present invention can be easily and inexpensively realized by a one-chip microcomputer having a plurality of counters and a required program.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a display device according to the present invention.

FIG. 2 is a time chart illustrating measurement of a period of a synchronization signal of a display device according to the present invention.

FIG. 3 shows a horizontal synchronization signal period of a display device according to the present invention;
FIG. 11 is a diagram illustrating an example of a relation table between a combination with a vertical synchronization signal cycle and a display mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronous circuit part 2 Clock generation part 3 Gate part 4 H counter part 5 H period counter part 6 V period counter part 7 Storage part 8 Judgment part 9 Operation part 10 Control part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/74 H04N 5/74 Z

Claims (7)

[Claims] 1. A display device for determining a display mode of a video signal based on a synchronization signal and selectively displaying the video signal, a synchronization circuit unit for separating a synchronization signal from an input video signal, and a clock generation unit for generating a required clock signal. When,
A gate for gate-controlling the synchronization signal; an H-cycle counter for measuring the cycle of the horizontal synchronization signal; a V-cycle counter for measuring the cycle of the vertical synchronization signal; a storage for storing the measured cycle; And a determination unit for determining the display mode based on the period of the display device. 2. The method according to claim 1, wherein the H-period counter and the V-period counter are reset at the falling edge (rising edge) of the synchronizing signal, and count the clock signal from the falling edge (rising edge) to the next falling edge (rising edge). The display device according to claim 1, wherein: 3. The display device according to claim 1, wherein the H counter is reset at the falling edge (rising edge) of the vertical synchronizing signal so as to count the number of horizontal synchronizing signals. 4. The display device according to claim 1, wherein the gate section controls the passage of the horizontal synchronization signal by the number of horizontal synchronization signals. 5. The display device according to claim 1, wherein the determination unit determines the display mode from a relation table between a combination of a cycle of the horizontal synchronization signal and a cycle of the vertical synchronization signal and a display mode. 6. The display device according to claim 1, further comprising a calculation unit for calculating an average period of the synchronization signal. 7. The display device according to claim 6, further comprising an H counter for counting horizontal synchronization signals, wherein said arithmetic unit calculates a horizontal average period based on a horizontal period after a predetermined number of horizontal synchronization signals. .