JPH1065516A - Driver ic and electronic device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the flow of a through current from the side of a high- voltage power source to the side of a low-voltage power source when outputting a high-level voltage by driving one of transistors on the output stage while using an intermediate voltage as the output of a level converting circuit. SOLUTION: A level converting circuit 100 and an output driver circuit 200 exist as many as the output bits of a driver IC. When switching a voltage output from 'L' to 'H' at the time of operating, a signal corresponding to a voltage VCC is inputted from a shift register 400 to the gate of an FET N2, a signal corresponding to a voltage VSS is inputted from the shift register 400 to the gates of N1 and N3 respectively, the N1 and N3 are turned off and the N2 is turned on. A voltage between the gate and the source of an FET MP2 exceeds a threshold voltage, and a P1 is turned on by the drop of a source voltage V2 at the MP2. When a source voltage V1 at an MP1 gets closer to a high power supply voltage HV, the P2 is turned off, and the voltage V2 is kept at a prescribed value. At such a time, the P2 and MP2 are turned off so that no through current can flow through the N2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for level-converting a low voltage to a high voltage and an integrated circuit having a drive circuit driven by the circuit.
Further, the present invention relates to an electronic device using the same.

[0002]

2. Description of the Related Art As a level conversion circuit of a conventional high voltage driver IC, two high voltage NMOSs and two high voltage PMs are used.
2. Description of the Related Art There is known a circuit including an OS and having PMOS drains connected to each other. This driver IC
14 is shown in FIG. The level conversion circuit 100 and the output driver circuit 200 have the number of outputs of the driver IC (for example, 64 outputs or 128 outputs).

As another level conversion circuit of a conventional high voltage driver IC, a circuit using a constant current source composed of a resistor and an NMOS switch is known, and the circuit configuration of this driver IC is shown in FIG. .

[0004]

In the former prior art,
In the case of a high-voltage driver IC (for example, the voltage of the high-voltage power supply HV is several tens of volts or more), PMOSs P1 and P for level conversion
2 and the voltage of the high voltage power supply HV is applied as it is between the gate and the source of the PMOS P3 of the output driver section. Therefore, the gate oxide films of the PMOSs P1 to P3 need to have a sufficient film thickness so as not to cause current leakage and dielectric breakdown even when the voltage of the high-voltage power supply HV is applied, and the channel structure becomes complicated. There is a problem that it is difficult to make. Further, when the high voltage power supply HV is 150 V or more, the gate oxide film thickness is 0.6 μm in consideration of reliability.
LOCOS (L
Since the thickness of the oxide film is about the same as or greater than the thickness of the oxide film, there is a problem that isolation between elements becomes difficult.

In the latter prior art, the voltage of the high-voltage power supply HV is not applied between the gate and the source of the MOS transistor.
Since the NMOS switch N1 provided in series with the resistor R1 is connected to the low voltage power supply VSS from the high voltage power supply HV, the resistors R1 and N
A through current flows through the MOS switch N1. Therefore, when all the outputs are at the high level, the through current becomes large. To prevent this, it is necessary to increase the value of the resistor. However, if this value is too large, there is a problem that the operation speed of the level conversion circuit is reduced and the layout area is increased. SUMMARY OF THE INVENTION It is an object of the present invention to provide a level conversion circuit in which a through current does not flow from a high-voltage power supply to a low-voltage power supply when a high-level voltage is output, and a low-power-consumption high-voltage power IC using the same.

[0006]

A driver IC of the present invention is characterized in that a driver IC having a level conversion circuit for converting a low voltage signal into a high voltage signal and a driver circuit driven by an output of the level conversion circuit. Means for suppressing the voltage between the gate and the source of the P-type MOS transistor provided on the high-voltage power supply side of the level conversion circuit to a voltage sufficiently lower than the voltage of the high-voltage power supply and preventing a through current flowing from the high-voltage power supply to the low-voltage power supply. Is to have.

Another feature of the present invention is that in the level conversion circuit, first and second MOS transistors are provided on a power supply side, and gates of the first and second MOS transistors are connected to each other drain. The first and second MOS transistors are connected in series on the opposite side of the power supply side from the first and second MOS transistors, respectively.
, And the difference between the gate voltage of the second MOS transistor and the gate voltage of the second MOS transistor not in series with each other is equal to or less than a predetermined voltage. And the output of the level conversion circuit is set to the first level.
Alternatively, it is obtained from the gate of the second MOS transistor.

Still another feature of the present invention is that the level conversion circuit is provided with a first and a second MO having one conductivity type channel.
An S transistor, third and fourth MOS transistors having a channel of the other conductivity type, first and second switch means, a first MOS transistor, a first switch means, and a third MOS transistor. The transistors are connected in series, the second MOS transistor is connected to the second switch means, and the fourth MOS transistor is connected in series. The gate of the first MOS transistor is connected to the second MOS transistor and the second switch. Connected to the common connection point of the means,
The gate of the second MOS transistor is connected to a common connection point of the first MOS transistor and the first switch means, and terminals other than the gates of the first and second MOS transistors are connected to the first and second switch transistors. The terminal which does not have a common connection point with the means is connected to the high voltage power supply, and the terminal other than the gates of the third and fourth MOS transistors is a terminal which does not have a common connection point with the first and second switch means. The terminal is connected to the first low-voltage power supply, and is a terminal of the first and second switch means, and has a common connection point with any of the first, second, third, and fourth MOS transistors. The third terminal is connected to a reference voltage source, and the voltage of the reference voltage source is set to a voltage lower than the high voltage power supply by a predetermined voltage.
The gate of the OS transistor is connected to the output of a logic circuit using the second low-voltage power supply as a power supply, and the third and fourth M transistors are connected.
The OS transistors operate complementarily to each other,
A gate of the first or second MOS transistor is used as an output terminal of the level conversion circuit, and a next-stage transistor is driven by an output signal of the level conversion circuit.

In the present invention, the gate voltage of the first (second) P-type MOS transistor, that is, the second (first) P-type MOS transistor is used.
When the drain voltage of the S transistor is about to be lowered to the voltage of the low-voltage power supply VSS, the voltage is changed to the high-voltage power supply H
When the voltage drops to a predetermined voltage slightly lower (for example, about 5 V to 20 V) than the voltage of V, a second (first) clamping P-type M provided in series with the second (first) P-type MOS transistor.
The OS transistor turns off.

[0010] This is the first and second clamping P-type M
Since the gate voltage of the OS transistor is set lower than the voltage of the high-voltage power supply HV by a predetermined voltage (for example, about 5 V to 20 V), the drain voltage of the second (first) P-type MOS transistor, that is, the second (1st) Clamping P
When the source voltage of the type MOS transistor drops by a predetermined voltage from the voltage of the high voltage power supply HV, the gate-source voltage of the second (first) clamping P-type MOS transistor becomes a threshold voltage (about 1-2 V). This is because:

Accordingly, the gate-source voltage of the first (second) P-type MOS transistor and the second (first) clamping P-type MOS transistor is a predetermined voltage (for example,
(About 5 V to 20 V). Also,
Since the second (first) clamping P-type MOS transistor is turned off, no through current flows.

Further, since the output driver circuit at the next stage is driven by the gate voltage of the first or second P-type MOS transistor, the gate-source voltage of the P-type MOS transistor used in the output driver circuit is also a predetermined voltage value. Never exceed.

[0013]

FIG. 1 shows a first embodiment of the present invention. 100 is a level conversion circuit, and 200 is an output driver circuit. HV indicates the voltage of the high-voltage power supply, VSS indicates the voltage of the first low-voltage power supply, and VCC indicates the voltage of the second low-voltage power supply. V
SS is a voltage of the lowest voltage level, and is usually a ground potential.

The level conversion circuit 100 and the output driver circuit 200 determine the number of output bits of the driver IC (for example, 6
4) only exist. The level conversion circuit 100 includes four P-type MOS transistors P1, P2, MP1, and MP2 and two N-type MOS transistors N1 and N2.

The sources of the P-type MOS transistors P1 and P2 are connected to a high-voltage power supply HV, and the gates of P1 and P2 are connected to the drains of other P-type MOS transistors. P-type MOS transistors MP1, MP2
Are provided in series with P1 and P2, respectively, and their gates are connected to a reference voltage (VG) generating circuit 300, and a voltage VG lower than the voltage HV of the high-voltage power supply by a predetermined voltage is applied.

N-type MOS transistors N1 and N2 are provided in series with MP1 and MP2, respectively. The sources of N1 and N2 are connected to a first low-voltage power supply VSS, and the gate receives the output signal of shift register 400. I have. And
The inverted signal of the signal input to the gate of N1 is input to the gate of N2.

The output driver circuit 200 comprises a P-type MOS transistor P3 and an N-type MOS transistor N3.
The source of the transistor P3 is connected to the high-voltage power supply HV, the gate of P3 is connected to the drain of the transistor P2 and the gate of the transistor P1, and the drain of P3 is connected to the output terminal. The source of the transistor N3 is connected to the first low-voltage power supply VSS, the gate of N3 is connected to the shift register 400 and the gate of the transistor N1, and the drain of N3 is connected to the output terminal. The clock signal CLK and the data signal DIN are input to the shift register 400, and the data signal DIN is transferred in the shift register 400 every cycle of the clock signal.

Next, the operation of the circuit of the present invention will be described by taking as an example a case where the voltage output switches from a low level to a high level. At the time of switching, a voltage signal corresponding to the voltage VCC of the second low-voltage power supply is applied to the gate of the transistor N2, and the voltage V1 of the first low-voltage power supply is applied to the gates of the transistors N1 and N3.
A voltage signal corresponding to SS is input from the shift register 400. Therefore, the transistors N1 and N3 are turned off, and the transistor N2 is turned on.

Here, HV = 160V, VG = 140
V, VCC = 5V, VSS = 0V, transistor MP2
Is -1V. Since the output voltage is initially at the low level, the transistor P3 is in the off state, so that the source voltage V2 of the transistor MP2 is 1
60V. Therefore, the gate of the transistor MP2
Source-to-source voltage is VG-V2 = 140-160 = -20V
Since the threshold voltage Vt exceeds -1 V, the transistor MP2 is on. Therefore, as the transistor N2 turns on, the source voltage V2 of the transistor MP2 decreases. And the voltage of V2 is VG
When −Vth = 140 − (− 1) = 141 V,
The transistor MP2 turns off. As the voltage of V2 decreases, the transistor P1 is turned on. When the voltage V1 approaches the voltage HV of the high-voltage power supply, the transistor P2 is turned off. Therefore, the source voltage V2 of the transistor MP2 is 141V.
Is kept. At this time, the gate-source voltages of the transistors P1 and P3 are both V2-HV = 141-160 =-
19 V, which can be sufficiently lower than the voltage HV of the high-voltage power supply. Further, since the transistors P2 and MP2 are turned off, no through current flows from the high-voltage power supply to the low-voltage power supply via the transistor N2.

The same applies to the case where the high-level voltage output is switched to the low-level voltage output. In this case, the transistor MP1 is turned off, and the transistor MP1
Is kept at 141V. Therefore, the gate-source voltage of the transistor P2 is -19 V, which can be sufficiently lower than the voltage HV of the high-voltage power supply. Further, since the transistors P1 and MP1 are turned off, no through current flows from the high-voltage power supply to the low-voltage power supply via the transistor N1.

The transistors P1, P2, P3, MP
1 and a voltage of about 20 V is applied between the gate and the source of MP2.
Transistor N to which 5 V is applied between gate and source
1, N2, and N3, which are thicker (about 3
~ 4 times).

Here, the role of the diode 500 will be described. The diode 500 functions when the voltage HV of the high-voltage power supply of the driver IC is reduced for a certain period when the load is driven. For example, the HV is changed from 160V to 60V.
VG generation circuit 30 when the voltage is rapidly lowered.
In some cases, the operation of 0 may not be able to keep up, and the HV may temporarily become considerably lower than the VG. As a result, the high speed operation of the driver IC may be hindered. At this time, if the diode 500 is present, HV does not become lower than VG by about 0.8 V or more. For this reason, even if the HV is rapidly lowered to 60 V, the operation recovers to the predetermined value of VG (40 V in the embodiment) in a short time, so that the operation delay of the driver IC hardly occurs. FIG. 2 shows a second embodiment of the present invention. Instead of the first and second clamping MOS transistors MP1 and MP2 in FIG.
This is a case where the bipolar transistors BP1 and BP2 for clamping are used. Both BP1 and BP2 are PNP-type bipolar transistors, and their bases are both connected to the VG generation circuit 300. The emitter of BP1 is P
The drain of the type MOS transistor P1 is connected to the gate of the P-type MOS transistor P2, and the collector of BP1 is connected to the drain of the N-type MOS transistor N1.
The emitter of BP2 is a P-type MOS transistor P2
Is connected to the gate of the P-type MOS transistor P1, and the collector of BP2 is connected to the N-type MOS transistor P1.
2 drain.

The operation of the circuit of the present invention will be described by taking as an example a case where the voltage output switches from a low level to a high level.
At the time of switching, a voltage signal corresponding to the voltage VCC of the second low-voltage power supply is applied to the gate of the transistor N2.
A voltage signal corresponding to the voltage VSS of the first low-voltage power supply is input from the shift register 400 to the gates of 1 and N3. Therefore, the transistors N1 and N3 are off,
2 is turned on. Here, HV = 160V, VG =
140V, VCC = 5V, VSS = 0V, transistor B
The forward voltage VBE between the base and the emitter of P2 is 0.8 V
And Since the output voltage is initially at the low level, the transistor P3 is in the off state.
2 has an emitter voltage V2 of 160V. Therefore, the transistor BP2 is on. Therefore, as the transistor N2 is turned on, the transistor BP2
, The emitter voltage V2 decreases. When the voltage of V2 drops to VG + VBE = 140 + 0.8 = 140.8V, the transistor BP2 turns off. As the voltage of V2 decreases, the transistor P1 turns on. When the voltage V1 approaches the voltage HV of the high-voltage power supply, the transistor P2 turns off. Therefore, the emitter voltage V2 of the transistor BP2 becomes 1
It is kept at 40.8V. At this time, transistors P1, P
The gate-source voltage of No. 3 is V2-HV = 140.
8-160 = -19.2V, and the voltage HV of the high voltage power supply
Can be sufficiently reduced. Further, the transistor P
2 and BP2 are turned off, the transistor N2
No through current flows from the high-voltage power supply to the low-voltage power supply via the power supply.

The same applies to a case where a high-level voltage output is switched to a low-level voltage output. In this case, the transistor MP1 is turned off, and the transistor BP1 is turned off.
Is maintained at 140.8V. Therefore, the gate-source voltage of the transistor P2 is −1
9.2 V, which is sufficiently lower than the voltage HV of the high-voltage power supply. Further, since the transistors P1 and MP1 are turned off, no through current flows from the high-voltage power supply to the low-voltage power supply via the transistor N1.

Since a voltage of about 20 V is applied between the gate and source of the transistors P1, P2 and P3,
The gate oxide film thickness of these elements is larger (about 3 to 4 times) than the gate oxide film thickness of the transistors N1, N2, and N3 to which 5 V is applied between the gate and the source.

FIG. 3 shows a third embodiment of the present invention. The basic circuit configuration is almost the same as that of the first embodiment.
The level conversion circuit 100 includes four N-type MOS transistors N1, N2, MN1, and MN2 and two P-type MOS transistors P1 and P2.

The sources of the N-type MOS transistors N1 and N2 are connected to a first low-voltage power supply VSS.
The gate of N2 is connected to the drain of another N-type MOS transistor. N-type MOS transistor MN
1, MN2 are provided in series with N1 and N2, respectively, and their gates are connected to a reference voltage (VG) generation circuit 300,
A voltage VG higher than the voltage VSS of the first low-voltage power supply by a predetermined voltage is applied.

P-type MOS transistors P1 and P2 are provided in series with MN1 and MN2, respectively. The sources of P1 and P2 are connected to a high-voltage power supply HV, and the gates are shift registers.
400 output signals are input. The inverted signal of the signal input to the gate of P1 is input to the gate of P2.

The output driver circuit 200 comprises an N-type MOS transistor N3 and a P-type MOS transistor P3. The source of the transistor N3 is the first low-voltage power supply VSS.
The gate of N3 is connected to the drain of the transistor N2 and the gate of the transistor N1, and the drain of N3 is connected to the output terminal. The source of the transistor P3 is connected to the high-voltage power supply VH, the gate of P3 is connected to the shift register 400 and the gate of the transistor P1, and the drain of P3 is connected to the output terminal. The clock signal CLK and the data signal DIN are input to the shift register 400, and the data signal DIN is transferred in the shift register 400 every cycle of the clock signal.

The operation of the circuit of the present invention will be described by taking as an example the case where the voltage output switches from a high level to a low level.
Here, HV = 0V, VG = -140V, VCC = -5
V, VSS = -160V, and the threshold voltage Vth of the transistor MN2 is 1V. When switching, transistor P
The voltage signal corresponding to the voltage VCC of the second low-voltage power supply is input to the gate of the second low-voltage power supply, and the voltage signal corresponding to the voltage VH of the high-voltage power supply is input to the gates of the transistors P1 and P3 from the shift register 400. Therefore, the transistors P1 and P3 are turned off, and P2 is turned on.

Since the output voltage is initially at the high level, the transistor N3 is in the off state, and the source voltage V2 of the transistor MN2 is -160V. Therefore,
The gate-source voltage of the transistor MN2 is VG-V
2 = −140 − (− 160) = 20V, which exceeds the threshold voltage Vth of 1V, so that the transistor MN2 is on. Therefore, as the transistor P2 is turned on, the source voltage V2 of the transistor MN2 increases. Then, the voltage of V2 is VG−Vth = −14.
When the voltage rises to 0-1 = -141 V, the transistor MN2
Turns off. As the voltage of V2 rises, transistor N1
Is turned on, and the voltage V1 is the voltage V1 of the first low-voltage power supply.
Since the transistor N2 is turned off when approaching SS, the source voltage V2 of the transistor MN2 is kept at 141V. At this time, the gate-source voltages of the transistors N1 and N3 are both V2-HV = -141-(-160) = 19.
V, which is sufficiently smaller than the absolute value of the power supply voltage of 160 V. Further, since the transistors N2 and MN2 are turned off, no through current flows from the high-voltage power supply to the low-voltage power supply via the transistor P2. The same applies to the case where the low-level voltage output is switched to the high-level voltage output.

The transistors N1, N2, N3, MN
1, and a voltage of about 20 V is applied between the gate and the source of MN2.
Transistor P to which 5 V is applied between gate and source
1, P2, and P3 are thicker (about 3
~ 4 times).

FIGS. 4 to 6 show an embodiment of the VG voltage generating means used in the driver IC of the present invention.

FIG. 4 shows an example in which a bipolar transistor 310, resistors R10 and R20 and a constant current source 320 form a VG voltage. The resistors R10 and R
When a current flows through the transistor 20 and the voltage of the resistor R10 exceeds the built-in voltage VBE (about 0.7 V) between the base and the emitter of the bipolar transistor 310, the bipolar transistor 310 turns on and the voltage of the resistor R10 is clamped at VBE. . Therefore, VG can be set to a predetermined voltage by appropriately selecting the resistance ratio between the resistors R10 and R20. For example, if VBE = 0.7V, R10 = 1 kΩ, R20 = 29 kΩ,
A voltage 21 V lower than HV is generated as VG.

FIG. 5 shows an example in which a VG voltage is formed by a P-type MOS transistor 311, resistors R 10 and R 20 and a constant current source 320. Threshold voltage V of transistor 311
Assuming that th is -1V, the voltage of R10 is determined to be about 1V. Therefore, VG can be set to a predetermined voltage by appropriately selecting the value of R20 as in the case of FIG.

FIG. 6 shows a Zener diode 312 and a resistor R.
An example in which a VG voltage is formed by 10, R20 and a constant current source 320 is shown. By connecting three Zener voltages in series at 7 V, a voltage 21 V lower than HV is generated as VG.

The constant current source 320 is formed by, for example, forming an N-type transistor and a resistor provided on the source side thereof, and selecting a suitable resistance value to adjust the gate-source voltage.

FIG. 7 shows a fourth embodiment of the present invention. First
The first and second MOS transistors P1,
P2 is the first and second bipolar transistors B1, B
2 has been replaced. The operation of the circuit is basically the same as that of the first embodiment.

FIG. 8 shows a modification of the output driver circuit according to the first embodiment of the present invention. Both the pull-up and pull-down of the final stage of the output driver are N-type MOS transistors N
4, N3. A Zener diode 40 is provided between the gate and source of the transistor N4, and a predetermined voltage (for example, 6 V) or more is not applied between the gate and source. The transistors P30 and N40 charge and discharge the gate capacitance of the N-type MOS transistor N4 on the pull-up side, and determine ON / OFF of N4.

FIG. 9 shows another modification of the output driver circuit according to the first embodiment of the present invention. Insulated gate bipolar transistors IGB1 and IGB are provided at the last stage of the output driver.
2 is used. By using an insulated gate bipolar transistor having a higher load driving capability than a MOS transistor, the element size can be made smaller than that of a MOS transistor when the same current flows.

FIG. 10 is a block diagram of a driver IC using the level conversion circuit of the present invention. 1000 is a driver IC, Q1 to Q64 are output signals for driving a load, CLK is a clock signal, DIN is an input data signal,
DOUT is an output signal for transmitting a data signal to the next driver IC. Level shift and data latch circuit 400, level conversion circuit 100, output driver circuit 20
For 0, there are a total of 64 circuits, one for each of the output signals Q1 to Q64, but the VG voltage generating means may be one circuit per driver IC.

Although the VG generation circuit 300 is provided in the chip in the embodiments described above, the VG voltage may be supplied from an external power supply. In this case, there is no need to provide the VG generation circuit 300 in the chip.

FIG. 11 shows a driver IC of the present invention connected to EL (E
electro Luminescence), LED (Light Emitting Diod)
e) is a configuration diagram in the case of using as an IC for driving a display panel such as plasma or liquid crystal. 200
0 is a VGA color display panel of 480 × 640 (X3) pixels, and 1100 is a data (address) driver I.
C, 1200 is a scan driver IC, 1110 is an address electrode wiring, and 1210 is a display electrode wiring. For the sake of simplicity, the drawing shows only the wiring on the outer periphery of the panel, and the cells are not shown. The circuit block configuration of the data driver IC 1100 and the scan driver IC 1200 is the same as the configuration of the driver IC 1000 shown in FIG. Assuming that the number of output bits of the data and scan driver ICs is 64, 30 data driver ICs and 8 scan driver ICs are used. Using this driver IC, a load in the panel, that is, a capacitance parasitic on a cell (not shown) and an electrode wiring capacitance are charged and discharged. The number of driver ICs used for a display panel is large, and the number will be further increased with higher definition in the future. Therefore, by reducing the power consumption of the driver IC, lower power consumption of the panel can be realized.

FIG. 12 is a configuration diagram around a head portion when the driver IC of the present invention is used in an ink jet printer.

Reference numeral 3000 denotes a head portion of an ink jet printer, 3100 denotes a nozzle, 3200 denotes a common electrode, 330
0 is an individual electrode, 3400 is a heater, 3500 is an ink groove, 3600 is a partition separating each nozzle, 3700 is an orifice plate, 3800 is a silicon substrate, 1300
Denotes a driver IC according to the present invention, and the level conversion circuit 100, the output driver circuit 200, and V shown in the embodiment of the present invention.
It has at least a G generation circuit 300. The bonding pad 1310 for signal output of the driver IC 1300 and the individual electrode 3300 of the head portion are connected to the bonding wire 331.
0 is connected. In this embodiment, the heater 3400 is the main load driven by the driver IC.

When the output voltage of driver IC 1300 goes high, a voltage is applied to individual electrode 3300. And
When current flows through the heater 3400 provided between the common electrode 3200 and the individual electrode 3300 to heat the heater, the ink filled in the nozzle 3100 thermally expands and is ejected from the nozzle.

By using the driver IC of the present invention, the power consumption of the ink jet printer can be reduced.

FIG. 13 is a configuration diagram when the driver IC of the present invention is used in a motor device.

4000 is a DC brushless motor, 410
0 is a Hall IC, 5000 is an AC power supply, and 5100 is a rectifier. 1400 is a driver IC of the present invention,
An output driver circuit 200, a level conversion circuit 100, and a VG generation circuit 300, which are drive circuit units using high-voltage power elements, and a logic control unit using low-voltage elements are integrated on a single chip. 1410 and 1430 are comparators, 1420 is an oscillator, and 1440 is a three-phase distributor. This driver IC can be used by being incorporated in a motor device.

In the brushless motor control shown in the figure, the transistor N3 and IGB2 of the lower arm are set to about 20 kHz,
The transistors P3, N4, and IGB1 of the lower arm are driven at a low frequency of 100 kHz or less according to the rotation speed of the motor. The motor speed is changed by controlling the lower arm by pulse width modulation (PWM). That is, a signal indicating the position of the magnetic pole of the motor detected by the Hall IC is transmitted to the driver IC.
1400 receives and performs U, V, W phase switching,
A motor control microcomputer (not shown) detects the number of rotations of the motor from the output signal of the Hall IC, and transmits a signal VSP obtained by comparing this with the speed command to the driver IC 1400. driver
The IC 1400 determines the pulse width of the lower arm by comparing the VSP and the carrier signal of the PWM control.

The case where the present invention is applied to a display device, an ink jet printer device, and a driver IC for driving a motor device has been described above. However, the present invention is applicable to a facsimile device, an LED, a liquid crystal printer, or a device other than these electronic devices. The present invention can be applied as a driving IC for an electronic device using inverter control such as an inverter lighting device.

[0052]

According to the present invention, a voltage higher than a predetermined voltage (for example, 5 V to 20 V) is not applied between the gate and the source of the MOS transistor constituting the level conversion circuit and the output driver circuit. A gate oxide film with a high withstand voltage is not required, and the fabrication of a MOS transistor is facilitated. Also, since a through current does not constantly flow at the time of high-level voltage output, a high-voltage power IC with multi-bit output is provided.
Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a level conversion and output driver unit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a level conversion and output driver unit according to a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a level conversion and output driver unit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing one embodiment of a reference voltage generating means used in the driver IC of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the reference voltage generating means used for the driver IC of the present invention.

FIG. 6 is a circuit diagram showing still another embodiment of the reference voltage generating means used in the driver IC of the present invention.

FIG. 7 is a circuit configuration diagram of a level conversion and output driver unit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram showing a modified example of the output driver section in the first embodiment of the present invention.

FIG. 9 is a circuit diagram showing another modified example of the output driver section in the first embodiment of the present invention.

FIG. 10 is a block diagram of a driver IC according to the present invention.

FIG. 11 is a block diagram of a display device using the driver IC of the present invention.

FIG. 12 is a block diagram of a printer device using the driver IC of the present invention.

FIG. 13 is a block diagram of a motor device using the driver IC of the present invention.

FIG. 14 is a circuit configuration diagram of a level conversion and output driver unit used in a conventional driver IC.

FIG. 15 is another circuit configuration diagram of a level conversion and output driver unit used in a conventional driver IC.

[Explanation of symbols]

100: level conversion circuit, 200: output driver circuit,
300: VG generation circuit, 320: constant current source, 400: shift register and latch circuit, 1000, 1100, 120
0, 1300, 1400: Driver IC, 2000: Display panel, 3000: Inkjet printer head, 3100: Nozzle, 3200: Common electrode, 33
00: individual electrodes, 3400: heater, 4000: brushless motor, 4100: Hall IC, HV: voltage of high-voltage power supply, VSS: voltage of first low-voltage power supply, VCC: voltage of second low-voltage power supply.

Continued on the front page (72) Inventor Masahiro Iwamura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] 1. A level conversion circuit for converting a low voltage signal into a high voltage signal, and a driver circuit driven by an output of the level conversion circuit, wherein the level conversion circuit constantly performs level conversion. Switch means for detecting and turning off a predetermined voltage that is an intermediate voltage between the highest voltage and the lowest voltage of the output voltage of the driver circuit so that a through current does not flow; and the intermediate voltage as an output of the level conversion circuit Using
A driver IC for driving at least one of the output stage transistors. A level conversion circuit for converting a low-voltage signal into a high-voltage signal; and a driver circuit driven by an output of the level conversion circuit, wherein the level conversion circuit includes first and second power supply circuits. 2nd M
An OS transistor, and gates of the first and second MOS transistors are connected to each other, and the level conversion circuit is connected in series to a side opposite to a power supply side of the first and second MOS transistors. And first and second clamping MOS transistors provided, wherein the first and second clamping MOS transistors have their own gate voltage and the gate voltage of the second and first MOS transistors which are not in series with each other. A driver IC which operates so as to be turned off when a voltage difference falls below a predetermined voltage, and wherein an output of the level conversion circuit is taken from a gate of the first MOS transistor. 3. A level conversion circuit for converting a low-voltage signal into a high-voltage signal, and a driver circuit driven by an output of the level conversion circuit, wherein the level conversion circuit includes first and second power supply circuits. 2nd M
An OS transistor, the gates of the first and second MOS transistors are connected to each other, and the level conversion circuit is connected in series on the side opposite to the power supply side of the first and second MOS transistors. The first and second clamping bipolar transistors are provided, and the first and second clamping bipolar transistors are provided.
The bipolar transistor for clamping operates so as to be turned off when the difference between the gate voltage of the second and first MOS transistors and the base voltage of the second and first MOS transistors which are not in series with each other becomes less than a predetermined voltage. A driver IC wherein the output of the circuit is taken from the gate of the first MOS transistor. 4. A first and a second having one conductivity type channel.
MOS transistor, third and fourth MOS transistors having the other conductivity type channel, and a level conversion circuit including first and second switch means, the first MOS transistor and the first switch means , And a third MOS transistor are connected in series, a second MOS transistor and a second switch means, and a fourth MOS transistor are connected in series, and a gate of the first MOS transistor is connected to a second MOS transistor. A transistor connected to a common connection point of the second switch means; a gate of the second MOS transistor connected to a common connection point of the first MOS transistor and the first switch means; A terminal other than the gate of the transistor and having no connection point with the first and second switch means is connected to the high-voltage power supply, A terminal other than the gate of the fourth MOS transistor and not having a common connection point with the first and second switch means is connected to the first low-voltage power supply, and a terminal of the first and second switch means. A terminal that does not have a common connection point with any of the first, second, third, and fourth MOS transistors is connected to a reference voltage source, and the voltage of the reference voltage source is higher than that of a high-voltage power supply. Are also lower by a predetermined voltage, and the gates of the third and fourth MOS transistors are respectively connected to outputs of a logic circuit using the second low-voltage power supply as a power supply,
The third and fourth MOS transistors operate complementarily to each other, and use the gate of the first or second MOS transistor as an output terminal of the level conversion circuit, and use the output signal of the level conversion circuit to output the next transistor A driver IC characterized in that the driver IC is driven. 5. A first and a second channel having one conductivity type channel.
MOS transistor, third and fourth MOS transistors having the other conductivity type channel, and a level conversion circuit including first and second switch means, the first MOS transistor and the first switch means , And a third MOS transistor are connected in series, a second MOS transistor and a second switch means, and a fourth MOS transistor are connected in series, and a gate of the first MOS transistor is connected to a second MOS transistor. A transistor connected to a common connection point of the second switch means; a gate of the second MOS transistor connected to a common connection point of the first MOS transistor and the first switch means; Terminals other than the gate of the transistor, which do not have a common connection point with the first and second switch means, are connected to the first low-voltage power supply. The other terminal than the gates of the third and fourth MOS transistors, which does not have a common connection point with the first and second switch means, is connected to the high voltage power supply. A terminal having no common connection point with any of the first, second, third, and fourth MOS transistors is connected to a reference voltage source, and the voltage of the reference voltage source is And the gates of the third and fourth MOS transistors are respectively connected to the outputs of logic circuits using the second low-voltage power supply as a power supply,
The third and fourth MOS transistors operate complementarily to each other, and use the gate of the first or second MOS transistor as an output terminal of the level conversion circuit, and use the output signal of the level conversion circuit to output the next transistor A driver IC characterized in that the driver IC is driven. 6. The driver I according to claim 4, wherein:
C, wherein the first and second switch means are MOS transistors, and a gate terminal thereof is connected to the reference voltage source. 7. The driver I according to claim 4 or claim 5.
C, wherein the first and second switch means are bipolar transistors, and a base terminal thereof is connected to the reference voltage source. 8. The driver IC according to claim 2, wherein:
3. The driver IC according to claim 1, wherein the first and second MOS transistors and the first and second clamping MOS transistors have a gate oxide film thickness greater than the gate oxide film thickness of other MOS transistors. 9. The driver IC according to claim 2, wherein:
A power supply line to which a gate voltage of the first and second clamping MOS transistors, a base voltage of the first and second clamping bipolar transistors, and a voltage of the reference voltage source are applied; A driver IC having a diode connected between a power supply wire and a power supply line of the low-voltage power supply so as to be reversely biased. 10. A driver IC according to claim 1, wherein said electronic device has a plurality of loads therein and functions by charging / discharging or energizing said loads. An electronic device for driving the load by using any one of the above.