JPH10509544A - Monolithic PC audio circuit - Google Patents

Abstract

(57) Abstract A monolithic integrated circuit for enhancing the audio performance of a personal computer has been disclosed. The monolithic circuit comprises a wavetable synthesizer and a full-function stereo coding / decoding circuit (CODEC), which is capable of analog-to-digital and digital-to-analog data conversion, data compression and mixing and multiplexing of analog signals. And a local memory control module for interfacing with an external memory, a game MIDI port module, a system bus interface, and a control module for compatibility and circuit control functions.

Description

DETAILED DESCRIPTION OF THE INVENTION Title of the Invention: Monolithic PC audio circuit                               Background of the Invention   1. Technical field of invention.   The present invention relates generally to computer-controlled audio systems, and more particularly to desktop computers. For use with system boards and expansion cards for laptops and portable computers It relates to an audio circuit. A preferred embodiment of the present invention is MS-DO S, Windows, UNIX, and OS / 2 operating systems generally called IBM compatible Compatible with the assembled system to implement the rating system Is specifically designed to The present invention includes a stereo audio COD Equipped with EC and digital wavetable audio synthesizer I have.   2. A brief description of the related art.   Normally, personal computers are made with only limited audio functions Is done. These limited functions generate a mono sound and alert some users Audible signals for various simple functions such as call signals Things. None of the voice features are generally high quality. General personal Multimedia computer and video game applications To provide stereo and high-quality audio, which are desirable additional extensions for Function is not provided. Built-in machine to generate and synthesize music and other complex sounds No function. Music synthesis (synthesizing) function via computer The sound played on the external instrument to generate sound using a composition application. Required when recording or recording. Also analog speakers, multimedia The same applies to the (CD-ROM) application. Compositing function is required . Standard sound cards provide a MIDI interface and game port. Input from a MIDI device such as a keyboard or a game joystick. Power To receive.   In addition, users can use external analog sound sources, such as stereo instruments and microphones, Digitally record or decode before recording or playback by computer. I want the ability to use non-MIDI instruments for mixing with digital sound sources There are cases. To meet these demands, a number of additional equipment products have been developed. Company The industry calls one such product line a soundboard. these Sound boards are supplied by computer manufacturers with numerous integrated circuits and users. This is a circuit board that holds a related circuit attached to the expansion slot. This expansion slot Attaches an ISA interface to the system bus and sends a sound to the host processor. Access the device and control board functions under the control of application software Be able to control.   Currently, the most popular sound board in the industry is Sound Blaster. Und blaster) and Adlib (ad lib). On these sound boards Is a monolithic FM synth that generates sound from data supplied by system memory A sizer circuit is incorporated. These sound boards include digital signal processing. There is also an integrated circuit for D / A conversion, A / D conversion, and application software. Processing commands from the host CPU under the control of the hardware, and generating control signals for other circuits. Processing, processing of input / output MIDI data, expansion of stored data, and the like. other Interfaces integrated and discrete circuits to analog input or output ports Or, inter alia, a separate circuit for the system bus interface.   These conventional systems also had limited functions, and were justified by audiophiles. System that cannot generate high-quality sound, consumes much power, and cannot use expansion slots. The problem is that it is not suitable for use in a board application. Further In addition, conventional systems of this type require plugs that require compliance with industry standard self-setting methods. -Not suitable for an and play environment. Conventional sound cards use a host CPU In order to supply the design data to the company, a built-in jumper switch was used.   The latest version of Sound Blaster, Sound Blaster P ro and Pro2 are upgraded FM synthesizer integrated circuits, stereo output Power jack, stereo digital recording and playback, separate mixer integrated circuit, separate CD- By adding a ROM interface, stereo is added to the sound output function equipped. The Pro DSP circuit has a maximum of 44.1KHz monaural and stereo Recording and playback up to 22.05 KHz were provided. The mixer is used to Audio, line input, CD input and digital sound, background CD audio Mixing of sounds from Dio performance is now possible.   Such systems require multiple integrated circuits and are plug-and-play. It does not provide compatibility, has limited mixing functions, consumes much power, and simply It was limited to use only when lot design was available.   In addition, unlike more advanced wave table synthesizers, The sizer function was also processed and limited to the number of FM-based voices. This kind of The system requires limited mixing, panning, and control functions to achieve its effect. There was no individual sound effect.   Further, such a conventional system includes a local memory interface for temporarily storing audio data. Interface to the system memory to transfer all data without an interface. Access was needed. With this restriction, audio data for recording and playback is obtained Requires frequent DMA or programmed I / O cycles, Caused an excessive and extra burden on the processor.   These conventional systems are limited by the 8-bit sampling size. , Dynamic range limited to 256 steps, large bit sampling It produced more pronounced aliasing than with the technique. Sound The latest Sound Blaster called d Blaster 16 ASP Products include 16-bit playback / recording sampling and 44.1KHz stereo support. Achieved the sampling rate. This latest version incorporates multi-chip Wavetable synthesizer circuit or chip, dedicated processor Circuit or chip, separated bus interface chip, separated A / D and D / C times Circuits, analog amplifiers and other related circuits on the expansion board. This cis System for enhanced programmability, higher sampling rates, and larger samples. Mainly suitable for use with expansion slots despite offering pulling sizes This has led to the adoption of multiple chips and high power consumption. This latest version Is No local memory, no plug and play compatibility, no application And a dedicated processor for processing instructions and composite instructions. Wave table Option requires a separate daughter board, which is A 4 megabyte ROM for storing wavetable data. Was.   Conventional CODECs that are widely used have a recording / playback model of 5. Only 14 sampling rates are available in the range between 51 and 48.0 KHz . In addition, each of the ODEC devices of the related art is capable of simultaneous recording and playback. Can only use the same sampling rate. The ratio between recording and playback is simply Programming is impossible in Germany.   Another prior art system is Advanced under the name Ultrasound. Provided by Gravis and Forte. This system is Incorporating another expansion slot sound board mode, a single chip A synthesizer, MIDI and game interface, DMA control and Adlib So Unblaster compatible logic was built in. In addition to this ASIC, Ultrasound cards have onboard D for wavetable data. RAM (1 megabyte), address decode chip, analog input and output Separate analog circuit with interface connection, separate programmable ISA bus ・ Interface chip, interrupt PAL chip, separation D / A, A / D conversion chip Equipped.   All conventional systems have a single-chip synthesizer and data compression / decompression. CODEC for D / A and A / D operation, mixer, analog interface, system System bus interface, interrupt and DMA control, and compatibility I didn't. Multi-chip aspects relate to cost, size, speed, and power consumption. There were obvious limitations.   Incorporating all the essential and desirable functions in a single chip No noise and other signal contamination, while limiting the total integration, or It was an obstacle. Another obstacle is an efficient configuration design for a single chip embodiment. It was not possible. Note that other obstacles control individual modules, It lacked an efficient way to manage a fully integrated system.   In addition, each of the legacy systems includes a variety of industry standard software or hardware. There were one or more limitations on hardware compatibility. Conventional system throat None provided plug and play compatibility that could be freely selected . Prior art systems provide a wide range of host CPUs as synthesizer functions. Or had a dedicated synthesizer processor, More cost or excessive demand on host CPU overhead Caused the operation to slow down.   The system of the present invention addresses each of these issues in a number of unique and efficient ways. Is to solve it. In addition, the system of the present invention It provides the improved performance.                               Summary of the Invention   SUMMARY OF THE INVENTION The present invention provides a monolithic PC audio integrated circuit. Circuits include AT ISA compatible system bus interfaces, plugs, System control module and system control register with and play compatibility , System control logic and interrupt generation, compatible with existing PC audio software Sexual function is included. The system according to the present invention performs A / D conversion and D / A conversion. Nau coding and decoding module (CODEC), data compression Analog mixing and multiplexing of audio signals It is equipped with. Digital wavetable audio synthesizer Modules, MIDI, and game port modules are also provided. In the present invention The circuit according to the present invention further provides a local memory module, the circuit comprising an external DRA Connection with M, ROM and serial EEPROM for plug and play compatibility To be able to Data transfer for the circuit according to the invention is mounted on a chip It is easily transferred via the register / data bus and the control circuit. Circuit of the present invention Includes noise reduction attribute, external address decoding function, buffered input / output Power functions are provided as well as resource protection functions mounted on the chip.                             BRIEF DESCRIPTION OF THE FIGURES   For a better understanding of the present invention, reference may be had to the detailed description of the preferred embodiments in connection with the accompanying drawings, in which: This can be achieved by considering the detailed explanation.   FIG. 1 is a schematic diagram of the configuration of the basic module of the circuit C.   FIG. 2 is a schematic diagram of the actual layout of the circuit C.   FIG. 3 is a table summarizing the assignment of circuit C to pins.   FIG. 4 is a diagram of an alternative layout of circuit C, showing the noise used in circuit C. And the main clock signal.   FIG. 5 summarizes the assignment of circuits C to pins grouped by module. This is the table shown.   FIG. 6 shows a representative PC audio circuit C with associated circuits, buses and interconnections. It is a schematic diagram in which typical full functions are implemented.   Figure 7, a table summarizing the functions related to pin assignment and local memory control. is there.   FIGS. 8, 9, and 10 show simplified registers with appropriate indexes and module assignments. It contains a table of storage names.   FIG. 11 is a schematic diagram illustrating an embodiment of a multiplexing circuit.   FIG. 12 is a schematic block diagram of the system control module of the circuit C.   FIG. 13 shows a circuit C including a modular interface to the register data bus. It is a block schematic diagram of.   FIG. 14 is a schematic diagram of a detailed implementation of the register data bus.   FIG. 14a is a schematic diagram of a portion of the ISA bus interface circuit.   FIG. 15 is a timing chart showing a failure example of the ISA bus timing of the circuit C. You.   FIG. 16 is a timing chart related to the buffer input / output of the circuit C.   FIG. 16a is a schematic diagram of some emulation logic for circuit C. .   FIG. 16b shows the application software and the emulation TSR program. FIG. 4 is a schematic block diagram relating to the possibility of accessing the circuit of Gram.   FIG. 17 is a schematic diagram of a plug and play state machine included in circuit C. You.   FIG. 18 shows a serial EE relating to plug and play compatibility from an external circuit. FIG. 6 is a timing chart related to reading of PROM data.   FIG. 19 shows a PNP for a circuit C from an external circuit via a register data bus. 4 is a schematic diagram of a circuit that facilitates data transfer.   FIG. 20 shows the execution of the activation key for accessing the plug and play register. 5 is a schematic diagram of a linear feedback shift register necessary for the present invention.   FIG. 21 illustrates the isolation of the plug and play circuit associated with circuit C (isolation). From configuration mode to configuration mode or sleep mode 9 is a flowchart showing a state of transition to.   FIG. 22 is a diagram showing a plug-and-play compatible serial EEPROM data program. 5 is a table summarizing resources required for ramming.   FIG. 23 provides data on all events that cause an interrupt in circuit C. It is a table that can be read.   FIG. 24 illustrates the external oscillator utilized by circuit C and its associated stable logic. FIG.   FIG. 24a illustrates the logic and counting circuits associated with the various low power modes of circuit C. It is a schematic diagram.   FIG. 24b illustrates the response of circuit C to a suspend (suspend) mode operation. It is a flowchart which shows.   FIG. 24c is a flowchart illustrating various register controlled low power modes of circuit C. It is.   FIG. 25 is a schematic diagram with details of the clock oscillator stabilization logic of FIG.   FIG. 26 is enabled by the bit state in the register PPWRI included in the circuit C 6 is a table describing events that occur according to various power saving modes.   FIG. 27 shows the various power saving modes and the signals and clock signals used by circuit C. FIG. 4 is a timing chart showing the relationship between the signals.   FIG. 28 requires pins associated with the system bus interface in circuit C. It is a table to be reduced.   FIG. 29 shows a basic module including the local memory control module of the circuit C. It is a block schematic diagram which illustrated.   FIG. 30 illustrates the master stage associated with the local memory control module of circuit C. 2 is a schematic block diagram illustrating a port machine.   FIG. 31 shows the suspend mode control signal and the 32 KHz clock used by circuit C. FIG. 4 is a timing chart illustrating a relationship with a lock signal.   FIG. 32 is utilized by circuit C during suspend mode operation. 5 is a state diagram illustrating a refresh cycle.   FIG. 33 is a timing chart of the suspend mode refresh cycle. .   FIG. 34a is a timing diagram of an 8-bit DRAM access.   FIG. 34b is a timing diagram of a 16-bit DRAM access.   FIG. 34c is a timing diagram of the DRAM refresh cycle.   FIG. 35 illustrates a method of obtaining a real address from a circuit C to an external memory device. FIG.   FIG. 36 is a schematic diagram of a control circuit for recording and reproducing FIFO in the local memory. It is a block diagram.   FIG. 37 shows a local memory by the data stored in the system memory and the circuit C. FIG. 3 is a diagram illustrating a relationship with data interleaved in a memory.   FIG. 38 shows data of 8-bit and 16-bit sample sizes under the control of DMA. 9 is a table describing a transfer format.   FIG. 39 shows the system memory via the local memory control module of the circuit C. Illustrates a circuit that executes DMA data interleaved from FIG.   FIG. 40 is a schematic diagram illustrating a game port interface between an external device and a circuit C. It is a block diagram.   FIG. 41 illustrates the execution of a single bit for the game input / output port of circuit C. FIG.   FIG. 41a illustrates the detection of an input signal through the game port of circuit C. You.   FIG. 42 is a schematic block diagram illustrating a MIDI transmission / reception port for the circuit C. .   FIG. 43 is a schematic diagram illustrating the MIDI data format used by the circuit C. It is a block diagram.   FIG. 44 is a block diagram of various functional blocks for the CODEC module of the present invention. It is a lock schematic diagram.   FIG. 45 illustrates a preferred implementation for the left channel stereo mixer of the present invention. 2 is a schematic diagram of an embodiment.   FIG. 45a is a table of gain values and attenuation values.   FIG. 46 is a schematic diagram of a partial waveform showing signal discontinuity with respect to attenuation / gain change. is there.   FIG. 47 is a block diagram showing a zero detection circuit for removing "zipper" noise. You.   FIG. 48 is a block diagram showing a clock generation function in the present invention.   FIG. 49 is a block diagram of a serial data transfer function according to the present invention.   FIG. 49a is a block diagram of the serial transfer control block.   FIG. 50 illustrates the internal and external data paths, supported by the present invention. FIG. 2 is a block diagram showing connection at an interface with an external device.   FIG. 51 is a block diagram of the D / A converter block of the present invention.   FIG. 52 is a block diagram of a front end of a D / A converter block according to the present invention. It is.   FIGS. 53a-53f illustrate various stages of the DAC block, including the frequency response. It is a graph which shows an output.   FIG. 54 shows six output and frequency responses at various stages of the DAC block. It is a graph.   FIG. 55 is a schematic diagram showing one block of the interpolation circuit and phase 1 of FIG.   FIG. 56 is a schematic diagram showing one block of the interpolation circuit and phase 2 of FIG.   FIG. 57 is a schematic diagram showing two blocks of the interpolation circuit of FIG.   FIG. 58 is a graph of a frequency response in the interpolation circuit 2 block of FIG.   FIG. 59 is a graph showing in-band attenuation in the two blocks of the interpolation circuit of FIG. You.   FIG. 60 is a schematic diagram illustrating an embodiment of the interpolator 3 block of FIG. is there.   FIG. 61 is a schematic diagram showing another embodiment of the interpolation circuit 3 block of FIG. You.   FIG. 62a is a graph of the frequency response of the interpolator 3 block of FIG. 52. .   FIG. 62B is a graph showing the attenuation of the pass band in the interpolation circuit 3 block of FIG. 52. It is.   FIG. 63 is a schematic diagram showing the noise shaper (noise shaper) block of FIG. You.   FIG. 64 is a signal flow graph of the noise shaper block in FIG. (SFG).   FIG. 65 shows the number of poles and zero in the s plane in the noise shaper block of FIG. It is a graph.   FIG. 66 shows the magnitude of the transfer function in the noise shaper block of FIG. This is a graph.   FIG. 67 shows the number of poles and zero in the z plane in the noise shaper block of FIG. It is a graph.   FIG. 68 is a graph of the transfer function of the noise shaper filter of FIG.   FIG. 69 illustrates the ideal and achievable zero of the noise filter block of FIG. It is a graph.   FIG. 70 shows the noise transfer function 2 for the noise shaper block of FIG. 6 is a graph comparing two embodiments.   FIG. 71 shows transmission of noise and signals in the noise shaper block of FIG. It is a graph of a function.   FIG. 72 shows the phase and pass band in the noise shaper block of FIG. 52. 5 is a graph showing the magnitude of the signal transfer function of FIG.   FIG. 73 shows the group delay (seconds) in the noise shaper block of FIG. It is a graph of.   FIG. 74 illustrates constants in embodiments in the noise shaper block of FIG. 5 is a graph showing the attenuation / gain shape of the graph.   FIG. 75 illustrates one embodiment of the noise shaper block of FIG. A_max6 is a graph showing noise gain κ.   FIG. 76 shows g = −90 dB in the noise shaper block in FIG. 52. And is a grab representing one embodiment of noise gain κ versus bandwidth.   FIG. 77 is a graph showing the impulse response of the D / A FIR filter.   FIG. 78 is a graph showing the frequency response of the D / A FIR filter.   FIG. 79 is a schematic diagram showing one embodiment of the D / A conversion circuit of the present invention.   FIGS. 80 and 81 show another embodiment of a different D / A conversion circuit of the present invention. It is a schematic diagram.   FIG. 82 is a block diagram of the CODEC ADC of the present invention.   FIG. 83 is a block diagram of the front end of the CODEC ADC.   FIG. 84 shows the output of the sigma-delta (σ-δ) modulator for the ADC of the present invention. 4 is a graph showing a spectrum range and a phase.   FIG. 85 is a graph showing in detail the output spectrum of the sigma-delta (σ-δ) modulator. It is rough.   FIG. 86 is a graph illustrating the output spectrum of the synchronous 6 decimal 1 filter output. You.   FIG. 87 is a graph illustrating the output spectrum of the half-band decimal two filter output. You.   FIG. 88 is a graph illustrating the output spectrum of the 16-bit decimal 3 filter output. It is.   FIG. 89 is a block diagram of the decimal 1 filter.   FIG. 90 is a graph illustrating the frequency response of the decimal 1 filter.   FIG. 91 is a graph illustrating the detailed frequency response of the decimal 1 filter.   FIG. 92 is a block diagram of a direct form of a half-band decimal two filter.   FIG. 93 is a block diagram of a substituted form of the half-band decimal two filter.   FIG. 94 is a graph illustrating the frequency response of a decimal two filter.   FIG. 95 is a graph of the detailed frequency response of the decimal 2 filter.   FIG. 96 is a block diagram of a compensation filter of a CODEC D / A conversion circuit. It is.   FIG. 97 is a graph illustrating the frequency response of the Decimal 3 filter.   FIG. 98 is a graph illustrating the detailed frequency response of the Decimal 3 filter.   FIG. 99 is a graph illustrating the frequency response of the compensation circuit (uncompensated).   FIG. 100 is a graph illustrating the full frequency response of the in-passband compensation circuit (not shown). compensation).   FIG. 101 is a graph illustrating the total frequency response for the compensation circuit in the passband. Yes (compensated).   FIG. 102 is a block diagram of the synthesizer module of the present invention.   FIG. 103 is a signal flow diagram in the synthesizer module of the present invention.   FIGS. 104a-104f illustrate the addressing of the synthesizer module of the present invention. 6 is a graph illustrating a data designation control option.   FIGS. 105a-105e show the volume in the synthesizer module of the present invention. Fig. 4 is a graph illustrating a team control option.   106a-106b illustrate the low frequency required for the synthesizer module of the present invention. It is a graph of an oscillator waveform.   FIG. 107 shows an address control for the synthesizer module of the present invention. FIG.   FIGS. 108a-108b illustrate the operations performed by the address controller of FIG. FIG. 5 is a timing chart of a perlation.   FIG. 109 shows the volume control of the synthesizer module of the present invention. FIG.   FIG. 110 shows the operation performed by the volume controller of FIG. FIG.   FIG. 111 is a view showing a configuration of a register array for the synthesizer module of the present invention. FIG.   FIG. 112 is a timing diagram showing the operation of the register array shown in FIG. 111. FIG.   FIG. 113 shows a volume control circuit for the synthesizer module of the present invention. FIG. 2 is an overall configuration diagram.   FIG. 114a is a logic diagram of the comparison circuit shown in FIG. 113.   FIG. 114b is a timing diagram of the operation of the comparison circuit of FIG. 114a. It is.   FIG. 115 shows the configuration of the LFO generator for the synthesizer module of the present invention. FIG.   FIG. 116 is a configuration diagram of a signal path for the synthesizer module of the present invention. is there.   FIG. 117 is a timing chart showing operations performed by the signal path shown in FIG. 116. FIG.   FIG. 118 shows the accumulation of the synthesizer module of the present invention. It is a block diagram of a logic.   FIG. 119 shows an operation performed by the accumulation logic of FIG. 118. FIG. 6 is a timing chart of the operation.   FIG. 120 illustrates the operations performed by the synthesizer module of the present invention. FIG. 4 is a timing chart of the entire operation. The following figures are based on D-5733: Make a copy of these two figures. When:   FIG. 1 is a functional block diagram of the sigma-delta modulator of the present invention.   FIG. 2 is a schematic diagram of a sigma-delta modulator of the present invention.                         Description of the preferred embodiment   The following description describes a preferred embodiment of a monolithic PC audio circuit. I will tell. The description includes system architecture, implementation, power management, system control, Includes timing and memory interfacing and execution of key details. I will. Various optional circuits suitable for use with the present invention are disclosed in U.S. Pat. The content of each is disclosed in this document as a reference. Clock drive An alternative approach to reducing power consumption by dynamic circuits is disclosed in US patent application Ser. No. 07/918. 622, “Clock Generation Capable of Shut Down Mode and Clock” Generation Method "and assigned to the common assignee of the present invention. A statement that a single bit state in the register or field is desired to affect A preferred method and apparatus for performing such a single bit operation throughout the text is No. 08 / 171,311, filed on Feb. 21, 1993. Issue 3 is “Method and Apparatus for Modifying the Contents of a Register Vi a a Command Bit ", assigned to the common assignee of the present invention.   There are various references to timers, gate controls, and other control logic. Throughout the text, unless otherwise stated, obtain specific implementation details for appropriate logic circuits. And it may be difficult. Computer aided theory applied to VLSI logic circuit design Given the current state of the art, such as physical design and layout techniques, In other words, implementation details are considered trivial.   In view of the state of the art, such details apply to VLSI circuit purposes. Selectable, programmable logic arrays or blocks based on standard logic circuits It is executed according to. For example, a timer may generate a clock signal derived from an external oscillator signal. It can be easily implemented by giving the signal to an appropriate logic circuit. 80 microseconds The lock signal is obtained by dividing the 16.9 MHz oscillator signal by 1344. Can be The status of various data held in the register in the circuit C The generation of the corresponding control signal is simple, blocking the control input or an array of gate circuits. To satisfy the desired input / output or truth table requirements. Yes. Accordingly, those details which did not regard the claimed invention as important are But also not obtained, but this is clearly not a normal technical level This is because a person skilled in the art is familiar with the range. I. Architecture overview   FIG. 1 will be described. Outline of the architecture of the basic module of circuit C It is important. Circuit C has five basic modules. That is, the system control mode Module 2, coder / decoder (CODEC) module 4, synthesizer module Module 6, local memory control module 8, MIDI and game port module Le It is 10. These modules are formed on a monolithic integrated circuit. Les The register data bus 12 is connected between the modules and between the circuit C and the system bus interface. Data can be exchanged with the source 14. The timing of circuit C The control is provided by a logic circuit in the system control module 2. Is fed by one or two oscillators 16, 18 at the request of the particular system Operates in response to a clock signal. Control of circuit C is usually contained in module 2 Is determined by the logic circuit to be implemented, and then the logic circuit is installed in the circuit C. It is controlled by various registers and ports.   FIG. 1 is a functional block diagram, and the actual layout used in the embodiment of the integrated circuit is shown in FIG. It does not correspond directly. Those that facilitate the functions specified or specified in FIG. Seed circuits, interconnects, registers, etc. may be provided as needed and dictated by the manufacturing process, For convenience and other reasons known to those skilled in the art, the It is. The circuit of the present invention is fully assembled using conventional assembly techniques known in the art. You. The circuit according to the invention is a 160 pin plastic quadrilateral flat pack (PQ FP) is packed by the method described later.   A.Actual layout features and noise reduction.   The actual layout of various modules and the pin arrangement device are designed, The present invention was able to isolate the circuit and I / O section from the noisy digital circuit and pins. It is a feature of. FIG. 2 will be described. Various parts of the circuit C and places in the module An example of the desired actual layout relationship is shown schematically. Trigger in analog form in digital form In order to minimize the noise generated, the most sensitive element of the circuit C, For example, the elements related to the analog side of CODEC, especially Digital local memory control module and synthesizer module almost opposite Placed near the edge of the side circuit.   To further isolate noise induced in digital form in analog circuitry, Connect the pin arrangement device of the device to the analog mixer input / output pin From the most noisy digital output pin and clock input located in 2 Isolate just to move. In addition, the most affected pin groups 20 It is located on the side near the low noise input in regions 26 and 28. Representative pi The pin assignments are shown in Figure 3 and the pin names correspond to industry standard designations. . These industry standard designations include the ISA Plug and Play standard, version 1.0, available from Microsoft Corporation, May 28, 1993 And the industry standard ISA bus standard AT Bus Design (author Edward d Solari, Published Annabooks, San Diego California state. ISBM 0-929392-08-6). Content incorporated herein by reference It is. Alternate pin assignments are recorded in Figure 3a and include the desired physical relationship among the various modules. Entrance is being held.   The present invention is based on existing standard or well-known hardware software, for example, ISA Plug and Play Standard, Adlib, Sound Blaster And compatibility with Graves Forte ultrasound applications ISA, PNP, Adlib, GUS, etc. References to some signals and register abbreviations in the Relevant for compatible configurations. The # symbol following the signal abbreviation or bit status indicator is , Note that they are "active low" .   According to FIG. 3, the analog pin generally includes a plurality of analog power supplies (AVCC). 96 to 113 pins, including ground and AVSS pins . The noise reduction feature of the present invention is a separate SS for most individual analog pins. And VCC pins. Pins 82-95 and 114 are Fewer input pins. Other layout features include an external oscillator pin XTALI 1 [I, Q] and XTAL2 [I, Q] are connected to the clock block of the system control module. To place it near the rack. This system control module clock block The clock must also be placed near the CODEC clock block 30. circuit All 16.9 MHz clocks used in C minimize distortion between them It is important that it be performed. Minimizing internal clock distortion It is as important for timing purposes as it is for noise reduction in current circuits.   Analog sampling and digital circuits by minimizing analog signal noise It is a feature of the present invention to ensure that its activities are clocked independently. Like In a preferred embodiment, separate analog clock signals having different frequencies and Digital clock signals are provided from a common oscillator. Analog clock signal Are not derived from digital and vice versa, so there is a fixed place between the two There is no relation. In addition, some overlap of digital and analog clock driven events An analog clock distortion circuit is provided to reduce the likelihood of confusion.   According to FIG. 5, further explanation of the pin assignment according to the general function group is provided. U. These pins associated with the system control module 2 are abbreviated and identified under the title. Listed using the number of components. Similarly, CODEC, local memory and port, And the pins associated with miscellaneous functions also appear under their titles, respectively. here Note that the same is true throughout this specification, except that the "CD" pin or CD D References to functions such as RQ usually specify the function of the pin associated with the external device EX It should be considered the same as "EX" such as DRQ.   B.Typical system implementation.   Referring to FIG. The figure includes related circuits, buses, and interconnections. A PC audio circuit C having a model full function is described. The configuration in FIG. Circuit C illustrates all available RAs to illustrate the use in PC audio cards M and EPROM resources for full compatibility with the ISA Plug and Play specification Flights are available.   In FIG. 6, a circuit C includes a system bus interface module 14 and And host via industry standard AT / ISA system control, address and data connections. Interface to the strike computer system. These include: It is. That is, system data (SD), system address (SA), system Byte high enable (SBHE), interrupt requests (IRQs), input / Output channel check (IOCHCK), direct memory access request ( DRQ) and acknowledge response (DAK), input / output read (IOR), input / output write (IOW), reset, address enabled (AEN), terminal count (T C), input / output channel ready (CHRDY), input / output chip selection 16 (IO CS16). With these connections, a standard is provided between the circuit C and the host computer system. Standard communication and control functions are possible.   In a standard embodiment, the following input / output lines and associated circuitry and / or equipment The class is interfaced to the CODEC module 4. This equipment is The quasi jack 42 is used for four sets of stereo input and an external stereo amplifier 46 and For stereo analog output (line out L, R) 44 with jack 48 Done. Via monaural microphone / amplifier input 50 and external amplifier 54 A mono output 52 is provided. By providing an external capacitor and a resistor circuit 56, To derive the reference bias current for various internal circuits, and To provide a ration capacitor. Programmable registers A controlled general purpose digital 2-bit flag output 60 is provided to provide some Used for application requests. The game / MIDI port 62 has 4 bits G. Game input terminal 65, 4-bit game output terminal 66, and MIDI transmission / reception A bi-directional interface 68 is included.   The system control external connection includes a 16.9344 MHz and 24.576 MHz clock. There are clocks 16, 18, and 32 KHz clock or suspend input 70. Said entry Force 70 is used for memory refreshing and power saving, and Multiplexed with other signals as detailed elsewhere in this section.   The interface of the local memory control module 8 has a frame synchronization (FR SYNC) and an effect (EFFECT) output 72 are included. Provide a synchronous clock pulse at the beginning of each frame of the raw cycle and additional special Optional external digital signal processing equipment used to provide effects and other DSP functions Used to provide access to the device 74.   The plug and play chip select 76 is disabled during system initialization. Section EPROM 78 provides configuration data for 3-bit data bus 80 It can be so. Data between the local memory control module 8 and the external memory device For communication of data and addresses, an external 8-bit data bus 82 and an 8-bit address bus are used. S 84 is possible.   The ROM chip selection 83 and the 2-bit ROM address output 85 are four Used to address one of the byte x 16 bit EPROMs 86. This EPROM 86, as described elsewhere herein, contains external data. It is provided for storing a command sequence. EPROM 86 is a ram column One of four signals multiplexed by the address strobe 90. Interfacing with circuit C via 4-bit output enable 88 to save resources save. One aspect of EPROM 86 addressing is a 3-bit real Provided by address input 92. The address signal on line 92 is Row and column address bits multiplexed for the given DRAM cycle on input 94. Multiplexed. Pin 96 (MD [7:01]) of circuit C is This is a two-way data bus, which is a data bus for DRAM cycles. Via the data [7: 0] line 98. Pin 96 is at E during the ROM cycle. As real address bits 18:11 for PROM 86 and for circuit C Multiplexed as input data bits 7: 0 (half of RD 15: 0). E The data communication from the PROM 86 is performed by the 8-bit buses 82 and 84 during the ROM cycle. 16-bit data output 100 (RD [RD [ 15: 0]). EPROM data input is performed during the ROM cycle. It is transmitted on a bidirectional line 96 and a bidirectional line 102 (RD [15: 8]). Line 102 is also occupied by eight bits during the multiplex ROM address and data transfer cycle. Addressing of the read ROM (RLA [10: 3]). Many lines 102 Row and column address bits during the DRAM cycle (MA [10: 3]) give.   Output 104 is a ROM address holding signal, which is output during circuit ROM access by circuit C. , Outputs 96 and 102, buses 82 and 84, and 16-bit address input line 10 6 is used to latch the state of the 16-bit ROM address obtained by step 6. 1 The 6-bit latch 108 latches the ROM address in response to the ROM address holding signal. It is provided for touching.   Circuit C contains up to four 4 megabyte x 8 bit memories used for local data storage. It supports the DRAMS110 of the Internet. Circuit C consists of the two 8-bits described above. Via various address, data and control lines maintained by buses 84 and 86. To interface with the DRAMS110. Row address strobe is R Obtained by AS output pin 112. The output 112 is the RA of each DRAM circuit 110. Provided directly at the S input. For clarity, in FIG. 6, the output 112 is also A writable (WE) output provided to a writable input of each DRAM circuit 110 It is shown as providing a control signal. In a preferred embodiment, it is writable. The active outputs are supplied from circuit C to separate output pins (see FIG. 3). DRAM power The RAM address strobe (CAS [3: 0]) causes B It is provided via the KSEL [3: 0] output pins 114. 3-bit DRAM row And column addressing are performed via output 116 for an additional eight address The DRAM size is determined by the bidirectional pin 102, bus 84 and DRAM input 118. It is multiplexed between cars. Overview of all local memory interface terminals Are listed in FIG.   FIG. 6 will be described again. Circuit C has seven interrupt channels 130 From which you can select up to three interrupts. In a preferred embodiment, Two interrupts are used for audio functions, the third interrupt is CD-ROM, or Or used for other external devices. Also, on line 130 (a group of 8 lines) ISA standard IOCHCK output is displayed and non-maskable interrupt by circuit C Is generated for the host CPU.   The circuit of the present invention is compatible with Sound Blaster and AdLib applications. General compatibility with other options. Memory-resident driver under MS-DOS -To run the sequence, make the host CPU active and compatible You have to get Such a driver sequence is an ultrasonic And sound board operating system (SBOS) It is. The application software usually executes commands in the game, circuit C, The register specified as the Sound Blaster or AdLib register When sending to the master, circuit C captures it and processes it using the IOCHK pin. Suspend Sessa. The non-maskable interrupt part of the SBOS driver Read access by Sound Blaster or AdLib function Perform software emulation.   Circuit C also provides six DMA channels 136 and a DMA acknowledge response line 138. From which three DMA functions can be selected. The three DMA functions include File file transfer and system memory transfer, wave file playback transfer, external DMA channels required by the CD-ROM interface are included. B Usefulness of local memory DRAM 110 and pre-emption of data register in DRAM The first-out facility is provided for the wave file DMA function as described below. The need for a wave file DMA channel in some cases. It can be completely eliminated.   Referring to FIG. 6, in a system including a compact disk drive For use, circuit C provides the necessary signals or hooks to provide an external CD interface. Facilitates the use of external PNPs such as source 125. Circuit C has an external interface Separate interrupt request and direct address request Supply. In a preferred embodiment, separate input pins (see FIG. 3) are provided. Have been. By the circuit C, the chip selection of the external device and the output of the DMA approval response are performed by the circuit C. The output supplied via a separate output pin (FIG. 3), shown collectively by line 126 in FIG. Data exchange between the path C and the external device drive is based on the ISA standard 16-bit bidirectional data. This is realized via the tabus 128. II. Register and address assignment   Generally, circuit C is a register control circuit where various logic operations and Alternate modes of operation and different bits stored in different registers Or the state of the bit group. Complete description and definition of registers And related functions are described in charts and other places. I will clarify. Circuit C also includes several blocks of input / output address space. , Especially including 5 fixed addresses and 7 relocatable blocks for addresses . In the description of registers here, register simple storage is based on the following rules based on. That is,   1. For the first character, specify the area or module to which the register belongs The code is attached. That is,     I (for interface) = system control,     G (for game) = MIDI and joystick,     S = synthesizer,     L = local memory control,     C = CODEC (code decoding module),     R = CD-ROM,     U (super audible sound) = Gus, sound blaster (sound                                     Blaster), AbLib compatible,     P = Plug and Play ISA   2. Intermediate second through fourth characters describe register function .   3. The last character is R for direct register, (register array with index P for a port (to access the I / O) or I for an indirect register Either.   A.Relocatable address block.   Table 1 below shows the seven monolithic address blocks included in the circuit C. refer. Therefore, PNP stands for Plug and Play, an industry standard. -N-Play) specification.   B.Overview of direct addresses.   Circuit C has eight functional groups that use programmable registers . The state of the programmable register is implemented by the host CPU system Follow the control according to the command. Eight functional groups and their associated direct addresses Are listed in Table 2 below. For plug and play registers Two of the addresses are 12 bits of the ISA address bus (SA [11: 0]). Decrypted. The remaining address is the first 10 bits (SA [9: 0]) Is decrypted.   See Figure for a complete list of all I / O programmable registers and ports 8 to 10. There, all address numbers are represented in hexadecimal You. The index value gives an alternative function address using one common base address. I can.   C.External decode mode.   In addition to the 10 and 12 bit address space used for internal I / O maps, Path C also provides an optional external decode mode. There are four systems Implemented as address bits (SA [3: 0], FIGS. 3 and 6) and SA [5,4]. Two chip select signals address the registers in circuit C. This mode Is the state of the address pin RA [20] at the fall of the system reset signal. Selected by state.   Address pin RA [20] goes low at the falling edge of the system reset signal. In the case of, normal decoding of the input / output address is executed. At this time, the system Address inputs SA [11: 0] are used to address all registers in circuit C. Set. Address pin RA [20] is on the falling edge of system reset signal If high, external decoding is performed as follows. That is, This multiplexing is provided in the manner discussed below with respect to other multiplexing pins and functions. Can be   The table below shows how directly addressed registers are in external decode mode. Indicates whether the port is accessed. Indexed registers are directly Internal decode except that the address is changed to the address shown in Table 3 below. It is accessed in the same way as in mode (see register table below).   D.DMA access.   First in first out (FIFO) address defined as multiple registers in circuit C The data space is accessible via a DMA read / write cycle. these Are listed in the table below. However, here, LMC and CODEC are Represents a module in the circuit C in which such a register or FIFO exists. That is, However, in Table 4 above, the DMA group is a register definition word and is an ISA standard. It does not indicate the quasi-DMA channel or the number of request acknowledgments.   The external decode mode is used in a system that does not support PNP, Provides access to internal registers and ports via decode logic.   E. FIG.Multiplexing terminal.   To conserve resources, the ROM / DROM multiplexed address and the data In addition to data transfer pins, some groups of external terminals or pins may be replaced. Are multiplexed between the switching functions. 4 of those groups Is the reset signal that occurs at power-up or when resetting another system. Multiplexed based on the state of the external pin with respect to the falling edge of   Referring to FIG. 11, in one state, suspend # and C32KHZ FRSYNC # and EFFE in different states with pins 139 and 140 corresponding to inputs It is desirable to multiplex with CT # output. Machines that are fulfilled by these signals Noh will be explained elsewhere. In the circuit C, the rising of the reset signal By sensing the state of terminal RA [21] (see FIG. 6) on the descent, These pairs of pins are multiplexed. Pull up on RA [21] pin By providing a resistance or not providing such resistance , The D input to the latch 144 can be set to a lower value or an upper value. is there. The latch 144 is synchronized with the fall of the reset signal, To provide the corresponding lower or upper value. This latch output is 4 It is provided to a multiplexing circuit 146 of the pair 2. Multiplexer 146 has a Q output Power Pins 139 and 140 attached to SUSPEND # and C32KHZ function when Let it. On the other hand, when the Q output is lower, pins 139 and 140 are connected to EFFECT # and FR Attached to the SYNC # output function.   Plug-and-play compatible expansion card mode and system board mode Multiplexing or selecting between the input pin PNPCS at the falling edge of the reset signal. Is provided in a similar manner by latching the state of By lower value Select the plug and play mode, and set the system board mode according to the higher value. Select the code. This choice is for systems where the circuit C is plug and play compatible Used on a system board, plug-and-play It depends on whether it is used in an incompatible system.   An overview of the pins that are multiplexed based on the mode selected during reset is given below. Provided in Table 5.   To further save resources and use circuit C, compact disk control and system Real port synchronization, external digital signal processing circuit or other external serial Related to the clock and data transfer used when the Multiplexing between external pins. This is described in the following description of the CODEC module. This will be described in more detail.   Referring to FIG. 6, a CD-ROM drive in the system control module Control of external devices such as EX IRQ # (interrupt request), EX DR Q # (DMA request), EX DAK # (authorization response) and CD CS # (chip Selection) via a pin. These four pins are shown in FIG. And 126 are schematically depicted. Circuit C is in serial transfer mode (the following When working in these (detailed in the description of the CODEC), these four Multiplexing of the external device control pins in the state of bit 7 of the register ICMPTI Therefore, it is controlled. When ICMPTI [7] is higher, the external serial transfer mode Is possible. In that case, the external device control pins are multiplexed as follows . That is,   The above ESSYNC, ESPCLK, ESPDIN, and ESPDOUT machines Function corresponds to the synchronization pulse, clock, input data, and output data, respectively. You.   The table below shows all the pins of circuit C classified by input / output pin type. Shown below. That is, III. System control module   A.System control function.   As shown in FIG. 1, the system control module 2 includes a large number of registers and compatible logic. Logic, Plug-n-Play ISA implementation logic, interrupts, DMA channels Various controls such as clock selection logic, clock, reset, test logic, etc. Includes file functions. The system control module 2 is shown in detail in FIG. ing.   As shown in FIG. 12, the system control module 2 has a system bus interface. Source block 150, industry software compatible logic block 152, interrupt And DMA channel selection logic block 154, Plug-n-Play Gic block 153, register data bus 12, various logic / timing Block 158 is included. Generally, the system control module has an operation mode, Various registers to help change power consumption levels and other control functions In addition to enabling responses to retained control functions, various The function of the circuit C is controlled according to the timing, and the signal is controlled.     1. System bus interface.   The system bus interface 150 is a processor bus 156 controlled by a processor. And the hardware ink between the various modules of circuit C and the various parts of the circuit. provide. Circuit C is completely compatible with Plug-n-Play ISA system bus specification. Designed to be compatible. Plug-n-Play ISA specifications are System configuration data is stored to provide configuration data to the Requires an interface to a serial EEPROM that can be used during system initialization Wanting. The system bus interface is an ISA bus specification ISA. Must also conform to parts. These two specifications are industry standards, Widely used.   The ISA bus interface 150 is connected to the 24, 12 or 3.2 in the 5V mode. An interface with a 16-bit data bus with any of the milliamp drive functions Interface compatibility. Power-on default value is 24 mA It is. In output mode, the data bus is edge rate controlled and The delay is manually skewed, reducing ground bounce effects.   Further, the ISA bus interface 150 is connected to a 12-bit address bus. Interface and two audios selected from the seven interrupt request lines 130 Also provides support for interrupts and one CD-ROM or external device interrupt You. IOCHK for generating a non-maskable interrupt to the host CPU It also supports the use of signals.   The interface 150 includes six sets of DMA lines 136 and corresponding D lines. Also provides support for three DMA channels selected from MA acknowledge line 138 . According to the ISA DMA specification, the available channels are 0, 1, 3, 5, 7 (Channels 0, 1, and 3 are 8-bit DMA channels; 7 is a 16-bit channel). The three DMA functions supported are: It is as follows. Wave file record transfer and system memory transfer, File file transfer, required by CD-ROM or external device interface DMA channel. Although they cannot be used at the same time, both recording and playback A mode is also provided in which functions can be mapped to the same DMA channel.     2. Register data bus.   Data distribution between the ISA bus and the circuit C is performed using the register data bus 12. Will be The register data bus 12 is provided through a system bus input / output and a circuit C. Facilitates DMA access to provided registers. As shown in FIG. The register data bus is connected to the synthesizer via the bidirectional data bus transceiver 160. Iser register 162, local memory control register 164, system control register 166, MIDI and game port, register 168, CODEC register It interfaces with 170. The purpose and function of these registers This is described in detail in the textbook. The register data bus 12 and I shown in FIG. Both between the ISA data bus 172 which is the data part of the SA system bus 156 A data bus transceiver 160 is also provided. In addition, details in this specification As described in detail, the register data bus provides various local memory 173, 174, 175 and CODEC FIFO 176, 178 Take a source   The circuit C converts an 8-bit or 16-bit data to and from the system data bus. Supports sending. In case of I / O access from ISA data bus, The alignment of data with the data bus is the least significant of the ISA address bus. Defined by bits. These are SA [O] and S, as shown in FIG. Recognized as BHE #. These two buses are connected as shown in Table VI below. For access to other than the typical input / output data port (18 / 16DP) Is executed. That is,   Note that any eight bits are passed to the second half of register data bus 12. ISA Using the conditions of SA [0] and SBHE #, which are not allowed in the bus specification, Specifies high byte access from the default card. For 8-bit cards, the card Designer pulls the SBHE # bit high.   FIG. 14 illustrates the details of the register data bus control. cash register The star data bus 12 includes two 8-bit buses 180 and 182. . The low byte bus 182 uses a data bus transceiver 184 to transmit system data. Interface with the low byte of the data bus 128 (see FIG. 6). Hi-by G Bus 180 interfaces with the high byte of system data bus 128 . Controlled bus driver 186 responds to control / decode logic 190 Then, data is transferred between the buses 182 and 180, and the data specified in the table above is transferred. Perform data conversion. The control logic 190 controls the inputs SBHE # and SA [0 ] In response to a control signal via lines 192, 194, 196, 198, 200. Create a signal and perform the data transformations described in the preceding table.   Until the high byte, which provides 16-bit I / O access, becomes active, An 8-bit latch 202 for latching byte data is provided. Controlled The driver 204 responds to a control signal from the control / decode logic 190. In response, a low byte and high byte simultaneous I / O access is executed.   Control logic 190 also enables read / write access, respectively. , ISA bus signals IOR # and IOW #. Shown on lines 208 and 210 As with the input signals shown, these inputs are shown as signal lines 206. As such, they are provided at individual pins to circuit C. Control of logic circuits 190 and 212 The PNP data transfer under control involves the bus 182 and the controlled bidirectional transceiver 214 Provided using PNP logic functions and registers are described in detail in this document. It is explained in detail. The control / decode logic 190 is an industry standard ISA system. Provides system bus interface control and address decoding, as described above. It can be implemented by the usual appropriate method of implementing a data processing protocol. Likewise , PNP logic circuit 212 provides an interface that is compliant with industry standard PNP Can be implemented by ordinary circuits.   The control / decode logic 190 performs normal handshake, decode, Provides an interface circuit to interface with industry standard ISA system bust I take the.   Access to all PNP registers uses an odd 8-bit address. IO CS16 # is not asserted for these accesses, so the CS16 # 8 bits are used. This corresponds to the lower 8 bits of the register data bus. Handed over to each other. IOCS16 # is an industry standard declared through an external pinout (See FIG. 6).   I8DP at P3XR + 5 and I16DP at P3XR + (4-5) Used to access 8-bit and 16-bit index registers included in path C It is. I16DP is a port of circuit C that allows 16-bit I / O access. I can't do it. ISCS16 # provides all access to these general data ports. Expressed in The general I / O data port address is translated as follows: You. That is,   The system bus interface 150 has two 8-bit 16-bit I / O divided into write (first even byte, then odd byte) Responsible for writing conversion. In this case, the even byte write is Latched, and through the second half of the register data bus during subsequent odd byte writes. Provided. The register data bus provides an even 8-bit I Provides last latched in / O write.   In the case of DMA access, the data width depends on the DMA channel used as follows. Is determined by That is,   When reading 8-bit DMA and I / O, the ISA data bus 128 The appropriate byte is driven. Other bytes are not driven, high impedance It remains.   The voltage of the register data bus will be in the transition region when not driven. In order to ensure that no ー Dobak inverter ("keeper" circuit or "sticky bit" circuit) It must be noted that they are offered. This circuit reduces the float of the node voltage. Provide a weak feedback path to prevent.   Considerations for ISA data bus drives.When the data bus is driven In order to reduce the required peak return current, three special There is an ISA data bus design. First, the output drive capacitor is programmable Selectable between 24, 12 or 3.2 mA via register (When VCC is 5V). Second, an output buffer that slows down the edge rate There is a built-in special current limiting circuit. This circuit is a PC Net ISA chip It is implemented in the same way that 79C960 / 1 uses. Third, FIG. As shown in FIG. 3A, the data bus has a small number of groups each skewed from the other. Are divided into groups.     3. Register data bus I / O decode.   The address space to be decoded contains 7 relocatable blocks and 4 There are non-relocatable blocks. The details are as follows. That is,   The notation PPWRI [SD] in the above table is used for writing I / O to PPWRI. This indicates that the circuit C is started in the shutdown mode.   2XX and 3XX decoding are further divided as follows. That is,   AEN.The previous decoding is enabled only when AEN is low.   IOR and IOW.Along with the previous decode, the SBI 150 Provides IOR and IOW. Assumed when interfacing to these signals The worst ISA bus timing that must be shown is shown in FIG. This figure is Access to one addressable 16-bit port in the IC Note that only the fastest I / O cycle occurs (P 3XR = (4-5)). All other ports are much slower 8-bit timing (IOCS 16 # is not activated). IOR # and IOW # Remains active for about 530 nanoseconds in an 8-bit I / O cycle .   IOCHRDY control.Access from PSXR + 2 to PSXR + 7 Only by deactivating IOCHRDY, the ISA bus I / O The cycle can be extended. All P2XR, port, CODEC, Plug-n -Access to the Play ISA register does not extend the cycle. Registers that can extend the cycle (including 46 registers pointed to by IGIDXR) In the case of a star, the following categories exist. That is,   Buffered I / O writes are important because the CPU can continue without waiting . However, if not handled properly, the order in which I / O cycles are handled Problems can arise. For example, buffered I to local memory Immediately after the / O write, the write to the local memory I / O address register Cause writes to local memory to be sent to the wrong address . This problem can delay access to circuit C while buffered I / O writing is in progress. Is handled by letting As shown in FIG. 16, IIOR #, IIOW # , IBOWIP # are internal signals. IIOR # and IIOW # are IBIO WIP # (buffered I / O write) became inactive and triggered Becomes active when the previous buffered write is completed. IIOR # and IIO W # is not gate-controlled by IBOWIP # during the DMA cycle. Note that.   A register called a buffered register that allows buffered I / O writing is , Synthesizer audio specific register, IGIDXR = 51h, local memory system Control (LMC) 16-bit access register IGIDXR = 51h, LMC byte This is the data register LMBDR. I / O write to any of these registers Automatically, IBOWIP # becomes active and IOCHRDY Becomes inactive at the next I / O access to the circuit C. Any buffered cash register By reading the I / O to the host, the logic (1) (IBIOWIP # is activated) Deactivated IOCHRDY (whether or not active), and (2) IBI When OWIP # is active, it becomes inactive and IOCHRDY becomes inactive. (3) Wait for read data to become available on the ISA bus, (4) Allow IOCHRDY to become active. At this point, The cycle is completed like a cycle.   Control of IGIDXR.IGIDXR is in auto increment mode (S VSR), IGIDXR writes 8-bit data to P3XR-5. Or the fall of either 16-bit write to P3XR + (4-5) Increment by If the write is to a buffered port , IGIDXR are incremented after the falling edge of IBOWIP #.     4. Compatibility with existing game cards.   The system control module 2 is compatible with existing game card software. Have the necessary logic and registers to do so. Circuit C is in native mode U ltrasound, MPU-401, Sound Blaster, AdLi Compatible with software written for b. Logic circuits and tags for compatibility The image is generally designated as block 152 in FIG. This includes: Features are included. (I) Register described in the register description section of this document (Ii) 80 microsecond resolution and 320 microsecond resolution (Iii) two general purpose registers, (iv) MPU-40 1 Status emulation flag and control register.       a.AdLib timer 1 and AdLib timer 2.AdLib timer 1 8-bit preloader that increments to 0FFh before generating an interrupt It is a bull counter. Clocked by 80 microsecond clock Have been. AdLib timer 2 uses a 320 microsecond clock Same as 80 microsecond timer except that it is clocked The same. At the next clock after reaching 0FFh, the interrupt becomes active, It is reloaded by its program values (UAT1I and UAT21). Interrupt Only cleared and enabled by UASBCI [4]. Which Thailand Also change the 1MHz clock to run off by UASBCI [4]. Can be These timers are UADR [STRT1] and UADR [STRT1]. [STR2] enables it.       b.Auto timer mode.By writing to UASBC [0], Road C can be in auto timer mode. This mode is used for AdLib Used to emulate hardware. UAS for auto timer mode By reading the RR, the status of various flags, not UASWR, can be known. Oh When UACWR is set to 04h in timer mode, the following changes occur. You. (1) Writing to UADR does not cause an interrupt. (2) Writing to UADR Writes are not latched in registers readable from that same address , (3) Writing to UADR is related to control of AdLib timer Various flags are latched into registers that drive out.       c.General purpose register.The logic block 152 is also an MPU-401 emulator. Used to support other emulation software It has an 8-bit general purpose register. UGP11 and UGP21 general purpose registry ISA1 through UGPA1I, UGPA2I, ICMPTI [3: 0] It can be located anywhere in the 0-bit I / O address space. In fact, each Registers are the registers that are read for the application and the 2 shows two registers, one of which is written by a different option. register Is written (by the application) at the emulation address, The register is enabled and generates an interrupt. This register will be Using the backdoor access position on the hidden register data port (UHRDP) , Read (by the emulation software that received the interrupt) . Writing to this same backdoor location leads to a read operation The general register is updated. The outline of this emulation protocol is shown in FIG. It was shown to.       d.MPU-401 emulation.MPU-41 emulation Some controls have been added to the general purpose registers for support. MPU- The 401 emulation TSR is an application (generally game software). It is assumed that it is being executed in parallel with a). Matches MPU-401 card Emulation addresses (UGPA1I, UGPA2I, ICM PTI [3: 0]) is set to match the MIDI UART address. Wear. The two UART addresses indicate that the received / transmitted data is transmitted via P3XOR + 0 Accessed, control / status data is transmitted via IVERI [M401] Can be swapped to be accessed. Application to general-purpose registers Writing an application causes an interrupt (such as an NMI). Emu The translation software catches this interrupt and triggers a backdoor (UHRDP). To read the data in the emulation register and learn how to control the synthesizer. Use to Also, the application can be driven by the same interrupt, MP As with the U-401 card, the MIDI command is Also sent to UART.   FIG. 16b shows the accessibility of the application and the emulation TSR. FIG. 3 is a schematic block diagram showing the same. IEMUAI and IEMUBI emulation The switch symbol controlled by the control register is enabled.   MPU-401 status emulation.Read by UBPA1I Possible two MPU-401 status bits, DRR # (Data Rec eave Ready, bit 6) and DSR # (Data Send Re) ady, bit 7) is created. The initial meaning of these bits is It is as follows. DRR # indicates that the host (CPU) has a new command or data buffer. Active (low) when a site can be sent to the UART. DSR # Is active when there is data available in the UART's receive data register. -) The names of these bits are not MPU-400 hardware, but CPU. Note that this is taken from a hardware perspective. Read and emulate these bits The data actually written to the application register is from IEMUBI [5: 4]. It is what came.   Emulation address (ICMPTI [3: 0], UGPAIL, U GPA2I), writing to any of the emulation registers Then, if writing to that register is enabled, DRR # Set to inactive (high) by hardware. Backdoor (UHRDP) The state of this flag is also updated by writing to UGP1I [6] using. This bit defaults high on reset.   Use emulation address (ICMPT1 [3: 2], UGPA2I) DSR # is deactivated by hardware if there is one UGP2I read (High). To UGP1I [7] via backdoor (UHRDP) This flag is also updated by writing. This bit is reset Defaults to low at default.     5. Plug-n-Play logic.   The system control module 2 is a Plug-n-Play of Microsoft. It has the necessary registers and logic to implement ISA (PNP). circuit Within the C PNP block are several state machines (see description below). ), 16.9 MHz. Some use a clock obtained from an oscillator.   Circuit C has two PNP-compliant logic devices. AUDIO Functional Theory Processing devices include synthesizers, CODECs, ports, etc. Circuit C. External functions, ie, CD-ROM logical devices, Only tied to function.       a.PNP I / O ports and registers.In support of PNP, Path C provides a number of dedicated registers. These registers are PIDXR And read and write ports PNPRDP and PNPWRP. Is accessed.       b.Select PNP mode at power-on.The reset signal is output when the power is turned on. The state of the force pin 76 (PNPCS, FIG. 6) is latched to determine the PNP mode. B Circuit C, the serial EEPROM 78 (PNP card model) Card) is assumed to be on a PNP compliant card containing Latched high Circuit C does not include a serial EEPROM (PNP system mode) It is assumed to be on the system board.   In PNP system mode, the card selection number (CSN) is the PNP standard It is assigned in a different way than the law (see PCSNBR). This is This is the case when a system board implementation can exist without an external serial EEPROM. Outside When coding is selected in the section (for general description, see PIN Summary Section), all PNP registers are Accessible. Therefore, in this mode, access to the PNP register Assign a CSN or use any PNP protocol to obtain There is no need to incorporate hardware.       c.PNP state machine.As shown in FIG. 17, the PNP interface Are in one of three states: key wait, isolation, configuration, or sleep. You. In FIG. 17, wake is a wake command, and X is a command and The associated data value, CSN is the current card selection number. These lotus All are described in the Plug-n-Play ISA specification. PNP state machine As shown in the figure, the output of the input is PNPSM [1: 0].   Waiting for key.In this state, the PNP logic writes 32 to PIDXR. Wait for a byte key. In this state (except for PIDXR for the key) The NP register is also unavailable.   isolation.In this state, the PNP software sends the IO to the PIOCI. Run the R-cycle algorithm to disconnect each PNP card and separate it Is assigned. If circuit C is in PNP system mode, PI Parts are always "lost" in isolation due to SOCI readings, Enter sleep mode.   Constitution.From this state, the PNP software reads from the PNP EEPROM 78 Reads all resource data, resources (I / O address space, IR Q number, DMA number) and a specific command (such as activate) Send   sleep.In this mode, the PNP hardware is dormant.       d.Interface with serial EEPROM.Audio logic When the device is not activated (PUACTI [0]), the PNP serial EE The PROM 78 can be accessed. Selected by PSEENI [10] There are two access modes: PNP initialization and PNP control . In the PNP initialization mode, based on the state of PNPSM [1: 0] as follows: Then, the data is automatically read from the EEPROM. That is,   As shown in FIG. 18, the timing for reading the serial EEPROM data is Is provided. What is standard data in serial EEPROM? Note that it is necessary to enter circuit C in the reverse order. Bits [7: 0] are even Represents several bytes (the first byte is read through PRESDI) [15: 8] represents an odd byte. The serial block SK has a frequency of 99 6 KHz ICLK1M (see below).   In PNP control mode, the EEPROM pin is set to the PSECI bit. Therefore, it is directly controlled.       e.Initiation key and linear feedback shift register.P To access the NP register, a linear feedback shift register (LFS R) requires a hardware / software unlocking mechanism that requires implementation You. See FIG. 20 for the implementation of the LFSR 230. Unlock the software It completes after the software writes the following 32 values to PIDXR: 6A, B5 , DA, ED, F6, FB, 7D, BE, DF, 6F, 37, 1B, 0D, 86 , C3, 61, B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74 , 3A, 9D, CE, E7, 73, 39. These values are internally stored in LFSR23 Calculated as 0. If all 32 bytes have been written to PIDXR, the PNP The state machine transitions from the key waiting mode to the sleep mode (see FIG. 17).       f.Isolation mode.Serial in isolation mode The data contained at the beginning of the EEPROM 78 is shifted one bit at a time. And used in the algorithm shown in FIG.   The PNP specification is calculated or simply brought from the serial EEPROM 78. The last eight bits of the serial identifier, the checksum, are acknowledged. these The value is not calculated by circuit C. Transferred directly from serial EEPROM 78 It is. The algorithm of FIG. 21 has a configuration mode from the isolation mode. Or transition to the sleep mode is allowed.       g.Card selection number register.Plug-n-Play specification is a card A selection number (CSN) is assigned to every device on the system bus and its Require that the number be accessible. Circuit C has a card selection number ( Designated as card selection number backdoor (PCSNBR) where CSN) is stored There is an 8-bit register that is being used. CSN, PNP state machine is isolated Writable in the case of the operation mode. PNP state machine is in configuration mode Is readable.   By using the following procedure, you can bypass the normal PNP protocol , CSN. That is,   1. Put the pull-up register in PNPCS, and turn on the card when power is turned on. Switch to system mode.   2. When the AUDIO logical device is not active (PUACTI [0] = 0), put the PNP state machine in the isolation mode.   3. Write the CSN to the game control register 201h.       h.Plug-n-Play resource requirement map.PNP serial EE FIG. 22 shows an example of resources required for programming the PROM 78.     6. Interrupt and IRQ channel selection.   An interrupt has a group of signals that are tied to the interrupt. Details The details are as follows. That is,   These are built into the three IRQ channel selectability of circuit C as follows: I will. That is,   The following equations show how the previous three equations map to the IRQ pin. (See FIG. 3). Here, x of the IRQ designates an IRQ number. (UIC The notation I [2: 0] == IRQx) is described as "UICI [2: 0] replaces IRQx. Specify. "   The Non-Maskable Interrupt (NMI) function (low impedance and high impedance Is controlled as follows. That is,   In the previous and following equations, the / before a variable or signal means logical negation. Note. * Indicates an AND function, and + indicates an OR function. /, *, + The first, second, and third priorities are shown, respectively. The program associated with the previous expression The programmable bit fields and signals are as follows. That is,   Interrupt event.The table in FIG. 23 shows all interrupt driving events in circuit C. And provide data on events. Circuit C is in auto timer mode and UA If CWR is written to 04h, writing to UADR will interrupt Note that it does not generate.     7. DMA channel selection.   The following are the signals used in circuit C that are tied to the DMA data transfer request. You. That is,   These are three DRQTY channel selectable for circuit C as follows It is summarized in the sex. That is,   The following equation shows how the previous three equations map to the DRQ pin (see FIG. 3). Shows the law. Here, x in DRQx designates a DRQ number. The notation UDCI [2: 0] == DRQx is based on the expression “UDUDI [2: 0] is DR Specify Qx ".   Enable DRQ from high impedance.Below is the high impedance This is an expression of a signal for enabling the DRQ from the sense. That is,   Drives data bus during DMA.By reading the DMA of the circuit C, the circuit C Only when the A request signal is set, the system data bus is driven. Also , Circuit C, if a confirmation occurs without a DMA request, all DMA writes Ignore only.   DMA rate.In DMA transfer between local memory and system memory, transfer Speed is controlled by LDMACI [4: 3]. The best of all MA transfers At speed, from about the half from the end of the last DAK signal to the beginning of the next DRQ signal One microsecond. This is two ICLK2M, 2MHz clock Incorporated by counting edges.     8. clock.   Circuit C has a number of internal clock requirements. In this section, A description of all internal clocks created from crystals 16 and 18 ( (Fig. 1). As shown in FIG. 24, generated by this block of crystal 16 All clocks are in steady state when the oscillator is not enabled (held high). Guaranteed to start again when the oscillator stabilizes Have been. This logic is used when the oscillator is about to stabilize. This is because there is no glitch in the clock. This is the oscillator stability shown in FIG. This is the purpose of the stabilization logic 232. And is used for: (1) suspension Exit from Pend mode, (2) Exit from shutdown mode, (3) IC Is in shutdown mode following a software reset (PCCCI) To stabilize the oscillator. If the RESET pin is active, it will be bypassed. It is.   In FIG. 24, the IOSC16M signal is a 16.9344 MHz clock 16 From the input clock signal. This clock signal is applied to the control on line 233. Clock signal to the oscillator stabilization logic 232 via a clock or gate signal Provided as Gate control logic 242 is also enabled on line 235. A signal is generated, and ON / OFF of the clock 16 is controlled.   As described below, the gate control logic 242 includes Provides output ICLK16M via buffer 237, used as system clock Different clock signals with different frequencies for a particular sub-circuit or function. 239 used by logic block 241 to generate the signal To provide 16.9344 MHz. If necessary, a similar stabilization Note that a Gic can also be provided for Crystal 18. In the current implementation, Christa In response to the activation signal PPWRI (PWR24), the buffer 18 is buffered on line 234. Provides a Fado 24MHz output.   Oscillator stabilization logic.As shown in FIG. 25, the oscillator stabilization logic 232 , A 16-bit counter 238 clocked by the oscillator 16, And a flip-flop 240 for controlling the data 238. As a result, Gotting to allow a rock pass or disable it glitch-free It is a gate to the logic 242 (FIG. 24). 16.9 MHz clock 16 signals STOP CLK is in suspend and shutdown mode. Clear the counter 238. In the preferred implementation, a software reset ( PCCCI) determines whether or not circuit C is in shutdown mode. System reset in either 256 or 64K states of PCARST # remains active (see below) . Cheap The logic counter in the stabilization logic 232 is also controlled to achieve the required delay. Provide a signal. Signal GO CLK is asserted when the RESET pin is active. The control flip-flop 240 is set. Circuit C is suspended and shut down When exiting the down mode, STOP CLK is deactivated and the counter 238 is set to 6 4K state is clocked out, and CLOCK of circuit 238 is output. ENABLE output Becomes active. STOP CLK and GO The CLK signal is described elsewhere. In response to the state of the power control register and the reset signal, Generated from the logic circuit.   FIG. 24a illustrates the details of the clock generation and control / stabilization circuit. Figure The logic and counter shown in FIG. It should be noted that this is only an example of how this can be implemented. Those skilled in the art will recognize that there are various other variations while keeping the function specifications. You can understand.   System reset signal 430 is an external ISA bus signal. System reset 430, before signal PCARST # on line 431 goes inactive (high). Allow at least 10 milliseconds to allow time for oscillators 16 and 18 to stabilize. (Which enables PCARST #). signal PCARST # supports most memory functions (registers, latches, flip-flops) Default, bits of RAM), all ISA bus activity is ignored To stop the local memory cycle. System reset is free GO to flip flop 240 Provided as CLK asynchronous set signal 435 . This signal causes the Q output to go high on line 233, immediately To enable the 16-MHz clock signal. Cable. 24MHz clock is also PWR24 bit of register PPWRI 24 bits of the PWR respond to the PCARST # signal. Set high by default, so it is enabled by reset. You.   In FIG. 24a, the PCCCI signal is controlled by the state of the PCCCI register. I / O mapped command from PNP logic (software reset) controlled Is. The PCCCI assertion is asserted on line 434 by the signal PCARST #. Provided as an alternative source.   In FIG. 24a, in response to an active input from the Suspend # pin, Enter suspend mode. For reference, the suspend mode logic is shown in FIG. a in the active / positive mode. Active input suspend The signal is on line 446, with inputs to ORGATE 448 and ANDGATE 450 Provided. In response, ISUSPRQ asserts gate 454 and gate 454, respectively. The I2LSUSPRQ and I2SSUSPRQ modular signals are activated via 456. It becomes active at the activating line 452. Suspend input on line 446 Provides 80μ second delayed output to ORGATE448 and ANDGATE450 To provide a two-bit delay counter 458. The delay circuit 458 is connected to the line Clocking by the internally generated clock signal ICLK12K provided at 460 Is If necessary, this signal can be used to generate a modular suspend signal. Provided to For example, if ISUSPIP is input to ORGATE 464 Provided, modular I2LSUS for local memory module of circuit C Generate a PIP signal. This signal is low during normal operation. Disable the 16.9 MHz clock signal used by the local memory module. Used to make cables.   ISUSPIP is an approximately 80μ second oscillator after ISUSPRQ is asserted. Through ORGATE 467 and ORGATE 466 to ground Line 436 to clear the counter 238 Provided as CLK It is. The counter 238 is cleared when the suspend signal is deactivated. After that, the oscillator 16 needs to stabilize. Similarly, IS USPIP uses ORGAT to disable the 24 MHz oscillator 18. Provided as input to ANDGATE 468 via E470.   Various clocks.As for the system clock, the clock circuit of Joule 2 Provides various clocks for various functions. The following summarizes these clocks. You. That is,   IKLK1M is designed to meet the requirements of PNP serial EEPROM 78 , 9 clock high and 8 clock low duty cycles. So All other clocks have their duty cycles as close to 50-50 as possible. It is implemented as follows.   Test mode requirements.When the chip is in test mode, these many The clock circuit is bypassed (see register description below). In addition, 1 The 6.9 MHz and 24.5 MHz clocks may be Directly controlled without a counter.     9. Power consumption mode.   Circuit C is a device that prevents the various blocks of logic from consuming large amounts of current. Have noh. In addition, a shutdown mode can be set. In that case, Both oscillators are disabled. Also, in suspend mode, both The shaker is disabled and most of the pins are inaccessible. various Control to disable the block and put circuit C into shutdown mode. Control comes from the programmable register PPWRI. Suspend mode is SU Controlled by the SPEND # pin (see FIG. 6). Depending on the suspend mode , I / O pins change operation as shown in the following table. That is, SA [11: 6], SBHE #, DAK [7: 5,3], SD [15: 8] The pins have a small internal pull-up resistor. However, these registers The power supply to be turned on is driven so that the drive voltage is not applied to the ISA bus during the suspend mode. It can be disabled by VERI [PUPWR]. Stop power consumption For pins that are put into a high-impedance state for Is done. In suspend mode, this buffer is disabled and its The output (input to circuit C) is grounded.       a.Register controlled low power mode.The register PPWRI is connected to the Reduce the power consumed by the various blocks of 7-bit register used to store The table shown in FIG. What happens when various bits in register PPWRI are cleared or set Explains what is coming. Each bit of PPWRI is low when in low power mode. It is defined as:   The 100 millisecond timer in FIG. 26 includes a logic block 158 (FIG. 12). Normal timer cycles, each driven by ICLK100K (divide by 10) The road is constructed. One of the timers counts the transition time to the low power mode. Other timers count the time to exit low power mode. Used to go out. Use these same timers for suspend mode Can be.   In FIG. 24a, register PPWRI is outlined as register 472. Has been. Responds to each bit of register 472 cleared to logic low state Then, the shutdown mode is activated. State of each bit of register 472 Provides an output to timer 476 when all bits are low, ANDGA Provided as an inverted bit to TE 474. After a 100 μ second delay, No bits in register 472 have changed to logic high due to provisional delay To disable (ground) the oscillator via ANDGATE 480 At 478, an output is provided. This status check provides one second , Enable input to ANDGATE 480, ORGATE 482 Provided through. When the output of the timer 476 exits the shutdown mode, Counter 238 of the stabilizing circuit 232 to provide sufficient delay STOP to rear Provided as CLK input.   As noted elsewhere, the state of the PWR 24 bit is asserted via gate 468. The power to the shaker 18 is controlled. Depending on the state of each bit of the register 472, the module Dual power mode is implemented (PPWRI). For example, bit 4 (PW RS) state to the counter circuit, ORGATE486, ANDGATE488 Is provided as input. These circuit elements are the synthesizer suspend request signal. Signal 490 and the synthesizer clock signal via gate 493. Delay Synthesizer Suspend-in-Progress Provide a signal. Local memory modules have similar delay / logic times. A road 494 is provided. Other bits of register 472 are described in this specification. As can be seen, the status of the various modules and modules in circuit C Control. A schematic diagram of the logic implementation of these functions is shown in FIG. 24a.   FIG. 24b shows an overview of the response of circuit C to activation and deactivation of the suspend mode. It is a flowchart showing the abbreviation. FIG. 24c shows a register control low power mode. It is a flowchart which shows.       b.Suspend mode.When the SUSPEND # pin becomes active, Circuit C behaves the same as in the shutdown mode. The tie in Figure 27 The diagram shows how the oscillator, clock, and signals go to the SUSPEND # pin. To respond to the request. In FIG. 27, the ICLK24M signal is stable. Note that it is described as This condition is optional. ISUSP RQ is I2LSUSPRQ and I2SSUSPR of the shutdown logic. It is logically ORed with Q. ISUSPIP is logically ORed with I2LSUSPIP (See FIG. 26). Circuit C already shuts down when SUSPEND # is asserted When in the down mode, (i) the I / O pin is in the suspend mode as described above. (Ii) The codec analog circuit, which changes to match the requirements of If not in low power mode, enter this mode. CODEC analog circuit Outputs the ISUPIP signal on line 461 via an inverter 465 E to provide a low power mode when SUSPEND # is active. Enter   After ISUSRQ # is asserted, the logic clocks to other circuits C. And wait at least 80 milliseconds before disabling the oscillator. Departure The clock signals ICLK16M and ICLK24M from the vibrators 16 and 18 have distortion and Disabled (re-enabled) so that there is no glitch. High stage Will never return to low. Oscillation after SUSPEND # is deactivated Is enabled again, but the clock signal ICLK16M is It does not toggle again until it stabilizes after 8 ms. this is, Occurs when the oscillator 16 is clocking normally at 64K time. ICL After K16 toggles at least 80 milliseconds, the ISUSPRQ # signal The assertion is released so that the logic of the circuit C can operate. All ISA Baspi Before attempting to access circuit C, the SUSPEND After the # is released, it must be delayed about 10 milliseconds. ISUSPI P (suspend in progress) is active while the internal clock is not valid. is there. I / O pin at the local memory control module for each suspend request Used to change the operation of the computer (suspend mode refresh).     10. reset.   The reset is performed by the following two methods. (1) RESET pin assertion, (2 ) I / O mapped command for reset from PNP logic (PCCCI) De. Both generate long pulses for the PCARST # signal. In addition, Synthesizer caused by writing to the USRTI Zamo There is also a reset of the Joule 6 and Gravis Ultrasound function. Also , MIDI interface controlled by bits in GMCR You.   PCARST #.PCARST # is the most memory function of the C register, Switches, flip-flops, and RAMs that return RAM bits to their default state Signal. When active, all ISA bus activity is ignored and local No memory cycle occurs. PCARST # is reset when the RESET pin is reset. Is created as a logical OR with the software reset (PCCCI) described earlier. It is. The RESET pin allows the oscillator to stabilize before PCARST # deactivates. Need to be asserted at least 10 milliseconds to make time for is there. Software reset when IC is in shutdown mode If so, PCARST # will be active and the oscillator stabilization logic will , Count for 64K state before releasing PCARST #. IC shut PCARST if software reset occurs when not in down mode # Active for 256 16.9 MHz clocks (approximately 15 milliseconds) become. While PCARST # is active, all 16.9 MHz and 24 . The 5 MHz clock is passed to other blocks in the IC. However, the previous CLOCK The various divided-down clocks shown in section S are The divide-down circuit used to generate the So don't toggle.   RESET pin dedicated function.The following items are affected by the RESET pin However, it is not affected by PCARST #. At the trailing edge of the reset The state of the I / O pin to be switched, PCSNI, PSRPAI, PSPSM [1: 0 Registers, state machines that have their own reset requirements, test controllers Roll signal (ITCI), control for oscillator stabilization logic (software Used to count out a wear reset). All other features Reset to default state.   Software reset PCCCI.Software reset is 16.9 MHz Oscillator in 256 state (shutdown in progress or ITCI [BPOS C] is active) or clocked through 64K state Keep PCARST # active while   Synthesizer RAM block.After PCARST # becomes inactive, the synthesizer IsaLogic (see below) will send all 32 voices R to clear out. Process AM blocks sequentially. This takes about 22 milliseconds.   External function interface.When PCARST # is active, pin RAS # And ROMC # become active (RAS # = ROMCS # = 0). this Is the only way such a condition can occur. When this happens, external functions For example, decoding by CD-ROM) and reset is active You can know.   B.Outline of system control PIN.   The pins shown in FIG. 28 are tied to the system bus interface .   C.Summary of system control registers.   In the following register definitions, RES or RESERVED is a reserved bit. Is specified. All such fields must be written with zeros. No. Reading will return an undefined value. Read Modify Write Opera The option can write back the value that was read.     1. P2XR direct register       a.Mix control register (UMCR). Address: P2XR = 0 read, write Default: 03h   See IVE for how this register controls access to hidden registers. See RI [HRLEN #] CRS control register selection. When URCR [2: 0] is set to 0               In this case, this bit determines the interrupt control register (UICI)               Indexing or indexing of DMA control register (UDC)               Choose a thing. 1 = UICI; 0 = UDCI. MLOOP MIDI loopback. Logic 1 converts MIDITX to MIDIRX               Cause a loop. This is the transfer of data from MIDITX.               Do not block sending. However, data via MIDIRX               Block reception. GF122 channel synthesizer interrupt. Logic 1 is (1) all thin               Selector 1 and IR with channelizer and CODEC interrupt               Perform a logical OR on the Q pin to connect to the selected channel 1 IRQ pin.               Mask the synthesizer interrupt. IQDMA IRQ and DMA enable. Logic 1 connects IRQ and DRQ pins               Enable (for audio function only, EX IRQ and EX D               The specific IRQ of the external device controlled by the RQ pin,               It does not affect the DRQ line. A logic 0 causes all IRQs and               DRQ pin goes to high impedance mode (audio function               designated). ENMIC Enable mono and stereo microphone input. Logic 0 is               And stereo microphone inputs are disabled               (No sound). ELOUT Enable line output. Logic 1 is stereo line out output               Disable (no sound). This switch is c               all enable and attenuator of the odec module               After. ENLIN Enable line input. Logic 1 decodes the stereo line-in input.               Disable (no sound). This switch is code               Before all enable and attenuator of c module       b.Sound blaster 2X6 register (U2X6R). Address: P2XR + 6write   By writing to this address, the AdLib status register (UAS RR) 2X61 RQ bits are set. At this address, data is transferred, Is not touched.       c.IRQ status register (UISR). Address: P2XR + 6read Default: 00h (after initialization)   This register specifies the cause of various interrupts. DMATC DMA terminal count IRQ. High is ISA Buster Mina The count signal TC is the result of DMA activity between system memory and local memory. The result indicates that it has become active. The flip-flop driving this bit is , LDMACI are read. Tied to the synthesizer Is logically ORed with the interrupt. When the TC interrupt is not enabled (LDMA CI [5]), even if the interrupt flip-flop is set Is read as VOLIRQ Volume loop IRQ. Logic 1 is one volume of voice               Indicates that the ramp has reached the endpoint. This bit               In the general index register (IGIDXR),               The value 8Fh for accessing the voice interrupt register SVII is written.               Cleared after being rushed. LOOIRQ Address loop IRQ. Logic 1 is local to any voice               Indicates that the memory has reached the endpoint. This bit               General index register (IGIDXR) is added to SVII.               Cleared after being written by 8Fh which is the value to be accessed               . This bit is enabled by URSTI [2] (               However, it is not cleared). ADIRQ AdLib sound register IRQ. This is a write-to               -UADR interrupt bit (high by writing to UADR)               ), Write-to-U2X6R interrupt bit               (Set by writing to U2X6R), write-               to-UI2XCR interrupt bit (write to UI2XCR               Is set by OR). Drive UADR interrupt               Flip-flop is enabled when UASBCI [1] is high.               And asynchronously cleared when UASBCI [1] is low               Is done. The other two bits are when UASBCI [5] is high               Enabled, asynchronously when UASBCI [5] is low               Cleared. ADIRQ is compatible with AdLib-Soundblaster               ORed with the associated IRQ. ADT2 AdLib timer 2. This bit indicates that AdLib timer 2 is FF               Is set when rolling to the preload value UAT2I. U               Cleared by ASBCI [3] and disabled.               The flip-flop driving this bit is an AdLib-Sound               ORed with the interrupt associated with Doblaster. Also, UA               It can be read by SRR [1]. ADT1 AdLib timer 1. This bit indicates that AdLib timer 1 is FF               Is set when rolling to the preload value UAT1I. U               Cleared by ASBCI [2] and disabled.               The flip-flop driving this bit is an AdLib-Sound               ORed with the interrupt associated with Doblaster. Also, UA               It can be read by SRR [2]. MIDIRX MIDI receive IRQ. Logic 1 indicates that the MIDI receive data register               Indicates that you have data. By reading GMRDR               Cleared. MIDITX MIDI send IRQ. Logic 1 indicates that the MIDI transmit data register               Indicates that it is empty. Cleared by writing to GMTDR               It is.       d.AdLib command read and write register (UACRR,             UACWR). Address: P2XR + OAh read (UACRR);               P2XR + 08h and 338h write (UACWR) Default: 00h   This register is used to emulate AdLib operations . This register programs the internal synthesizer and Written by AdLib application software to duplicate And read by the AdLib emulation software.       e.AdLib status read and write register (UASRR,             UAWR). Address: P2XR + 08h and 388h read (UASRR);               P2XR + 0AH write (UASWR) Default: 00h   When not in auto timer mode, this has various values for read and write addresses This is a read / write register. In auto timer mode (UASBCI [0]), Is latched but not readable. By reading As a result, the following status information is obtained. That is, OR56 OR of bits 5 and 6. This bit is the same as bit 5 of this register Represents the logical OR of bit 6. T1M Timer 1, maskable. This bit indicates that AdLib timer 1 is FF               Set high when rolling to preload value UAR1I from               . This bit is set by writing to UADR [AIRST].               Cleared. This bit is set by the AdLib timer 1 mask               Is not activated (UADR [MT1]). T2M Timer 2, maskable. This bit indicates that AdLib timer 2 is FF               Set high when rolling to preload value UAR21 from               . This bit is set by writing to UADR [AIRST].               Cleared. This bit is set by the AdLib timer 1 mask               (UADR [MT2]) does not become active               . 2XCIRQ Write to 2xC interrupt. This is the writing to UI2XCR               UI2XCR interrupt bit set high only by               Is written to. The flip-flop driving this bit is               , UASBCI [5] is high and UASG               Cleared when CI [5] is low.               2X6IRQ Write to 2x6 interrupt. This is UI2X               U2X6R percent set high by writing to CR               This is a write to the inset. Flip-flop driving this bit               Lop is enabled when UASBCI [5] is high,               Cleared when UASGCI [5] is low. T1NM Timer 1, masking not possible. This bit indicates that AdLib timer 1               Set high when rolling from FF to preload value UAT1I               It is. This bit is cleared by UASBCI [2],               Disabled. Flip-flop driving this bit               Is the interrupt associated with AdLib-SoundBlaster               ORed. It can also be read with UISR [2]. T2NM Timer 2, masking not possible. This bit indicates that AdLib timer 1               Set high when rolling from FF to preload value UART21               Is done. This bit is cleared by UASBCI [3].               , Disabled. Flip-flop driving this bit               Is an interrupt associated with the AdLib-SoundBlaster               Is ORed. It can also be read with UISR [3]. DIRQ Data IRQ. It is set high by writing to UADR.               Write-to-UADR interrupt bit.               The flip-flop driving this bit is UASBCI [1]               Is high when UASBCI [1] is low.               Cleared asynchronously. AdLib-Connect with Soundblaster               ORed with the interrupt. Read with UISR [4]               Is possible.       f.AdLib data register (UADR). Address: P2XR + 9 and 389h read, write Default: 00h   This register is based on the state of the various bits, as follows: Perform the replacement function. That is,   In case 2, the following AdLib timer emulation bits are written It is. All of these bits default to low after reset. MSB Note that if is set high, the other bits do not change. IVERI When [RRMD] is active, the following bits are UASBCI [0] or The UACWR can read from this address regardless of the state. AIRST AdLib IRQ register. If set to logic 1, UA               Flip-flip driving SRR [T1M] and UASRR [T2M]               The lop is cleared. This bit is set to UASRR [T1M].               Is automatically cleared after UASRR [T2M] is cleared               . Also, when this bit is written high,               Are not changed. This bit is written as low               Then, the other bits in this register are latched. MT1 Mask timer 1. If high, drive UASRR [T1M]               Flip-flops cannot be active. MT2 Mask timer 2. If high, drive UASRR [T2M]               Flip-flops cannot be active. STRT2 Start timer 2. When low, the value in UAT2I is 320               AdLib timer on every rising clock edge in milliseconds               2 is loaded. When high, timer is 320 ms               Is incremented at every rising clock edge. Timer               After FFh reaches FFh, at the next clock edge, UAT2I restarts.               Loaded into the timer. STRT1 Start timer 1. When low, the value in UAT2I is 80               AdLib timer 1 for every second rising clock edge               Is loaded. When high, the timer runs for 80 milliseconds.               Incremented at every Ising clock edge. Timer is F               After reaching Fh, at the next clock edge, UAT1I restarts.               Loaded to Ima.       g.GUS Hidden Register Data Port (UHRDP). Address: P2XR + OBh write   This is a port for accessing hidden registers. Note: Hidden register See IVERI [HRLEN #] for a way to restrict access to.       h.Sound blaster interrupt 2XC register (UI2XCR). Address: P2XR + 0Ch read, write Default: 00h   An interrupt is generated by writing to this simple read / write register. this Registers can also be written via U2XCR without interrupts . The interrupt is cleared by writing UASBCI [5] = 0.       i. Sound blaster 2XC register (U2XCR) Address: P2XR + 0Dh write Default: 00h (after initialization)   This is a sound blaster interrupt 2xC register that does not generate an interrupt ( UI2XCR).       j.Sound blaster register 2XE (U2XER). Address: P2XR + OEh read, write Default: 00h   This is a simple read / write registry used for sound blaster emulation It is. An I / O read of this register will interrupt (if enabled) generate.       k.Register control register (URCR). Address: P2XXR + 0Fh write, read (IVERI [R               RMD] is active) Default: 0000 0000   Note: This register is read when IVERI [RRMD] is active. Will be possible. If IVERI [RRMD] is not active, this address When read, USRR data is obtained.               Interrupt made by reading IQ2XE U2XER               Enable. When logic 1, interrupt by reading U2XER               Only occurs. This interrupt is triggered by the SoundBlaster-AdLib               It is logically ORed with the interrupt. EGPRA Enable general purpose register access. Logic 1 is               , ICMPTI [3: 0], UGPA1I, UGPA2I               Access to general-purpose registers through the address specified by               Cable.               TG2XC. 2xC toggle bit 7. Logic 1 is UI2XC               R [7] toggles each I / O read of that register. GP2IRQ General purpose register 2 interrupt. Logic 1 is ICMPT               1 [3: 2] and the address specified by UGPA2I               Read or write to general-purpose register 2               Enable interrupts to be created. Interrupt sounds               It is logically ORed with the blaster / AdLib interrupt. UHRDP,               Access to this register through the backdoor generates an interrupt               Do not live. GP1IRQ General purpose register 1 interrupt. Logic 1 is ICMPT               1 [1: 0] and the address specified by UGPA1I               Read or write to general-purpose register 2               Enable interrupts to be created. Interrupt sounds               It is logically ORed with the blaster / AdLib interrupt. UHRDP,               Access to this register through the backdoor generates an interrupt               Do not live. RS [2: 0] register selector. This field is the hidden register data port               Register accessed through writing to UHRDP               Select the data.               0 = DMA and interrupt control registers (UDCI and UICI)               1 = General purpose register 1 backdoor (UGP1I)               2 = General purpose register 2 backdoor (UGP2I)               3 = General register 1 address [7: 0] (UGPA1I)               4 = General register 2 address [7: 0] (UGPA1I)               5 = Clear IRQ (UCLR2I)               6 = Jumper register (UJMPI)       l.Read Status Register (USRR). Address: P2XR + 0Fh read Default: 01h   This register provides the status of various interrupts. Even if multiple bits are the same Even when active, all are cleared by writing to UCLRI1. It is. Note: When IVERI [RRMD] is active, the data in this register Cannot access the data. IQ2XE 2xE interrupt. Logic 1 indicates that reading U2XER               Indicates that it has occurred. IQGP2R General purpose register 2 read interrupt. Logic 1 is U               Address specified by CMPTI [3: 2] and UGPA2I               Read of general-purpose register through the interface caused an interrupt               Is shown. IQRG2W General purpose register 2 write interrupt. Logic 1 is U               The address specified by CMPTI [3: 2] and UGPA21               Read of general-purpose register through the interface caused an interrupt               Is shown. IQRG1R General purpose register 1 read interrupt. Logic 1 is U               Address specified by CMPTI [3: 2] and UGPA1I               Read of general-purpose register through the interface caused an interrupt               Is shown. IQGP1W General purpose register 1 write interrupt. Logic 1 is U               The address specified by CMPTI [1: 0] and UGPA1I               Read of general-purpose register through the interface caused an interrupt               Is shown. PURES Always read as low. Cannot write. IQDMA IRQ / DMA enable bit, UMCR [3] status               including. ENJMP Always read as high. Not writable     2. URCR [2: 0], UHRDP indexed register.       a.DMA Channel Control Register (UDCI). Address: P2XR + 0Bh read, write; indexes               To UMCr [6] = 0 and URCR [2: 0 = 0 PUD1SI               Changes the DMA1 [2: 0] field, and the PUD               Writing to 2SI changes the DMA2 [2: 0] field               . The function to change bits [5: 0] through this register is ICMPT               It can be disabled using I [4]. Note: To this register               For information on how to restrict access to               #]               See Default: 00h EXINT Extra interrupt. Both interrupt sources are UIC [6]                     Set this bit high if you are coupling through                     By the channel 2 interrupt selection bits DMA1 [2: 0]                     To drive the IRQ line selected. CMBN combine DMA channel. Logic 1 is the channel selection DM                     Combine both DMA channels using A1 [2: 0]                     You. DMA2 [2: 0] DMA selection channel 2 (codec reproduction). DMA1 [2: 0] DMA selection channel 1 (local memo from system memory                     Codec recording to re).       b.Interrupt control register (UICI). Address: P2XR + 0Bh read, write; indexes               UMCR [6:] = 1 and URCR [2: 0] = 2 PUDIS               Writing to I changes the DMA1 [2: 0] field and               Writing to UD2SI changes DMA2 [2: 0] field               I do. The function of changing bits [5: 0] through this register is               Can be disabled using CMPTI [4]. Default: 07h   Note: For information on how to restrict access to this register, see IVERI [HR LEN #]. ALSB AdLib / Soundblaster vs. NMI. Logic 1 is IO                     CHK # (NMI) will release SoundBlaster and AdLib “i                     aalsb ", the channel 1 selection bit (UICI [2:                     0]) disables the IRQ selected by                     sb. CMBN combine interrupt channel. Logic 1 is IRQ [2: 0]                     Connects both interrupt sources to the IRQ selected by                     Combine. IRQ2 [2: 0] Channel 2 (MIDI) IRQ selection:                     0 = No interrupt 4 = IRQ7                     1 = IRQ2 5 = IRQ11                     2 = IRQ5 6 = IRQ12                     3 = IRQ3 7 = IRQ15 IRQ1 [2: 1] channel 1 (codec, synthesizer, sound brass)                     Data, AdLib) IRQ selection:                     0 = IOCHK # 4 = IRQ7                     1 = IRQ2 5 = IRQ11                     2 = IRQ5 6 = IRQ12                     3 = IRQ3 7 = IRQ15       c.General Purpose Register 1 (UGPI1). Address: P2XR + 0Bh read / write;               index URCR [2: 0] = 1 Default: 00h   General purpose (general purpose) register 1 is composed of AdLib, sound blaster, Two 8-bit registers UGP1I I used for MPU-401 compatibility N and UGP1I OUT. Do not control any signals in circuit C No. This address (UHRDP) and UCMPT1 [1: 0] and UGPA1I (Emulation address) Is accessed. UGP1I IN is written via emulation address And read via UHRDP. UGP1I OUT is emulation Via UHRDP and written via UHRDP. Emulation Access to these addresses using the application address (if enabled) Generate an interrupt. Note: How to restrict access to this register See IVERI [HRLEN #].       d.General Purpose Register 2 (UGP2I). Address: P2XR + 0Bh read / write;               index URCR [2: 0] = 2 Default: 00h   General-purpose register 2 includes AdLib, Sound Blaster, MPU-40 Two 8-bit registers UGP2I IN and UGP2 used for 1 compatibility I OUT. It does not control any signals of circuit C. This ad (UHRDP) and UCMPT1 [3: 2] and UGPA2I (Emulation (Access address). UGP2I IN is written via the emulation address and UHRD Read via P. UGP2I OUT indicates the emulation address. And written via UHRDP. Emulation address Access to these addresses using a source will generate an interrupt (if enabled). Let it live. Note: See IVER for how to restrict access to this register. See I [HRLEN #].       e.General Purpose Register 1 Address (UGPA1I). Address: P2XR + 0Bh write;               index URCR [2: 0] = 2 Default: 00h   This register controls an address used for accessing the general-purpose register 1. The 8 bits written are bits [7] of the emulation address of UGP1I. : 0]. Emulation address [9: 8] is ICMPT1 [1: 0] ]. Note: How to restrict access to this register See IVERI [HRLEN #].       f.General Purpose Register 2 address (UGPA21). Address: P2XR + 0Bh read write;               index URCR [2: 0] = 4 Default: 00h   This register controls an address used for accessing the general-purpose register 2. The 8 bits written are bits [7] of the emulation address of UGP2I. : 0]. Emulation address [9: 8] is the same as ICMPT1 [3: 2]. ]. Note: How to restrict access to this register See IVERI [HRLEN #].       g.Clear interrupt register (UCLRII). Address: P2XR + 0Bh write;               index URCR [2: 0] = 5   Writing to this register clears all interrupts described in USRR. Is rearranged. Note: For information on how to restrict access to this register, see IVE See RI [HRLEN #].       h.Jumper register (UJMPI). Address: P2XR + 0Bh read, write;               index URCR [2: 0] = 6 Default: 06h   Note: For information on how to restrict access to this register, see IVERI [HR LEN #]. ENJOY Enable joystick. Logic 1 is the game at 201h               Enable port address decoding. ENMID Enable MIDI. Logic 1 makes P3XR + 0 and P3XR + 1               Enable certain MIDI address decoding.     3. P3XR direct register.       a.General index register (IGIDXR). Address: P3XR + 3 read, write Default: 00h   This register specifies the index address to various registers in circuit C I do. The data ports associated with this index are ISDP and I1 6 DP. In the case of the auto increment mode (SVSR [7]), The value of the register is written in I / O to I8DP or I16DP (I16DP (Except for writing 8 bits to a byte).       b.General 8 / 16-bit data port (I8DP, I16DP)             . Address: P3XR + 5 for 18DP, P3 for I16DP               XR + 4-5h, read, write   This is a data port for accessing various registers in circuit C . 8-bit I / O access to P3XR + 5 is used to transfer 8-bit data You. 16-bit I / O access to P3XR + 4 is for transferring 16-bit data used. Also, 8 access to P3XR + 4 with 8-bit access to P3XR + 5 16-bit data can also be transferred using bit I / O access. Oh In the case of the increment mode (SVSR [7]), the value of IGIDXR is I8 I / O write to DP or I16DP (Rover of I16DP, P3XR + 4 (Except for 8-bit writing to a byte).     4. IGIXR, 18DP-116DP, index register.       a.AdLib, sound blaster control (UASBCI). Address: P3XR + 5 read, write;               index IGIDXR = 45h Default: 00h   This register controls the AdLib and Soundblaster compatible hardware Used for SBIEN Sound blaster interrupt enable. U2X6R or UI2               Enable interrupts for writing to XCR. logic               When set to 1, interrupts are enabled. Logical 0               When set to, interrupts are disabled and asynchronous               Is cleared. ETTST Enable timer test. Logic 1 controls AdLib timers 1 and 2               Enable the high-speed clock to operate. Logic 0 is               Enable the normal clock to operate the timer. high speed               The clock is 0.9961 which is 16.9344 MHz divided by 17.               4 MHz. EIRQT2 Enable timer 2 interrupt. Logic 1 is the AdLib timer               Enable the interrupt associated with 2. Logical 0 is divided               Disables and clears asynchronously. EIRQT1 Enable timer 1 interrupt. Logic 1 is the AdLib timer               Enable the interrupt associated with 1. Logical 0 is divided               Disables and clears asynchronously. EDIRQ enable data interrupt. Logic 1 is the AdLib data register               Enables interrupts generated from writing to the UADR               To A logic 0 disables this interrupt and               Clear ATOFF Disable auto timer mode. This low bit is               To auto timer mode. This high bit is               Disable mode. For the auto timer mode,               Auto timer mode and UASRR, U of system control module               See the description of ASWR and UADR registers.       b.AdLib timer 1 (UAT1I). Address: P3XR + 5 read, write;               index IGIDXR = 46h Default: 00h   Timer 1 load value. It is loaded into AdLib timer 1 when: Value. (1) UADR [STRT1] is high and this timer is set to 0FF is incremented beyond h. Or (2) UADR [STRT1] is low The rising clock edge of this timer is 80 microsecond clock. (16.9344 MHz divided by 1344). This register Reading gives the preload value, not the actual state of the timer.       c.AdLib timer 2 (UAT21). Address: P3XR + 5 read, write;               index IGIDXR = 47h Default: 00h   Timer 2 load value. It is loaded into AdLib timer 2 when: Value. (1) UADR [STRT2] is high and this timer is set to 0FF is incremented beyond h. Or (2) UADR [STRT2] is low And the rising clock error of the 320 microsecond clock of this timer. (The clock of timer 1 divided by 4). Reading this register By taking, the preload value is obtained instead of the actual state of the timer.       d.GF-1 reset register (URST1). Address: P3XR + 5 read, write;             index IGIDXXR = 4Ch Default: XXXX X000 DMIE synthesizer interrupt enable. This high bit is               Isa loop and volume interrupt (UISR [6: 5])               Navel. Disabling interrupts with this bit               , The interrupt is not cleared. DACEN D / A conversion enable. This high bit is the synthesizer DAC               Enable. This low bit is used by the synthesizer DAC.               Reduce output. RGF1 reset GF-1. This low bit is used for multiple MIDI and synth               Reset the sizer and GUS compatible registers. The following are               Is reset by this bit. Writing to U2X6R and concluding               Interrupts associated with writing to UI2XCR               Interrupts, D to local memory (including IOCHRDY)               MA or I / O read / write, LDMACI, LMCI [1: 0]               , LMFSI, LDICI, SGMI [ENH], TC interrupt               Flip-flop (IDMATC), URST1 [2: 1], U               ASBCI, UADR [AIRST, MT1, MT2, STRT               , UA associated with writing to [2, STRT1]               SRR [T1M, T2M, 2XCIRQ, 2X6IRQ, T1N               M, T2NM, DIRQ], MID               All memory elements of I UART and associated logic. Also,               Is low, all synthesizer IRQs are cleared               The operation of the state machine of the synthesizer stops. Stay frozen               , No sound is created. This bit is set by software.               Fully controlled. Note: This bit is used in the synthesizer register               Hardware and software to ensure that the array initializes properly               At least 22 milliseconds after the reset is completed               Must be up to.       e.Compatibility register (ICMPT1). Address: P3XR + 5 read, write;               index IGIDR = 59h Default: 0001 1111 STM [2: 0] Serial transfer mode. This is the codec module serial                   Specify the transfer mode. This block is a codec model                   Fully specified in joules. When STM [2] is high,                   The four external function (CD-ROM) pins are switched,                   Becomes a serial port pin. Possible modes are:                   It is. That is,   OPEN compatibility enable. When high, this is UDCI [5                       : 0] and writing to UICI [5: 0] are allowed.                       Indicates that Not allowed when low. This bit                       PUD1SI, regardless of the state of CPEN,                       Writing to PUD2SI, PUI1SI, PUI2SI                       It can be changed by just looking. GPR2A [9: 8] General purpose register 2 address [9: 8]. This                       This is the ISA address of the relocatable register UGPA21.                       Specify less bits [9: 8]. GPR1A [9: 8] General purpose register 1 address [9: 8]. This                       This is the ISA address of the relocatable register UGPA1I.                       Designate dress bits [9: 8].       f.Decode control register (IDECI). Address: P3XR + 5 read, write;               index IGIDXR = 5AH Default: 7Fh   This register enables / disables decoding of various address spaces. Cable. IAC22 Codec interrupt for channel 2. When high, c             The interrupt associated with the odec is the channel 1 IRQ pin.             But not on the channel 2 IRQ pin. For low, this             Occurs in channel 1. EICH1 Interrupt on enable channel 1. If high, split channel 10             Is enabled. If low, the selected channel 1 IR             The Q output becomes high impedance. EICH2 Interrupt on enable channel 2. If high, channel divided by 20             Is enabled. If low, selected channel 2 IR             The Q output becomes high impedance. EINMI Enable NMI interrupt. If high, IOCHK # interrupt             Be enabled. If low, IOCHK # is high impedance             Become ECOD Codec decode enable. If high, PCODAR 4             I / O read / write to codec address space             Become a navel. When low, decoding of these addresses is disabled.             Become sable. E3889 Decode enable for 388h and 389h. AdL if high             ib command-status and fixed add of data registers-388, 389             Less is enabled. If low, decoup these addresses             The code is disabled. EEDC 2xE, 2xD, 2xC decode enable. If high, P2             Reading and writing to XR + Eh, P2XR + Dh, P2XR + Ch is rice             Table. When low, decoding of these addresses is disabled.             Be able to. EA98 2xA, 2x9, 2x8 decode enable. If high, P2             Reading and writing to XR + Ah, P2XR + 9h and P2XR + 8h are rice             Table. When low, decoding of these addresses is disabled.             Be able to.       g.Version number register (IVERI). Address: P3XR + 5 read, write;               index IGIDXR = 5Bh Default: 0000 0100 VER version number. This includes the die version number. for example               For example, 0h = rev A Silicon. This field is read               designated. RRMD register read mode. When high, this bit               Three reads of a normally unreadable register result in this               Specifies that the data written to the register is returned. UADR               By reading (P2XR + 9,389h), UASBCI [0]               Or the bit [AIRST regardless of the state of the UACWR               , MT1, MT2, 0, 0, 0, STRT2, STRT1] are returned.               Is done. By reading URCR (P2XR + Fh), USR               Returns the last data written to that address, not R               . By reading GMCR (P3XR + 0), it is not GMSR.               The last data written to the address is returned. PUPWR Pull-up power. This low bit corresponds to the signal IOCS16 #, I               RQ [15.12, 11, 7, 5], SA [11: 6], SBH               E #, DRQ [7: 5,3], DAK [7: 5,3] #, SD [               15: 8] Disable power to internal pull-up resistor               , These signals drive voltage to ISA bus in suspend mode               In general, do not add a current load. This               The high bit enables all pull-up resistors on these signals to               Cable. Normally, this bit is high for 120-pin parts.               , And is set low for 160-pin parts. M401 MPU-410 emulation mode. This high bit is               Enable the following: (1) MIDI send / receive register (G               MTDR, GMRDR) moved from P3XR + 1 to P3XR + 0               And the MIDI control status registers (GMCR, G               MSR) is moved from P3XR + 0 to P3XR + 1. HRLEN # Hidden register lock enable. If high (inactive), U               Access to registers in HRDP is always enabled               . When low (active state), access to a register in UHRDP is               Process must comply with the protocol. The protocol is               Enable next I / O access to hidden registers in UHRDP               Initialized by writing to the UMCR. (AE               P2XR + 0 (UMCR) or P2XR + (when N is low)               I / O read to address except 0Bh (UHRDP) or               Write locks subsequent I / O access to hidden registers.               Go out.       b.MPU-401 emulation control A (IEMUAI). Address: P3XR + 5 read, write,               index IGIDXR = 5Ch Default: 00h   The emulation address described in the previous bit definition is UGPA1I, UGPA1I PA21, an address specified by ICMPT9I [3: 1]. URRE # UART receive buffer read enable. If low, UART             Of the received data buffer GMRDR is permitted. High Place             Read from that buffer is internally ignored (but             The ISA data bus is driven). USRE # UART status read enable. If low, UART stay             Reading of the status register GMSR is permitted. If high, the ba             Reading from the buffer is ignored internally (but ISA data             Ta             The bus is being driven). E2RE # Emulation register 2 read enable. For low, Emi             Emulation register 2 UG using the emulation address             P2I reading is allowed. Emulation add if high             Reading of UGP2I using a host is ignored internally (but             , ISA data bus is driven). E1RE # Emulation register 1 read enable. For low, Emi             Emulation register 1 UG using the emulation address             Reading of P1I is allowed. Emulation add if high             Reading of UGP1I using the address is ignored internally (but             , ISA data bus is driven). UTWE # UART transfer buffer write enable. MIDI if low             Read of UART transmit buffer GMTDR is allowed             You. If high, writing to the buffer is disabled by the UART.             Is seen. UCWE # UART command buffer write enable. If low, MI             Writing to the command register GMCR of DI UART is permitted.             You. If high, writing to that register is disabled by the UART.             Is seen. E2WE # Emulation register 2 write enable. If low, d             Emulation register 2 U using emulation address             Writing to GP2I is allowed. If high, UGP2I             It does not change when writing to the simulation address. E1WE # Emulation register 1 write enable. For low,             Emulation register 1 using emulation address             Writing to UGP1I is allowed. If high, UGP1I             It does not change when writing to the emulation address.       i.MPU-401 emulation control B (IEMUBI). Address: P3XR + 5 read, write;               index IGIDXR = 5Dh Default: 30h MRXE # MIDI receive data enable. For low, the MIDIRX pin               k received MIDI data is permitted and passed to the UART. High Place               If so, data cannot enter the UART. MTXE # MIDI transfer data enable. If low, M from UART               IDI transfer (transmit) data is allowed and the MIDITX               Cross over. When high, data cannot exit the pin.               No. SLSE7 I / O read selection state emulation register 1 bit               [7]. The circuit C is emulated by this high bit.               Dress ([ICMPTI [1: 0] and UGPA1I [7: 0])               UGP to the data bus when reading IGP1IOUT via               Enable 1IOUT [7]. With this low bit,               The circuit C reads the DSR # on the BIT [79] of the data bus during reading.               Enable. DSR # reads UGP2IOUT               Is enabled (IEMUAI [5]), the emulation               Via the application address ([ICMPTI [3: 2], UGPA21)               When there is a read UGP2IOUT read, the DSR #               Is set to an inactive state (high) by hardware. this               The flag indicates UGP1IOUT [via the backdoor (UHRDP).               7]. SLSE6 I / O read selection state emulation register 1 bit               [6]. The circuit C is emulated by this high bit.               Dress (ICMPTI [1: 0], UGPA1I [7: 0])               UGP1 to the data bus when reading UGP1IOUT via               Enable IOUT [6]. This low bit allows               The path C inputs the DRR # to BIT [6] of the data bus at the time of reading.               Navel. DRR # indicates that writing to that register is rice               Emulation (IEMUAI [1: 0])               Address ([ICMPTI [3: 0], UGPA1I, UGP               Writing to UGP1IIN or UGP2IIN via A2I)               DRR # is inactive by hardware when               Sexual state (high). This flag indicates that the backdoor (UH               By writing to UGP1IOUT [6] via RDP)               Is also controlled. E2WIE # Emulation register 2 write interrupt enable. Low               Case, ICMPT1 [3: 2] and UGPA for UGP2I               By writing to the address selected by 1I [7: 0]               An interrupt occurs. If high, write to UGP2I               No interrupt is generated. E1WIE # Emulation register 1 write interrupt enable. Low               Case, ICMPT1 [1: 0] and UGPA for UGP1I               By writing to the address selected by 1I [7: 0]               An interrupt occurs. If high, write to UGP1I               No interrupt is generated. E2RIE # Emulation register 2 read interrupt enable. Low               Case, ICMPT [3: 2] and UGPA1 for UGP2I               Split by reading the address selected by I [7: 0]               Jam occurs. If high, split by reading UGP2I               No intrusion occurs. E1RIE # Emulation register 1 read interrupt enable. Low               Case, ICMPT [1: 0] and UGPA1 for UGP1I               Split by reading the address selected by I [7: 0]               Jam occurs. If high, split by reading UGP1I               No intrusion occurs.       j.Test control register (ITCI). Address: P3XR + 5 read, write; index IGI               DXR = 5Fh; In external decoding mode, this register               Data can be read directly (for external decoding mode).               See the register summary for details.) Default: 000 0000b; For BIT [7] default,               See TE below.   Access to this register is controlled by the MIDIT It can be disabled depending on the state of X. See Pinsa for more information. See Marie. Also, any bits of this register are Not reset by CCI. Reset only after activating the RESET pin Can be TE test enable. This high bit indicates that the device                   This indicates that the system is in the card state. If low, the device is                   , In the normal operation mode. The default state of this bit is                   , Trailing edge of reset depending on the state of MWE # pin                   Latched. TE is high if MWE # is low                   . When MWE # is high, TE is low. This bit                   , Reset by software reset (PCCCI)                   Not done. BPOSC Bypass oscillator stabilization circuit. 16.9 MHz from high                   Oscillator clock counter to ensure that the shaker is stable                   The oscillator stabilization circuit that is in charge of the                   Only count. When low, the oscillator stabilization logic                   , 64k are counted out. This bit is RES                   Reset by the ET pin. Software reset (                   PCCCI). TMS [5: 0] Select test mode. This bit is used for various circuit test modes.                   Used to select This bit is the RESET pin                   Reset by Software reset (PCCC                   Not set by I).     5. PNP direct register.       a.Card selection number backdoor (PCSNBR). Address: 0201h write Default: 00h   Circuit C is PNP (latched by the state of PNPCS at the end of reset) When in the system mode, the AUDIO logical device is not activated. (PUACTI [0] = 0), PNP state machine is in isolation mode , The card selection number (CSN) is written to the circuit C through this I / O port. You can get in.       b.PNP index address register (PIDXR). Address: 0279h write Default: 00h   This is an 8-bit index pointing to a standard Plug-n-Play register. Register.       c.PNP data write port (PNPWRP). Address: 0A79h write   This is the Plug-n-Play indexed by PIDXR. Used for writing to the ISA register.       d.PNP data read port (PNPRDP). Address: The address is a relocatable read-only address between 003h and 3FFh.               It is for. For the address, (1) Write 00h to the PIDXR register.               And (2) PNPWRT through 2               Set by writing the byte representing nine. Bit 0 and               Both bits 1 are assumed to be high (11).   This is the Plug-n-Play indexed by PIDXR. Used to read from registers.     6. PIDXR, PNPWRP-PNPRDP PNP index drain Jista.   This PNP register is indexed by PIDXR, PNPRDP And accessed using PNWRP. Many registrations after PIDXR = 30h Data is further indexed by a logical device number register (PLDNI). Is done. All of these registers are available when the PNP state machine is in the Configure state. Access.       a.PNP set read data port address register (PSRPA) I). Address: 0A79H write; index PIDXR = 0 Default: 00h   By writing to this register, the PNP read data port (PNPRD) SA [9: 2] of the address P) is set. Think SA [1: 0] is high Is defined. When writing to this register, the PNP state machine This is only allowed if the mode is optional.       b.PNP isolate command register (PISOCI).   Address: PNPRDP read; index PIDXR = 1   By reading this register, the circuit C becomes the PNP serial EEPROM 78 A specific value is driven on the ISA bus 156 based on the data read from the Return the data to circuit C to see if it is. As a result, loose loose The PNP state machine enters a sleep mode. Circuit C PNP system mode (see Power-up PNP mode selection section) In this case, the serial EEPROM 78 is not present, and reading from this register It is assumed that the data is not being driven onto the bus due to data transfer. PNP system In the case of the mode, the reading of the PISOCI causes the circuit C to reduce the isolation. "Lost", enter sleep mode. Reading from this register is the PNP state Permitted only when the machine is in isolation.       c.PNP Configuration Control Command Register (PCCCI). Address: 0A79h write; index PIDXR = 2 RCSN Reset CSN PNP state machine sleep, isolate             Or in configuration mode, a high on this bit             N is set to zero. This command is used when the PNP state machine is             -Ignored when in wait mode, but enabled in other three modes             It is effective. WFK Wait For key When this bit is high, the PNP state is set.             The machine enters the key waiting mode. This command sets the PNP status             Ignored if the scene is in key wait mode, but the other three             Valid in mode. RESET Driving this pin high resets circuit C. This allows             On a general-purpose reset line, a 3 to 10 millisecond             Luss occurs. This command causes the device to             (PNP Set Read Data Port), PCSN             I (PNP Card Select Number), PNP             Only the state machine. This command is used when the PNP state machine             Ignored when in key wait mode, but in the other three modes             It is valid.       d.PNP WAKE [CSN] Command Register (PWAKEI). Address: 0A79h write; index PIDXR = 3   Writing to this register depends on the status of the CSN register and the data to be written. On the PNP state machine. Data is 00h and CSN is 00 If h, the PNP state machine enters the isolation mode. data Is not 00h and the CSN matches the data, the PNP state machine Enters the configuration state. If data does not match CSN, PNP state machine Enters sleep mode. This command also sets the address to that part. Reset the included serial EEPROM 78 control logic. This Is ignored if the PNP state machine is in key wait mode, , And is effective in the other three modes.       e.PNP Resource Data Re lister (PRE SDI). Address: PNPRDP read; index PIDXR = 4 Default: 00h   This register stores the local data read from the PNP serial EEPROM 78. It provides data for the memory control module 8 (LMC). Note: Serial EEPROM 78 is in direct control mode (PSEENI [0]) If it is, wake command before accessing with PRESDI. Have to do it. This command changes the PNP state machine to the configuration state. Only valid if       f.PNP Resource Status Register (P RESSI). Address: PNPRDP read; index PIDXR = 5 Default: 00h   When bit 1 of this register is high, the next PNP resource data Can read bits. All other bits are reserved. PR When ESDI is read, this bit is cleared until the next byte is available. Is done. This command is only valid when the PNP state machine is in the configured state. You.       g.PNP Card Select Number Register r (PCSNI). Address: 0A79h write; PNPRDP read;               index PIDXR = 6 Default: 00h   Write to this register when the PNP state machine is in the isolation state. The CSN of circuit C is set and changes the PNP state machine to configuration mode . This register is read-only when the PNP state machine is in configuration mode. You.       h.PNP Logical Device Number Regi ster (PLDNI).   Address: 0A79h write, PNPRDP read;                 index PIDXR = 7   Default: 00h   This register indexes the PNP address space to the logical device I do. The circuit C has the following two logical device numbers (LDN). 00 h = all AUDIO functions, synthesizer, codec, port; 01h = out (CD-ROM) interface. This register contains the PNP state machine. It can be accessed only when it is in a mature state.       i.PNP Audio Activate Register (PU ACTI) .   Address: 0A79h write, PNPRDP read;                 indexes PIDXR = 30h and PLDNI = 0   Default: 00h   When bit 0 of this register is high, all AUDIO functions are activated. It is. All other bits are reserved. If low, the AUDIO function Dress space is not decoded and interrupts and DMA channels are enabled. No.       j.PNP Audio I / O Range Check Regi ster (PURCI). Address: 0A79h write, PNPRDP read;               indexes PIDXR = 31h and PLDNI = 0 Default: 00h RCEN Range Clock Enable This bit is high.             And read all AUDIO logical device address spaces             Drives either 55 or AA based on the state of H5LA.             Be moved. This is because PUACTI [0] is not set (O             Only works if the audio device is not activated). H5LA High 55-Low AA RCEN is active             , This bit is the data value returned on the ISA data bus when reading             Select The high indicates that 55h is driven, and the low is AAh.             To be moved. Note: This register is used for external decoding.             Cannot be used in blog mode.       k.PNP Address Control Registers.   The following table describes all the controls for the addresses of blocks of I / O space in circuit C. All PNP registers are shown.   Note: There are three indices that control P2XR equally. This is a P2XR Supports non-contiguous addresses for locks. First index P2X0 [H , L] I are used for P2XR only.   All unused bits in the previous PNP address control register are reserved It is. All PNP address control registers are written using 0A79h And read using PNPRDP. P2XR, P3XR, PCODA It is assumed that all unspecified LSBs of R, PCDRAR are zero. various For functions controlled by a special address block, see General See the description section.       l.PNP Audio IRQ Channel 1 Select Register (PUI1SI). Address: 0A79h write, PNPRDP read;               indexes PIDXR = 70h and PLDNI = 0 Default: 00h   Bits [3: 0] select the IRQ number of the channel 1 interrupt as follows I do.   Bits [7: 4] are reserved. By writing to this register appropriately Therefore, UICI [2: 0] changes.       m.PNP Audio IRQ Channel 1 Type R register (PUI1TI). Address: PNPRDP read;               indexes PIDXR = 71h and PLDNI = 0 Default: 02h   This register describes the type of interrupt supported by circuit C. The data back to standard PNP software. Edge trigger, active It is read back as 02h indicating a high-high interrupt.       n.PNP Audio IRQ Channel 2 Select Register (P (UI2SI). Address: 0A79h write; PNPRDP read;               indexes PIDXR = 72h and PLDNI = 0 Default: 00h   Bits [3: 0] select the channel 2 interrupt IRQ number as follows: You.   Bits [7: 4] are reserved. By writing to this register appropriately And UICI [5: 3] changes.       o.PNP Audio IRQ Channel 2 Type R register (PUI2TI). Address: PNPRDP read;               indexes PIDXR = 73h and PLDNI = 0 Default: 02h   This register describes the type of interrupt supported by circuit C. The data back to standard PNP software. Edge trigger, active It is read back as 02h indicating a high-high interrupt.       p.PNP Audio DMA Channel Select R registers (PUDISI, PUD2SI). Address: 0A79h write; PNPRDP read;               indexes PIDXR = 74h (PUDISI),               PIDXR = 75h (PUD2SI) and PLDNI = 0 Default: 04h   Bits [2: 0] of these registers are used for channel 1 and channel Select the DMA request number of rule 2.   Bits [7: 3] are reserved. By writing to this register appropriately And UICI [5: 0] changes.       q.PNP Serial EEPROM Enable (PSEEN I). Address: 0A79h write; PNPRDP read;               index PIDXR = F0h and PLDNI = 0 Default: 00h   This register is accessible only when the PNP state machine is in the configuration state. You. ISADR ISA-Data-Bus Drive. This is ISA data               Bus output low drive function Iol, SD [15: 0], IOC               HRDY, IOCS16 # and IOCHK # are specified. At 5V               , 00 = 24 mA, 01 = 12 mA, 10 = 3 mA, 11 = re               serviced. At 3.3V, drive is ISADR =               00, 01, and 10 are at least 3 mA. SEM Serial EEPROM Mode. Low is serial EE               Specifies that the PROM interface circuit is in initialization mode               You. In this mode, data transfer is controlled by the PNP state machine.               Controlled. High indicates that the serial EEPROM 78 is directly PSE               Specifies the control mode controlled by the CI.       r.PNP Serial EEPROM Control (PSECI). Address: 0A79h write; PNPRDP read;               index PIDXR = F1h and PLDNI = 0 Default: XXXX 000X   In the control mode (PSEENI [0]), when PUACTI is inactive, Used to directly control serial EEPROM 78 using bits [3: 0] It is. Bits [7: 4] are the various latched on the trailing edge of RESET. This is a read-only status bit that indicates the status of the control signal. , See the Pin Summary above). This register contains the PNP state machine But Accessible only when in configuration state. SUS32 SUSPEND-C32KHZ Select. RESET               Internal signal latched on RA [21] pin at trailing edge               Provides the status of IPSUS32. XDEC External Decode Select. RESET               Internal signal latched on RA [20] pin at trailing edge               Provides the status of IPPNPSYS. VCC VCC is 5 volts. Provides the status of the internal 5V-3V detection circuit               I do. High at 5V, low at 3.3V. SECS Serial EEPROM Chip Select. this               Writing to a bit is reflected on the PNPCS pin. reading               As a result, a latched value is obtained. SESK Serial EEPROM Serial Clock. this               Writing to the bit is reflected on the MD [2] pin. reading               As a result, a latched value is obtained. SEDI Serial EEPROM Data IN. To this bit               The write is reflected on the MD [1] pin. By reading,               The value that was touched is obtained. SEDO Serial EEPROM Data Out. This bit               It will be ignored. By reading, the state of the MD [0] pin is known.       s.PNP Power Mode (PPWRI). Address: 0A79h write; PNPRDP read;               index PIDXR = F2h and PLDNI = 0 Default: X111 1111   This register disables the clock for the main section of circuit C, and Used to enable power mode. Writing to this register is This is done in a different way. ENAB which is the MSB of data is 1 or 0 Used to specify whether to write the offset. For bits [6: 0], high is , ENAB indicates that a bit is written to a bit, and a low Indicates that you want to keep. Therefore, a subset of bits [6: 0] need to be modified When there is, the software must first determine the state of the bits that do not change. No need to read registers. For example, setting bit [0] high To write, 81h must be written and bit [4] is cleared low Needs to write 10h.   Clear bits [6: 1] to low state (0111 111X I / O write When one command is received, the circuit C operates in the shutdown mode. Mode, the 16.9 MHz oscillator 16 is disabled. Hereafter, bit [ 6: 1] is set high, the 16.9 MHz oscillator 16 Re-enabled. After being re-enabled, the 16.9 MHz clock Requires 4-8 milliseconds to stabilize.   This register is accessible only when the PNP state machine is in the configuration state. You. ENAB Enable. Specify the value to be written to bits [6: 0] of the register.             Used to determine (see above). In all seven cases, c             A indicates that the block is operating, and a low indicates low-power mode.             Indicates that there is. PWR24 24.576 MHz Oscillator Enable. This             24.576 MHz oscillator 18 is stopped by the bit low of             It is. When CPDFI [0] or CRDFI [0] is low             It is not recommended to disable the oscillator at this time. But C             Regardless of the state of PDFI [0] and CRDFI [0],             Setting this bit low as part of a             No problem. PWRL Local Memory Control Enable. this             The bit low is 16 bits to the local memory control module 8.             . Disable 9Mhz clock, C32KHZ input 72             Slow refresh cycle to local DRAM 110 using             forgive. PWRS Synthesizer Enable. This bit row is             Disable 16.9 MHz clock to the synthesizer module 6             To the synthesizer DAC input to the codec mixer.             Disable lock (for this application             , See description of synthesizer and DAC input). PWRG Game-MIDI Ports Enables. This bit             Low disables all clocks to port module 10.             And the internal and external resistances of the current consumption are disabled. PWRCP Codec Playback Path Enable. this             Bit low is used for playback FIFO, format conversion,             Clocking to codec playback path, including             Disable the lock. PWRCR Codec Record Path Enable. This bit             Rows are record FIFO, format conversion, filtering,             Disable clock to codec record path, including ADC             Bull. PWRCA Codec Analog Circuit Enable.             This bit low disables all codec analog circuits.             To low power mode. If low, all analog             -MIC [L, R], AUX1 [L, R], AUX2 [L,             R], LINEIN [L, R], MONOIN, LINEO             UT [L, R], MONOOUT, CFILT, IREF-             Goes into a high impedance state.       t.PNP CD-ROM Activate Register (P RACTI). Address: 0A79h write; PNPRDP read;               index PIDXR = 30h and PLDNI = 1 Default: 00h   When bit 0 of this register is high, the external interface (eg, C The D-ROM function is activated. All other bits are reserved. Low In this case, the external function (CD-ROM) address space is not decoded. Outside If function (eg CD-ROM) interrupts and DMA channels are enabled Absent.       u.PNP CD-ROM I / O Ranges Check Re gister (PRRCI). Address: 0A79h write; PNPRDP read;               index PIDXR = 31h and PLDNI = 1 Default: 00h RCEN Range Check Enable. With this bit high,             All external function address space reads are in H5LA state             55 or AA is driven based on. This is PRA             CTI [0] is not set (external device is activated             Only works when no). H5LA High 55-Low AA. When RCEN is active,             Bits select the data value to be read back. High drives 55h             To be activated, low specifies that AAh is to be activated.       v.PNP CD-ROM High, Low Address R register (PRAHI, PARAI).   See the previous PNP address control register.       w.PNP CD-ROM IRQ Select Register (PRISI). Address: 0A79h write; PNPRDP read;               indexes PIDXR = 70h and PLDNI = 1 Default: 00h   Bits [3: 9] indicate the IRQ number of the external function (CD-ROM) interrupt below. Choose like. That is,   Bits [7: 4] are reserved.       x.PNP CD-ROM IRQ Type Reister (PR ITI). Address: PNPRDP read;               indexes PIDXR = 71h and PLDNI = 1 Default: 02h   This register contains the interrupt type supported by circuit C. Return data to standard PNP software. Always have an edge trigger, active It is read back as 02h indicating an interrupt.       y.PNP CD-ROM DMA Select Register (PRDSI). Address: 0a79h write, PNPRDP read;               indexes PIDXR = 74h and PLDNI = 1 Default: 04h   Bits [2: 0] of this register correspond to the external function (CD-ROM) as follows. ) Is selected. That is, Bits [7: 3] are reserved. IV. CODEC module   FIG. 44 shows a block diagram of various functions and features included in the CODEC module device 505. It is shown in diagram format. The CODEC 505 has 16 samples, 32 Bit length ON-CHIP memory, record and playback FIFO, 538, 532, data read and write Configurable thresholds that can generate DMA and I / O interrupts for embedded operations include. Mixing and Analog Functions block 510 has left and right channels Includes analog mixing, multiplexing, and loopback functions. Left and right channel stereo, single channel mono, and analog audio signal It is summarized in Mixing and Analog Functions block 510. With these things Stereo audio signal from CODEC 505 to Analog Output Pins 522 for external use Is output. The input to the Mixing and Analog Functions block 510 is  Input Pins 520, Synthesizer Digital-to Analog Converter block 512 Analog output (this is a processing block outside the CODEC 505 or inside the CODEC 505 It consists of it and a playback Digital-to-Analog Converter 514. Analog audio output from Mixing and Analog Functions block 510 is recorded Analog Passed to -to-Digital Converter block 516. Synth Digital-to Analog Conv The erter block 512 receives digital data from the Synthesizer 524. This manual The Synthesizer 524 is either an external device or the same monolithic as the CODEC device 505. It may be integrated on the IC.   The recording path for CODEC 505 is depicted in FIG. Analog audio data is Mixi ng and Analog Functions Block 510, and output and record Analog-to-Digital Co The data is passed to an nverter (ADC) block 516 and converted into 16-bit signed data. The sample rate specified for the recording ADC 516 depends on the sample rate for the recording ADC 516. The higher the level, the higher the quality of the recorded digital audio signal. Affects sound quality, such as getting closer. Fourth Order Cascaded Sigma- The functions and operations of the Delta Modulator are illustratively implemented in the recording ADC 516. And described in Application No. 08 / 071,091, dated 12/21/93, "Fourth Order Casc aded Sigma-Delta Modulator ″. It is specified in assignee. The converted digital audio data is then Sent to the Format Conversion block 536 where the 16-bit digital audio data Is converted to a data format specified in advance. Formatted data The digital data is then 16 bit left channel data and 16 bit right channel The data is sent to the 32-bit record FIFO 538 as data. These are further external systems Register Bus526 for output to system memory, or Off-Chip Local Memory R Handed over to ecord FIFO 530 (LMRF).   The playback path for the CODEC 505 includes a digital Data, which is stored in the Off-Chip Local Memory Playback FIFO (LM PF) From Block 528 or external memory, via Register Data Bus 526, It is sent to the playback FIFO 532 of bit length. In this application, LMRF530 and LMPF 528 is a discrete Off-Chip FIFO or Off-Chip Loc configured as FIFO It is assumed to be a dedicated address space in al Memory110. Formatted data The data is then input to the Format Conversion block 534, where the 16-bit Converted to signed data. The converted data is then used by the CODEC playback DAC 514. , Where it is converted to an analog audio signal and mixed and analog functions Output to block 510.   Serial Transfer Control block 540 includes serial to parallel and parallel to serial Conversion function, 32-bit record FIFO 538 output and 32-bit playback FIFO532 And a loopback function between the input to the input. Also, Synthesizer Seri al Input Data Port 542 (Figure 44) receives serial data from Synthesizer 524 And communicate with the Serial Transfer Control block 540. Serial Transfer Contro l Block 540 is via recording FIFO 538, P playback FIFO 532, Local Memory Control 790 Off-Chip Local Memory 110 (or LMRF530 and LMPF), Synthesizer Serial In Connect to put Data Port542 and External Serial Interface. External Serial Interface544 has an external serial port through which bidirectional serial Data communication is provided to Serial Transfer Control block 540 (FIG. 49). Exte The rnal Serial Interface 544 may be a UART or a synchronously or asynchronously controlled system. Other devices that provide real data transfer may be used. External Serial Interfac e544 (Figure 44) is out for off-chip generation of special audio effects Some digital signal processors (DSPs) or bidirectional serial data communication It can be connected for serial communication with other devices that can. Also, External Ser ial Interface 544 is serial data from the External Synthesizer Serial Input Port 542. Data path. In addition, bidirectional data transfer is performed using the Serial Transfer Control This can also be done via the data path between l540 and Local Memory Control 790. Wear.   Various loopback and data conversion functions related to Serial Transfer Control 540 Are shown in more detail in FIGS. 49 and 49a.   The CODEC 505 has an A / D (analog / digital) conversion function in the recording path, Includes a D / A (digital / analog) conversion function. These conversion functions A / D and D / A operations can be performed simultaneously at different sample rates It can operate independently and has different sample rates and data formats. Have The loop access circuit (in the Mixing block 606) Sample the voice signal, perform A / D operations at one rate, digitize the signal, Then play the samples digitized by playback D / A at different sample rates It has a function that can be played.   Counters, Timers and Miscellaneous Digital Functions518 with block specification Has A / D and D / A conversion of CODEC 505, format conversion blocks 532, 536, and A circuit for controlling the data transfer function is included. In CODEC505 operation, Data format is possible. That is, 8-bit unsigned linear, 8-bit Μ-law, 8-bit A-low, 16-bit signed little endian, 16-bit signed Big endian, or 4-bit 4: 1 IMAADPCM format.   Figure 45 shows the CODEC analog mixer 60 of the Mixing and Analog Functions block 510. Six left channels are depicted. The layout of the right channel of mixer606 is the left channel. Same as channel, but not shown in FIG. Minor signal name correction With the exception of, all descriptions of left channel signals and functions are also apply.   CODEC analog mixer 606 is more programmable than previous CODEC audio devices It has various features and functions. Five input lines to analog mixer 606 in Figure 45 (LTNFINL682, MICL684, AUXIL686, AUX2688, and MONOIN690) And programmable attenuation / amplification control circuits 608, 610, 612, 614 and 696 respectively. It is rare. All inputs and outputs to analog mixer 606 are stereo signals You. However, only the input MONOIN690 and the output MONOOUT668 are mono signals. Also, It is possible to specify whether the audio signal is mono or stereo, input or output.   The triangle block in FIG. 45 shows a programmable attenuation / amplification control circuit. Control each attenuation / amplification control circuit and the attenuation / amplification range for that circuit The registers are shown next to each triangle block in FIG. It is in the er block 566. The description and location of each of these registers is given below. It is on the street. The individual bits in these registers are described in the ″ Method and Apparatus for  Modifying the Contents of a Register via a Command Bit ″ As described in application Ser. No. 08 / 171,313 of U.S. Pat. This includes Describes how to operate on a single bit without specifying the entire register, It is specified in the common assignee of the present invention and is hereby incorporated for all purposes. Have been included.   The range of attenuation values for these registers is shown in FIG. 45a. each The value stored in the attenuation / amplification control register can be found in Counters, Timers and Misc. Digit al Function block 518 and the Gain / Attenuation block described below. In the CODEC control logic in step 734 (Fig. 47), the specified amplification value or attenuation value is Used to supply. Analog audio signal input to each attenuation / amplification circuit Force amplitude is controlled by the value stored in each attenuation / amplification control register. Is controlled.   A summary of the registers used in CODEC505Register block 566 and their desired The new features are as follows: CODEC505 is CS4231 (modes 1 and 2) and AD1848 and its It is designed to be generally register compatible with other previous technologies. Indirect ad The addressless method is used for accessing most CODEC registers. Model 1 (below) Has 16 indirect registers and model 2 (below) has 28 indirect registers , And Model 3 (below) have 32 indirect registers.   In the following register definition, reserved bits are indicated by RES or RESERVED. all Must write such a field as 0. In reading, undefined value Will come back. The read-modify-write operation allows you to write back the value you read. CODEC direct register CODEC INDEX ADDRESS REGISTER (CIDXR) Address: PCODAR + 0 Read and write Default: 0100 0000 Mode: Bits [7: 5, 3: 0] Modes 1, 2, and 3; Bit [4] Modes 2 and 3 INIT Initialization. CODEC is in initialization phase and responds to I / O activity            If not, consider read-only bit high            Is done. This bit is set only by a software reset,            Clear when 16MHz oscillator is stable and CODEC 505 is initialized            It is. MCE mode can be changed. This bit protects CPDFI, CRDFI, and CFIG1I from writing.            (Except CFIG1I [1: 0], which can be changed at any time). This bit            If the signal is high, the protection register can be changed. Also, DAC output            (CLDACI and CRDACI) are forcibly muted. Bit must be high            The protection register cannot be changed. DTD DMA transfer is not possible. If this bit is high, CSR3R sample            DMA transfer when one of the data interrupts becomes active            Is stopped. Mode 1: DMA is stopped (regardless of playback or recording)            Zu). And after the sample counter interrupts,            The pull counter stops; the active FIFO no longer has data.            Data cannot be transferred to CODEC 505. GINT is cleared or DTD is            When cleared, DMA transfers, FIFO transfers, and sample counters            Resumes. Modes 2 and 3: Record sample counter interrupted            Cause recording DMA, recording FIFO, and recording sample counter            Stops; when the playback sample counter interrupts,            The raw DMA, playback FIFO, and playback sample counter stop.            The appropriate interrupt bit in CSR3I is cleared or            When the DTD is cleared, the appropriate DMA transfer and sample counter            To resume. In mode 3, this bit also controls the CODECFIFO, LMRF, and LMPF            Works to stop data transfer between. LA [4: 0] Indirect address pointer. These bits are used by registers in the indirect address space.            Used to indicate a star. In mode 1, 16-bit register space            Is defined; LA [4] is reserved. Models 2 and 3 use 32-bit            Register space is defined. CODEC INDEXED DATA PORT (CDATAP) Address: PCODAR + 1 read / write Modes: 1, 2, and 3   This is the access port through which all CODEC index registers ( These are pointed to by the CODEC index address register (CIDXR [4: 0]) ) Is read or written. CODEC state 1 REGISTER (CSR1R) Address: PCODAR + 2 read (and writing to this address clears GINT Do) Default: 11001110 Modes: 1, 2, and 3   This register reports interrupt status and various playback and recording FIFO conditions. Ma When this register is read, CSR2I [7: 6] and CSR3I [3: 0] are set if they are set. Once cleared. Writing to this register will cause all CODEC interrupts Cleared. RULB Record channel upper / lower byte indication. Record when this bit is high          When reading the FIFO, the upper byte (bits [15: 8]) of the 16-bit sample is          Returned, or indicates that the recorded data is 18 bits or less          .          If this bit is not high, a 16-bit sample          Indicates that the lower byte of the pull (bits [7: 0]) is returned. Finally          After the last byte of the sample is read from the recording FIFO,          The state of this bit in that byte until a sample of          does not change. RLR Recording channel left / right sample indication. Record when this bit is high          Reading the FIFO returns the left sample, or the recording path is          No mode or ADPCM mode (or both)          You. If this bit is not high, the read returns the right sample          . Last byte of last received sample is read from record FIFO          After that, this view on that byte is received until the next sample is received.          The state of the kit does not change. RDA recording channel data valid. If this bit is high, read from the record FIFO.          Indicates that valid data exists. If this bit is not high,          Indicates that nothing is in the FIFO. SE sample error. Recording FIFO over          Run or underrun of the playback FIFO (OR of CSR2I [7: 6])          This bit is set when data is lost. Re-record channel          If both raw channels are valid, the specific          The channel is determined by reading CSR2I or CSR3I. PULB Play channel upper / lower byte instruction. Play if this bit is high          The next write to the FIFO is the upper byte (bit          [15: 8]) or the playback data is 8 bits or less          Is shown. If this bit is not high, writing to the playback FIFO is 16          Indicates the lower byte (bits [7: 0]) of the bit sample. Regeneration          When the FIFO is full, the last write until the FIFO is full          The state of the inserted byte does not change. PLR Play channel left / right sample instruction. Play if this bit is high          The next write to the FIFO will be the left sample or the playback path will be          No mode or ADPCM mode. This bit must be high          If so, the right sample is assumed. When the playback FIFO is full,          Until the FIFO becomes free, the state of the last written byte changes.          Absent. PBA playback channel buffer enabled. When this bit is high, the playback FIFO          Indicates that there is room for additional data. If the bit is not high,          Indicates that the FIFO is full. GINT Global interrupt status. Active that can request an interrupt          This bit is set when in the state. This is in CODEC: CSR3I [6: 4]          By ORing all of the interrupt sources          Implemented. Playback and recording data register (CPDR, CRDR) Address: PCODAR + 3 Read (Record FIFO), Write (Play FIFO) Modes: 1, 2, and 3   The data written to this address is loaded into the playback FIFO. This ad The data read from the address is removed from the recording FIFO. In status register 1 Bits indicate whether the data is on the left or right channel and the 16-bit sample Indicates the top or bottom of the sample. Is the playback FIFO in DMA mode? Or the playback path is not valid (CFIG1I). Writes to the I / O are ignored; the recording FIFO is in DMA mode or the recording path is If it is not valid (CFIG1I), reading from this address is invalid. Is seen. CODEC CIDXR, CDATAP index register   Left and right A / D input control (CLICI, CRICI) Address: PCODAR + 1 read, write; left index CIDXR [4: 0] = 0, right in Dex CIDXR [4: 0] = 1 Default: 000X 0000 (both) Mode: 1, 2, 3   This pair of registers specifies the input source to the A / D converter and can be used for individual signal paths. Used to specify the magnitude of the applied gain. These two registers are the same One controls the left channel and the other controls the right channel. LSS [1: 0] Left and right ADC source specification. These bits specify which input source. RSS [1: 0] Sent to the analog-to-digital converter. RWB read / write bit. This bit has no control. Writing              Everything you read is read back. LADIG [3: 0] Left and right A / D input gain specification. The specified input source has a gain stage              A / D via RADIG [3: 0] Transmitted to the converter. These four bits are applied to the signal applied to the signal.              The amount of in is indicated. These values are from 1.5h in 0h = 0dB              It changes up to 0Fh = + 22.5dB (see FIG. 45a). Left and right AUX1 / SYNTH input control (CLAX1I, CRAX1I) Address: PCODAR + 1 read / write; left index CIDXR [4: 0] = 2, right index               Index CIDXR [4: 0] = 3 Default: 1XX0 1000 (both) Mode: 1, 2, 3   This pair of registers is multiplexed by SYNTH (CFIG3I [1]) to left and right AUX1 or MIXER. Control input). The two registers are the same, one is the left channel The other controls the right channel. LA1ME, left and right AUX1 / SYNTH mute enabled. This bit is high RA1ME and the specified input sound are muted. If not high             Input is done normally. LA1G [4: 0], AUX1 / SYNTH gain specification for left and right. This allows the RA1G [4: 0] Indicates the amount of gain applied to the AUX1 / SYNTH input signal             It is. These values are from 1.5h to 00h = + 12dB to 1Fh =             It changes to -34.5dB (see Figure 45a). AUXILIARY input control for left and right (CLAX2I, CRAX2I) Address: PCODAR + 1 read / write; left index             CIDXR [4: 0] = 4, right index CIDXR [4: 0] = 5 Default: 1XX0 1000 (both) Mode: 1, 2, and 3   This pair of registers controls the left and right AUX2 inputs to the MIXER. These two records The registers are the same, one controls the left channel and the other controls the right channel. Control. LA2ME, left and right AUX1 / SYNTH mute enabled. This bit is high RA2ME and AUX2 inputs are muted. If not high, input             It is done through. LA2G [4: 0], left and right AUX2 gain specification. This allows the AUX2 input signal The amount of gain applied to RA2G [4: 0] is shown. These values are 1.5dB             The unit changes from 00h = + 12dB to 1Fh = -34.5dB (Fig.             45a). Left and right playback DAC control (CLDACI, CRDACI) Address: PCODAR + 1 read / write; left index             CIDXR [4: 0] = 6, right index CIDXR [4: 0] = 7 Default: 1X00 1000 (both) Modes: 1, 2, and 3   This pair of registers controls the left and right DAC analog output when input to MIXER I do. The two registers are the same, one controls the left channel and the other One controls the right channel. LDME, left and right silence enabled. When this bit is high, RDME DAC input is muted. If not high, input is           Will be LA [5: 0], left and right DAC attenuation specification. This allows the signal to be applied to the DAC input signal. RA [5: 0] indicates the amount of attenuation. These values are 00h = 0 in 1.5dB units.           It varies from dB to 3Fh = -94.5dB (see Figure 45a). Playback data format register (CPDFI) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = 8 Default: 0000 0000 Mode: The definition of this register changes based on the mode.   This register determines the sample rate (which of the two oscillators to use, Specify the oscillator division), stereo or mono, linear or companded data , 8 bits or 16 bits. The mode change enable bit (CIDXR [6]) is active This change can only be made when.   In mode 1, this register controls both the playback path and the recording path.   In mode 2, bits [3: 0] of this register determine the recording sample rate and playback sample rate. Control both pull rates (these must be the same), bits [7: 4] Indicates the state of the data format of the reproduction path.   In mode 3, this register controls only the playback path; recording sample rate Is controlled by CRDFI. PDF [2: 0] Playback data format selection. These three bits are for CODEC            2 shows a reproduction data format of the first embodiment. * Modes 2 and 3 only. In mode 1            Means that PDF [2] is treated as 0 regardless of the user's specification. PSM playback stereo / mono selection. When this bit is high, stereo operation is disabled.            Selected; samples alternate between left and then right. this            If no bit is set, mono mode is selected; playback sample            Is sent to both the left and right FIFOs. Recording sample (mode 1            At) comes only from left ADC. PCD [2: 0] Regeneration clock division specification. With these three bits, play in mode 3            The clock rate is set to the recording rate and playback rate in mode 1 and mode 2.            Indicates a port number. * This function works when XTAL1 is less than 18.5MHz.            These division values can be reduced. PCS playback crystal designation. When this bit is high, the playback sample frequency is            A 16.9344 MHz crystal oscillator (XTAL2) is used for the number. This bit            If not high, a 24.576 MHz crystal oscillator (XTAL1) is used.            It is. Configuration Register 1 (CFIG1I) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = 9 Default: 00XX 1000 Mode: 1, 2, 3   This register allows the I / O cycle or DMA to service the CODEC FIFO. Used, DMA operation is one channel or two channels, recording path and Specify whether to enable or disable the playback path. Bits [7: 2] are protected CIDXR [MCE] must be set to write to protected bits. Absent. RFIOS Record FIFO I / O designation. If this bit is high, the recording FIFO is          It is serviced by Kuru. If not, DMA operations are supported. PSIOS Playback FIFO I / O designation. If this bit is high, the playback FIFO is          It is serviced by Kuru. If not, DMA operations are supported. CALEM Calibration emulation. This is a read / write bit. This is high          If so, it affects CSR2I [5]. DSI / 2 One or two channel DMA operation specification. If this is high, a single channel          Panel operation is specified; only recording operation or only playback operation is possible          But not both; both record and playback DMA operations are possible in this mode          If so, only playback transfer is served. This must be high          For example, DMA operation on two channels is possible. RE recording enabled. When this is high, the recording CODEC pass is valid. Standing         If not, the recording path is disconnected and the recording data use status bit (status register         Star 1) is kept unavailable. PE regeneration enabled. When this is high, the playback CODEC path is valid. Standing          If not, the playback path is disconnected and the playback buffer usage status bit (status          Register 1) remains unavailable. External control register (CEXTT) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = Ah Default: 00XX 0X0X Mode: 1, 2, 3   This register has two general purpose external output pins together with global interrupt enable control. Includes control bits for GPOUT [1: 0] General purpose output flags. The state of these bits is reflected on GPOUT [1: 0] pins              Is done. RWB read / write bit. This is a readable and writable bit              is there. No control is performed in the device. GIE Global Iantarupt permission. If this is high, the CODEC interrupt              Becomes effective. If not high, a CODEC interrupt is specified              Not passed to the IRQ pin. The status bit indicates the status of this bit.              Therefore it is not affected. Status register 2 (CSR2I) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = Bh Default: 0000 0000 Mode: 1, 2, 3   This register indicates the status of certain FIFO errors and the data request bits for recording and playback. Report. And allow testing of the A / D path for clipping. RFO Record FIFO overrun. Recording FIFO is full, CODEC             Need to load some samples (the samples are discarded)             Whenever this bit is set. This bit is             Read or clear when CIDXR [MCE] changes from 1 to 0              Is done. PFU Playback FIFO underrun. The playback FIFO is emptied and the CODEC is              This bit is set whenever a pull is needed. this              The bit is read from CSRIR or CIDXR [MCE] changes from 1 to 0.              Cleared when touched. In mode 1, the previous sample is              Used once. In modes 2 and 3, CFIG2I [0] programming              Second, the previous sample is used again or the data is forced              To 0). CACT Calibration activity simulation. This bit if CFIG1I [3] is high              Indicates that the mode change enable bit (CIDXR [6]) has become inactive              Is set up. This bit completes the first continuous read of CSR2I.              Where it is cleared. DRPS DMA request pin status. This bit indicates whether the record or playback DMA request pin is              You can stand whenever you are active. RADO [1: 0], left and right out of range detection. These pairs of bits are Whether the signal to DAC at LADO [1: 0] is clipping            Or changed to reflect that. Mode designation, ID register (CMODEI) Address: PCODAR + 1 read and write;           Index CIDXR [4: 0] = Ch Default: 100X 1010 Mode: 1, 2, 3   This register specifies the mode of operation of the CODEC and reports the revision number of circuit C . ID [4], revision ID number. With these 5 bits, the CODEC times of the present invention ID [3: 0] Specify the revision number of the road C (the first number is 1,1010). This             These numbers are read-only and cannot be changed. MODE [1: 0] Specify the mode. (0,0) = mode 1; (1,0) = mode 2; (0,1) = reserved; (1,              1) = Mode 3. To switch to mode 3, write 6Ch to this port              Must be done; that is, bit [5]              Cleared for writing. Loopback control register (CLCI) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = Dh Default: 000 00X0 Mode: 1, 2, 3   This register controls the output of the gain stage of the ADC path (at the time of input to the ADC) and DA Allows and specifies the analog path attenuation to and from the C loopback sum input. This Register affects both left and right channels. LBA [5: 0] Loopback attenuation. Suitable for loopback signals before summing at the DAC output.            Specifies the amount of attenuation used. 00h = 0dB in 1.5dB steps            To 3Fh = -94.5dB (see Figure 45a) LBE loopback permission. If this is high, the loopback path will exit the DAC.            Mix with power is allowed. When cleared, the signal is rejected and the signal            Muted. Upper and lower playback count registers (CUPCTI, CLPCTI) Address: PCODAR + 1 read and write;           Upper index CIDXR [4: 0] = Eh,           Lower index CIDXR [4: 0] = Fh, Default: 0000 0000 (both) Mode: The definition of these registers depends on the mode   These registers together make up the 16-bit used by the playback sample counter. Supply preload values. CUPCTI provides upper half preload bits [15: 8], CLPCTI Supplies the lower half preload bits [7: 0]. All 16 bits write upper byte The counter is loaded while writing; therefore, the lower byte is written first. However, only the lower byte is written and the counter Will cause a new value to be placed in the timer. Reading these registers and writing to them is not the current state of the counter The returned value is returned. In Model 1, this register is used for both playback and recording. Modes 2 and 3 are only used for playback. Configuration Register 2 (CFIG2I) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = 10h Default: 0000 XXX0 Mode: 2, 3 OFVS output maximum voltage specification. When this is high, the maximum output is 2.9V for Vcc = 5V        And becomes 1.34 for Vcc = 3.3V. If not high, the maximum output is        It becomes 2.0V for Vcc = 5V and 5V for Vcc = 3.3V. This bit        Affects the left and right signals exiting the Mixer before entering CLOAI and CROAI        This bit also changes the input to the recording multiplex. TE timer enabled. When this is high, the timer and its associated        Is activated. If not, the timer does not run. timer        The counter is specified by CLTIMI and CUTIMI. RSCD recording sample counter invalid. If this is high, the recorded sample cow        Will not work. This bit is valid only in mode 3,        It only affects the sample counter. PSCD playback sample counter invalid. If this is high, the playback sample cow        Will not work. This bit is valid only in mode 3,        It only affects the sample counter. DAOF D / A output forced valid. If this is high, the playback FIFO has an underrun error        Whenever occurs, the output of the D / A converter is forcibly set to the intermediate value of the maximum output.        You. When this is cleared, the last valid sample is an underrun        Output in the state of Configuration Register 3 (CFIG3I) Address: PCODAR + 1 read and write;             Index CIDXR [4: 0] = 11h Default: 0000 X000 Mode: bits [7: 1] mode 3; bits [0] modes 2 and 3   In mode 3, this register is used to program the FIFO threshold and the I / O mode F Provides interrupt generation for IFO services. RPIE Record FIFO service request interrupt enabled. I / O operation with recording path enabled           Is specified (CFIG1I), the FIFO / DMA interface of status register 3           Generate an interrupt request whenever the interrupt bit is set           Becomes possible. This bit can be accessed only in mode 3. PPIE Play FIFO service request interrupt enabled. Playback path is valid and I / O operation           Is specified (CFIG1I), the FIFO / DMA interface of status register 3           Generate an interrupt request whenever the interrupt bit is set.           Is possible. This bit can be accessed only in mode 3.           You. FT [1: 0] FIFO threshold specification. These two bits are either DMA or           Record and playback FIFO thread for when a           Specify the shoulder. These bits are only accessible in mode 3.           Mode 2 and mode 2 have no effect. PVFM playback variable frequency mode. When this bit is high, the playback variable frequency mode is        Is selected. In this mode, the sample rates are CPDFI [0] and CPVFI        Variable frequency between 3.5KHz and 32KHz, selected by coupling        Becomes When in this mode, audio quality may be reduced. This        Are accessible only in mode 3. SYNA AUX1 / SYNTH signal selection. This bit is set to CLAX1I before entering the left and right Mixers.        Select the signal source that enters the CRAX1I attenuator. If this bit is not set        , AUX1 [L, R]. When this bit is high, the output of the SYNTHDAC         Select This bit can be accessed only in mode 3. RWB read / write bit. This bit enables reading and writing. Inside the device        Does not control anything. This is only accessible in mode 2 and mode 3        Is possible. Left and right line input control registers (CLLICI, CRLICI) Address: PCODAR + 1 read and write;             Left index CIDXR [4: 0] = 12h,             Right index CIDXR [4: 0] = 13h Default: 1XX0 1000 (both) Mode: 2, 3   This pair of registers controls the gain / attenuation applied to the LINEIN input to the Mixer. I will. These registers are the same, one controls the left channel and the other one Control the right channel. LLIME, left and right LINE input mute enabled. When this bit is high, RLIMF, LINEIN input sound is suppressed. Otherwise normal             Works. LLIG [4: 0], left and right LINE input amplification designation. This is the LINEIN [L, R] input signal Specifies the amount of amplification applied to RLIG [4: 0]. These values are only 1.5 dB             From 0 = + 12 to 1Fh = -34.5dB (see Figure 45a             reference) Upper and lower timer registers (CLTIMI, CUTIMI) Address: PCODAR + 1 read and write;             Lower index CIDXR [4: 0] = 14h,             Upper index CIDXR [4: 0] = 15h, Default: 0000 0000 (both) Mode: 2, 3   Together, these registers are 16-bit pre-rows used by general-purpose timers. Supply the value. These counts are expressed in 10 microseconds (650 millimeters total). Seconds). CUTIMI sets the upper half preload bits [15: 8] and CLTIMI sets the lower half preload bits. Supply the data bits [7: 0]. Writing CLTIMI turns all 16 bits into a general-purpose timer Loaded. Reading these registers will return the value of the counter instead of the current value. Is returned. Left and right MIC input control registers (CLLICI, CRLICI) Address: PCODAR + 1 read and write;             Left index CIDXR [4: 0] = 16h,             Right index CIDXR [4: 0] = 17h Default: 1XX0 1000 (both) Mode: 3   This pair of registers controls the left and right MIC inputs to the Mixer. These regis The same, one controls the left channel and the other controls the right channel . LLME, RMME Left and right MIC silencing allowed. When this bit is high, the MIC input is muted. Is done. If not high, it works as usual. LMG [4: 0], RMG [4: 0] Left and right MIC gain specification. This applies to MIC [L, R] input signals. Specify the amount of gain to be applied. These values range from 0 = + 12 to 1Fh = -34.5dB in 1.5dB steps. Changes (see Figure 45a) Status register 3 (CSR3I) Address: PCODAR + 1 read, write (to clear certain bits); Index CIDXR [4: 0] = 18h Default: X000 0000 Mode: 2, 3; The definition of bits [5: 4] depends on the mode.   This register is the cause of various interrupts with other FIFO status information. And report. TIR, RFDI, and PFDI bits each have 0 as the active bit Cleared by writing. Writing 1 is ignored. These bits Is also cleared by writing an arbitrary value to CSR1R. Obera [3: 0] of the under-run bits are cleared by reading CSR1R Is done. These bits also clear the CIDXR mode change enable bit. Sometimes cleared. TIR timer interrupt request. When this bit is set, the timer Indicates that there is a tap request. This writes a 0 to this bit, or Cleared by writing any value to CSR1R. RFDI record FIFO interrupt request. When this bit is set, the recording path Indicates that there is a put. This writes 0 to this bit or any value Is written to CSR1R. Mode 2: This bit is recorded Indicates that there is an interrupt from the sample counter. CFIG1I [7] = 0 in mode 3 (DMA): This bit indicates that there is an interrupt from the recording sample counter. Show. In mode 3, CFIG1I [7] = 1 (I / O): This bit is the recording FIFO threshold (CFIG3 Indicates that I) has been reached. PFDI Play FIFO interrupt request. When this bit is set, the playback path interrupt Indicates that there is a put. This writes 0 to this bit or any value Is written to CSR1R. Mode 2: This bit is played Indicates that there is an interrupt from the sample counter. CFIG1I [6] = 0 in mode 3 (DMA): This bit indicates that there is an interrupt from the playback sample counter. Show. In mode 3, CFIG1I [6] = 1 (I / O): This bit sets the playback FIFO threshold (CFIG3 Indicates that I) has been reached. RFU Record FIFO underrun (modes 2 and 3). Read from empty record FIFO Once this bit is set. RFO Record FIFO overrun (modes 2 and 3). ADC fills record FIFO with sun This bit is set if a pull needs to be loaded. This is the same as CSR2I [RFO] One. This bit is set if there is a PFO. PFU Playback FIFO underrun (modes 2 and 3). ADC sampled from empty replay FIFO This bit is set if a request is needed. This is the same as CSR2I [PFU] is there. Left and right output attenuation register (CLOAI, CROAI) Address: PCODAR + 1 read / write; left index CIDXR [4: 0] = 19h, Default: 1XX0 0000 (both) Mode: only 3; in mode 2, CLOAI reads 80h when reading This is a dedicated register. This pair of registers controls the left and right MONO and LINE output levels. Also LINE output The MUTE control bit is also in this pair of registers. LLOME, RMOME line output mute enable. When high, the LINE output is mu Is If not high, it works as usual. LLOA [4: 0], RLOA [4: 0] LINE output attenuation specification. This applies to MONO and LINE output signals Specify the amount of attenuation to be applied. These values are from 00h = 0 to 1Fh = -46.5dB in 1.5dB steps. Changes (see Figure 45a) MONO I / O control register (CLOAI, CROAI) Address: PCODAR + 1 read / write; Index CTDXR [4: 0] = 1Ah Default: 110X 0000 Mode: bits [7: 6, 4: 0] modes 2 and 3; bit [5] mode 3   This register specifies the amount of attenuation applied to the MONO input path. MONO input and Here is also the silence control of the output. MIME MONO input silence permission. When this bit is set, the MONO input is muted. If not high, it works as usual. MOME MONO output silence permission. When this bit is set, the MONO output is muted. If not high, it works as usual. AR3S AREF to high impedance. AREF is high when this bit is set. It is set to the speed mode. If not high, it works normally. This bit is Access is possible only in C3. MIA [3: 0] MONO input attenuation. This indicates the amount of attenuation applied to the MONO input path. these Varies from 0 = 0 to 0Fh = -45dB in 1.5dB steps (see Figure 45a) Recording data format register (CRDFI) Address: PCODAR + 1 read / write; Index CIDXR [4: 0] = 1Ch Default: 0000 0000 Modes: 2 and 3; register definitions vary by mode.   This register determines the sample rate (which of the two oscillators is used, And specify the splitting element for that oscillator), stereo operation or mono operation, Indicates whether it is linear data or companded data, 8-bit data or 16-bit data. Mo This change can be made only when the code change permission bit (CIDXR [6]) is active.   In mode 2, bits [3: 0] are not used (record pass sample rate is CPDF I defined). Bits [7: 4] indicate the data format of the recording path.   In mode 3, this entire register controls the attributes of the recording path; the playback attribute is CP Controlled by DFI. RDF [2: 0] Recording data format specification. With these three bits This shows the recording data format for CODEC. Only in modes 2 and 3 The unit is accessible. RSM recording stereo / mono selection. When this bit is set, stereo operation is selected. Selected; samples alternately switch to the left and then to the right. This bit stands If not, mono mode is selected; recording samples come only from the left ADC. This Are accessible only in modes 2 and 3. RCD [2: 0] Specify recording clock division. These three bits are the recording clock Specify a rate. These bits can be accessed only in mode 3. Mo In mode 2, these bits are reserved. * When XTAL1 is smaller than 18.5MHz In order to work, these division values can be reduced. PCS recording crystal selection. When this bit is set, the playback sample frequency is set to 1 A 6.9344 MHz crystal oscillator is used. 24.57 if this bit is not high A 6MHz crystal oscillator is used. This bit can be accessed only in mode 3. No; in mode 2, this bit Reserved. Upper and lower recording count registers (CURCTI, CLRCTI) Address: PCODAR + 1 read and write; upper index CIDXR [4: 0] = 1Eh, Lower index CIDXR [4: 0] = 1Fh, Default: 0000 0000 (both) Modes: 2 and 3: In mode 1, functions are transferred to CUPCTI and CLPCTI.   These registers together are the 16-bit used by the recorded sample counter. Supply preload values. CURCTI provides upper half preload bits [15: 8], CLRCTI Supplies the lower half preload bits [7: 0]. All 16 bits write upper byte The counter is loaded while writing; therefore, the lower byte is written first. However, only the lower byte is written and the counter Will cause a new value to be written into the timer. You. Reading these registers writes to them instead of the current state of the counter. The returned value is returned. Reproduction variable frequency register (CPVFI) Address: PCODAR + 1 read / write; Index CIDXR [4: 0] = 1Dh Default: 0000 0000 Mode: 3 only. This 8-bit register is used when variable frequency playback mode is enabled in CFIG3I [2]. Shows the reproduction frequency of the. The reproduction frequency is PCS / (16 * (48 + CPVFI). CS is the frequency of the oscillator specified by CPDFI [0]. 3.5KHz for 16.9MHz oscillator Supply up to 22.05KHz, and the 4.5MHz oscillator supplies from 5.0KHz to 32KHz. When changing the value of this register, it is not necessary to set CIDXR [MCE].   In the Mixer 606 of FIG. 45, the state of the control register CLICI604 for the recording pass of the CODEC 505 Means that four analog audio signals are attenuated / gay The multiplexer (MUX) 602 is controlled so as to pass through the multiplexer control circuit 664. If decrease If the sound is not muted by the attenuation / gain control circuit 664, the designated signal is Passed to the ADC 666 or loopback through the attenuation / gain control circuit 606. And the output of the playback Mixer 678 and the output of the left playback DAC 680 are summed. This loopback Is performed through the loopback path 676. Loopback path 676 is in playback mode The output signal of MICL684, LINEINL682, AUX1L686, LEFT SYNTH DAC692 is left playback DAC6 System to be superimposed through audio signals coming out of 80 outputs Provides a loopback path for testing and "dub-over" functions. This is "Ka The stored audio signal output from the left reproduction DAC 68 is supplied to the rioke-type ″.   The contents of control register CFIG3I [SYNA] are analog input AUX1L686 and LEFT SYNTH DAC Used to control LEFT SYNTH694 for selection between 694. Selected The analog audio signal is then input to the MUX 602 and the attenuation / gain control circuit 612. Passed. The output of the attenuation / gain control circuit 612 is then input to the primary Mixer 698. And mated with all other non-silent analog audio input signals.   Primary Mixer loopback path 677 feeds Mixer 698 output to MUX 602 input . Also, the output of Mixer 698 is attenuated / gained to pass to Mono Mixer 672 as LEFTOUT. It is supplied to the in-control circuit 674. For Mixer672, LEFTOUT and right channel Mixer These analog outputs RIGHOUT616 are combined. Signals LEFTOUT and RIGHOUT are mono mix sum in er672, then through mute control 604, analog output signal MONOOU Transmitted to T668. The LEFTOUT signal is also input to the attenuation / gain control circuit 602 . Unless muted, LEFTOUT is the analog output left channel stereo signal LINEOUT Used as L670.   The analog audio input signal 960 passes through the attenuation / gain control circuit 696, and becomes an input signal. Handed over to the main Mixer698. The right channel is used as the analog mono input signal 618. Passed to Le Major Mixer.   As shown in FIG. 47, CODEC 505 is an individual analog audio in analog Mixer 606. The amplitude of the signal is adjusted to ensure that the signal is maintained until it reaches its normal value. Includes roads. This is achieved by the zero detection circuit 715. New decay / ge The analog audio signal to be operated with the in-control value is 0 volt 714 (FIG. 46). ) Or the timeout count is 25ms with timer 718 Until that time, the modified attenuation / gain control information is stored in the respective attenuation / gain control registers. Will not be loaded. When the timeout occurs, the contents of the Register block 566 (Fig. 50) A new attenuation / gain control value is loaded into each attenuation / gain control register. Will be.   The attenuation / gain control circuit 710 surrounded by the dotted line in FIG. Reserved for each attenuation / gain control register in lock 566 . Specifically, 16 attenuation / gain control registers (CLCI, CLICI, CRICI, CLAX1I , CRAX1I, CLAX2I, CRAX2I, CLDACI, CRDACI, CLLICI, CRLICI, CLMICI, CRMICI , CLOAI, CROAI and CMONOI), which store the gain and attenuation stored therein. Written to change the control value. And the values are written in order Of the analog audio signal being processed by a particular attenuation / gain control register. Used to change the amplitude. More or less in other applications A decay / gain control register has been implemented.   During operation, whenever one of the attenuation / gain control registers is written, gister Select Decode block 716 passes attenuation / gain control value to GainLatch730 . After decrypting the data written to the attenuation / gain control register, select Register Decode block 716 is 25ms Timer block 718 and 100 TO 300 Microsecond Time r An operation signal is sent to the block 720, and electricity flows. Then electricity is 100-300 my For 100 seconds to 300 microseconds for each of the Near Zero Detect blocks 732  The Comparator Power-On block 720 is activated by the Timer block 720. And supplied.   25ms Timer block 718 counts up to 80 using 3.15KHz clock ICLK3K. To The timing of the 100 TO 300 Microsecond Timer block 720 is 3.15 kHz. Taken by the logic waiting for the two ends of the lock ICLK3K. When electricity flows, sound Near Zero Detect block 732 is triggered when voice input signal 740 approaches the nominal voltage. Generate lobes.   The zero detection logic in the Near Zero Detect block 732 uses comparators and audio input signals 7 An output signal can be provided whenever 40 equals a predefined reference voltage. Can be realized by using the above circuit. Zero detection strobe has new attenuation / gain for LATCH726 Used to send in value. Zero detection circuit part 732 is fixed 25 ms Timer71 Power does not drop until 8 finishes counting.   The analog reference voltage (AREF) is that when VCC is 5 volts, the value of AREF is nominally V Used to be CC * 0.376. When VCC is 3.3 volts, the value of AREF is The name is VCC * 0.303. By controlling CMONOI [AR3S], AREF is 250 Can be raised to icroamps.   If input signal 740 reaches nominal voltage for 25 ms before Timer 718 finishes counting If not, the new attenuation / gain control value, as a default condition, but still Loaded into each attenuation / gain control register. 25 ms timeout Before writing to any of the attenuation / gain control registers in REGISTER block 566 (Figure 50) If there is a write, Timer718 resets for 25 ms regardless of the state of the counter Is done.   The zero detection circuit 715 is a “zipper” when the amplitude of the input signal 740 increases or decreases. Minimize noise and discontinuous sounds. When the attenuation / gain register is written Zero crossing is sensed by powering up the zero sense circuit 732 only when Each time the comparator or other voltage detection circuit in the Near Zero Detect block 732 The required noise is removed.   In FIG. 46, by increasing the gain at the zero crossing point 732 of the input signal, Signal discontinuities are removed. By using the Zero Detect block 732 , The input signal 740 changes amplitude at the point of zero crossing, and as output signal 736 (FIG. 47) Output from zero sense circuit 715, and continues at new amplitude along curve 712 .   All CODEC505 programmable attenuation / gain control circuits (Analog Mixer6 (Triangle 06) includes a zero detection circuit 715. Zero detection circuit 715 is Register Equally for each attenuation / gain control register in lock 566 (Figure 50) Execute.   The additional noise management of the CODEC 505 is used to eliminate power-up noise. Used. Power is applied to audio abnormalities from audio output LINEOUT670 and MONOOUT668 (Figure 45) Or when being removed from the CODEC 505 or entering a low power mode They are removed when they leave. All power ups or power downs During this period, the output amplification of the CODEC 505 in the muffling circuits 602 and 64 is in a mute state.   16.9MHz system clock rising edge to improve CODEC performance Digital operation is performed on the falling edge of the system clock or the system clock. At some point before the next rising edge of the tuck, analog operation is performed. Generally, digital Controls must be attenuated as much as possible before analog controls are performed. Noise. Uses different ends of the system clock and is more digital Regarding the clock used in the circuit, the system clock used in the analog circuit Delaying the clock generated from the clock has the desired effect. Analog functions require quiet supply and grounding. For example, a comparator has the right ratio To be able to make comparisons, make sure that low-level background noise can detect 1 millivolt. Need to be   The CODEC 505 recording and playback paths use different sample rates for recording and playback. It can be independently programmed to supply. Continuous variable rate playback mode Provided for playback DAC 514 (FIG. 44). This gives two samples from 3.5 to 22.05KHz and from 5.0 to 32.00KHz -The clock can be specified. 256 increase for each sample rate Includes clock rate. Change the state of control register CFIG3I [2] to By enabling the variable playback mode, the playback frequency for the DAC514 is 256 An audio sample rate that can be changed continuously over steps to produce high quality sound Can make a smooth transition between them. Previously, only 14 different samples Sample rate data was increased and rewritten because rate was used. I had to get it. Then, transition between the required sound and the sample rate In order to be able to do so, the rate must be increased again and the signal rewritten won. This required excessive processor intervention.   Using the feedback loop in CODEC Analog Mixer606 (Figure 45), The sample rate of the recording ADC 516 and the playback DAC 514 can be programmed independently to allow The analog audio signal can be sampled and recorded at one rate. Can now be converted to files. This feature includes recording and replaying at different sample rates. It has a function to convert between generated audio signals. For example, compact Disc (CD) directly, or formatted without extreme deterioration of sound quality Digital audio data (DAT) to a tape that has been analyzed is analyzed through a 44.1KHz playback DAT514. Created by the CD audio data that is converted to audio and then recorded through the ADC516 circuit Serial or parallel recorded by an external audio device with a 48KHz DAT It can be used as digital audio data.   In the present invention, the continuous variable reproduction frequency mode increases sampling and rewrites. Playback in CODEC 505 without the intervention of an external processor. It is possible to specify that the pull rate is gradually increased. If possible, The number range is specified by control register CPDFI [0] in Register block 566 (FIG. 50). Field is desirable. This control register is programmable, always uses the playback frequency, You can specify whether a clock is used. See FIG. For this, some sort of External processor intervention requires loading frequency-specific instructions, but earlier It's not as burdeny as our voice system. Software compatibility with existing systems For this purpose, the playback variable frequency mode uses 14 samples of the playback DAC 514 and the recording ADC 516. Different from rate mode operation.   Oscillator 560 with external crystal (Fig. 50) is for playback variable frequency mode Used to generate the frequency range of If possible, two with ON-CHIP circuit Two external crystals, one at 24.576 MHz and the other at 16.9344 MHz. The field used to make the lock is desirable. 16.9MHz at SELECTLOGIC circuit 762 When the clock is specified, one 256 step frequency range from 3.5KHz to 22.05KHz Is provided. If you specify a 24.5MHz crystal, 15.0 from 35.0KHz to 32.00KHz Two 256 step frequency ranges are provided. To supply each of the 256 steps in one specified frequency range, specify Crystal oscillator makes X256 clock (256 times sample rate) To divide by three or more. Then, convert X256 clock to X64 clock (sample Divided by 4 to make 64 times the rate). X64 clock is in the specified range Repeat a periodic pattern of 8 cycles to generate frequencies within. Figure 48 The various clocks generated by the divider logic of FIG. Used to change the sample rate (pitch) during playback. as a result The higher the sample rate, the higher the pitch, the lower the sample rate The pitch is also lower. This continuously variable playback sample rate feature However, it can be used and is not limited to the Σ- △ reproduction DAC 514 described here.   Table C1 contains the priority for specifying the sample frequency for each band. The formula used is noted.   Table C2 shows that the first clock frequency in one band is 16.9MHz external crystal oscillation Fig. 4 shows a method produced using a vessel.   Table C3 shows the preferred method of using X256 to create the waveforms shown in Table C2. doing. The 4-cycle pattern shown in Table 3 is the state of register SMX64 [1: 0]. X64 clock is preferably 50% load cycle Should be used to ensure that the file is maintained.   Figure 48 shows a sample rate that can be specified independently for the recording and playback paths of CODEC 505. Clock designator circuit and a continuously variable playback sampler for the playback DAC 514. The rate. Playback DAC514 and recording The ADC516 (Figure 44) each has 14 different sample rates ranging from 5.5 to 48.0 KHz. It can operate on one of the ports. These sample rates are preferentially two clear Extracted from the stall oscillator 560 (FIG. 50). CODEC505 SELECTLOGIC circuit 762 , Depending on which sample rate is being used, the 16 MHz or 24 MHz oscillator Controls 2: 1 MUX766 to specify output.   GATELOGIC block 752 in the recording path and 764 in the playback path are slower than specified LOGIC block 754, divides specified clock signal to supply clock Supply to 756, 760 and 757 respectively. As shown in FIG. 48, the control register C PDPI [0], CPDFI [3: 1], CRDFI [0], CRDFI [3:10], CFIG3I [2] and CPVFI [7: 0] Control the split LOGIC to be used to generate the specified clock signal I will. Clock CP256X is used to control the operation of playback DAC 514. K Lock CP64X is used to control the operation of the quasi-digital filter 804 ( (Figure 51).   In Figures 49 and 49a, CODEC 505 has logic for converting serial digital audio data. And control, parallel to serial (TS) conversion block 788,789, and serial to parallel (STP) conversion logic 782 is included. Record multiplexer (MUX) 784 is a control register It is controlled by the star ICMPTI [8: 6]. If bits [8: 6] are 0, MUX784 The parallel digital audio data is designated from the recording ADC 516. If bits [8: 6] are 1 If so, the MUX 784 specifies the output of the STP conversion logic 782. In the recording path, the output of MUX784 Power is supplied to the CODEC regeneration FIFO538. Referring to FIG. 44, the output of the recording FIFO 538 is REG On the ISTER DATABUS526, the signal passes through the parallel converter 789, parallel transfer control 540, and data path 550. LOCALEMORY CONTROL790 (this is OF data for storage as a record FIFO) Transfer to F-CHIPLOCALMEMORY110, on Figure 44) and at the input of PTS block 789 ,Available. The PTS block 789 allows the data to be transferred to the SERIALTRANSFERCONTROL block. After lock 540, record FIFO 538, playback FIFO 532 (Converter from serial to parallel 782) or supplied to EXTERNAL SERIALINTERFACE544 Is done.   As shown in FIG. 49a, in the CODEC playback path, the playback MUX 794 controls the control register. It is controlled by ICMPTI [8: 6] and LMFSI [PE]. If ICMPTI [8: 6] is not 1 Or if LMFSI [PE] is 1, then the audio data from STP block 782 Are available as inputs to the playback FIFO 532. Otherwise, REGISTER DATA B Data from US526 is available in FIFO532. As shown in FIG. 49a, L Data from OCALMEMORY CONTROL790 (this has data from LOCAL MEMORY110 44) is passed to the playback FIPO 532 via the playback MUX 794. SYNTH DSP79 6, or data from the record FIFO 538, is also available at the input of the playback MUX 794 . As shown in Figure 49a, the value of ICMPT [8: 6] controls the operation of serial transfer control MUXES 554 and 548. I will. The operation of the serial transfer control MUX 546 is controlled by the state of LMFSI [PE].   As shown in FIG. 44, the audio data from SYNTH DSP796 also Available when entering 12 The output of SYNTH DAC512 is CODEC analog Mixer606 (Fig. 45) to the left SYNTH DAC MUX649 (and the right SYNTH DACMUX, not shown) Provided as input. The SYNTH DSP796 can be an external device or a CODEC5 As a CODEC device 505, to increase the flexibility and speed of operation between 05 and SYNTH It may be in the SYNTH module on the same monolithic IC.   STP and PTS conversion logic blocks 782 and 789, respectively, and SERIAL TRANSFERC By placing ONTROL 540, the digital between the recording and playback path of CODECC 505 ・ The loop function has been completed. This allows external devices or OFF from the record FIFO 538 or the playback FIFO 532, or via the LOCAL MEMORY CONTROL 790 -To CHIPLOCALMEMORY110 (Fig. 44) or to an external system memory The flexibility of data transfer and test is increased. PTS and STP blocks Through 789 and 782, the digital data path (Figures 44 and 49) is connected to the record FIFO 538 output. Pictured during the playback FIFO532 input. Between the playback DAC 514 output and the recording ADC 516 input The loop is analog, in the Mixer 606, Figure 680, left playback 680 to the left recording ADC666 It is drawn in a loop.   EXTERNAL SERIAL INTERFACE544 is connected to SYNTHDSP with serial input and output. Is also good. This causes the SYNTH DSP to go through the SERIAL TRANSFERCONTROL block 540 Serial data can be received from the recording FIFO 538, and the SERIAL TRANSFERCONTRO The serial data can be sent to the reproduction FIFO 532 via the L block 540.   Recording and playback MUXES784 and 79 in the serial data conversion logic of CODEC 505 4 means that bitstream MUX is desirable. Perform a transfer if possible To generate and operate the necessary control signals and clocks, a state machine Is preferably used. Description of control signals during serial data transfer above checking ... Most transfers within the SERIAL TRANSFERCONTROL block 540 2.1MHz 50% load divided by 16.9344MHz crystal oscillator by 8 Operate in cycles. Transfers from DSP796 to external devices are based on the SYNTHDSP frame rate. Uses 32 clocks per frame, based on frame rate. STP logic broser RANSF The pulse STSYNC generated by the ERCONTROL block 540 is first MSB, then Followed by 16-bit data.   For PTS blocks 788 and 789, the data structure and order are for a 16-bit DMA transfer. The same is true. S after the LSB of each 16-bit left or right data sample is transferred TSYNC switches. In the conversion operation of each PTS conversion block 788, 789, 16 bits Data is sequentially shifted. The number, data structure and data order for transfer are as follows Depends on the specified transfer mode.   The PTS blocks 788, 789 are for 16-bit DMA, as described in Table C4 below. It operates similarly to the transfer to the FIFO. (For example, if you are in 8-bit mode, , The first sample is LSB and the second is MSB Thus, there is one serial transfer for every two data samples. 16-bit station In Leo mode, there are two transfers for each sample received. )   PTS blocks 788 and 789 have flags set and there is data to transfer Is shown. The serial transfer control block 540 indicates transfer of serial data starting from the MSB. Responds by generating a pulse, STSYNC (serial transfer SYNC). 16 bit After the transfer, the clear pulse is sent from the serial transfer control block 540 to the PTS block 78. 8, sent to 789. As a result, new data is loaded into PTS blocks 788 and 789. You. If possible, all audio data multiplexed by the serial transfer control block 540 Desirably has three input sources and three output destinations.   The contents of the control register, ICPMTI in REGISTER block 566, are shown in Table C5. The various modes of operation can be specified by modifying the Can be determined.   Generally, if the recording or reproduction FIFO 538, 532 is a data output destination, Format and sample rate must match those shown in Table C5 No. Otherwise, the data transfer will not be accurate. For example, if STM = 2 Then the playback path sample rate and format are Synth DSP796 (16 bit Teleo, 44.1MHz). If STM = 3, the playback path sun The pull rate and format must match the recording path. In mode 4 Has a playback sample rate of 44.1KHz or less. In that mode, SynthDSP796 The sample rate can be less than 44.1KHz and the synthesizer global The value in the mode register SGMI [ENH] is 0, indicating that the active synthesizer voice is active. Register SAVI [AV] is set to 14 or more. You That is, if more than 14 voices or signals have been processed, -The rate is possible even at 44.1KHz or less. Otherwise, the first 14 signals are 4 Processed at 4.1KHz. For STM = 1 and STM = 2 modes, CODEC 505 is 44.1KHz Support sample rate. In these two modes, if Synth DSP796 Does not work properly if it operates at other than 44.1KHz.   While in the playback mode, as shown in FIG. 50, the external system memory Digital audio data can be DMA or I / O in several specifiable formats. EXTER via transfer CONTROL LOGIC & EXTERNAL BUS INTERFACE568 Passed to NAL BUS 562, and as 16-bit stereo data for left and right channels, It is sent to GISTERDATA BUS526, and finally 32 bit playback FIFO532 or LMPF528 (Figure 44).   The LMPF528 (Figure 44) is an existing 16-bit digital stereo left and right channel. Download audio data directly to the playback FIFO 532 through REGISTER BUS526. You may.   By doing so, previous I / O or DMA transfers can be Made between memory and LMPF528, between external system memory and CODEC playback FIFO532 Many DMA transfers required will be reduced. During playback, most data transfer common The main mode is DMA transfer between the external system memory and the CODEC reproduction FIFO 532. I Even in the case of a shift, the audio data is then output to the playback FIFO 532 and Formats 16-bit signed data as described in ONVERSION block 534. (Decomposed) and then as 16-bit signed data to the playback DAC 514. Is entered. That data is then described earlier in connection with the description of FIG. 45, Sent to MIXING FUNCTION block 510 containing left and right analog Mixers.   In the recording path, an external analog sound input through CODEC analog input pin 520 Voice signals are sent through the MIXING AND ANALOGFUNCTION block 520, Passed to recording ADC 516 as channel stereo 16 bit signed digital signal . The 16-bit left and right channel stereo data from the recording ADC 516 * 538 is sent to the format specified in advance, and is sent to REGISTER DATA BUS5 26, then to EXTERNAL BUS 562, and then by DMA or I / O data transfer. To the external system memory or LMRF 530 (FIG. 44). In recording mode, D MA data transfer is LMRF530 (LMRF530 uses audio data from ON-CHIP RECORD FIFO538 Or external system memory through EXTERNALBUS562 Alternatively, it is performed directly between the ON-CHIP RECORD FIFO 538 and the external system memory.   CODEC 505 is an external system memory and CODEC ON-CHIP recording and playback FIFO 538, 532 System, and also between system memory and the OFF-CHIP LMPF528 and LMPF530. I / O can be performed to increase system flexibility.   In FIG. 50, the playback path of the CODEC 505 is in the mono mode, and the control register CPDFI [4] When the bit is not set, the left and right channel stereo DA of the playback DAC514 block C is the same as the audio data from playback FIFI532 Things are passed. If the recording path is in mono mode and the bit in control register CPDFI [4] When the camera is not standing, data from only the left stereo ADC (Data from the right stereo ADC is ignored) and passed to the recording FIFO 538 It is desirable.   In another structure of stuff mode, only the data from the right stereo ADC is recorded FIF Passed to O538. The audio signal frequency is greater than the Nyquist rate, i.e. 0. Wrapping problem when processed at a rate greater than 5f (1/2 the sample rate) Occurs. The passband and the cutoff circuit reduce signal reflections that are multiples of f and reduce signal frequency. Used to add or subtract. Pass at .6F for 22KHz Preferably, the band discontinuity is at least 75 dB. Passband sever, regenerate To reduce high-frequency images (reflection) during the DAC / D / A conversion, an analog filter Used with Luther. Oversampling is lower in the recording ADC 516 This is done by multiplying the sample rate by 64 during bit analysis. The signal is then required Until you get the analysis result and sample rate, for example 44.1KHz for 16 bit , Are sampled and filtered in the recording ADC 516. Recording ADC516 circuit function and operation The detailed explanation of the work is as follows. Table C4 above shows the DMA transfer unit Sample of audio data to be transferred, DMA for 8-bit or 16-bit DMA transfer It contains information about the number of cycles per transfer. This number is the specified DMA Depends on the type of For example, in 8-bit DMA transfer mode, 4-bit ADP The audio data formatted as CM mono audio data is two in one DMA cycle. Are transferred. In 16-bit DMA transfer mode, four 4-bit ADPCM monosamples are transferred in one DMA cycle. 16-bit DMA cycle The first byte to the playback FIFO 532 is [7: 0] and the second byte is bits [15: 8]. Simultaneous recording and playback operations (read and write) are possible . During I / O activity, the external system processor determines if I / O activity is required In order to CODEC505 Status register to determine which part of CODEC 505 requested the data. , Specify CODEC505 via CONTROL LOGIC ANDEXTERNAL BUS INTERFACE568 . External system control asynchronously transfers data to playback or recording FIFOs (532, 538) To perform I / O operations. For record FIFO538 and playback FIFO532 Error conditions are shown in Table C6.   16 bits are dedicated to left channel data and 16 bits are dedicated to right channel The 16-sample, 32-bit recording and playback FIFOs 538, 532 provide 0, 7, 15 support. Recording and playback at the sample address FIFO538, 532 threshold, so-called tap Corresponds to “sky”, “half full”, and “full”. I / O interrupt required Request (IRQ) or DMA request (DRQ) of the CODEC 505 These ads can be generated by state (only mode 3 and described below). Signals are monitored by control logic block 568. This behavior will be explained in detail later. explain.   Separate DRQ signals are generated for the recording and playback FIFOs 538,532. One for CODEC505 In an external system that can only use the DMA channel of A mode is provided that allows it to function as a recording DMA or playback DMA . Alternatively, a system without a DMA function may use I / O transfer. DMA transfer mode Is a Register This is specified in the configuration control register CFIG11 of the block 566 (FIG. 50). If the record or If the playback path is not valid (through CFIG11 [1: 0]), the corresponding DRQ request signal Active, as if the audio data samples were waiting for an acknowledgment Transfer continues as if the source was still active. The last audio sample After being transferred, no other DMA requests are serviced.   If the recording path is not valid according to CFIG1I [1], or both recording and playback Path is being enabled for DMA transfers, but single-channel DMA operation is If 1I [2: 0] = [1,1,1], the recording FIFO is reactivated. In order to prevent old data from being processed when All data is cleared. But before being disabled, it's record FIFO 538 The recording path before the transfer is performed by the format conversion block 536 (FIG. 44) and the It is not cleared during four sample periods, including the filter function.   When the playback path is invalid by CFIG1I [0], the playback audio is muted directly and replayed. All samples remaining in the raw FIFO 532 are output from the FIFO 532 at that sample rate. Removed. During four sample periods, the playback FIFO 532 is in the later FIFO playback path. After being emptied with 0 at, the playback path is disabled to minimize power consumption .   OFF-CHIP LOCAL MEMORY110 (Fig. 44) is preferably ON-CHIP playback and recording FIFO 532, 538 However, it is desirable to use it. LOCALMEMORY110 is as large as possible Read and record FIFOs 532 and 538, each with an approximate 8-bit address of 16 megabytes It is desirable to configure the bit size. CODEC COUNTERS, TIMERS The 19-bit counters in the block 518 are used to make the respective LMPF523 and LMRF530 Is programmed to specify the area size of the DRAM. These are 512K sun It can be configured to hold up to the pull. LMPF528 and LMRF530 or local me Approximate voice sample memory for mory, design and application requirements Composed of Low cost and low power It is desirable to use DRAM instead of SRAM for this purpose.   CODEC 505 interleaves data transfer between external system memory and LMPF528. Have a mode for In data mode with interleave, external digital Audio data samples are stored in the external system memory as L1, R1, L2, R2, ... Number, and transfer to LOCALMEMORY CONTROL790 (Fig. 49) through EXTERNAL BUS562. Sent. In the CONTROLLOGIC block 528, before the data is stored in the LMPF528 The format has been converted. And the left channel data sample is OFF-CHIP LOC Stored in one area of the AL MEMORY 110 as L1, L2, L3 ... blocks. Right cha Channel data samples are stored in another area of the LOCAL MEMORY 110 in the R1, R2, R3 ... It is stored as a lock. In mono mode, the same data is available in both blocks of LOCALMEMORY. Stored in the lock. The same method is used in reverse for the CODEC505 recording mode. For example, the same sample is sent from LMRF 530 to external system memory.   There are two 16-sample counters in the COUNTER, ETC block 518 (Figure 44). One for raw FIFO532 and one for record FIFO538. Sample counters are stored in individual FIFOs. Count the number of samples coming or going. The individual counters are AD In non-PCM modes, it is decremented by one for each sample period. Counter goes to 0 If unmasked, an interrupt will occur and the counter Will be reloaded. The count value of the counter is calculated in the REGISTER block 566 (Fig. 50). Record and playback count register (CURCTI, CORCTI, CUPCTI, CLPCTI) Is grammed. The status of the counter is passed through the control register CSR3I of the REGISTER block 566. Will be reported. In mode 3, as described below, the CODEC playback counter When MA transfer is performed from external system memory to OFF-CHIP LOCAL MEMORY110, Also, ON-CHIP recording or playback FIFO 538, 532 from external system memory is performed. When it is reduced.   Table C7 shows the relationship between the data format and the event that decreases the sample counter. The clerk is shown.   Table C8 lists the events that decrease the sample counter and the variables used in the Boolean equations below. There is. These are used to provide valid inputs to the counter.   Table C9 shows that audio data is recorded and replayed from external systems and microprocessors. Indicates the format passed or received to the raw FIFO 538,532. Table C9 The letter "S" refers to "sample" and the number after the letter "S" refers to the sample number . "R" or "L" after sample number is right or left channel stereo Refers to audio data.   The CODEC timer in the COUNTERS ANDTIMES block 518 (Figure 44) Used to time external system functions, such as the length of time to issue. When the timer count is completed, an interrupt is generated. CODEC505 is the machine It is desirable to use as few timers as possible for use. But industry It is necessary to provide this function for interchangeability and expandability.   The CODEC 505 can operate in three modes during playback or recording. CODEC505 Generally operates in mode 1 and mode 2 to allow the It is compatible with Vista. The indirect addressing method is that of REGISTER block 566 (Fig. 50). Used to access most of the CODEC registers inside. In mode 1 , Preferably 16 indirect registers. In mode 2, there are 28 indirect registers. Is desirable. In mode 3 unique to CODEC505, there are 32 indirect registers. desirable. The operation in these modes is as follows.   Mode 1.The playback sample counter in the COUNTERS, ETS block 518 Is valid (CFIG1I [0]) or when the recording path is valid (CFIG1I [1]). Be sent. If both paths are valid, only the playback path affects the counter and the recording Not used for sample counters. REGISTER CODEC INDEX ADDRESS REGISTERCID If XR [DTD] is set and the active path causes an interrupt (CSRI R [GINT]), the sample counter stops counting. The counter indicates that interrupt When the count or CIDXR [DTD] is cleared, counting starts again. DMA Alternatively, the I / O cycle control bits, CFIG1I [7: 6], It does not affect.   Mode 2.The playback sample counter indicates when the playback path is valid (CFIG1I [0]). Is reduced. The recording sample counter indicates when the recording path is valid (CFIG1I [1]). If CFIG1I [2] and CFIG1I [0] are not valid, they are decremented. CODEC INDEX ADDRES SREGISTERCIDXR [DTD] is set and the active path is interrupted When it wakes up (CSR3R [5: 4]), each path that requested an interrupt stops working . When the interrupt or CIDXR [DTD] is cleared, the data path is activated. Start the work and start counting again. DMA or I / O cycle control bit, CF IG1I [7: 6] does not affect the operation of the sample counter.   Mode 3.Sample counter counts when in I / O mode (CFIG1I [7: 6]) The same operation as in mode 2 is performed except that the operation is not performed. Also, configuration register, CFIG The sample counter can be operated while 2I [5: 4]. This is an altitude mode with independent recording And playback pass sample rate, record and playback programmable FIFO threshold, Sy Additional analog Mixer input valid for nth DAC audio signal, Mixer606 (Fig. 45) LIME / MONO Attenuation / gain control for output, programmable continuously variable sump in playback path Frequency mode is possible.   Modes 2 and 3 provide a programmable 16-bit timer. This The immer is roughly on the order of 10 milliseconds and uses a 100KHz clock, CLK100K. You. Enabled by timer CPIG2I [6].   A pair of programmable registers in the CODEC505 is 16BITCOUNTERPRESET (CUTIM I, CLTIMI), and the counter is decremented to 0 every 10 milliseconds. 0 Then, the timer interrupt bit is set in the status register 3 and the status register Interrupt bit is set in data 1 and if enabled (CEXTI [1]) , An interrupt occurs. The CUTIMI value and CLTIMI value will be changed again at the next timer clock. Load Is done.   The record and playback FIFOs 538 and 532 are stored in the respective FIFOs from the external system memory. Is a programmable threshold for communicating IRQ or DRQ to the FIFO. Or taps. The threshold operation is as follows: record and playback If the pointer tree is 0 in the FIFOs 538 and 532, the address has no data and is 1 If so, data exists. For a specific address in either FIFO, When the pointer tree transitions from 1 to 0, the external system is set in advance. To fill the playback FIFO 532 above the threshold level (playback) Below the preset threshold level (recording) for the external system Trigger an IRQ or DRQ interrupt to empty the recording FIFO 538.   CODEC logic control block 568 (Figure 50) is connected to one of the FIFO taps You. The configuration register CFIG3I [4,5] threshold specification is empty, full, or medium. Determine which of the thresholds will be selected. Logic control block 568 pulls Monitors taps continuously and features that are designed to perform it automatically Generate and execute (ie, generate DMA or I / O interrupts). Tap is thread Detect if the shoulder address is empty (play) or full (record) Depending on whether the tap is full, empty or medium in the FIFO. Request is generated. COUNTERS, TIMERS, DMA counter of ETC block 518 (Fig. 44) Is set so that a certain number of data samples are transferred to and from CODEC 505 . When a counter completes its count, an interrupt request is generated.   The value of the index pointer of the recording and reproduction FIFO 538, 532 is set to the CODEC control block 568. Passed to. When the index pointer reaches the FIFO threshold, the REGISTER block One bit in one status register of lock 566 is changed. This state The unit is read by external system processing to perform recording and playback operations with the FIFO. REGISTER block 566 Status register is set when the threshold (tap) changes from 1 to 0 by FIFO. Changed to Zodiac. When that happens, a bit in the status register toggles. When the status register is checked by an external system processor, The processor determines which device is requesting the interrupt. REGISTER The CODEC register of block 566 is directly addressed through REGISTER DATA BUS526, Alternatively, depending on the index register method in REGISTER block 566, Addressed through the contact address.   The CODEC 505 generates the following interrupts: (1) Record and Playback FIPOI / O The threshold has been reached; (2) the record and playback sample counter has reached zero; (3 ) The CODEC timer has reached 0. CODEC in CONTROL LOGIC block 568 (Fig. 50) The results of the interrupt logic are combined into one interrupt signal, IACODEC, To be. It passes to the interrupt selection logic of CONTROL LOGIC block 568 Is done. The interrupt is masked by Global enable, CEXTI [1] . The status of the interrupt is indicated by the GLOBAL STATUS REGISTER in the REGISTER block 566. , Displayed in CSRIR [0] (Fig. 50).   The following interrupt equation is the CONTROL LOGIC block associated with the CODEC505 interrupt. To set (CSET) or clear (CCLR) the logic of lock 568 Shows the necessary state. Activate any of the three interrupt status bits on CSR2I There is one latch in the CONTROL LOGIC block 568 to allow See Table C10 Then the definition of the variables is given in the following interrupt equation.   Two general control signals, GPOUT [1: 2], are passed from CONTROL LOGIC block 568 . The state of these digital outputs is controlled by external control in the REGISTER block 566 (Figure 50). It shows the state of the corresponding control bit in the register (CEXTI).   CODEC has a low power mode. The three programmable bits are CODEC 505 low power shutdown state, power control level in REGISTER block 566 (FIG. 50) Specify the register PPWRI [2: 0] to specify the recording path, playback path or analog The circuit can be disabled. Other structures use some bits Maybe. In shutdown mode, the external crystal oscillator 560 (Figure 50) Disabled, but all registers in REGISTER block 566 are readable is there. In hibernate mode, specified by the external computer system or processor The CODEC 505 has all three bits in the power control register, PPWRI. As if selecting a low power state, both oscillators 560 were disabled and the CODECI / O pin To run as if most of them are inaccessible. Dedicated hibernation mode The control pin, SUSPEND #, forces the CODECI / O pin up, down, or Switches to digital or analog high impedance mode. Table C11 three It describes the state of the I / O pins in hibernate mode. clock How to reduce the power consumed by the working circuit is described in application serial number 07/918 , 622 Title "Clock Generator capable of Shut-Down Mode and Clock gen eration Method ", which is designated as a shared assignee in the present invention and It is incorporated here for all purposes.   Table C12 shows what PPWRI [2: 0] causes to CODEC 505 in shutdown mode. Has been described.   When the SUSPEND # pin becomes active, the CODEC will put it in shutdown mode. Make a movement similar to the one you take. The signal ISUSPRQ is Depending on the lock, the logical sum of I2LSUSPRQ and I2SSUSPRQ is obtained. ISUSPIP is intelligent Is ORed with I2LSUSPIP. If the CODEC 505 is in shutdown mode when SUSPEND # is confirmed, (1 ) The I / O pins are changed to meet the requirements for the sleep mode described above. And (2) Reproduction DAC514, recording ADC516, and Synth DAC512 (if Synth DAC512 is CODEC CODEC 505 analog circuit (if incorporated as a processing block in 505) , If it is not already in that mode, it is put into a low power mode.   After the SUSPEND # has been verified, the logic of the CONTROL LOGIC block Before stopping the clock and before disabling the oscillator, Wait on. 16MHz clock ICLK16M and 24MHz clock ICLK24M are free from distortion and abnormalities. As such, it is disabled. When the clock is in one of the high phases, hibernate mode It remains so until it is invalidated. After SUSPEND # pauses, The shaker 560 does not re-toggle the wide K24M until the oscillator 560 stabilizes after 4 to 8 seconds. This occurs after the oscillator 560 has successfully measured 64K times. Low output clock After toggling for at least 100 microseconds, the SUSPEND # signal goes to the remaining logic of CODEC 505. Is placed in an indeterminate state to activate the lock. While the clock is not valid, The signal ISUSPIP (during sleep) goes active. It depends on the I / O for each pause requirement in Table C11. Used to change pin state.   The CODEC 505 can operate with VCC = + 3.3 or 5 volts. Control logic The power detection circuit in block 568 (Figure 50) operates in CODEC 3.3 or 5 volt operating mode. Determine if there is. The operating state depends on the output of the voltage detection circuit register AVCCIS5. It is determined. External computer or processor has signal greater than operating VCC An operation detection circuit is used so that it is notified that it is not running. for example For example, when operating at 3.3 volts, no 4 volt signal is generated. It is also analog It is also used to set the maximum reference voltage and the range of digital I / O pin driving force. You.   CODEC505 can interact with external CD-ROM interface 568 (Figure 50) Noh. Chip designation, DMA request, DMA acknowledgment, and CD-ROM interface Signals containing these interrupt requests are supported by CODEC 505.   External serial EPROM or EEPROM (Fig. 50) uses CODEC505 Plug-n-Play (PNP) with ISA, ET Used by CODEC 505 to be compatible with SA or other industry standard buses and equipment Is also good. Configure CODEC 505 for external computer or processor Commercially available PNP software is used to control serial EPROM and EEPROM as You may. If an external serial EPROM or EEPROM is not available for the PNP function, The CD-ROM interface cannot be accessed with the CODEC. A. Digital signal processing section of CODEC playback path CODEC playback DAC514 (Fig. 44), if DAC512 is included in CODEC505, Synth DAC51 2 is an interpolation block 800 (Fig. 51), NOISE Shaper802, semi-digital FIR filter80 Includes 4 for left and right channel stereo audio data. Left channel An injury is shown in FIG. 51 and will now be described. The operation of the right channel is similar .   The operation of the CODEC playback DAC 514 will now be described. Synth512 included in CODEC505 If so, the operation is the same. If not, it will be different.   The 16-bit digital audio signal 806 comes from the FORMAT CONVERTION block 534 (Fig. 44). The INTERP of the playback DAC 514, which outputs and combines the signals as signed data signals Input to OLATOR block 800 (FIG. 51). After the first three interpolation stages, The digital audio signal 840 with several bits collected is output to the input to NOISE SHAPER802. Where it is quantized and converted to a 1-bit digital output signal 842. One The cut signal 842 is then input to a semi-digital FIR filter 804. There What is important is removed from the band frequency and the signal is converted to an analog audio signal 808 Is done. Then, it is used when the reproduction DAC 514 outputs. Left channel analog audio The signal 808 is used as an input to the left channel CODEC playback Mixer 678.   Referring to the front part of the reproduction DAC 514 in FIG. 52, the 16-bit digital audio signal 806 is It is interpolated first, then quantized and noise shaped. Play DAC 514 At the sample rate f, a 16-bit digital audio signal 806 is received as input, and INTERPO When outputting the LATOR block 800 (Fig. 51), One sample that was sampled at 64 times the sample rate (64 times oversampling) The cut signal 840 is generated. Because one stage requires a lot of filters The interpolation is performed in three stages in the INTERPOLATOR block 800. Circuit duplication The complexity is 2 for Interp. 1 blocks 810 and 812, 2 for Interp. 2 block 814, and I In nterp.3 block 816, three interpolation Minimized by performing 64 up-sampling interpolations on the page .   The specific input spectrum to Interp. 1 blocks 810, 812 is for frequencies up to f / 2. Components and unwanted images concentrated at integer multiples of f. specific See FIG. 53a for the input spectrum.   To perform the first interpolation in Interp. 1 block 810 for f = 2 × f, Has a number or bandwidth expanded to about 0.40f as much as possible, and also at about 0.60f Preferably, an FIR filter with a stop band that starts is used. Also The passband expands to about 0.45f, and it is hoped to start the stopband at about 0.55f. Good. The stop band attenuation of the filter should be 100 dB or more if possible, Desirably, the passband ripple is about +/- 0.1 dB. For this, 0.45f or less The lower frequency image is guaranteed to be attenuated every 100 dB. However Higher frequencies along with the image are inside the transition band of the filter. And the attenuation is reduced. Therefore, useful bandwidth is about 3.6KHz at f = 8KHz Or about 19.8 KHz at f = 44.1 KHz.   The spectrum of the output of Interp. 1 blocks 810 and 812 is applied to the input indicated by 53a. In contrast, it is shown in FIG. 53b.   The impulse response coefficients used in Interp. 1 blocks 810 and 812 are as shown in Table C13. It is on the street. The values of these coefficients will differ if the passband or stopband changes. Come.   This interpolation filtering works in the analog domain when operating at the lowest rate. Done digitally to avoid filtering. At the lowest rate Rapid transitions, requiring unlog filters. Such an analog filter Without, the image will not appear on output. Analog filter is sump It is necessary to have a variable cutoff to accommodate changes in ring rate.   The second interpolation stage executed in block 814 is the sampling rate. Is changed to f = 4f. In this stage, a sinc filter is used, roughly 30dB image attenuation is provided. Spectrum of output of second interpolation stage 814 Is depicted in FIG. 53c.   The third interpolation stage, executed in Interp. 3 block 816, has a coefficient of 16 Further change the sampling rate to f = 64f. With two differential delays, sin c interpolator is used. This interpolator serves the following purpose: Interpolation, so as not to exceed the noise level introduced by noiseshaper802 The vessel decays approximately 4f. And 0 is introduced again at 2f. It is the interpolation stage 28 Along with 14, provide sufficient attenuation for roughly 2f images. Third stay The spectrum for the output of di 816 is as in FIG. 53d.   The last block in front of the playback DAC, and the last stage of the interpolation filter The fifth order is noise shaper 802 (FIG. 52). noise shaper802 Multi-bit output 840 from the third stage 816 to 1-bit signal 842 Convert. It shapes its noise according to Chebyshev fast transform function . The spectrum for the noise shaper 802 output is as shown in FIG. 53e. noise sh The operation of the aper block 802 is described herein.   The 1-bit signal from the noise shaper 802 is then converted to a semi-digital FIR filter80 Filtered in 4 (Figure 51). semi-digital FIR filter 804 is noise shaper8 Compensate for the attenuation caused by 02. Also, about 20KHz when f = 8KHz To achieve a relatively smooth noise level that is enlarged to noise shaper802 gain Is less than unity gain.   The spectrum of the semi-digital FIR filter 804 analog output is as shown in Figure 53f. You. Processed by interpolator 800, noise shaper 802, semi-digital FIR filter 804 FIG. 54 illustrates an example of the time domain of the digital signal.   B. Interpolator processing blocks (810.812, 814, and 816) Interp. 1 blocks 810, 812 Is symmetric (with 2N-1 taps (N separate coefficients) and N = 40 in this structure) Linear phase) FIR filter. The interpolation coefficient of this block is 2. So This is due to the attenuation of about 100 dB or more in the stopband and about +/- 0.1 dB or less in the passband. Designed to have a pull. The passband response is sinc Interp. 2 Introduced by Jib 814, sinc Interp. 3 Stageb 816, and noise shaper802 The semi-digital used in the reconstructed DAC514D / A conversion process, as well as the gain variation Compensate for roll-off introduced by FIR filter 804 To compensate.   The FIR filter in this Interp.1 block 810, 812 will be introduced in the next stage Pass achieved by combining all the frequency variations performed into one function Includes band compensation.   Referring to FIG. 52, when used as an interpolator, the FIR filter It operates on the input sequence of the bit input signal 806. Where all data samples go to 0 Equal (because it is interpolated by 2). This is because one odd output sample signal 832 is Int This is because the calculation is performed using only the odd coefficients of the erp.1 phase 2 block 812. So Then, the next even-numbered output sample signal is the even-numbered signal of Interp. It is calculated using only numbers, but with the same set of 16-bit input signals 806. This This is shown in FIG. Polymorphic implementations shown as 1 810 and 812 (In the case of U, two phases).   There, two sub-filters are run in parallel and filter outputs 832 to 834 Are interleaved in a known manner to produce an Interp. 1 signal output 836. So 836 is then passed to Interp. 2 block 814.   In the time domain, odd and even outputs from the two phases of Interp. Signals 834 and 832 are: Phase 1 (even coefficient) for even output signal 834, for odd output signal 832 Is phase 2 (odd coefficient): All delays are made at the input sampling rate.   Interp.1 blocks 810 and 812 have phase linearity and impulse response is midpoint Symmetric about the value. The symmetry condition is given by: This reduces the structure of filters 810 and 812, respectively, as shown in FIGS. Reflects.   In particular, the impulse response contains very small coefficients. Larger outage bandwidth , These coefficients are very important. To keep precision, the coefficient is , Are scaled such that their magnitudes are between 1 and 1/2. Then go In the circuit 818 (FIGS. 55 and 56), the partial product corresponding to the smallest coefficient is added first, and Leveled and then added to the product corresponding to the next higher coefficient. If the word width is This is not summed in any order unless increased to preserve precision Means that. That is, the taps are performed in the same order as the modified order. 2. Interpolator 2.   The second interpolation stage 814Interp.2 is a sinx interpolator filter. This block There are two interpolation coefficients. The attenuation provided by the semi-digital filter 804 For this, a high attenuation of 2 × f is not required and a relatively simple structure is used.   The filter forwarding function for Interp.2 stage 814 is: Expanded to Thus, the Interp. 2 filter 814 has coefficients of only integers. Pass band Roll-off is compensated in Interp. 1 blocks 810 and 812.   The Interp. 2 filter 814 is interpolated by two, so other filters are used as shown below. It operates on a sequence in which the number is zero.   This is similar to Interp. 1810, 812 block, as shown in FIG. Leads to one implementation. In H2a and H2b, a delay occurs at the input sampling rate f. Interp.2 filter 81 In both phases of 4, the common term of the transformation function saves some hardware. ing. FIG. 57 shows the configuration of the Interp. 2 filter 814. The magnification of 2 is the whole Applied through.   The frequency response, normalized to DC, is shown in FIGS. 58 and 59. 3. Interpolator 3   The transfer function of Interp. 3 block 816 is: The interpolation coefficient of the blocks is 16. The differential delay is two. order is 2. The implementation structure of the transfer function is shown in FIG. Differentiator 839 is more Running at a lower rate, integrator 841 runs faster. Differentiator with two delays is 1 It is decomposed into a differentiator with one delay and two accumulators. That is: Another block diagram for Interp. 3 block 816 is shown in FIG. Each These signal samples are used 16 times higher by the integrator 846, which runs at the highest rate. You. 0 is introduced at 4f. The two delay blocks 841A and 841B in FIG. 60 and 846A in FIG. Operate to introduce another 0 at f. It is an interpolator sinc filter 814 Provide sufficient image attenuation together with the sinc for Interp. 2 block 814 More economical than using filters. Frequency response of interpolator 3 filter 816 Is normalized to DC and is shown in FIGS. 62a and 62b. You. C. Noise shaper   The final phase of the interpolator, Noise Shaper block 802 (FIGS. 51, 52), is the third complement. Interstage stage, receives multi-bit signal output from Interp. 3 block 816 (Fig. 52). And while adjusting the quantization noise according to the fast function, Convert to issue. A shaper for Shaper802, preferably a fifth order shape The lock diagram implementation is shown in FIG. 1 bit The output signal 842 is also input to the integrator 822.   Predefined as determined by the rest of the digital path shown in Figure 63 To stabilize the loop over a range of input amplitudes, the integrator 822 input is You must have the rate, k1-5. Simple additive noise shown in Figure 63 The model is used to represent quantization.   Two transfer functions are defined for this circuit. Signal transfer function (STF) Y / X, here Where X is the digital audio input signal 840 (Figure 52) and its noise transfer function (NTF) Y / E, where E is the quantization noise (modeled as additive, white, uniformly distributed noise). NTF Is fixed, the STF is also determined. Because the system is not a FIR filter , The response is no longer directly phase linear. However, in the passband Dose variation is very small, on the order of 0.05, and the amplitude is .1 Can be interpolated in 810 and 812 blocks.   The signal flow graph (SFG) for the noise shaper block 802 is shown in Figure 64 I have.   The transfer function is developed as follows: Forward path gain: Cumulative gain of all possible directional paths from input to output: Non-touching Loops:   The Gain product of the loop sets that do not have any common nodes is calculated. At first, A pair of Non-touching Loops must be identified. Then the 3 bit Site is found, then 4 bits, etc. In the illustrated configuration, a pair of non- Switch loop exists. A pair of Non-touching Loops must be identified. Then the 3 bit Site is found, then 4 bits, etc. In the illustrated configuration, a pair of non- Switch loop exists.    L1, G1    L1, G2    L1, L2 queue It is defined from the loop gain as follows: In the illustrated configuration, there are no 3-bit bytes in the non-touch loop, so Submatrix For X:   All loops are touched by T1. So △₁= 1   For E:         T1 = 1-LI-L2 + L₁L_TwoAgainst₁= △   Transfer functions can be created for X and E using Manson's rules. here, For noise, the transfer function is: For signals, Referring now to FIG. The coefficients are chosen to match the Chebyshev function. And pass band and smooth An equiripple quantization noise in a clear stop band is obtained. The values for Ai and Bi are , By matching the noise TF to the required shape function, Ci and W in the above equation Obtained from i.   If possible, evenly spaced within the noise stop band (ie, signal band) For NTFs that have zero and a smooth high frequency response, Preferably, a number is chosen. For the illustrated configuration, the stop area edge, stop attenuation, And the filter order must be determined. Stopband attenuation is 90 if possible dB, stopband edge is approximately 6 kHz for an input sampling rate of 8 kHz, and Thus, for a maximum sampling rate of 48KHz, it is about 36KHz, and filter ord er is preferably 5. I.e. noise stop for noise shaper802 The bandwidth is extended by at least 0.70f, and preferably to 0.75f.   It exceeds the signal bandwidth by more than 0.25f. This allows the quasi-digital fill The design requirements for the data are slightly less stringent.   First, a continuous time zero and poles are obtained. Where zero is given by Is: And the poles are given by: Where N = 5, m is from 0 to 4, ω = stop band edge = 2π.36000, and ε1 is related to attenuation G And given in dB by: A pole-zero diagram in the s-plane is shown in FIG. Frequency up to 300MHZ A plot of the response is depicted in FIG. Next, discrete zeros and poles use bilinear equations Can be obtained: Here, T = 1 / f, and f = 64 × 48 KHz = 3.072 MHz. This activates the noise shaper Highest sampling rate, highest sampling rate for input signal Corresponds to 64 times oversampling. However, noise shaper is It is necessary to know that it operates at the (lower) sampling rate.   Solving these equations gives the following: Figure 67 shows a pole-zero diagram in the Z-plane for the noise shaper802. You. K is the gain of NTF at f = f / 2 (or z = -1) and is an important parameter for stability. You.   The desired frequency response of the discrete filter for the noise shaper 802 is shown in Figure 68. ing.   The numerator of the transfer function of the specified structure must match the discrete filter. The zero property realized by that is to set the numerator of the noise NTF to zero and calculate the following equation Can be found by: The root of this equation is z1 = 1; the other roots are given by C1 and C2 are not independent. Because they are as shown by the NTF equation , B1 and B2. The formula to get the other four roots is:   The structure shown in FIGS. 63 and 64 allows one zero and two pairs of duplicates at DC (z = 1). Prime zero is now possible. They both have real parts equal to one You. This means that they are not on a single cycle. However, If their angles are small enough, they will be well damped. Single cycle In order to be able to actually have zero in Loops (ie, more coefficients) must be used.   B1 and B2 are the same angles as required by the ideal transfer function with zero as possible Is specified. This is shown in Figure 69, where the angle is exaggerated It is drawn.   Then, B1, B2 are set negative. Then the individual angles α are: The values of BL, B2 also depend on the values of K2 and K4. Generally, shown as k1-k5 in FIG. The reference coefficient k is the noise shaper 802 within the required range of the amplitude for the input signal. Need to be adjusted to be stable. If possible, follow the criteria below: Should be: ・ The reference coefficient k is equal for the second and fourth integrators 822a (FIG. 63), and the third The same is true for the eye and the fifth integrator 822b. This allows the two integrators 822 and One hardware block 830 including a series of adders 830 changes the reference coefficient k. It can be reused without using it. Hardware block 830 is surrounded by a dotted line in FIG. You. ・ The reference coefficient k is the only negative power of two. So, do not multiply, Only a wear shift is performed. ・ The reference coefficient k is the output of the integrator 822 such that the required word length is uniform throughout the structure. To make the signal width the same. ・ The reference coefficient k is set so that the stability range is compatible with the required input signal level. Cut. The reference coefficients reserved for an input signal range of +/- 0.25dB are:    k1 = 0.25    k2 = 0.5    k3 = 0.25    k4 = 0.5    k5 = 0.125 The feedback coefficient values B1 and B2 use these reference coefficients to make them zero. Is secured. if you can, The coefficients for the denominator of the NTF equation, H (z), are given by To obtain the above Wi value, the denominator D of the discrete filter and then the given equation And by combining the values of B1 and B2. In this example, FIG. Then there is a unique solution. To locate the poles, the feedback coefficient of this example A1-A2 is: A1 = -4.273 A2 = -4.3682518 A3 = -5.2473373413 A5 = -1.28061104 These feedback factors are 10 times before the STF begins to be affected in the signal band. Quantized to bits. here: A1 = -4.265625 A2 = -4.359375 A3 = -5.234374 A4 = -1.75 A5 = -1.265625   The actual size of the NTF is the NTF obtained with all zeros at DC (z = 1) in FIG. Is compared to the size of The noise power of the signal band uses Chebyshev zero For a given structure, it is easier than it is for a simple structure with all zeros in DC. Seems to be about 16.3dB. 1． Single transfer function (STF) for Noise Sahper   Once the feedback coefficients, A and B, shown in FIG. The STF for e Sahper 802 is fixed. If oversampling rate is large enough At best, the STF has little effect on the signal bandwidth. Otherwise, the poles are to some extent Pulled, but undesirable because stability is compromised. Better structure Compensates for any distortion in the first interpolation filter interp. 1 blocks 810, 812. ST The magnitudes of F and NFT over the entire frequency range are shown in FIG. Pass band The desired STF response in the region is detailed in FIG. Glue in the passband The loop delay is shown in FIG.   Passband tilt has a desirable +/- 0.1dB ripple requirement for the entire playback path Meaningful enough to violate. However, with regard to group delay, it is still But acceptable.   The difference between the maximum and minimum group delay is 21.95 nanoseconds. f = 8KHz at 3.6KHz The phase deviation from the shape is equal to: 2． Noise transfer function (NTF) for Noise shaper   In the linear analysis employed to obtain the transfer function described above, the quantizer is off. Predict signal level effects when additional noise model fails due to overload Can not. However, it is known that stability is directly related to the maximum value of NTF. Have been. A value close to 2 is the limit for stable operation. Maximum value of NTF in the structure shown Is obtained for f = f / 2 (z = -1). There, the parameters of the NTF interact . ・   For a fixed stop band, the larger the noise attenuation, the greater the noise gain K, f = f / 2 The value at becomes larger. ・   For fixed noise attenuation, the larger the stop band, the larger the noise gain value. It will be good.   The fixed value of the noise gain K at f / 2 is equal to the noise attenuation if the bandwidth is correct. Can be obtained for any value. FIG. 74 illustrates a constant noise gain shape.   In the structure presented, a noise gain of 1.7 is used, which gives almost the best stability Amplitude Amax close to. Noise gain of K = 1.85 or more seems to have poor stability Seems to be.   This means that the transition from stable (K = 1.7) to unstable (K = 1.85) is rather steep. The maximum input amplitude Amax that the circuit can tolerate before becoming unstable is directly determined by the noise gain value Related to   For example, all loop configurations that keep shape for K = 1.8 have Amax = 0.2 . On the other hand, for the shape with respect to K = 1.71, A = .4. The arrow in Fig. 74 is safe in GB space. It shows the direction from constant to unstable. Amax increases to infinity as K increases Absent. It is highest at K = 1.71. This is partially determined by the value of the integrator gain. (Figure 75).   If the bandwidth is constant and the noise attenuation G changes, for a bandwidth of 20 kHz, Amaxvs. K is as shown in FIG. If the noise attenuation G is constant and the bandwidth changes, The pole result is as shown in FIG. This was obtained for G = 90 dB. K = The 1.8 stability reaches its limit at around 40KHz bandwidth. For a bandwidth of about 36KHz, The noise gain value K is about 1.707, which also matches the peak Amax = 0.4 I do. To ensure stable operation, the maximum amplitude into the loop, preferably It is desirable to keep it at 0.25.   Implementation of digital sigma-delta modulator that creates noise shaper The options are as follows:   Referring to FIG. 121, the noise shaper filter block 2010 is a multi-bit digital filter. One input signal 2012 (preferably 64xF, preferably 25 bits in frequency) Perform a sigma-delta conversion to convert to a digital output signal. This one Quantization to a cut output signal causes noise in the signal. It is the next high-speed signal transfer function. Adjusted according to number. This noise shaper filter 2010 has the following noise transfer function:   Where E (Z) is the digital noise input signal. Coefficients C1, C2, C3, C4, C5 are Given in table C19.   As shown in FIG. 121, this noise shaper block 2010 has a total of 12 2 3-bit addition operation, two multiplication operations, and five in five integration stages I1-I5 A scaling operation is included. The addition operation of 12 is executed by the adders a1-a12. The multiplication operation of 2 is performed by the multipliers 2016 and 2018. The five normalization operations are illustrated 121 (ie, 1/8, 1/2, 1/4, 1 / 2, and 1/4). The scaling is performed by a bit shifting operation. Noise sha in Figure 122 Used to control the data path implementing per block 2010 The clock signal used is set at a rate 256 times the sample frequency (256F). The coefficients C1-C5, which implement the poles for the transfer function above, are transferred in the signal band. It is quantized to 10 bits without adversely affecting the transfer function. noise shaper block The implementation of 2010 is based on the quantization output 2014 (+1 or -1) of the quantizer 2020. Have any value) and have coefficients C1-C5 multiplied by Coefficient C6 And C7 implement the transfer function zero and are reduced to two items. So Each of the items It is a power of two. The values of the coefficients C1-7 are shown in Table C19.   The noise shaper block 2010 output signal 2014 has four 256F clock cycles, or Or at a rate 64 times the sample frequency (64F). Data input and output are 6 Occurs at the rate of 4F. The fixed bit length in the noise shaper block is Filter-normalized data consisting of 23 bits, 3 of which are 19-bit integers G is a decimal number. Implementation of noise shaper block 2010 in Figure 121 Is schematically depicted in FIG. 122.   There, some adders are used to save hardware or increase efficiency. It is used.   The digital sigma-delta modulator and noise shaper circuit shown in Figure 122 The structure of the 2050 is shown in Figure 121 with the sigma-delta modulator noise shaper function block. An implementation of locking that reduces the number of adders required. Thus, the amount of hardware could be reduced. Thus, as shown in FIG. The structure used uses an adder as depicted therein. That is, FIG. The five stages of integration shown in FIG. 1 are reduced by the structure shown in FIG. No adder, and the multiplexed adder here in FIG. The adder of Figure 122 can be multiplexed to perform more than a force-by-force integration operation. And is performed by In FIG. 121, for each of the five integration stages Each adder performs only one operation per output. As a result, FIG. The depicted structure is more efficient and cost effective It is designed to be useless.   Some adders (mux3 controlling adder 1, mux4 controlling adder 4, addition Mux6 controlling adder 2, mux2 controlling adder 5, and mux1 controlling adder 1 122) controlling the multiplexing device shown in FIG. 122 or the multiplexing device shown in FIG. For other devices that select one digital output signal from among many digital input signals Therefore, the implemented device is selected.   Adders a1, a4, a9, and a11 are powers of two and are then drawn in Figure 121. The scaling factor being implemented is implemented by a bit shift operation . In FIG. 121, the addition operation of the adder a6, the standardization operation of 1/4 between the adders a6 and a7, The addition operation of the adder a7 and the shifter3 in FIG. It is executed. The input sh3 to shift3 ￥￥ in FIG. 122 is generated by the control circuit, The adder 1 is shifted by 2 to the power of 2 or 2 to the power of 3 as necessary in the calculation.   In FIG. 121, the two addition operations performed by the adders a11 and a12 on the basis of 1/4 are the minimum. During the first clock cycle, it is implemented by adder 1 and adder 2 in the structure of FIG. Is performed. In FIG. 121, the addition operation of the adder a4, the normalization of 1/2 between the adders a4 and a5, Then, the addition operation of the adder a5 is a fixed shift of 2 −2 after the adder in FIG. 122 is performed by the adder 4 and the adder 5 in FIG. In FIG. 121, the adder a9 And the two addition operations performed by adder a10, together with the scaling by 1/2, Executed by adder a4 and adder a5 in the structure diagram in FIG. 122 during one clock cycle Is done. That is, as described earlier, another click other than the operations of a4 and a5 in FIG. 121 is performed. The lock cycle is also executed on the adders 4 and 5 in FIG.   In FIG. 121, the addition operation of the adder a1, the normalization of 1/8 between the adders a1 and a2, and the addition The addition operation of the adder a2 is executed by the adder 2 and the adder 3 in FIG. Control input Shifter3 raises the output of the adder 1 to the power of 2−3 by the force sh3. In FIG. 121, the adder a3 Therefore, the addition operation performed is mux3 set to 1. set to 0 by sel By "1" input to mux3 and by clearing register r8 This is performed as depicted in FIG.   In FIG. 121, the addition operation performed by the adder a8 is performed by the adder 4 and the adder 5 in FIG. It is executed. The addition operation performed by the adder diagram a8 in FIG. 121 is a sum of two terms. Therefore, the input to the adder 4 in FIG. cleared using clr And the output of adder 4 is added to the output from mux2 in adder 5 By doing so, it is kept at zero.   The feedback coefficients C6 and C7 in FIG. 121 are shifter1, shifter2, and shif in FIG. Executed by ter1. These two feedback coefficients are given in Table C19 Are quantized by the shift sum of two terms shown in FIG. A series of 64F clocks are noi Used to generate se shaper circuit 2050. Different blacks in this series In the clock cycle, the values in integrators I3 and I5 in FIG. 121 are supplied to register r3 in FIG. 122. It is. Inputs C6-7 allow shifter1 to read the data in register r3 and C6 and C7 respectively. With a factor of 2−3 or 2−2 as required to implement Shift. The registers r1-r8 of FIG. 122 are the integration stages I1, I2, I3, I4 of FIG. , And is used to hold the value of I5 along with the outputs of adders a3 and a9 . Its value is 256F, and the eight registers in FIG. It will continue to be measured to make the data available.   The feedback term that implements the zero in the transfer equation is equal to the integrator I3 in FIG. It works by multiplying the output by a factor C6 and adding the product to the input of integrator I2. Can be   Similarly, the output of the integrator I5 is multiplied by the coefficient C7 and added to the input of the integrator I4. At different clock cycles in the order of the four 64F clocks, the integrators I3 and I5 in FIG. Is supplied to the register r3 in FIG. Product with feedback filter coefficient C6 The product of the output of the integrator I5 and the output of the integrator I5 is Similarly, it is executed using shifter1 and shifter2 in FIG. Control input C6-7 is suitable Control shifter1 and shifter2 to implement coefficients C6 and C7 when appropriate Used to do. shifter1 is -2 **-3 and 2 **-2 magnification for C6 and C7 respectively Can be switched between operations. shifter2 is 2 **-5 and 2 **-7 times for C6 and C7 respectively Switch between rate calculations available. The product of C6 and integrator I3 is held in register r11 in FIG. 4 used. Then, the product of C7 and integrator I5 is held in register r11 in FIG. 122. You.   The order of the four clock cycles and the operations performed there is provided in Table C20. Provided.     There, each clock cycle is at a rate of 64F.   In the previous paper, assigned to Crystal Semiconductor of Austin, TX, U.S Pat. For "Fourth Order Digital Delta-Sigma Modulator". No.5,196 , 850 include a sigma-delta modulator consisting of a series of cascaded integrators. To implement a single adder with a row of registers connected in series. The use is described. As revealed, the output of the integrator is Must be bundled to produce the output of the digital sigma delta. Current In the invention, the digital sigma-delta modulator uses two sets of adders . Each set contains calculations for the integration stage and outputs for the coefficients and the integration stage. To implement the sum of the quantized output multiplied by the force In this configuration, there are five adders. To calculate 1-bit output Is shown in Table C20. The calculations shown in the circuit of FIG. Assigned to one of the four clocks used to calculate each output value . In table C20, n produces one quantized output 14 shown in FIG. Represents the current order of four clock cycles. Q (n) is a 1-bit quantum Output signal 14 representing the polarity of the output 2022 of the integrator I5 in order n You. Ix represents the value of each of the five integrators I1-I5 in FIG. Where x = 1-5 It is. Description of the operation of table C20 for each clock cycle   In cycle 0, two intermediate values are calculated at the outputs of adders a3 and a9 in FIG. Addition The output of the interpolator a3 is C4 multiplied by the current interpolator I1 output and the 1-bit quantized output 2014. Is the sum of The output of a3 is stored.   The output of a8 is the sum of the current interpolator I3 output and C2 multiplied by 2014. a8 Is stored.   In cycle 1, a new value for interpolator 1 is calculated. Coefficient C5 and scaled input The sum of the output 2014 multiplied by 2012 is scaled by 1/8. The sum is interpolated Is added to the previous value of unit I1. This new value of I1 is stored. Also, interpolator I5 The product of the coefficient I7 is stored.   In cycle 2, the new value of interpolator 5 is calculated. Output 2014 is multiplied by coefficient C1 Is added to the previous value of the interpolator I4. The sum is scaled by 1/4 and before the interpolator I5 Is added to the value of This new value of I5 is stored. In cycle 2, supplementary The new value of the interstellar I5 is calculated. The output of adder a8 previously stored in cycle 0 is In cycle one, it is added to the product of the previously stored coefficient C7 and the output 2014. Or that The sum is scaled by 1/2 and added to the previous value of the interpolator I4. This new I4 The value is stored. In cycle 2, the product of the interpolator I3 and the coefficient I6 is stored.   In cycle 3, the new value of interpolator 3 is calculated. Output 2014 is multiplied by coefficient C3 Is added to the previous value of the interpolator I2. The sum is scaled by 1/4 and before the interpolator I3 Is added to the value of This new value of I3 is stored. In cycle 3, supplementary The new value of the interstellar I2 is calculated. First, adder a3 previously stored in cycle 0 Is added to the product of the coefficient C6 and the interpolator I3. This sum is scaled by 1/2, Added to previous value of interpolator I2. This new value of I2 is stored. This series 4 One cycle is repeated. A series of operations using the noise shaper circuit 2050 in Fig. 122 The calculations made for each of the four clock cycles are shown in Table C21. You. Table C21 contains each clock cycle for noise shaper circuit 2050. The data transfer made in the file is depicted. Used by noise shaper circuit 2050 122 is generated to the outside of FIG. Multiplexer control signal, coefficient C Toggle input to shifters 1 and 2, select between shifters 1 and 2 to select between inputs 6 and C7 Input, input to shifter3, then clear signal for registers rII and r8. Fig. 121 Shifter3 has a 1/8 scaling factor before the integrator (I1) and a 1/4 scaling factor before I3 and I5. Number Used to implement. Shifter3 to scale by a factor of 1/4 Shifts a multi-bit digital signal by 2 bits. To normalize by a factor of 1/8 Next, shifter3 shifts the bit stream by 3 bits. Register r1-r8 is 256F It is measured continuously with a clock. If I5 output signal 2020 (Fig. 121) is less than 0 Then, the quantized output bit signal 2030 in FIG. 122 takes a value of 1.   If the output signal 2020 is greater than or equal to zero, it takes a value of zero. In this way, the output signal No. 2030 is the code of the quantized output bit signal 2014 of the noise shaper block 2010 in FIG. 121. Express the issue.   FIG. 122 shows two groups of data registers arranged in series. . The registers r5-r8 store the output of the adder a8 and the data values representing the values of I2 and I4 in FIG. 121. Is a group of serially configured data registers used to . The output of the adder 5 is passed to the first data register r5 in the serial configuration. Series configuration The last register r8 in the group of data registers is passed as input to mux3 and mux2. It is. Another group of serially configured data registers includes registers r1-r4 In. This group of serially configured data registers is just the output of adder a3. Data values, and the values of the integrators I1, I3 and I5 in FIG. 121. You. The first data register r1 in this group receives input from the output of adder 2. You. The last data register r4 in this group passes its output as input to mux6 . Each of the two groups of data registers arranged in series has two middle There is a data register between them. In the first group they are r6 and r7. Second In the group they are r2 and r3. In the first group, the output of r6 is one Passed to mux4 as input. In the second group, the output of r3 is one input Are passed to mux6 and mux5, and are also passed as one input to shifter1 and adder 3.   The coefficient decoding (coef.decode) block 2032 may be a RAM, ROM, Is another memory storage device, but the output from the coefficient decoding block 2032 is sent to the adder 1. External control circuit to select the coefficients C1, C3, C4 or C5 to be Receive the control signal. If the 1-bit output in Figure 121 or Q (n) is equal to 1 If so, the decryption block 2032 inserts the one's complement multiplication of Cx * (-1) by the selected coefficient. Execute to implement. The Q (n) value in Figure 121 is based on the number of click cycles. Then, as the output of register r9 or r10 in FIG. Is forced. The purpose of mux1 is to make its output 2034 equal to the quantized output of integrator 5, Qn. It is to be. The new value of integrator 55n + 1 still requires the current quantized output Qn. Both are stored in registers r9 and r10, since they are calculated while they are needed. You. In FIG. 122, the input r9 from one control circuit Ten ck is adder 2 in cycle 3 Is latched in the register r9 as Qn + 1. Regis in this same cycle The current Qn of r9 is Latched by the register r10.   As shown in Table C20, during clock cycle 0-2, for mux1 The mux selection signal is set to 0, so that the output of r3 becomes the mux1 output signal 2034. Passed. During clock cycle 3, the mux select signal for mux1 is set to one. As a result, the output of r10 is passed as the mux1 output signal 2034. mux1 out Force signal 2034 to complete the two's complement of the selected coefficients C1, C2, C3, or C5 Is used as carry-in (cin) 36 to the adder 1.   Many operations in table C21 are implemented in noise shaper circuit 2050 in FIG. The common hardware is integration and multiplication of noise shaper block 2050 in Figure 121 , So that the addition function can be executed. For example, cycle on table C21 At zero, the coefficient C4 from FIG. 121 is prescaled by 4 and then C4 * 4 It is stored in FIG. 122 and then scaled by 1/4 in shifter3 of FIG. 122. This operation , Shifter3 is the integration stage I1, I3, or I5 from FIG. As shown, whether or not it was performed by the implementation in Figure 122 The shift required by shifter3 so that the signal can be scaled by 1/4 or 1/8. Is performed to reduce the number of   In cycle 0, a fixed multiplication coefficient of 1/2 is executed by the adder a4 output signal 2042. To compensate for this, the value of register r1 is set to 2 before r1 output signal 40 enters mux. It is put on the standard of. Thus, the five stages of integration shown in FIG. All of (I1-I5) is achieved by the hardware shown in FIG.   In the cycle 0, the outputs of the adders 2 and 5 in FIG. 3 and the output of the adder 8. Fig. 122 The sum of the adder 2 is calculated by the coefficient decoding block 2032. This is the result from the input C4 that selects the coefficient C4 * 4. Coefficient C4 is implemented in shifter3 The common coefficient of 1/4 is stored as C4 * 4 to allow for other calculations. mux The output at 3 is a 0 from register r8. That r8 is r8 Cleared by clr. Addition The output of arithmetic unit 1 is equal to Qn * C4 * 4. With input sh3 = 0, shifter3 is the result of Qn * C4 1 Shift this value by 2 for a factor of / 4. The output of the integrator 1I1 in FIG. 122 is in the register r3. Input mux6 sel = 1 and Fig.122 adder The output of No. 2 is the output of a3 in FIG. 121 and is equal to I1n * C4 * Qn. This value is then Stored in the register r1. In cycle 0, the sum of the adder 5 in FIG. sel = 0 , Mux4 sel = 1, r11 This is the result from clr = 1. This r11 clr = 1 is the integrator I of FIG. The output of the adder 4 in FIG. 122 is made equal to the value of the register r1 which is the output of 3n. Adder The output of 4 is reduced by 1/2, mux2 Added to Q2 * C2 from sel = 0. Figure 122 Adder The output of 5 is the output of FIG. 121a8. This value is then stored in register r5.   In cycle 1, the output of adder 2 of FIG. 122 is the new output of integrator 1I1n + 1 of FIG. is there. Input c5 and mux1 sel = 0 selects coefficient decoding block 2032 and follows Qn2034 To output the coefficient C5 or -C5. There it is added to the input value. With input sh3 = 1 , Shifter3 shifts the output of the adder 3 by 3 for a 1/8 coefficient. Input mux6 se l = 0. The output of shifter3 is the register that holds the current output of integrator 1I1n in Figure 121. Add to r4. The output of the adder 2 in FIG. 122 is the new output of the integrator 1I1n + 1 in FIG. is there. This value is then stored in register r1. In cycle 1, FIG. The output of 2 shifter 2 is the feedback from integrator 5I5n to FIG. 121a9. Entering Force C6 By 7 = 1, the value I5n of the register r3 in FIG. Multiplied by the coefficient C7 using The one's complement of C7 * I5n is stored in register r11. It is. When this term is used in cycle 2, the carry to adder 4 in FIG. Input signal r11 The use of ck gives the two's complement. In cycle 1 , The output of FIG. 122 is not used.   In cycle 2, the output of adder 2 of FIG. 122 is the new output of integrator 5 I5n + 1 of FIG. It is. Input C1, mux3 sel = 1 and mux1 sel = 0 selects coefficient decoding block 2032. And outputs coefficient C1 or -C1 according to Qn2034. So it is the register in Figure 122 It is added to the value of integrator 4 I4n in FIG. When input sh3 = 0, shifter3 is 1/4 Shift the output of adder 1 by 2 with respect to the number. Input mux6 sel = 0. shifter3 output Is added to a register r4 having the current output of the integrator 5I5n in FIG. Figure 1 The output of adder 2 of 22 is shown in FIG. This is a new output of 5I5n + 1. This value is then stored in register r1. Also In cycle 2, the output of the adder 5 in FIG. 122 is the new output of the integrator 4 I4n + 1 in FIG. It is. input mux4 from r6 mux2 from sel = 0 and r8 sel = 1 is the register in Figure 122 The output of the adder a8 previously stored in FIG. 121 is selected from the output of the In addition to the feedback previously stored in FIG. Output of adder 4 The force is shifted by 1 by a factor of 1/2 and applied to the integrator 4 I4n of FIG. 121 in register r8 of FIG. available. FIG. 121 The new value of the integrator 4 I4n + 1 is stored in the register r5.   In cycle 2, input C6 7 = 0, the integration of Figure 121 in register r3 of Figure 112 The unit value I3n is multiplied by a coefficient C6 using the term shown in Table C19. . The one's complement of 67 * I3n is stored in register r11. This term is used in cycle 3. When the input signal r11 is carried as a carry to the adder 4 in FIG. to use ck Thus, a two's complement is obtained. After the new Figure 121 integrator 5I5n + 1 output is calculated In order to measure the value Qn in the register r10 and the value Qn + 1 in the register r9 in the next cycle, Input r9 Ten ck changes from 0 to 1.   In cycle 3, the output of adder 2 in FIG. 122 is the new output of integrator 3I3n + 1 in FIG. is there. Input C3 and mux1 sel = 1 selects coefficient decoding block 2032 and follows Qn2034 To output the coefficient C3 or -C3. So it's Figure 122 Integration in Figure 122 register r8 2I2n. When input sh3 = 0, shifter3 adds 2 for 1/4 coefficient The output of the unit 1 is shifted. Input mux6 sel = 0. The output of shifter3 is the integrator 3 in Figure 121. Add to register r4 which has the current output of I3n. Output of adder 2 in FIG. 122 Is the new output of the integrator 3I3n + 1 in FIG. Then this value is stored in register r1 It is memorized.   In cycle 3, the output of the adder 5 in FIG. 122 is the new output of the integrator 2 I2n + 1 in FIG. Output. Input mux4 sel = 1, muz5 sel = 1 and mux2 sel = 1 is the register in Figure 122 The output of the adder a3 previously stored in FIG. 121 is selected from the output of the In addition to the feedback previously stored in FIG. Output of adder 4 The force is shifted by 1 by a factor of 1/2 and applied to the integrator 2I2n of FIG. 121 in register r8 of FIG. 122. available. Figure 121 The new value of integrator 2 I2n + 1 is It is stored in the register r5.   As can be seen by carefully reading table C21, noise shaper block 20 in FIG. The operation here in 10 is implemented by the calculation formula of table C21. D.Playback Semi-Digital Filter (SDF)   Semi-Digital Filter 804 is the last elementary stage of CODEC playback DAC 514, Sample for a 16-bit input signal 806 that is the input to the block 800 (FIG. 51). Filter the 1-bit signal 842 at 64 times the rate and convert the 1-bit signal 842 to an analog signal. Signal output signal 808. Semi-DigitalFilter804 coefficient should be a positive value if possible It is desirable that the ratio between the maximum value and the minimum value is 40 or less. Figure 77 shows the impulse response FIG. 78 shows the frequency response of the Semi-Digital Filter 804. . Semi-Digital Filter 804 performs the following functions: 1) A single digital signal Convert to a analog signal. 2) Filter high-frequency noise created by noise shaper802 Luta out. Semi-DigitalFilter804 has D / A conversion function and analog low-speed filter Data function. By doing so, high frequency noise can be Remove distortion.   The Semi-Digital Filter 804 includes a shift register 850 (FIG. 79). data Tap 853 is the input point to a series of flip-flops 852 in shift register 850 It is in. The logic state of each data tap 853 is coupled to the corresponding data tap 853 Used to switch current sink 855. The value of the current sink 855 here is Represents the coefficients used to produce the desired impulse for the filter I have. All current sinks 855 use opamp 854 and resistor856 They are combined and converted into one voltage.   Shift register 850, which is preferably a 107-bit long shift register I made a digital delay line. Thus, each flip flop 852 is 1 Represents the unit delay. That way, if the input to shift register 850 is x (k) If present, the first data tap 853 has the same value as x (k) but is delayed by one clock unit Thus, the next data tap 853 is represented by x (k-2), and so on. Before As noted, individual data taps 853 control individual current sinks 855. Like this Thus, the total current, IOUT857, is equal to the sum of the respective current sinks 855. this is , Represented by the following equation:   The op amp 854 and the resistor 856 convert the current IOUT857 into a voltage output signal VOUT858. This is represented by the following equation:   The coefficient of the Semi-Digital Filter 804 is determined by the value of each current. Current The value of each coefficient represented by link 855 is not a function of 1-bit signal 842. So The function of helps maintain the linearity of the structure.   In another configuration shown in FIGS. 80 and 81, two different currents, IOUT857 and IOU T * 859, is used. There are only two 1-bit signals 842 output from noises haper802 Value: take logic1 and logic0. For each bit of shift register 850, If logic1 exists, the current sink 855 corresponding to that bit is connected to the IOUT line. It is. If logic0 is present, the current sink 855 corresponding to that bit is the IOUT * line Connected to The following is an example of a Semi-Digital Filter with two taps is there. In this example, there are four possibilities, as shown in table C14.   There are two things to note about table C14. First, the current sink Since the data tap can be used and only the value of 0 and 1 can be made with Turkey, UT857 and IOUT * 859 are positive or zero. Thus, the Semi-Digital Filter There are built-in DC offsets that must be excluded. In the previous example, IOUT857 And IOUT * 859 take values from 0 to I0 + I1. As a result, the unique DC offset is IO Present in UT857 and IOUT * 859. These two bit examples have a value of (I0 + I1) / 2. ing. The DC offset in this example is a fixed amount of current (I0 + IOUT) from IOUT857 and IOUT * 859. 1) effectively exclude by subtracting / 2 be able to. Eventually, the effective IOUT85 7 and IOUT * 859 current are as shown in Table C15.   In Figures 80 and 81, two offset current sources, 880 and 882 exclude intrinsic DC offset Have been used to Current source IOFFSET * 880 is the total current node 88 of amp1 1860 Connected to 4. Current source IOFFSET882 connected to sum current node 886 of amp1 2861 Have been. The values of the current sources IOFFSET * 880 and IOFFSET882 are (I0 + I1 + ... + In) / 2.   For each shift register data tap combination, IOUT * 859 is IOUT Has the same amplitude and opposite sign as 857. Distortion and common mode as differential structure Noise is reduced. The differential current is then applied to a pair of op amps, op amp1 860 and op a Converted to voltage by mp2861. Each has a resistor resistor as shown in Figure 81. It has feedback 862 and storage device 865, and voltage signal DACOUTA 863 is DACOUTB864 Is made. The high frequency is in parallel with the resistor 862 corresponding to amp1 860 and amp1 861. Excluded by the livestock electronics 865. The differential voltage DACOUTA-DACOUTB is a resistor 872 , 874, 876, and the differential single-ended conversion circuit including the 878 and the op amp3 870. Thus, the signal is converted into a single-ended voltage output signal VOUT858. positive to op amp3870 The input is coupled to a reference voltage VREF through a resistor 878. This reference voltage is For example, it is desirable to be ground, but an intermediate voltage between VCC and ground may be used. E.CODEC Recording ADC architecture   The CODEC recording ADC 516 (Fig. 82) changes the sampling rate of the input signal from 64xf to f. While reducing (where f is the output sampling rate), the CD quality (90 dB Maintain a high signal-to-distortion ratio (STD) compatible with (higher) speech. Record The ADC 516 uses a decimal filter block 902 to convert the 64x oversampled signal by 64. Reduce the oversampled audio signal so that it is unsampled. The following reduction process To reduce the circuit complexity by using coefficients of 16, 2 and 2 respectively. This is done in three stages within the decision filter block 902.   82 and 83, recording ADC 516 receives analog audio signal 906 as input. this The signal is 64xf oversampling rate according to fourth order Σ- △ A / D900. The signal is converted into a 7-bit signal 908 by the default (64x oversampling). decimation f The ilter block 902 receives the 7-bit input signal 908 and has a sampling rate f Produces a 16-bit output signal 910.   The spectrum of the sampled analog input signal 906 has frequency components up to f / 2. And the image is clustered near an integer multiple of 64xf. Here, Force signal 908 is banded by an anti-aliasing filter in the recording path before Σ- △ A / D900. It is assumed to be band limited (filter out high frequencies). Wrap prevention Filter is installed by the user on the Mixer606 or somewhere in front of the Σ- △ A / D900. You may tall.   The output spectrum of the recorded ADC 516 is shown in FIG. 84 up to 64 × f / 2. Passband details (4KHz in this case) is shown in FIG. Decim.1 914 changes the first decision to f = 4xf (16 Sinc filter is used to execute up to the decimation coefficient. Decim. The output spectrum of 1914 is shown in FIG.   The next decision stage Decim.2 916 increases the sample rate from f '= 4 to f ″ = 1 / 2f' = 2 Change to f. Half band filters are used with stopband attenuation of approximately 100 dB. The spectrum of the output is shown in FIG. Last Decimation Stage Decim. 3918 Changes the sample rate to f ′ = f with a coefficient of 2 using a linear phase filter. This stay The filter is an equiripple FIR filter with a passband broadened to approximately 0.45f and a 0.55f It consists of stop bands starting with f. Stop band attenuation of Decim.3918 is 100 dB or more. Therefore, the stop band ripple is +/- 0.1 dB or less. As a result, the frequency below 0.45f Numbers guarantee no wrapping. F.Additional explanation of processing block 1． Decim.1 Stage   decimator is a sinc integrator-comb filter, implemented as shown in Figure 89. Has been mentioned.   All register 920 shown in FIG. 89 have the same MSB weight (this is the input word length). Depends), the decision factor (16), and the order of the decimeter (6). This time Is that Decim.3 914 correctly represents all possible input levels in output signal 915 You have been chosen to be able to. Here, saturation is performed and the maximum analog input Get closer to power. LSB truncation is done using known methods. The indicated bee The cut length is kept around 120dB STD. Register 920 implemented as RAM If done, they will all be the same length.   Each integrator includes a summing node 922 and a delay block 920. 64xf integrator Works at high rates. Each differentiator 924 has a differential node 923 and a delay block 920. Contains. Differentiator 924 operates at a low rate of 4xf. 16 generated by integrator 921 Operates on one of the samples. The transfer functions performed in this block are: The frequencies are shown in FIG.   The response is not flat in the pass band. Roll-off details are shown in Figure 91 . 2． Decim.2 Stage   The second decimator, Decim. 2916, is a half-band linear phase FIR filter. This file The filter has a stop band of the same size as the pass band. Stop ripple is 100dB Filter must be flat in the passband because it is very low to ensure attenuation There is. This filter has the impulse response with all other coefficients equal to 0. There are characteristics. However, the middle coefficient is equal to one.   Decim.2 when configured as one decimal by two filters 916 is structured into two basic types. The first is the modification "direct", the structure shown in Figure 92 become. The second is obtained by inverting the first signal follow graph in the replacement form. 93 is shown in FIG. In FIG. 93, C1-C5 are coefficients, and the coefficient of xnm1 is equal to 1. individual Multiplier 925 multiplies the same input signal sample by the individual filter coefficients C1-C5 It is. The delay block 926 and the total nodes 927 and 928 are connected as shown in FIG. Person in charge The outputs of the individual multipliers 925 for the numbers are passed to summing nodes 927 and 828. Coefficient C1 Is passed to the delay block 926 and the summing node 928. Replacement of Figure 93 The structure has several advantages other than the direct advantages of FIG.   ・ Minimum delay   All processors can run at low rates The frequency response performed by the Decim. 2916 filter is shown in FIGS. The coefficients for Decim.2916 are as follows: 3． Decim.3 Stage   Decim.3 916 is a symmetric FIR filter. 100dB reduction in stopband It is designed to have decay and a ripple of +/- 0.1dB or less in the pass band. flat So that the bandpass filter is followed by a compensation filter Is designed. The frequency response of the half-band Decim.3 918 is shown in Figures 97 and 98. You.   When used as a decimator, Decim.3916 filter 918 has two samples Calculate one sample each time there is an input. In Figure 93, all filters are data Replacement half-band to operate at lower sampling rates including tap correction Structure is adopted.   Decim.3916 has a linear phase characteristic, which impulse response is It guarantees that there is. Where the symmetry condition is hk is a filter coefficient. If possible, N is odd and N has different symmetry conditions Desirably, it is even.   The symmetry condition where N is an odd number is reflected in the structure of Decim.3 916 filter 918. This is similar to that of FIG. In this structure, the block flow point method can be used. I can't. It can be used with the direct form shown in FIG.   The first 30 coefficients for the 916 filter 918 are listed. Half bandwidth filter Filter's response is stored in Table C17 using the coefficients listed in Table 17. Inserting zeros between the individual coefficients listed, as shown in Table C17 Similar to the format, it can be obtained after the intermediate coefficients have been reduced to one. Four. Compensation filter   Nyquist FIR compensation filter 904 (FIG. 53) can be coupled to the output of Decim.3916. Ma The sinc Decimator filter Decim.3914 provides a smooth response and gain compensation. Used to compensate for the roll-off introduced to provide compensation. FIR Filter 904 includes a series of multipliers 930. This is because the compensation input signal 910 and the compensation It is obtained by multiplying each of the filter coefficients C1-C4. The product of each multiplier 930 is Input to the total node 934.   The compensated audio output signal 912 (FIG. 96) is a 16-bit signed digital audio signal. Passed to the format conversion block 536 (FIG. 44) and the overrange detection circuit 913. It is. In the overrange detection circuit 913, the amplitude of the compensation output signal is , Detect whether output bits B0 and B1 are set. These bits are Used by the user to adjust the gain of the audio signal being detected . However, users must know how. Appropriate attenuation / gain control The circuit can be programmed to increase or decrease the signal amplitude.   The compensating filter 904 operates on the Nyquist rate, and only requires seven data taps. It is also a shape phase. It requires four coefficients. Decim after compensation filter 904 The frequency response of the ator is shown in FIG. Full for decimeter in passband The frequency response is shown in FIGS. 100 and 101.   Compensation filter 914 performs the following transfer function. : Here, “freq” is a normalized frequency.   The impulse response coefficients for the compensation filter 914 are as follows: V. Synthesizer module   A. Synthesizer module overview   This section gives an overview of the synthesizer module. Synths introduced in this section Various aspects of the sizer module are discussed in detail in the next section.   Synthesizer module includes 8 delay based effects and 32 high quality A wavetable synthesizer that can generate an audible digital signal or voice is there. Synthesizer module with tremolo and vibrato for any sound Effect can be added. This synthesizer module is Provides several improvements to the synthesizing table, and previously unavailable features Provides power enhancement.   Figure 102 shows the synthesizer module and local memory control module. Interface with the system control module 2 and the system bar of the system control module 2. Interface 14, CODEC module 4, and synthesizer DAC FIG. Furthermore, the logic inside the synthesizer module 6 4 shows a signal flow.   During each frame, which is about 22.7 microseconds in duration, the synthesizer Module 6 produces one digital output on each side. 32 for each frame Where each data sample (S) of the 32 possible voices is It is processed separately through the signal path shown at 102.   For each voice processed during a frame, the address generator 1000 Generates the address of the next data sample (S) read from the motion table data 1002 Let it. The wavetable address for data sample S includes an integer and a fractional part. Integer part The minute is an address for data sample S1, and data sample S2 is an address Is incremented by one to determine The fractional part is used to interpolate the data sample S The distance from S1 to S2 is specified. Based on this address, the interpolation logic 100 4 are two data samples S1 and S2 to be read from the wavetable data 1002. Cause. Wave table data is stored in a local dynamic random access storage (DR). AM) and / or read-only storage (ROM). This data , The interpolation logic 1004 extracts the data sample S. This interpolation process will be described in detail. Wavetable data can be compressed by μ-method. μ-law pressure In the case of compression, S1 and S2 control the signal path of the synthesizer module discussed below. It is scaled down before interpolation.   After generating each data sample S, the volume generator 1012 generates an envelope, low frequency Add shaker (LFO) fluctuation, right offset, left offset, and sound effect Generate a data sample to be multiplied by the three volume components. Left and right offset Provides positioning of the stereoscopic view, the effect volume is used when generating the echo effect , LFO fluctuations in volume add trelmo to the voice. LFO generator 1021 is LF O fluctuation is generated. As described in detail below, LFO generator 102 1 changes the LFO at the wavetable addressing ratio to add vibrato to the voice Used to generate. LOUT1006, ROUT1008, EOUT 1010 is the output resulting from the data sample S multiplied by the three volume components.   LOUT1006 and ROUT1008 are the left and right accumulators 1014, 1 016. If effect processing is occurring, EOUT1010 Sum to one of the effect accumulators 1018. All audio in the frame is processed After processing, the left 16-bit width and the right 16-bit width (total 32-bit width) ) Is converted from the parallel format by the converter 1019. Converted to serial format.   After conversion to serial format, the data in the left accumulator and the right accumulator Synthesizer DAC Interface Circuitry 10 25 can be output in series. Synthesizer DAC interface -Kitley 1025 has synthesizer module 6 with synthesizer DAC5 Connect 12 The interface circuitry is: (i) clock divider Control logic (not shown) for controlling circuitries and clock dividers; (Ii) A clock generation server for clocking the operation of the synthesizer DAC512 Kitley (not shown); and (iii) a serial-to-parallel converter (not shown). You. See also FIG. Clock Divider Circuitry And submitted here for reference. Hazard-free Div. US by David Suggs, entitled "ider Circuit") Patent application Serial No. Is described in   The serial-to-parallel converter in the interface circuit 1025 is an accumulator. Data to a parallel format, and convert this parallel data to an analog signal. To the synthesizer DAC 512 for conversion. Synthesizer DAC512 Preferably comprises the same circuitry as the CODEC playback DAC 514. The output of the synthesizer DAC512 is the analog mixer of the CODEC module 4. -606 (FIG. 45), the left synthesizer DAC MUX649 As the left analog input (also not shown, the right synthesizer DA (As right analog input to C MUX). To play the generated sound Applying the resulting analog signal to audio amplifiers and speakers Can be. See Section IV. See CODEC module.   Each effect accumulator 1018 may have any of the , Or collect all effect data, without having to collect any data Good. The data stored in the effect accumulator is the wave table data that is read later. Are written back as data. The effect accumulator 1018 is one sound to another sound Store a value that is longer than one speech processing time that allows signal flow to the voice.   The accumulator data of left 16-bit width and right 16-bit width are serially In a format, the serial trace of the CODEC module 4 is output through the serial output line 1020. It can also be output to the transfer control block 540. Accumley External data through the serial transfer control block 540. It can be output on line 1023 to Alport 798. See the section IV. See CODEC module. Test equipment, external DAC, or digital A signal processor can be connected to the external serial port 798. Siri Input data through the external serial port 798 and the synthesizer DAC Line to Interface Circuitry 1025 1047 to the serial-to-parallel converter in the interface circuitry. Convert to parallel format, then send to synthesizer DAC512 it can.   Synthesizer registers 1022 are programmed to govern each audio processing Included parameters. This section on the synthesizer module We will refer to these various registers through See Section V. N. The details are discussed in the register. Voice parameters Is a register data buffer with programmed input / output (PIO) operations. Register 1024 is programmed through register 1024.   FIG. 103 illustrates a signal flow during sound generation and effect processing. register When the bit EPE of the SMSI is set to zero (SMSI [EPE] = 0), the thin The synthesizer module 6 acts as a signal generator and produces a sound or Is recorded from the wave table data 1002 contained in the local ROM or the DRAM. Play back the data. For local memory, see Section VI. local It is discussed in detail in the memory control module. Wave table data 10 02 addressing rate controls the pitch or frequency of the generated audio output signal. I will. The address generator 1000 controls this addressing rate, which is It also depends on the LFO fluctuation. In FIG. 103, the reference numeral FC (LFO) is LFO. Frequency control that depends on variation (that is, affects the pitch or frequency of speech (Wave table addressing rate). LFO fluctuations add vibrato to audio You.   After the wave table data 1002 is addressed and the data sample S is interpolated , The data samples are sent through three multipliers as shown in FIG. De When a data sample passes through any of the three volume multipliers, three Multiplied by two individual volume components.   The first volume component is VOL (L). (L) is this volume under register control This shows that the components can be looped and tilted. The second volume component is V OL (LFO), which gives a volume LFO variation. LFO fluctuations in the volume Give Remolo. As shown, VOL (L) and VOL (LFO) After multiplying the components, the audio signal path is split into three, each with three volume multiplier paths . The top two paths generate stereophonic left and right data output for audio.   Stereophonic positioning of audio can be controlled in one of two ways: : (I) one pan value, placing the signal in one of the 16 pan positions from left to right Or (ii) where in the stereo field Also, separate the left and right offset values, ROFF and LOFF, to place the audio. You can ram. ROFF and LOFF affect full volume output Can also be used. The left and right volume outputs for this audio are then generated during the same frame. And the sum of all the left and right outputs of the other voices. Left and right outputs collected for the frame The force is then output to the synthesizer DAC 512 of the CODEC module 4.   EVOL (effect volume) controls the volume of the third signal path. This third signal path For effect processing. Effect data for any or all effect accumulators 1018 or not to any effects accumulator You may not. Each of the eight effect accumulators 1018 has a total Total audio output.   When bit EPE of the register SMSI is set to 1, the synthesizer module Module 6 acts as an effects processor. During this effect processing module, The synthesizer module 6 is used to control echoes, residual sounds, chorus and flanges An effect based on the delay can be generated. Audio is specified for effect processing If so, the data is stored in one of the eight effect accumulators 1018. After that, the synthesizer module 6 writes the data to the wave table data 1002. Put in. The current write address for this data is the synthesizer effect address register. Set to star. The current read address for all audio to be generated is This is the value in the synthesizer address register. Write address and read address Les differences provide a delay for echoes and aftereffects. Write address is always 1 Only incremented. The read address is incremented by an average of one, but appended by the LFO. It can have a given time variation. These LFO fluctuations cause chorus and flange Create an effect.   After reading the delay data, multiply the data by the volume components in the left and right To determine if such amount of delay data is cut off and the stereophonic position of the output . The audio signal path through the EVOL to the effect accumulator 1018 is Selected by setting the bit AEP in the data SMSI. SMSI [ [AEP] is not set, the synthesizer module 6 enters the sound generation mode. Yes, before the interpolated data sample S is output to the synthesizer DAC 512, Does not move through the effect processing path.   Synthesizer module 6 waves from one of the effect accumulators 1018 Data samples are written to table data 1002 and later After reading one, if the SMSI [AEP] is set, the data sample It can be sent back to the effect accumulator 1018. Data sample is effective When sent back to accumulator 1018, the volume will be Can only be attenuated. Data sample sent back to the same accumulator Provides a delay in the volume of the data sample to create an echo effect if EVOL can be used for this.   B. Sound generation   Synthesizer module 6 (Synthesizer global mode register (Controlled by the bit ENH in the uplift mode) Module 6 generates up to 32 voices at a constant 44.1KHz sample rate Can be done. The bit DAV of the register SMSI is used to process a specific voice. To control whether If bit DAV is set to 1, specific audio will be processed Will not be. When no audio is processed, the synthesizer module 6 Without updating any of the register values, the local memory control module 8 Will not require memory cycles from. Unused to save power Audio is not processed and other local memory control memory Eliminate Molly cycle restrictions.   When not in the uplift mode, a sample rate of 44.1 KHz will result in up to 14 active sounds Will only be maintained for voice. When the 15th sound is added, almost 1 . Add 6 milliseconds to the sample period and increase the sample rate of 41.2 kHz. Will result. For a more detailed description of frame enlargement, see the section VI. See local memory control module. 19.4KHz This same process continues when adding each voice up to 32 voices at a sample rate of . When sound generation is not performed in the uplift mode, the following equation is used to determine the sample rate. You can use:         Sample period = AV. 1.6 μsec Where AV equals the number of active voices, which is the synthesizer active voice register Controlled by AV may be in the range of values from 14 to 32. Sump If the audio rate changes, adjust all audio frequency control values to maintain the true pitch of the sound Must. Slow sample rates reduce audible quality. However, The option with this mode is when the synthesizer module 6 Make it fully compatible with the synthesizer. Quoted here for reference, "Wave Table Synthesizer" by Traverse et al. ("Wave Table")   Synthesizer "), in U.S. Patent Application Serial No. See 072,838.   C. Address control   Sound generation is at the position programmed in the synthesizer address register At the address generator 1000 that addresses the wave table data 1002 Start. The calculation of the next value stored in the synthesizer address register is 4 bits. Set: ENPCM (Modulated Enable Pulse Code), LEN (Loop Enable) ), BLEN (bidirectional loop enable) and DIR (direction) It is. LEN, BLEN and DIR are synthesizer address control registers Stored in the star. In essence, setting one or a combination of these bits The synthesizer module addresses through a block of wavetable data Then stop or let the synthesizer module loop through the data blocks. Or the synthesizer module is passing data forward or backward through the data. Decide whether to specify the dress. FIGS. 104a-104f show six addressing controls Options: (i) one pass in the forward direction; (ii) one pass in the reverse direction; (iii) forward (Iv) looping in the reverse direction; (V) two-way looping; and (vi) PCM playback. Show Thus, when enabled, each time an address boundary is crossed, an interrupt is generated . Address boundaries are defined by the synthesizer address start register and the synthesizer address. Address end register.   Digitally store any length of sound using a small fixed amount of storage Use ENPCM in synthesizer volume control register to play be able to. ENPCM interrupts the address control logic at an address boundary But continue to move addresses in the same direction without being affected by address boundaries. So that you can   A standard player that plays digitally recorded sounds with the synthesizer module 6 The law is as follows:         1. Add the first block of recorded data using DMA or PIO The data is stored in the local memory from the address START to the address END1.         2. START and END1 are set as address boundaries, and ENPCM = The audio processing is started by setting 1, LEN = 0, BLEN = 0, and DIR = 0.         3. Address the next block of recorded data using DMA or PIO END1 to an address END2.         4. When the audio causes an interrupt due to crossing END1, the address The data boundary is changed from END1 to END2, and LEN = 1 is set.         5. Add the next block of recorded data using DMA or PIO The data is stored in the local memory from the address START to the address END1.         6. When the audio causes an interrupt due to crossing END2, Change the data boundary from END2 to END1 and set LEN = 0.         7. Steps 3 to 6 are repeated until the reproduction of the recorded data is completed. De Using the synthesizer module 6 as a digital mixer, The above steps can be repeated for sound reproduction.   Further, the address generator 1000 controls the write address for effect processing. . When programming audio for effects processing, the write address is the read address Will form a loop between the START and END address boundaries. Present The current write address is stored in the synthesizer effect address register. Would. The effective mode of looping for write addressing is FC = 1, LE N = 1, BLEN = 0 and DIR = 0. Rubin for read addressing The mode of FC is FC = 1, LEN = 1, BLEN = 0, ENPCM = 1 and DI R = 0. Current write held in synthesizer effect address register Address and the current read address held in the synthesizer address register. The difference between wrestling sets the amount of delay for the effect. Distance between START and END address boundaries Sets the maximum delay available for release.   FC (LFO) determines the rate of increase or decrease of the synthesizer address register. Control. FC (LFO) is composed of components FC and FLFO. FC is a synth This is the value programmed into the sizer frequency control register. FLFO is LFO This value is modified by the synthesizer frequency LFO register. It is memorized. FLFO is added to FC before address calculation. FLFO If it is a signed value and FLFO is negative, the pitch of the sound will decrease, while F If the LFO is positive, the pitch of the sound will increase.   The table below shows all combinations of wavetable addressing and internal flags BC (intersection boundaries) Affects the next wavetable address. (END- (AD D + FC (LFO))) is negative and DIR = 0, or ((ADD− When FC (LFO) -START) is negative and DIR = 1, BC becomes 1. Wavetable interrupt request (IRQ) energy in the synthesizer address control register When enabled by an event, condition BC = 1 causes an interrupt. Ne The xt ADD column uses ADD, FC (LFO), START and END Shows the formula used to calculate the next address. ADD is a synthesizer This is the value contained in the Ether Address Register. START and END are synths Sizer start address register and synthesizer end address register This is the address boundary for address looping included in the address.   Bit ENH of register SGMI is equal to zero, LEN = 1, BLEN = When 0, if the data at the END and START addresses are not the same, Discontinuities within the signal can occur. Data addressed by END address And there is no interpolation method between the data addressed by the START address , A discontinuity occurs. SGMI [ENH] = 1, SACI [LEN] = 1, SACI [BLEN] = 0, SACI [DIR] = 0, and SVCI [ENPC M] = 1 is the combination between END addressing data and START addressing. Enable the data synthesizer module to interpolate. Digital audible playback And use this new interpolation mode during effects processing. In this new interpolation mode, E ND until the addressing data is no longer needed for interpolation. Interrupts that normally occur when crossing dresses are not generated.   When the SMSI [ROM] = 0, the synthesizer module 6 has 8-bit and 1 Use of an 8-bit wide DRAM to obtain 6-bit data samples. Can be. For audio using 8-bit data, in the address register All addresses represent the actual address space. Actual address space Indicates an adjacent DRAM address space. Sound using 16-bit data For voice, the address from the address register to the actual address space Conversion is performed. The conversion is performed by the synthesizer module 6 in the same way as 8-bit. Enables generation of addresses for 16-bit data and allows local memory Control module 8 accesses the two 8-bit values to provide a 16-bit sample. Enable DRAM first page mode to provide pull You. For address translation, see Section VI. Local memory control This will be described in the module.   When the SMSI [ROM] = 1, the synthesizer module 6 has 8-bit A 16-bit wide ROM can also be used to obtain 16-bit data samples. Wear. For audio using 8-bit data, the least significant bit of the address ( LSB) is maintained internally and which byte of the 16-bit wide ROM word is used. Decide what to use. If LSB = 0, the lower byte of the word is sampled If LSB = 1, the higher byte of the word is used . For audio consisting of 16-bit data, address generator 1000 directly Address the ROM.   D. μ-law expansion   Μ-law compression of wave table data to save local memory space can do. Before interpolating the data, the synthesizer module 6 Expand bit μ-law data to 16-bit linear data. Synthesizermo The ULAW bit in the module select register is set to 1 and the μ-law data Enlarge the data. μ-law expansion is based on the synthesizer signal path described below. Is controlled. To convert μ-law data to 16-bit linear data The algorithm used is specified by the IMA compatibility project. Reference IMA Compatibility Project, cited here for , Proposal for Standardized Audio Int update Formats (IMA Compatibility Project, Standardized Proposal for Audio Interchange Format, Version 2.12 (1992) April 24).   E. FIG. interpolation   During audio generation, interpolation logic 100 in the synthesizer module signal path (described below) 4 is the address specified by the integer part of the synthesizer address register. In step S1, a sample S1 is captured from the wave table data 1002. Then the integer part The minute is incremented by one and a sample S2 is captured from the wavetable data 1002. Supplement To obtain the interleaved sample S, the interpolation logic 1004 uses the synthesizer address Use samples S1 and S2 together with the fractional part of the register (ADDfr). S Use the following equation to derive The interpolation process is a 10-bit interpolation. Exactly 10-bit for 1024 divisor Must be multiplied by Thus, there is a possibility between samples S1 and S2. 1023 additional data samples can be interpolated.   F. Volume control   Control of automatic volume control device 1012 and signal path of synthesizer module (described later) Below, using three volume multiplying signal paths, the envelope, LFO variation, right offset, A left offset and an effect volume are added to each sound. See FIGS. 102 and 103 . The three signal paths are left, right and effect. In each signal path, three volume components Multiply each voice. After calculating the three components, they are summed and the sound of the three signal paths Used to control the amount. Below are three volume equations for each of the three signal paths Shown in The terms of the formula are defined below.     (1) Volume left = VOL (L) + VOL (LFO) -LOFF     (2) Volume right = VOL (L) + VOL (LFO) -ROFF     (3) Volume effect = VOL (L) + VOL (LFO) −EVOL, S When MSI [AEP] = 0     Note: Volume effect = EVOL, SISI [AEP] = 1. In other words, Synthesizer module 6 switches to alternate effect path mode (SMSI [AEP] = 1) At one time, the volume of a data sample can only be controlled by EVOL before it is output Can be adjusted. V. I. See Effect Volume EVOL.   The exact formula for volume multiplication is: Where O is the output data, V is the volume value, and S is the interpolated data sample. Value. The increment from 1 to V is about 0.0235 dB change in output O Cause. This formula must be implemented directly in digital logic for exponential terms Is difficult, but piecewise linear approximation is relatively easy to perform. The sum of each volume is 1 2-bit value. The 12-bit value is a 2-bit field, V [11: 8] and V [7: 0]. V [11: 8] and V [7: 0] bit fields Is used to provide the following volume multiplicative approximation:   This equation is used three times to obtain the right audio output, the left audio output, and the effect output. The error introduced by approximation for 0 ≦ V ≦ 4095 is 0 dB to 0.52 dB And the average is 0.34 dB. The difference in power below 1 dB is Error cannot be perceived if output electricity is performed by approximation because it cannot be perceived . After generating all volume components, sum them for each multiplied signal path volume I do.   Advances or reverses the VOL (L) component of the volume, or sounds in two directions Can be looped between volume boundaries, or ramped up and down to volume boundaries May just be. The VOL) L) component is for adding an envelope to speech. . The next value stored in the synthesizer volume level register is calculated in three bits. G: LEN (loop enable), BLEN (bidirectional loop enable), and And DIR (direction). LEN, BLEN and DIR are synthesizers It is stored in the Iser volume control register. 105a１０５105e shows five volume controls The control options are illustrated. If enabled, split each time a volume boundary is crossed. Will occur. See FIGS. 105a 105e. Volume boundaries are synthesis The sound volume is held in the start and end registers.   The table below shows the sound with UVOL (updated volume) and internal flag BC (crossing boundary). How all combinations of volume control affect the formula for the next volume level after VOL (L) Is shown. UVOL is an internal that controls the rate at which VoL (L) is modified This is a flag. If the volume rate bit in the synthesizer volume rate register is V Set the rate of OL (L) correction. The number of times the audio has been set by the volume rate bit The UVOL will remain at zero until processed. When UVOL becomes 1, V OL (L) increases under the control of LEN, BLEN, DIR. BC sets the volume boundary Whenever it crosses it will be 1. Volume I in the synthesizer volume control register BC will generate an interrupt if enabled by RQ enable U. "Next VOL (L)" column is VOL (L), VINC (volume increase) , START and END to calculate next volume level of VOL (L) Here are the formulas used for VINC is stored in the synthesizer volume ratio register Is done. START and END are the synthesizer start volume register and the synth The volume boundaries for volume looping contained in each sizer end volume register. You.   In the bit definition section of the synthesizer volume rate register described below, The effect of the volume rate bit on volume increase is defined, but the register For ramming, the following equation best describes the rate of change of volume: In this equation, I [5: 0] and R [1: 0] are the fields in the SVRI register. It is Ludo. The change in volume caused by the increase of 1 in VOL (L) is 0.0235 dB. The basic rate for updating VOL (L) is 44100 Hz. This Implementation differs from that used by ultrasonic wavetable synthesizers. Yes, but the calculations are compatible.   The volume increase (decrease) method of the present invention removes zipper sounds for slow rate bit values There is an advantage of doing so. Ultrasound wave table synthesizers produce sounds generated at a slow rate Increases the volume of the voice and may cause a zipper sound when the volume increase value is high. You. This bit shifting leaves only three bit positions for I [5: 0], It can be used to set volume increase, thereby slow volume increase Makes it impossible to take incremental steps greater than 7 at the rate. Of course, the present invention Are easily modified to prepare different maximum increase steps with slow volume increase rate obtain. The three bits shifted from I [5: 0] are the bit positions of register SVLI. To the position F [2: 0]. In bit position F [2: 0] of register SVLI The data is used to represent looping volume, VOL (L) values at high resolution. Includes additional data used. Section V. N. See Register.   G. FIG. LFO volume VOL (LFO)   The LFO generator 1021 generates an LFO fluctuation (VOL (LFO)), and Can be used to continuously modify the sound volume. Tremolo for continuous correction of audio volume Create an effect. VOL (LFO) value is the synthesizer volume LFO register Is within. VOL (LFO) is an LFO meter sequentially executed by the LFO generator 1021. This is the final result of the operation. The LFO generator 1021 and LFO operation are described in detail below. explain.   H. Volume offset / pan ROFF, LOFF   The sound volume generator 1012 performs stereophonic sound positioning of the sound generated by the following two methods. Control: (i) audio can be placed in one of 16 pan positions; or ( ii) Program right and left offset to sound anywhere in the stereo field You can put your voice. OFFE in the synthesizer mode select register N controls two different modes of stereophonic positioning. The table below shows 16 breads The left and right offsets corresponding to the position are shown. Note that equally spaced To place the sound in one of the 16 stereo positions placed That both methods of mounting can be used. The values listed in the table apply to all pan positions. In order to keep the total power constant. Synthesizer pan register value, left offset value, left attenuation (dB), right Offset value, right attenuation (dB)   The following equation gives the left and right offsets to give a finer pan position at a constant total power. To decide. The formula is executed by the system software. The following equation determines the attenuation resulting from the calculated offset: PanMax + 1 is the total number of desired pan positions. Bread is between zero and PanMax Is the desired stereo position.   Offset control allows the user to directly and accurately control the stereo position I do. In addition, the user can turn off the left and right volume output or separate from all other volume components Or to control the overall volume output. Once the total volume When negative, the volume multiplier sets the maximum attenuation for that signal path, so Each output is switched off by programming all offsets to 1. Can be Users should consider the left and right offset created by the two components Thus, the overall sound volume can be controlled. One component is a stereo position And is unique for left or right offsets, while the other component is It is common to the offset and controls the overall volume of the audio. Users can use system software Combines two components in the software to control both overall volume and stereo position Program the synthesizer offset register to   When bit OFFEN = 1 of the register SMSI, two registers are used. To control the value of each offset. Registers SROI and SLOI are offset to the left. (LOFF) and the current value of the right offset (ROFF). Register SR OFI and SLOFI contain the final values of SROI and SLOI. SROI and SLOI Until the current value in registers reaches the final value contained in registers SROFI and SLOFI. Is increased or decreased by 1 LSB per sample frame. This is one time Smooth offset change is possible only by writing. Smooth offset change Prevents zipper noise. Same for both current value register and last value register By writing the same value, an instantaneous offset change can be performed. Bit If OFFEN = 0, the current value cannot be increased or decreased. This mode Is used for compatibility with ultrasonic wavetable synthesizers.   I. Effect volume EVOL   EVOL affects the output volume of the effect signal path. As shown in FIG. In addition, the signal path for the effect is different from the signal path for sound generation. Register SMSI The [AEP] controls this difference. In case of voice generation, SMSI [AEP] is zero The division of the effect signal path comes after VOL (L) and VOL (LFO). Since VOL (L) and VOL (LFO) add an envelope and tremolo to the sound, V It is important to place the effect signal path split after OL (L) and VOL (LFO). You. Effects processing should be performed on all sounds including the envelope and tremolo. EV OL is a subtraction, and therefore provides a volume decay.   In the case of the effect processing, the SMSI [AEP] is 1, and the effect signal path is obtained after interpolation. To divide. In this mode, after the effect delay is created, it is the effect accumulator You can use EVOL to adjust the volume of the signal before it is sent back to 1018. it can. EVOL is not summed with the other volume components, but by itself It works to control the volume.   Two registers are used to control the value EVOL. Register SEVI is E Contains the current value of the VOL. SEVFI contains the final value of SEVI. Register SE The current value in VI stays until it reaches the final value contained in register SEVFI. It is increased or decreased by 1 LSB every sample frame. This is one time writing It enables a smooth change just by including Smooth changes prevent zipper noise I do. Write the same value to both SEVI and SEVFI registers. Thus, an instantaneous offset change can be performed.   J. Voice storage   After generating the left and right outputs for audio data samples, the synthesizer module The accumulation logic in the rule 6 has already been generated during the same frame as the left and right outputs. Sum the left and right outputs. See FIG. Left and right outputs are left and right accumulators 1014 and 1016. Synthesizer module 6 has the same frame Continue this process until all of the audio output processed during . The sum of the left and right accumulators 1014 and 1016 is CODEC module 4. Sent to the synthesizer DAC512 inside the for possible mixing functions Is converted to analog left and right output. Section IV. CODEC module reference. The voice storage logic will determine when the sum exceeds the maximum value, Ensure that you clip instead of making changes.   K. Effect accumulation   During delay-based effects processing, the audio is sent to eight effect accumulators 1018 It can be turned off, turned on all, or not turned on at all. Shin The synthesizer effect output accumulator select register controls this processing . During effects processing, one of the eight effect accumulators 1018 is connected to audio. Can come off. The table below shows which effect accumulator is connected to which effect sound And how to turn the sound effect path into an effect accumulator Indicates whether to turn. For example, audio 12 may be programmed to perform effects processing. If so, it will be connected to the effect accumulator 4. Synthesizer Set the Iser effect output accumulator select register to 10 hex. Directs any audio to have its effect path processed by audio 12. Can be This directs the effect path to the effect accumulator 4 .   If one or more voices are to have the same delay-based effect, these Summing each of the voices together into one of eight effect accumulators 1018 Can be. For example, if some voices are piano tones, add the chorus effect to the total Sum them into the first effects accumulator so that they can be generated Can be Furthermore, if two other sounds are flute timbres, this sum So that they can produce residual effects in the second effect Can be summed.   During the frame, the local memory control module 8 To allow up to eight accesses to the wavetable DRAM. Thus, in this manner Can generate up to eight delay-based effects during a frame. Up As mentioned, some sounds can be summed into one of eight accumulators. Generate one of eight possible effects for the voice summed into one of these Can be done.   One of ordinary skill in the art would instead be able to replace any of the accumulators 1018 with one After completing the collection of voice or data from multiple voices, from the accumulator Write the collected data to local memory and clear the accumulator You will easily recognize that voice can be used to do so. Once accumulator Clears the collected data from another sound or many different sounds. The accumulator can be reused for data. In this way, the eight The fact that there is a cumulator is a delay-based effect available between frames Is not necessarily limited to eight. The number of delay-based effects available during the frame Access to local memory allowed in a given time frame Based on numbers.   As described above, up to 32 sounds and up to 8 effects can be generated between frames. Can be. However, a frame is a set time with 32 slots Thus, there is a reciprocal relationship between the number of sounds generated and the number of effects generated. For example , If up to 8 effects are generated during one frame, up to 24 Can occur between two frames. Between this generated sound and the effect Reciprocity should not create unreasonable constraints on high quality sound generation.   L. Low frequency oscillators (LFOs)   If SGMI [GLFOE] = 1, all LFOs are enabled. Two Triangle LFOs are assigned to each of the 32 possible voices. One LFO is Vib Rate (frequency modulation), and other LFOs are dedicated to tremolo (amplitude modulation). You. All parameters for operation of the LFO generator 1021 are First, the data is written to the local memory. Then, during operation, Data is read and written by the LFO generator 1021. Each LFO Can be ramped from its current value to any value within the depth range You. The following is a summary of the capabilities of each LFO:   Various parameters are programmed for each LFO, at the address below Stored in local memory: The base address is a 14-bit programmable register, SLFOBI. You. VOICE is the number of voices associated with the two LFOs. V / T is LFOs Choose between; high vibrato and low tremolo. DATA SEL is as follows Will be decrypted as: There are two values for DEFO and WAVE for each LFO. Which value is the LFO Its use is controlled by the WS bit in the CONTROL word. this Features allow LFOs to be modified during their operation. For example, if LFO is T While using WAVE [0] and DEPTH [0], the LFO has a new program. Fixed copy TWAV without worrying about overwriting the programmed value E [1] and DEPTH [1] can be modified. After writing the correction value, The WS bit in the CONTROL word can be changed and converted to a modified value .   The CONTROL byte contains the following data:   LEN LFO Enable: If this is high, enable LFO                       Is done. If this is low, it may be necessary to process the LFO.                       No access occurs anymore.   WS wave selection: TWAVE [0] and DEPTH [0], or                       Or select between TWAVE [1] and DEPTH [1].                       You.   SH shift: waveform starts at 0 and rises to 7FFFh                       Shift the waveform to the right.   INV Invert: Flip the waveform around the x-axis.   TWAVEINC [10: 0] LFO frequency: This is the LFO frequency.                       specify. Values range from 21.5 for 7FFh to 00                       The range is up to 95 seconds for 1 h. LFO frequency                       The formula for is:   Frame, LFO frame, ramp frame: 1 LFO for each frame Be updated. Each 64 frames are converted to LFO frames (to update all LFOs) Required time). The current position for a depth of 1 LFO is updated every 8 frames. Be renewed. The depth for all LFOs is 8 LFO frames or 512 (64 × 8 ) Updated every frame. The 8LFO frame constitutes a lamp frame.   Processing each LFO typically requires four accesses to local memory. I However, during the lamp update cycle, the LFO needs six accesses. I do. Usually the first three accesses are CONTROL, DEPTTH, and TWAV Read E; after the new value is calculated, the fourth access writes TWAVE return. During the lamp update cycle, obtain DEPTTHFINAL and DEPTHINC. Another read cycle is needed to store the new value of DEPTH. Another write cycle is used for this.   Lamping: DEPTH is DEPTTHFINAL for each lamp frame ● Compared to 32. If they are equal, no ramping occurs. DEPT If H is smaller, the sum of DEPTH + DEPTHINC is calculated; Instead, if DEPTH is greater, the difference between DEPTH-DEPTHINC is Is calculated. If the sum / difference is greater / less than DEPTHFINAL32, The new value written to DEPTH is DEPTTHFINAL 32; so Otherwise, the value written is the sum / difference. The time required for the ramp is:   LFO Math: Modify either frequency or volume, register SF Creating the final LFO value stored in the LFOI or SVLFOI involves the following steps: Is done according to: TWAVEINC is added to TWAVE for each LFO frame. LFO wave Multiplying the shape size by the depth results in the final LFO. Figures 106a and 106b used It is a graph of four possible waveforms. For waveform selection, set INV bit and SH bit to LF Controlled by programming in the CONTROL byte of O.   The final LFO is an 8-bit two's complement value. Synthesizer register Ray describes the LFO amplitude / variation value used to modify the frequency and volume of the audio. Remember This value is added to the FC for the vibrato and Added to volume for b: If the last LFO is positive, the sign extensions are all zeros; if the last LFO is negative, In this case, the sign extensions are all ones. This is the maximum vibrato depth of 12.4% (FC 1) and provides a tremolo depth of 12 dB.   Over a set time period, each LFO uses the same LFO amplitude / variation as the audio frequency. Add to / decrease from volume. Thus, at the end of this set period, the audio The frequency and volume are the same as if no LFO amplitude / fluctuation was added.   One skilled in the art will be able to provide LFO variations in the frequency and amplitude of the generated speech. In addition, it is easy to recognize that a low frequency other than a low frequency triangular wave may be appropriate. There will be. For example, only used to provide LFO variation, assuming low frequencies. Nominating one of the 32 possible generated sounds as the sound to be used May be appropriate.   M. Handling interrupts   Synthesizer module 6 has an address for each active voice to be processed. A boundary interrupt between the source and the volume can be generated. Address and volume interrupt Is treated similarly for reporting and clearing. These two tags There are three levels of reporting for type I interrupts. Borders during audio processing When inserted, depending on the boundary, the voice specific register bit W of the register SACI TIRQ, or register SVCI voice-specific register bit VIRQ Either indicates the type of interrupt and the global register in register SVII The TARBIT WTIRQ # or VIRQ # will be set. Register S VII also contains the number of voices that caused the interrupt. Bits WTIRQ # and V IRQ # is a bit of the register UISR in the system control module 2. Reflected in LOIORQ and VOLIRQ. The interrupt service routine is The register UISR can be read to determine the interrupt source. And then The interrupt service routine stores the value of 8Fh in the register IGIDXR (system And the register SVII , This acts as a notification that an interrupt has taken place, and Process is latched and all three levels of reporting are cleared. You can start the service. Immediately after writing to IGIDXR with a value of 8Fh, The UISR [LOOIRQ, VOLIRO] bit is cleared. Interrupt When the generated speech is processed next, the SACI [WTIRQ] and SVCI [V IRQ] is cleared and all three levels of reporting are cleared .   Load multiple audio interrupts into specific registers in synthesizer module 6 Can be stacked. During processing, the audio reaches the boundary and register SVII is already active. If an active interrupt is included, the active interrupt is sent from register SVII Until cleared, register SACI voice-specific register bits Either WTIRQ or VIRQ holds the new interrupt. register The SVII is updated with a new interrupt while processing a new interrupt voice.   By reading register SVIRI, SVII [WTIRQ #, VI RQ #] and the number of voices that caused the interruption. register -Reading SVIRI clears any of the stored interrupt reporting bits. Do not rear. In this way, the interrupt service routine Before the interrupt reporting bit is cleared. In addition, the boundary state that caused the interrupt can be changed. Only SVII reads If dropped, you may get multiple interrupts reported for the same boundary condition it can.   M. register   Unless otherwise specified, all of the contents in the synthesizer module registers 1022 RES (reserved) bit must be written as zero. RES bit Reading the data returns an indeterminate value. Read-modify-write operation of the RES bit The read value can be written back.     1. Direct register   Synthesizer audio select register (SVSR): Synthesizer audio The select register is an audio-specific indirect for reading or writing data. Used to select a register. Synthesizer audio select register -0￣31 (0h￣1) to select one of the 32 sounds to be programmed Fh). Also, the register IGIDXR stores each write Bit to allow automatic increase to I8DP or I16DP at the same time. Can be set to 1. AI is held at 0 when SGMI [ENH] = 0 . Address: P3XR + 2h Read / Write Default: 00h     2. Indirect registers   There are two types of indirect registers in the synthesizer module 6. Gro Global registers affect the operation of all audio, and audio-specific registers -Affects the operation of only one voice. Access to global registers Is the same as accessing any other indirect register. Access to voice-specific registers Access to the synthesizer audio select register (SVSR) You have to specify the number of voices by inserting Audio specific registers A read is initiated by writing the read address to IGIDXR. sound Writing to the voice-specific register is done after writing to IGIDXR and SVSR. General 16-bit or 8-bit I / O data ports, I16DP and I8 Start by writing to DP. In addition, it is necessary to program audio. To reduce the number of necessary accesses, set SVSR [AI] to 1 and set register I The value in GIDXR automatically increases to I8DP or I16DP simultaneously with each write. Can be added. These features are described in the table below. Derive several different ways to access audio specific registers.   Standard access for writing and reading, column access for writing and reading Access, column access for writing, auto increment access for writing   The audio-specific register values in the synthesizer module 6 are stored in the register array. It is included in a dual port RAM called 1032. One side of the register array Is the system control module 2 system Interface 14 and the other side is a synthesizer module Access by core blocks 1000, 1012, 1028, 1032 Wear. Section V. O. See synthesizer module structure   When audio is generated, the synthesizer module core block registers Read the programmed value of the audio from the ray. When the sound generation ends, the core The block writes the self-correcting register value back to register array 1032. Les The read of the system bus interface 14 of the Must wait until read / write from register array is finished No. Synthesizer to speed up register array read access The read index of the indirect register of the Ether module is the write index And different. This makes it possible to pre-read the read data. Fast bus In the case of access, the system waits until the register array 1032 can respond. IOC while reading the data byte register to the system bus interface 14 HRDY pins are used.   When the system bus interface 14 writes to the register array, Miha: (i) The core block of the synthesizer module reads any audio (Ii) the sound modified by the writing Have to wait until it is no longer processed by the synthesizer module 6. No. The second state is a self-correcting register by the system bus interface 14. The data written to the star is stored in the register array 1 at the end of the audio processing. 032 is not changed by writing the core block.   Writing to the register array 1032 of the system bus interface 14 Is buffered. Index register or synthesizer audio select register Before writing the next system bus interface to the star, register array If the 1032 is not taking buffered data, the IOCHRDY pin will also Can be used to hold interface 14.   The present invention uses self-correcting to avoid having overwritten data. Suppose you have the system bus interface write data to the register twice It is designed to avoid undesirable methods in the prior art. Preceding Compared to this method in technology, the present invention guarantees the writing of data and Reduces the time that the user reads / writes from certain self-modifying registers I believe it will increase your confidence in your work.   Special care must be taken when writing to the active audio register. Synthesizer The core block of the Ether module writes a pair of audio-specific registers When reading register array 1032 during a short period, the generator performs undesired activities. May be Voice-specific registers with a pair of registers are: Address start, synthesizer address end, synthesizer address , The synthesizer effect address, and the synthesizer offset.   The synthesizer register is initialized by PCARST #. III. See System Control Module for a detailed discussion of PCARST #. The global register is initialized when PCARST # is active and voice specific Register array with registers PCARST with 128 clock sequence Initialized following an inactive edge of #. Four 16MHz clock sequences During the synthesis, the synthesizer module core block of the register array 1032 Writes from the side are initialized for each audio-specific register bit for a specific audio .   URSTI [RGF1] = 0 also uses registers SVII, SVIRI, SGMI, Initialize SLFOBI. Generally, URSTI [RGFI] = 1 is set for all systems. The operation of the synthesizer module 6 is stopped. Synthesizer module 6 Operate and read from / write to registers in the synthesizer module URSTI [RGFI] must equal one in order to perform Synth 16 MHz clock with PCARST # of 128 To a value that is compatible with the ultrasonic wavetable synthesizer. Be initialized. At this point, as occurs in the ultrasonic wavetable synthesizer , URSTI [RGF1] Will Reset Ultrasound Compatible Functions . SGMI [ENH] is set to 1, a new register and a new register Access to another PCARST # or their default state. Only the initialization routine that writes the register is compatible with the synthesizer module 6. State can be returned. URSTI [RGF1] = 0 is the register array This condition exists because it does not initialize the voice-specific registers within.     3. Global register       a. Synthesizer Active Voice Register (SAVI)   Synthesizer active voice register is an ultrasonic wave table synthesizer Only needed to maintain compatibility with. In uplift mode, the synthesizer Controlled by setting ENH in the global mode register to 1; The output of the synthesizer active voice register has no effect on operation. EN When H = 0, this register determines which audio produces output and affects the output sample rate. Used to control the effect. The number of active voices ranges from 14 to 32. May be in the enclosure. With 14 active voices, the output sample rate is 44.1K Hz or a sample period of about 22.7 microseconds. 14 Each additional sound exceeds 1.6 microseconds during the sample period I do. When ENH = 0, the frequency control value is delayed when 14 or more voices are active. Must be adjusted to compensate for the poor output sample rate. Programmed The value is equal to the number of active voices minus one. This register's programmed The value may range from 13 (CDh) to 31 (DFh). Address: P3XR + 5h Read / Write; Index IGIDX R = 0Eh write or IGIDXR = 8Eh read Default: CDh RES Reserved bits: When read bits 7 = 1, 6 = 1 and 5 = 0. AV [4: 0] Active Voice: These bits are the number of active voices. Is shown.       b. Synthesizer Voice IRQ Register (SVII)   The Synthesizer Ouis IRQ register indicates which audio requires interrupt service. And what type of interrupt service is needed. This cash register By indexing the star with the register IGIDXR = 8Fh, Synthesizer volume control specific to the audio that caused the / Or the IRQ bit in the synthesizer address control register Clear and then clear VOLIRQ and LOOIRQ in the IRQ status register. I do. Address: Read P3XR + 5h; Index IGIDXR = 8Fh   reading Default: E0h WTIRQ # Wave table IRQ: When this bit is 0, V [4: 0]                 The indicated voice crosses an address boundary, causing an interrupt.                 Let VIRQ # Volume IRQ: When this bit is 0, the finger is pressed by V [4: 0].                 The sound shown crosses the loudness boundary, causing an interrupt. RES Pending bit: will read 1. V [4: 0] Number of voices: These bits determine which voices require interrupt service.                 Indicate whether you need it. All bits except the RES bit are self-correcting.       c. Synthesizer voice IRQ read register (SVIRI)   Synthesizer voice IRQ read register is same as SVII register Includes bits but is read without clearing the internally stored interrupt condition Can be Address: Read P3XR + 5h; Index IGIDXR = 9Fh   reading Default: E0h WTIRQ # Wave table IRQ: When this bit is 0, V [4: 0]                 The indicated voice crosses an address boundary, causing an interrupt.                 Let VIRQ # Volume IRQ: When this bit is 0, the finger is pressed by V [4: 0].                 The sound shown crosses the loudness boundary, causing an interrupt. RES Pending bit: will read 1. V [4: 0] Number of voices: These bits determine which voices require interrupt service.                 Indicate whether you need it. All bits except the RES bit are self-correcting.       d. Synthesizer global mode register (SGMI)   Synthesizer Global Mode Register is an operation that affects all sounds Control the mode. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 19h write or IGIDXR = 99h read Default: 00h RAMTEST Ramtest: By setting to 1, the synthesizer ad                 AF [0] of res register is in bit position 15 of SAHI                 Be written / read. NOWVTBL No wavetable: If set to 1, the synthesizer will use a wavetable.                 Use no data, but instead up to 16-bit positive                 Value (LSB = 0) and negative maximum 16-bit value (LSB = 1)                 Synthesizer address register to interpolate between                 Will be used. GLFOE Global LFO Enable: By setting to 1, all                 Enable LFO operation. ENH Elevation mode: Elevation added to ultrasonic wavetable synthesizer                 Enabled features by 1.       e. Synthesizer LFO base address register (SLFOBI)   The synthesizer LFO base address register contains the audio LFO parameters Holds the base address for the location. Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 1Ah writing or IGDXR = 9Ah                 reading Default: 0000h A [23:10] LFO base address: audio LFO parameter                 Base address for location.     4. Audio-specific registers       a. Synthesizer upper address register (SUAI)   The upper address register of the synthesizer is the upper bit of the wavetable address for audio. Including The upper bits of the wavetable address are the synthesizer address for each voice. Start, synthesizer address end and add to synthesizer address Is done. The upper address bits store the audio in four 4 megabytes of memory space. Fix to one. Synthesizer module 6 is the upper address bits, It has access to 16 megabytes of memory. When SGMI [ENH] = 0, S UAI is kept at the default value. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 10h write or IGIDXR = 90h read; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h AI [23:22] Upper address bits.       b. Synthesizer address start register   When the sound is moving through the wavetable data 1022, the synthesizer address The integer part of the start register specifies the boundary address. Synthesizer The value of the dress start register is the value of the synthesizer address end register Less than. Allow voice to access 4MB of wavetable memory Therefore, AI [21:20] is added. When SGMI [ENH] = 0, AI [21:20] will be kept at zero.         (I) Synthesizer address start high register (SASHI ) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 02h or IGDXR = 82h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h         (Ii) Synthesizer address start low register (SASL) I) Address: P3XR + (4-5) h Read / Write; Index I                 Write GIDXR = 03h or IGDXR = 83h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h AI [21:20] Start address: 4 MB                 Extended integer part of the start address added to AI [19: 0] Start address: Integer part of start address. AF [3: 0] Start address: These 4 bits are the synthesizer frequency                 10-bit, completely represented in the control register                 Represents the upper bit of the fractional part.       C. Synthesizer address end register   The integer part of the synthesizer address end register is the wave table data 1002 Specifies the boundary address within The value of the synthesizer address end register is It is larger than the value of the synthesizer address start register. Voice is a wave table memo In order to be able to access Lee's 4 megabytes, AI [21:20] Has been added. AI [21:20] is kept at 0 when SGMI [ENH] = 0 Is done.         (I) Synthesizer address end high register (SAEHI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 04h write or IGDXR = 84h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h         (Ii) Synthesizer address end low register (SAELI) ) Address: P3XR + (4-5) h Read / Write; Index I                 Write GIDXR = 05h or IGDXR = 85h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h AI [21:20] End address: To access 4 MB                 Extended integer part of end address appended to. AI [19: 0] End address: The integer part of the end address. AF [3: 0] End address: These 4 bits are the synthesizer frequency control                 10-bit portion completely displayed in the control register                 Represents the upper bits of several parts.       d. Synthesizer address register   The integer part of the synthesizer address register is the current From where the synthesizer module 6 captures the sample data You. The fractional part is a sample of the location addressed by AI [21: 0] , AI [21: 0] +1 and the sample at the location addressed by Used for a while. This register is self-correcting, and the audio is The value changes as you move through the tree. AI [21:20] has sound wave It is added to allow access to 4 megabytes of table memory. When SGMI [ENH] = 0, AI [21:20] will be held at zero. An additional address fractional bit, AF [0], is used for interpolation, but is usually No access for mining. The reset and write of the SALI is AF [0 ] Is cleared. RA in the synthesizer global mode register If MTEST = 1, access AF [0] through bit 15 of SAHI it can.         (I) Synthesizer address high register (SAHI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = Ah writing or IGDXR = 8Ah reading                 Take; voice index SVSR = (00h￣1Fh) Default: 0000h         (Ii) Synthesizer address low register (SALI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = Bh write or IGDXR = 8Bh read                 Take; voice index SVSR = (00h￣1Fh) Default: 0000h AI [21:20] Address: Added to access 4 MB                 The expanded integer part of the address being addressed. AI [19: 0] Address: The integer part of the address. AF [3: 0] Address: Fractional bits used during interpolation. All bits except RES are self-modifying.       e. Synthesizer effect address register   During effect processing, the synthesizer effect address register stores data in the wavetable data. Indicates the current address to be written into the data 1002. The data to be written is From the effect accumulator 1018. Data is being written Therefore, the effective address is only an integer. The local DRAM has wave table data 100 Acts as 2.         (I) Synthesizer effect address high register (SEAHI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 11h writing or IGDXR = 91h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h         (Ii) Synthesizer effect address low register (SEALI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 12h writing or IGIDXR = 92h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h AI [21: 0] Effect address All bits except RES are self-modifying.       f. Synthesizer frequency control register (SFCI)   The synthesizer frequency control register uses the address generator 1000 Control the rate of travel through the wrestling. This sets the pitch of the generated voice. Decimal The modulo 1.0 default value represents the synthesizer frequency control register value. , It will regenerate the wavetable data 1002 at the same rate as when it was recorded. 1 F0 has been added to increase the fractional frequency resolution to 0-bits. F0 Is held at 0 when SGMI [ENH] = 0. Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 01h writing or IGIDR = 81h                 Read; voice index SVSR = (00h￣1Fh) Default: 0400h I [5: 0] Frequency control: integer part of frequency control F [9: 1] Frequency control: Fractional part of frequency control F0 frequency control: added to increase resolution to 10-bit                 Fractional part of frequency control       g. Synthesizer frequency LFO register (SFLFOI)   Synthesizer frequency LFO register used to modify audio frequency Including the value generated by the generated LFO generator 1021. SGMI [ENH] When = 0, SFLFOI is held at the default value. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 17h writing or IGIDXR = 97h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h FLFO [7: 0] LFO frequency value All bits are self-correcting.       h. Synthesizer address control register (SACI)   The synthesizer address control register is the wavetable of the synthesizer module. Controls how data 1002 and data width of wavetable data are addressed . Address: P3XR + 5h Read / Write; Index IGIDX                 R = 00h write or IGIDXR = 80h read; sound                 Voice index SVSR = (00h￣1Fh) Default: 01h WTIRQ Wavetable IRQ: When this bit is 1, WRITEN is set.                 And the wavetable address depends on the start or end address.                 Intersects with set boundaries. This bit is the audio interrupt                 Condition loaded into the synthesizer audio IRQ register                 The value 8F is written to the total index register.                 Cleared when inserted. This bit interrupts                 0 to clear or 1 to cause an interrupt                 Either can be written. DIR Direction: This bit sets the direction in which the wavetable is addressed.                 Set. If DIR = 0, the address is                 Increase toward the boundaries set by the jitter. DIR =                 If 1, the address is determined by the address start register                 Decreases towards a set boundary. This bit is a bidirectional                 Is enabled and the address generator is enabled when BLEN = 1                 Modified by 1000. WREN wavetable IRQ enable: if WTIEN = 1, address                 The WTIRQ bit is set when crossing a data boundary. WT                 If IEN = 0, WTIRQ is cleared and can be set.                 Absent. BLEN bidirectional loop enable: when BLEN = 1, wave table add                 The address changes direction at the start and end addresses. BLE                 If N = 1, the wavetable address is the start and end address.                 Will change direction. If BLEN = 0, wave table                 Address continues to loop in the same direction when crossing the end point                 Will be. When LEN = 0, BLEN is indifferent. LEN Loop enable: When LEN = 1, the wave table address is BL                 Loop between address boundaries controlled by EN and DIR                 Will do. When LEN = 0, the wave table address is the start and end                 To the boundary of the memory block indicated by the start address                 Move or in the synthesizer volume control register                 If ENPCM is set, move beyond that boundary.                 Will be. DW data width: This is 16-bit data for wavetable data 1002                 Addressed by data or 8-bit data                 If DW = 1, 16-                 Access bit data. If DW = 0, wave table data                 Data to access 8-bit data. STP1 Stop 1: Writing 1 to this bit is a sound generation activity                 To stop. STP1 and ST to control voice processing                 P0 must be 0. STP0 Stop 0: This bit is set by the address generator 1000.                 Will be modified. The audio is set to stop at the boundary                 If so, STP0 is set to 1 when crossing the boundary. sound                 A one can also be written to stop the voice. When reading                 To, it represents the state of the voice. To control the sound,                 Both STP1 and STP0 must be 0. * Indicates a self-correcting bit.       i. Synthesizer volume start register (SVSI)   The synthesizer volume start register contains the low point of the volume ramp (slope). No. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 07h writing or IGIDXR = 87h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h V [7: 0] Volume start value       J. Synthesizer volume end register (SVEI)   The synthesizer volume end register contains the high point of the volume ramp (slope). No. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 08h writing or IGIDXR = 88h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h V [7: 0] Volume end value       k. Synthesizer volume level register (SVLI)   The synthesizer volume level register contains the current value of the volume looping component . The volume is three of the three used for higher resolutions when choosing a slow rate increase. It has fraction bits (F [2: 0]). These three bits increase their bits. Until the volume rolls over to the LSB of V [11: 0]. Has no effect. Address: P3XR + (4-5) h Read / Write; Index I                 Write GIDXR = 09h or IGIDXR = 89h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h V [11: 0] Current looping volume value F [2: 0] Fractional volume value All bits except RES are self-modifying.       1. Synthesizer volume rate register (SVRI)   The synthesizer volume ratio register controls the rate at which the amount of looping Control the addition. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 06h writing or IGIDXR = 86h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h R [1: 0] Volume rate bits: These bits are the rate of increase added to the volume                 Controls the increment split.                 R [1: 0] = 0 Add increment value for each frame                       = 1 Add (increased value) / 8 every 8 frames                       = 2 Add (increment value) / 8 for every 8th frame                 To                       = 3 Add (increased value) / 8 every 64th frame                 Get I [5: 0] Volume increase bits: These bits control the amount of increase.       m. Synthesizer volume control register (SVCI)   Synthesizer volume control register starts the looping component of the audio volume Controls how it moves from to the end of the volume. This register also Enables sound to be played continuously in blocks of scode modulated (PCM) data Therefore, it also includes the ENPCM which controls the wave table addressing. VIRQ, DIR and And STP0 are self-correcting bits. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 0Dh write or IGIDXR = 8Dh read; sound                 Voice index SVSR = (00h￣1Fh) Default: 01h VIRQ Volume IRQ: When this bit is set to 1, VIEN                 Is set and the volume is set by the start or end volume                 Intersects with the boundaries that have been set. This bit is the audio interrupt condition.                 Is loaded into the synthesizer audio IRQ register                 And the value 8F is written to the total index register                 Cleared when it is This bit clears the interrupt                 0 to trigger or 1 to cause an interrupt                 You can write in it. DIR Direction: This bit controls the volume increase or decrease. this                 The bit is 0 to increase the volume, and                 Is 1. This bit enables bidirectional looping,                 Modified by volume generator 1012 when BLEN = 1                 You. VIEN Volume IRQ enable: If VIEN = 1, the volume boundary                 VIRQ is set when crossing. When VIRQEN = 0,                 VIRQ is cleared and cannot be set. BLEN Bi-directional loop enable: volume starts when BLEN = 1                 And change the direction at the end volume. Even if BLEN = 0                 If the volume continues to loop in the same direction as when crossing the end point,                 There will be. When LEN = 0, BLEN is indifferent. LEN Loop enable: When LEN = 1, the volume is BLEN and DI                 Will loop between endpoints controlled by R                 U. When LEN = 0, the volume moves to the volume boundary, and the volume                 Will be kept constant. ENPCM Enable PCM operation: If this bit is set to 1,                 If the wavetable address continues to cross the wavetable address boundary,                 There will be. This enables continuous play of PCM data. E                 NPCM = 1, synthesizer address control register                 -LEN = 1 in the synthesizer global mode                 New interpolation mode possible when ENH = 1 in register                 Enabled. This new mode is a synthesizer address                 Data addressed by the start register                 Address specified by the synthesizer address end register                 Allows interpolation between the data to be processed. STP1 Stop 1: Writing 1 to this bit is the volume loop.                 The change of the switching component is stopped. Changes in the volume looping component                 To enable STP1 and STP0 to be non-zero                 No. STP0 Stop 0: This bit is modified by volume looping logic                 Is done. If the volume is set to stop at a boundary,                 When crossing the world, STP0 is set to one. Volume lupine                 Can also be written to stop logging. Read                 At times, it indicates the state of volume looping. Operate audio                 For this purpose, both STPI and STP0 must be 0. * Indicates a self-correcting bit.       n. Synthesizer volume LFO register (SVLFOI)   The synthesizer volume LFO register is used to modify the volume of the audio Including the value generated by the LFO generator 1021. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 18h writing or IGIDXR = 98h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 00h VLFO [7: 0] Volume LFO value. All bits are self-correcting.       o. Synthesizer offset register   The synthesizer offset register is the sound generated in the stereo field Control voice placement. The synthesizer offset register is the synthesizer It has two operation modes according to OFFEN in the mode select register. O When FFEN is 0, use SROI [11: 8] to control left and right offset. To use. In this mode, 16 positions of the pan are available. The decimal value of 0 is The voice is placed on the far left, a value of 15 places the voice on the far right. This mode is ultrasonic Compatible with wavetable synthesizers. When OFFEN is 1, SROI [15: 4] and SLOI [15: 4] separately affect left and right channel outputs of audio Contains the current left and right offset values. The final value for the left and right offsets is the SROFI level. Included in the Sister and SLOFI registers. Audio processing Between the values RO [11: 0] and LO [11: 0] are equal to the values of ROF [11: 0] and LO It is increased or decreased by 1 LSB close to F [11: 0]. Synthesizer reflex Offset register affects operation when OFFEN is set Only.         (I) Synthesizer write offset register (SROI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 0Ch write or IGDXR = 8Ch                 Read; voice index SVSR = (00h￣1Fh) Default: 0700h RO [11: 0] Right offset current value. All bits except RES are self-modifying.         (Ii) Synthesizer write offset final value register (SRO) FI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 1Bh writing or IGDXR = 9Bh                 Read; voice index SVSR = (00h￣1Fh) Default: 0700h ROF [11: 0] Right offset current value. All bits except RES are self-modifying.         (Iii) Synthesizer left offset register (SLOI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 13h writing or IGDXR = 93h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h LO [11: 0] Left offset current value. All bits except RES are self-modifying.         (Iv) Synthesizer left offset final value register (SLO FI) Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 1Ch write or IGDXR = 9Ch                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h LO [11: 0] Left offset current value.       p. Synthesizer effect volume register (SEVI)   The synthesizer effect volume register contains the current value of the volume that controls the sound effect. No. During the audio processing, the value EV [11: 0] is changed to the value EVF [11] included in SEVFI. : 0]. Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 16h or IGDXR = 96h                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h EV [11: 0] Special effect sound volume present value. All bits except RES are self-modifying.       q. Synthesizer effect sound volume final value register (SEVFI)   The synthesizer effect volume final value register controls the final value of SEVI. Address: P3XR + (4-5) h Read / Write; Index I                 GIDXR = 1Dh write or IGDXR = 9Dh                 Read; voice index SVSR = (00h￣1Fh) Default: 0000h EVF [11: 0] Special effect sound volume final value.       r. Synthesizer effect output accumulator selection register (SEA           SI)   The synthesizer effect output accumulator selection register determines which effect accumulator It controls whether the lator 1018 receives the effect output. Effect accumulator Any or all of them can be selected, and none of them need be selected. Numbers 0-7 There are eight effect accumulators attached. When SGMI [ENH] = 0, SEASI is kept at the default value. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 14h writing or IGIDXR = 94h reading; sound                 Voice index SVSK = (00h￣1Fh) Default: 00h ACC [7: 0] Accumulator selection       s. Synthesizer mode select register (SMSI)   Synthesizer mode select register enables various features in audio Control. In addition, audio may be processed through sound generation or effect processing, or Controls whether to proceed without being processed. Programming unprocessed audio Does not cause access to wavetable data 1002 when the audio is processed, Allows a lot of access to local memory for the function. Address: P3XR + 5h Read / Write; Index IGIDX                 R = 15h writing or IGIDXR = 95h reading; sound                 Voice index SVSR = (00h￣1Fh) Default: 02h ROM ROM: 1 allows audio data to come from external ROM                 To ULAW μ-law: 1 means that the voice input data is within μ-law.                 to enable. Get 8-bit sample from local memory                 When ULAW is 1, SACI [DW] is also set to 0                 It must be. OFFEN offset enable: synthesizer offset register                 -Can control the left and right volume of audio separately with 1                 I do. AEP Alternate Effect Path: 1 enables an alternate signal path for audio. Deactivate DAV audio: specific when DAV is set to 1                 Is not processed. EPE effect processor enable: EPE is set to 0                 At times, the synthesizer module acts as a signal generator.                 Synthesizer module when EPE is set to 1                 Acts as an effect processor. Local memory 1                 During effect processing, the SACI                 [DW] must be set to 1.   O. Synthesizer module structure   This section is the next core block of the synthesizer module 6: the address generator 10 00 (FIG. 107); volume generator 1012 (FIG. 109); signal path 1028 (FIG. 11). 6); and the structure of the accumulation logic 1030 (FIG. 118) will be described. Furthermore, the synthesis The user module is a synthesizer register array 1032 (see FIG. 111). And an LFO generator 1021 (FIG. 115), a clock controller (not shown), And a start generator (not shown).     1. Address generator   FIG. 107 shows an address generator 1000, an address generator and a synthesizer Gister array 1032, storage logic 1030, local memory control module 8, the LFO generator 1021, and the junction with the signal path 1028 are shown. B Local memory control module 8 is described in section VI. Local memory The control module will be described. The address generator 1000: Controller 1034; result bus 1036; register array bus 1038; Signal extension logic 1040; adder / subtractor 1042; temporary registers 1044, 1 047, 1055; Number generators 1048, 1049; Foldable transistors Loader address incrementer 1035; effect address Data FIFO buffers 1037, 1039; address fraction buffer 104 1: LFO fluctuation register 1043; clocking line PHI1; and star Address generation line 1045.   As shown, sign extension logic 1040, adder / subtractor 1042 and temporary The register 1044 is shared with the address generation controller 1034. To both the result bus 1036 and the register array bus 1038. one The time register 1047 and the number generator 1048 are connected to the result bus 1036 and the address. Foldable transistor 1 while connected to 050, number generator 1049 and temporary register 1055 Device 1038 and an address generation controller 1034. Rhodab Address incrementer 1035, effective address / data buffer 103 7, 1039, address fraction buffer 1041, and L The FO fluctuation register 1043 is also connected to the register array bus 1038 and the address generation Controller 1034.   The loadable address incrementer 1035 is also Synthesizer register SUA through the memory control block 8 I. The effect address buffer 1037 is routed through line 1053. Connected to the register SUAI and the effect address / data buffer 103 9 is connected. The effect address data 1039 is stored in a register in the storage logic 1030. Star, storage logic control line LDED, and control lines LADDIN and LDAT B is connected to the local memory control block 8.   The address fraction buffer 1041 is a register and control line of the signal path 1028. It also has connections to DRADDFR and LDBUF. Address generation controller Roller 1034 directly contacts signal path 1028 through the start signal path control line. Continued. The LFO fluctuation register 1043 is a register of the LFO generator 1021. And an additional connection to the control line LDNFLFO. LFO generator Control line LFO audio match connects to address generation controller 1034 .   Through various control lines described below, the address generation controller 1034 It controls all of the circuit components of the address generator 1000 connected to it. Star Address generation controller through the G signal path and the LFO audio match control line 1034 is a signal path 1028 and the LFO generator 10 outside the address generator 1000. Directly connected to 21 logical components. Explain the functions of these other control lines I do.   The address generation controller 1034 has the following in the register array 1032. Synthesizer registers: SACI, SVCI, SGMI, SMSI, Synth Synthesizer address start register, synthesizer address end register Synthesizer address register, synthesizer effect address register , SFCI and SFLFOI. These synthesizer regis The following bit of the loader is the load control line (LDCTR) L): SACI [WTIEN, BLEN, LEN, STP1], SVCI [EN Address generation through PCM], SGMI [ENH], and SMSI [1,0] Connected to controller 1034. These bits are the address for address generation. Set the mode of the source controller. On the other hand, set the interrupt condition and To set the direction of table addressing and stop sound generation when crossing a boundary , The next bit in these registers: SACI [WTIRQ], and SACI [DIR, STP0] is passed through the LDCTRL line to control the address generation. Can be modified by the error 1034.   The following synthesizer registers store special parameters for address generation Do:     Synth address start register: stores start address information                                         Do     Synth address end register: Writes end address information.                                         Remember     Synth address register: The current address (ADD)                                         Remember     Synth effect address register: current wave for effect processing                                         Stores the table write address                                         To     SFCI: Store FC information     SFLFOI: Stores FLFO information The address parameters stored in these registers are the load register signals Line and drive register signal line (DR REG SINGALS, LD   REG SIGNALS) to register array bus 1038 You.   The sign extension logic 1040 adds / decreases another signed binary number of a different bit size. It is used to sign extend a signed binary number so that it can be calculated. LDSE system Control lines are signed from register array bus 1038 to sign extension logic 1040 Control number loading. DRSE line sign extension Move the number to result bus 1036.   Adder / subtractor 1042 converts the binary number on register array bus 1038 into a result buffer. Add or subtract with a binary number on step 1036. INVRES if enabled The control line and the INVRA control line are connected to the result bus 1036 and the register array bus. The data loaded from 1038 to the adder / subtractor 1042 should be negative. You. These control lines cannot be enabled at the same time. LDADDER line is added Latch the addition / subtraction result from the adder / subtractor 1042, and Drives the result to result bus 1036, while the DRADDDERRA line The result is moved to the register array bus 1038. SIGN line is address The result is provided to the generation controller 1034 in code. SIGN = 1 is a negative result While SIGN = 0 is a positive result. 108a and 108b to be described later. As reflected in the timing diagram, the values on the SIGN line indicate certain conditions. Show.   Temporary registers 1044 and 1047 store data used in address generation operations. Used to temporarily store data. Data is LDTEMP1 line and L Load register 1044 from result bus 1036 by DTEMP2 line These registers are controlled by the DRTEMP1 and DRTEMP2 lines. -Moved to result bus. Data is the result bus by LDTEMP3 line Loaded from 1036 into register 1047, by DRTEMP3 line The result bus is moved from this register.   When activated by the DR1 line, the number generator 1048 returns 1 as a result buffer. While activated by the DR0 line while moving to Moved by bus 1036. On the other hand, the number generator 1049 controls the DRN1 control line. When activated by the switch, a negative one is brought to the register array bus 1038.   Folding transistor 1050 is a 32-bit wide register array bus Used to move a zero to a particular bit position within 1038. Registrar If the data moved on ray bus 1038 is not 32-bit wide, zero is Is moved to a bit position that contains no data. Foldable transistor 1050 are DRPD [5: 0], DRPD [9: 6], DRPD [15: 8 ], DRPD [31:16], and DRPD [32] lines. It is made.   The PHI1 line uses the clocking control to clock the address generation operation. Clocking signal from the address generator (not shown) to the address generation controller 1034. Supply the issue. The start address generation line 1045 is connected to the register array 103. 2 starting pulses. This start pulse is applied to the address generation controller 10. 34 is controlled to start operation. A start generator (not shown) generates a start pulse. And send it to the register array. After some time, the register array is added. Start controller 1034 and volume controller 1056 To send a pulse. See FIG. Then the address generation controller 1034 controls start of signal path 1028 through the start signal path control line I do. Next, signal path 1028 is routed through the accumulation storage control line to the accumulation logic 103. 4 (see FIG. 116). In this way, the synthesizer module The sequence of all operations in rule 6 is governed.   The loadable address incrementer 1035 is controlled by the control line LDSA. When activated, address S1 is low from register AREIBASU 1038. When activated by the control line LDAINC, the address S2 is obtained. To increase this address by one. Addresses S1 and S2 are local memory LADDIN control line to capture data samples S1 and S2 from Is loaded into the local memory control block 8. Line 1051 is Loadable address incrementer 1035 included in register SUAI Connect to the top two address bits and add two bits to the S1 and S2 address fields Increase only By increasing the address field by 2 bits, The address generator 1000 uses a total of 16 megabytes of storage instead of 4 megabytes. Site can be addressed.   The effect address buffer 1037 can store up to three effect addresses. A possible FIFO buffer. Effect when control line LDEA is activated Address is from register array 1038 to the top of buffer 1037 Loaded. Line 1053 places buffer 1037 above register SUAI Part 2 bits, the address field of the effective address is increased by 2 bits Let   The effect address / data buffer 1039 is also a FIFO buffer and has five pairs. The effect address and its related effect data are stored. Effect address data The effect data associated with each effect address loaded in the buffer 1039 is a storage theory. When loaded into the top of the buffer from a register in the From the bottom of the effective address buffer 1037 to the effective address / data buffer. -Loaded on top of 1039. The storage logic control line LDED is a data low. Control the loading. When the control line LADDIN is activated, the effect data The effective address in the buffer 1039 is stored in the local memory from the bottom of this buffer. -While being transferred to the control block 8, the control line LDATAN is activated. When the effect data is stored in the local memory control from the bottom of this buffer Move to block 8. The local memory control block 8 has an effect address Store the effect data in local memory.   Effect The address and data buffers 1037 and 1039 are effective based on eight delays. The fruits are generated continuously. Appropriate effects, cited here for reference Noris. U.S. Pat.    See 4,805,139 and 5,095,462.   The LFO fluctuation value generated by the LFO generator 1021 is based on the LFO generator control line. When the in-LDNFLFO is activated, the signal in the LFO generator (see FIG. 115) Transferred from register to register 1043. LFO fluctuation value is associated with which voice Data indicating whether or not the address is generated by the LFO voice match control line. Controller 1034. DRNFLFO line shows LFO fluctuation Move from register 1043 to register array bus 1038. The value is It is stored in the star SLFFOI. Address generator 1000 sounds vibrato Use the LFO variation to add to the voice.   LDADDFR line is stored in the SYTHH address register ADDfr value (data used during interpolation) of register array bus 1038 Control the loading into the buffer 1041. Signal path 1028 control line DRADDFR moves this value to the signal path. See also FIG. Buffer 104 1 can store up to two ADDfr values. Certain voices are inactive Buffer 1041 stores only one ADDfr value. Signal path 102 LDBUF control line from 8 pushes this one value to the bottom of buffer 1041. When the DRADDFR control line is activated, its value can be moved to the signal path. Can be.   108a and 108b are timing diagrams for different modes of the address generation operation. is there. FIG. 108b shows bit ENH of register SGMI and bit ENH of register SVCI. Bit ENPCM and bit LPE of register SACI are all set to 1. And bits BLEN and DIR of register SACI are set to zero FIG. 7 is a timing diagram for the boundary mirror mode that occurs at times. Figure 108a shows the address FIG. 9 is a timing diagram for all other modes of occurrence. These timing diagrams are Each clock cycle of a set of 12 clock cycles in a given mode During this time, the operations performed by the address generator 1000 are described. these The timing diagram is tabulated and for each of the twelve clock cycles: (I) what data is on the result bus and the register array bus; (ii) If so, which operation is being performed on the data; (iii) which other Such operations are performed; and (iv) the formula for which arithmetic operation is executed Indicate that The "Expression" and "Comment" columns show the It reflects the general operation performed by the address generator 1000 in succession. Operation "18s" and "34s" in the operation column indicate that the bit width of the operation result is 18-bit, Or, indicate whether the number is a 34-bit signed number.     2. Volume generator   FIG. 109 shows a volume generator 1012, and a volume generator and a synthesizer register. 10 shows a junction with the array 1032, the LFO generator 1021, and the signal path 1028. Volume generator 1012 includes: volume generator controller 1056; result bus 1058; Register array bus 1060; sign extension logic 1062; adder / subtractor 106 4: Bus driver logic 1066; Temporary register 1068; Shift logic 10 70; bus transfer logic 1072; number generator 1074; folding type Transistor 1076; ROM 1078; right and left volume buffers 1059; 1061 and effect volume buffer 1063; LFO fluctuation register 1065; Clocking lines PHI1 and FR8, FR64; 1057 is included.   As shown, sign extension logic 1062, adder / subtractor 1064, shift theory 1070 and the bus transfer logic 1072 are volume generation controllers. 1056 and the result bus 1058 and the register array bus 106 0 is connected to both. Temporary register 1068 and number generator 1074 While connected to the result bus 1058 and the volume generation controller 1056, The transistor 1076 and the ROM 1078 are connected to the register array bus 1060. And the volume generation controller. The shift logic 1070 is a volume control. Connected to roller 1056, results bus 1058 and right and left volume buffers 1059 and 1061 and an effect sound volume buffer 1063.   The LFO fluctuation register 1065 is connected to the register array bus 1060 and the volume generation command. Controller 1056. The LFO fluctuation register 1065 also stores the LF It is also connected to the register of the O generator 1021 and the LDNVLFO control line. Figure See 115. LFO generator control line LFO audio match is volume generation control 1056.   In addition to being connected to the bus driver logic 1066, the right and left volume buffers 10 59, 1061 and the effect volume buffer 1063 are connected to the signal path 1028 (see FIG. 116). ), Signal path control lines LDBUR, DRRVOL, DRL VOL and DRVOL, and volume generation controller control line LDRVOL, Connected to LDLVOL and LDEVOL. Right volume buffer 10 59 stores up to two right volume values, and the left volume buffer 1061 stores up to two right volume values. The left volume value is stored, and the effect volume buffer 1063 stores up to two effect volume values. I do.   Through various control lines, the volume generation controller 1056 is connected to it. Control all the circuit components of the volume generator 1012 to be controlled. These control line machines Noh will be described.   The volume generation controller 1056 performs the following operations in the register array 1032. Synthesizer registers: SVCI, SVRI, SGMI, SMSI, SVSI , SVEI, SVRI, SVLFOI, SROI, SLOI, SEVI It is. The following bits in these synthesizer registers are load controlled Line (LDCTRL): SVRI [1: 0], SGMI [ENH], SVC I [VIEN, BLEN, LEN, STPI] and SMSI [OFFEN, AEP, 0] to the volume generation controller 1056. these The bit sets the mode of the volume generation controller for volume generation. On the other hand, interrupt Set the conditions, set the volume direction (increase or decrease), and To stop volume generation or to stop volume looping, Next bit of register: SVCI [VIRQ] and SVCI [DIR, STP 0] is corrected by the volume generation controller 1056 through the LDCTRL line. it can.   The following synthesizer registers store special parameters for volume generation :     SVSI: Stores volume start information     SVEI: Stores volume end information     SVLI: Stores volume level (VOL) information     SVRI: Stores the volume ratio (VINC) information     SVLFOI: Stores volume LFO value (VINC) information     SLOI: Stores left offset (LOFF) information     SROI: Stores right offset (ROFF) information     SEVI: Stores effect volume (EVOL) information The volume parameters stored in these registers are the same as the load register signal line. And drive register signal lines (DR SINGALS, LD SIGN) ALS) to register array bus 1060.   Sign extension logic 1062 adds / decreases to another signed binary number of different bit size It is used to sign extend a signed binary number so that it can be calculated. LDSE system Control lines are signed from register array bus 1060 to sign extension logic 1062 Control number loading. The DRSE line connects the sign extension numbers. Move to fruit bus 1058.   Adder / subtractor 1064 converts the binary number on register array bus 1060 into a result buffer. Add or subtract with a binary number on step 1058. If enabled, INVRA system Control line and the INVRES control line are connected to the register array bus 1060, respectively. The data loaded from the result bus 1058 to the adder / subtractor 1064 becomes negative. To do. These control lines cannot be enabled at the same time. LDADDER line Latches the addition / subtraction result from the adder / subtractor. DRADDER line Move the result from bus driver logic 1066 to result bus 1058. SIG The N line provides the result to the volume generation controller 1056 in code. SIGN = 1 is a negative result, while SIGN = 0 is a positive result. FIG. 110 described later. As reflected in the timing chart, the value on the SIGN line To instruct. The CLIP line indicates that when the volume value reaches the maximum and minimum values, Control ripping. If bit 16 of the addition / subtraction result is 1, the result is recognized. Less than the minimum value obtained, zero is the output from adder / subtractor 1064. If bit 15 of the addition / subtraction result is 1 and bit 16 is zero, the result is A binary value greater than the maximum allowed and equal to 32,767 is the adder / subtractor 1 064. If bits 15 and 16 are zero, the result of the addition / subtraction is It is between the minimum and maximum values and the result is output from adder / subtractor 1064. sound Clipping of the volume value when the volume value reaches zero does not result in a negative result Guarantee.   Left and right volume and effect volume are controlled by control lines LDRVOL, LDLVOL, LDEVO L, the right and left volume buffers 1059, 1061 and the effect Respectively loaded into the sound volume buffer 1063. When a particular voice is inactive, Each of the buffers 1059, 1061, and 1063 stores only one value. signal The LDBUF control line from path 1028 is connected to buffers 1059, 1061, 10 63 is pressed against the bottom of the buffer and the signal path control line DRR When VOL, DRLVOL, and DREVOL are activated, they move to the signal path. To be done.   The temporary register 1068 stores data used in the volume generation application. Used to temporarily store data. Data is transmitted by the LDTEMP1 line. Loaded from the result bus 1058 and these registers by the DRTEMP1 line. Carry from Jister to result bus.   Shift logic 1070 shifts the data loaded in shift logic to the right by 3 bits Thereby effectively dividing the data by eight. Shift logic 1070 slow volume increase At a rate, a volume increase step greater than 7 is prevented. LDSFT line and DRS HFT lines load and drive data to / from shift logic 1070, respectively . The DIV8 line enables bit shifting.   When enabled, bus transfer logic 1072 transfers data to result bus 10. 58 to the register array bus 1060. This bus transfer is DR Enabled by the XFER line.   When activated by the DR0 line, the number generator 1074 returns zero as the result buffer. To 1058.   The folding transistor 1076 is a folding transistor in the address generator 1000. Serves the same purpose as transistor 1050. Foldable transistor -1076 are DRPD-200, DRPD0603, DRPD08, and DRPD-200. It is selectively activated by the PD1409 line.   Dynamic ROM 1078 places audio in one of 16 evenly distributed stereo locations. For example, the left offset value and the right offset value are stored. The LDPAN line is where The 4-bit data from SROI [11: 8] representing the desired pan position is stored in ROM Load at 1078. The DROFF line indicates the left offset value or right offset value. 2 × 12-bit data representing the default value is read from the ROM 1078. Move to Gister Array Bus 1060. The INVPAN line is ROM1078 Controls whether to output the left offset value or the right offset value. EVA The L control line evaluates the ROM with this data input.     The LFO fluctuation value generated by the LFO generator 1021 is controlled by the LFO generator control. When the line LDNVLFO is activated, the LFO generator (see FIG. 115) Moved from register to register 1065. LFO fluctuation value is associated with which voice Data indicating whether or not the volume is generated by the LFO voice match control line. It is loaded on the controller 1056. The DRNVLFO line detects the LFO fluctuation value. Move from register 1056 to register array bus 1060. This value is Is stored in the SVLVFOI. Volume generator 1012 adds tremolo to audio For this purpose, the LFO fluctuation value is used.   The PHI1 line uses a clocking controller to clock the volume generation operation. -Supply clocking signal to volume generation controller 1056 from (not shown) I do. FR8 and FR64 lines are also controlled by the clocking controller The clocking signal is supplied to the controller 1056. The signal is especially tied to increase the volume every 8 frames and every 64 frames. Provide mining. The start volume generation line 1057 is the volume generation controller 10 The start of the operation of 56 is controlled.   FIG. 110 illustrates during each clock cycle of a set of 12 clock cycles, The operation performed by the volume generator 1012 is described. Figure 110 is a table And for each of the twelve clock cycles: (i) which data is on the result bus And (ii) if any, which operation is performed on the register array bus. (Iii) what other operations are being performed; and (iv) ) Indicate which arithmetic operation the expression is being executed for. The Expression column and the "Ment" column is performed by the volume generator 1012 in conjunction with volume generation. Reflect general operations. "17s" and "15u" in the operation column indicate that the operation result A 17-bit signed number or a 15-bit unsigned number Indicate if it is a member.     3. Register array   FIG. 111 shows the structure for the register array 1032, and the register array and the register. Star data bus 1024, I / O channel ready 1180, address generator 1 000, volume generator 1012, storage logic 1030, and connection with signal path 1028 Indicates a part. Register array 1032: dual port static RAM 1178; Register data port 1182; register array I / O bus 1184; RA M I / O port 1186; I / O port bus 1187; voice select register 1 188; column comparison circuitry 1190; column selection circuitry 1192; Star select register 1194; I / O read / write timing generator 119 6; dual port RAM timing generator 1198; synthesizer core read Read / write timing generator 1200; core I / O port 1202; A port bus 1202.   4 synthesizer core blocks, address generator to process audio 1000, storage logic 1030, volume generator 1012 and signal path 1028 Requires audio-specific parameters programmed by the I need it. At the start of audio processing, the entire length of the dual port static RAM 1178 is Is read. The result of reading is in the core I / O port 1202 during audio processing In the read buffer. Core blocks 1000, 1030, 1012 , And 1028 access readings during various processing stages. Furthermore, the processing stage During the floor, the core block places a value in the I / O port 1202 write buffer. After the audio processing is completed, the data in the write buffer is stored in the dual-port static RAM. It is written back to 1178. A complete read-to-write cycle is more than audio processing Since it takes longer, RAM cycles for audio overlap. This is the core The write buffer in I / O port 1202 contains the value from the previous audio while reading This means that the take buffer contains the data for the next audio.   The core read / write timing generator 1200 has four synthesizer cores. Overruns required to update locks 1000, 1030, 1012, 1028 -Generate lap timing. It has dual port static RAM 1178 A dual port RAM timing generator 1198 to be driven directly Drive. Column selection circuitry 1192 has audio number as input for reading And use the old voice number as input for writing.   Sound generation so that the system microprocessor can generate sound During this time, the parameters of the sound need to be corrected or inspected. System micro The processor goes over the register data bus 1024 to the dual port RAM1 178 can be read / written. From the register I / O side, Report RAM 1178 stores 32 voices (columns) in 26 voice-specific registers. Organized. To access one of 26 voice-specific registers for voice First, the system microprocessor first writes to the audio select register 1188. No. This selects one of the 32 audio register strings. Next, the system manager The microprocessor writes to the register select register 1194. This One of the 26 voice-specific registers is selected for access. Finally Read from the 16-bit register data port register 1182 Taken or 16-bit register data port register 118 2 is written. Register select register 1194 auto increments Includes a counter that allows you to. SVSR [AI] is set to 1 When data is written to the register data port register 1182 In addition, the register selection register 1194 automatically increases the current value in the register I do. RAM I / O port 1186 is dual with system microprocessor It acts as an interface between the report RAMs 1178. Register Day RAM I / O for system read of dual port RAM 1178 Latched at port 1186, but only for write to dual port RAM Is not latched.   Four synthesizer core blocks 1000, 1030, 1012, 1028 The access time of the system microprocessor is Dual Port RAM 1178 must be in time when not in use. Furthermore, writing from the system microprocessor occurs after audio processing To prohibit overwriting due to the writing of the synthesizer core, Writing to the audio of the system microprocessor You have to wait until after the write occurs. They read audio and audio It cannot occur during a write. The first criterion is the I / O read / write tie Generator 1196 from the core read / write timing generator 1200 It is satisfied by gating with the / O gating signal 1197. This It has dual port RAM 1178 access to the system microprocessor. Guarantee to occur during unused hours. System microprocessor In order to prevent the writing of the server from being overwritten, the audio selection register The output and the audio number are compared by the column comparison circuitry 1190. It If they are the same, the output of the I / O read / write timing generator 1196 is Gated. To make the system microprocessor access wait Use the I / O channel ready signal on line 1180. I / O channel Ready does everything to make system microprocessor I / O cycles longer Is a signal of the ISA specification used in the PC system.   To speed up the I / O cycle of dual port RAM 1178 , Writing is buffered. This is a dual port system microprocessor The RAM 1178 can be written only once, and the data is stored in a 16-bit register. -Held in data port 1182 and waiting for access to dual port RAM Means one. If a second write is attempted, the I on line 1180 Extend the I / O cycle using the / O channel ready signal. 16-bit cash register Writing to the star data port 1182 results in the dual port RAM 11 The writing to 78 is started. To speed up the read I / O cycle, Uses different register selection values for writing. This is a read cycle Write to the register select register 1194 to start System microprocessor reads 16-bit register data port Before the dual port RAM 1178 has a 16-bit register data port Only when data to 1182 cannot be obtained, the I / O channel ready used. While reading a register contained in dual port RAM 1178, the Only sense amplifiers associated with the jitter column are enabled. Dual port R The remaining columns in the AM1178 go through a normal read cycle, but Not evaluated by This saves power and probably results in PC audio It will reduce the noise on the analog part of the integrated circuit. Dual port RAM Associate to a register contained within 1178 during a write to that register Only the column is driven. Again, the remaining columns go through a normal read cycle. This allows you to modify only the selected columns.   At startup, the values in dual port RAM 1178 must be initialized . This pushes the initial values on all columns out of the core I / O port 1202 , Through all 32 voice selections.   When the sound is inactive, no processing for that sound occurs. This saves power and reduces Simplify programming. Bit to determine if a particular voice is active If is included in the register array, determine if the audio is active Need to read a dual port RAM in order to do so. Read dual port RAM In order to save the power needed to filter, the present invention Bit is placed on the edge of the dual port RAM on line 1206 You. Each of the RAM cells at the edge of the dual port RAM 1178 has a voice active To determine if the dual port RAM should be read In addition, an additional output that can be looked up on line 1206 at the beginning of the voice cycle Have the power.   FIG. 112 shows a timing diagram for the operation of the register array 1032. FIG. The operations / signals referenced in the left column of 2 are as follows:   Start SSGA CLKS generator clocking.   SRG CLKS Machine clock status 0-11 (1 per audio                   2 clocks).   Read dual port RAM from RD CYC synthesizer core                   cycle.   WR CYC Dual port RAM write cycle. RD (N) is current                   Represents a reading for the current voice. WR (N-1) is a synthesizer                   Represents the current audio write from Isercore.   RDATA Read data output from dual port RAM.   WD Write data input to dual port RAM.   DLY1, DLY2 to match the appropriate timing of the associated logic                   Used to delay the signal.   WRRAM1 Write buffer timing.   CKSBIRQ Gating signal (for system bus interface request)                   Check for).   VN Voice number.   VN (N-1) Old voice number.   LDOVN Load old voice number.   ADDR Column select address bus.   SVIROCYC,     SVIWRCYC System bus interface write / read                   Kulu.   Load LOAV active voice.   AV active voice bus.   As shown in FIG. 113, the core I / O port 1202 is connected to the core port bus ( Paths (not shown) include paths 1216, 1218 and 1220, Current value register 1212 and final value register 1 in port static RAM 1178 Includes an incrementer 1208 and a comparator 1210 connected to 214 . Synthesizer core block also has dual port RAM1 through path 1220 178. This structure is used to control the overall volume increase / decrease Is done.   The current value in register 1212 is output by the volume generator from the synthesizer module. Value used to add volume to force. The final value in register 1214 is The value at which the current value equals after increasing or decreasing over several sample frames It is.   In the first operation mode, the current value is incremented so as to approach the final value. 1208. In this mode, the system microphone The processor writes the final value to the final value register 1214. Process audio The current value is less than, greater than, or equal to the final value To this end, the current value and the final value are compared by a comparator 1210. Regis The current value from the counter 1212 is passed to the incrementer 1208 by the path 1218. , And loaded into comparator 1210 by path 1220 and At 1220, it is sent to the synthesizer core block. Register 1214 Is loaded into comparator 1210 by path 1222.   The current value loaded into the incrementer 1208 is Is incremented or decremented by 1, depending on the comparison of the current value with the final value Remains the same. If the current value is less than the final value, the incrementer controls Receives 1 from comparator 1210 on lines 1226, 1224, and Increase the value by one. If the current value is greater than the final value, the incrementer is Receives zero on control line 1226 and one on control line 1224 and returns the current value. Decrease by one. If the current value is the same as the final value, the incrementer 120 8 receives zero on control line 1224 and does not increase or decrease the current value.   At the end of the audio processing, the current value updated by the incrementer 1208 is passed. To the current value register 1212 of the dual port RAM 1178 through 1216 Written back. The next time this audio is processed, the comparison is done again and the current value is final It is increased or decreased by one to approach the value.   In the second operation mode, the current value needs to be changed immediately. This is the current value Writing the same value to both the register 1212 and the final value register 1214 Thus it can be achieved.   In the third mode, the PAN value of the ultrasonic wave held in the SROI register is increased. Not necessary for compatibility with ultrasonic wavetable synthesizers. This In this mode, the current value is increased using bit OFFEN of the register SMSI. Disable addition and reduction.   The current value registers are SROI, LROI and SEVI, and the last value register Are SROFI, SLGFI and SEVFI.   FIG. 114a is a logic diagram showing a preferred layout of the comparator 1210. You. FIG. 114b is a timing chart associated with the logic diagram of FIG. 114a. Ko The comparator 1210 determines whether one value is greater than, less than, or equal to another. The current value and the final value are compared to determine whether they are the same. Comparator 121 0 is a static comparator.   The comparator 1210 first determines the MSB of the current value and the MSB of the final value, V1 And V2, then two values are equal or one value is greater than the other If necessary to determine whether a bit is small, Continue comparing the default positions. The comparison of the MSB positions is the left stage of the circuit shown in FIG. (Or cell) 1228, while the MSB-1 position comparison is shown The LSB position comparison is performed in the middle stage 1230 of the In step 1232 to the right of the road. The current value and the final value to be compared are 12- The comparator 1210 requires 12 comparison stages (or cells). Note that for simplicity, only three stages (or cells) are shown in FIG. 114a. ing.   First, to determine the highest difference, the MSB of the current value and the final value, V1 and V2 is compared. At each stage, the current value and the final value, the bit position of each of V1 and V2 Are input on lines 1236 and 1234, respectively. Input bit When there is a difference between them, the signal DIFF on line 1238 is one. DI equal to 1 The FF closes the CMOS transfer gate 1240 and one NMOS transistor Breaking the carry chain by dropping the output at star 1242 U. The carry chain is a CMOS that passes the voltage VCC (ie, a value of 1) from left to right. It is formed by the transfer gate 1240. Carry chain is carry chain By detecting how much one MSB has transmitted at the input to the chain To determine the highest difference.   Each bit comparison stage has as input a carry-in for that cell (signal DIFF). It has a NAND gate 1244 with power. EVAL is set by carry chain This is a timing signal that does not rise until it is completed. When EVAL goes high, At the stage having the highest difference, the CMOS transfer gate 1246 If V1 is determined to be smaller than V2 by the comparison, If so, 0 will be moved to line 1248. V1 and V2 Are equal, the carry chain transmits a 1 over its entire length.   The signal at the end of the carry chain on line 1250 is signaled on line EQ. And EVAL by NAND gate 1252 to generate You. The signal NEQ, which is the complement of the signal on line EQ, is Inputs to 54 and 1256. Further, NAND gate 1254 has as its input It has an EVAL timing signal and a signal on line 1248. Further NAND Gate 1256 has as its inputs the EVAL timing signal and NAND gate 12 It has an output from 54. NAND gates 1254 and 1256 each have a line Signals are output on LT and GT. When V1 and V2 are equal, signal NEQ is NAND Gates 1254, 1256 are prohibited from draining power. When V1 and V2 are equal , Line 1248 floats. When V1 is less than V2, LT is equal to 1 and V1 When 1 is greater than V2, GT is equal to 1, and when V1 and V2 are equal, EQ is equal to 1. equal.   Comparator 1210 is an improvement over prior art comparators that use adders It is. Since the comparator 1210 does not use an adder, it is small, Uses less power than a comparator that uses a detector. Further comparators -1210 is not believed to be achievable in a one-circuit static comparator The comparison value is determined. Comparator 1210 has a value less than another value Is greater than or equal to, or whether the two values are equal. Prior art static compa In one circuit: (i) equal values; or (ii) one Value is greater than another value, or one value is less than another value, or another value It is believed that you can only judge whether equal to.     4. LFO generator   FIG. 115 shows an LFO generator 1021, and an LFO generator and a local memory controller. The structure for the LDATOUT and LDATIN joints with the troll module It is illustrated. The LFO generator 1021 includes: LFO generator controller 1148 Data buffer 1150; registers 1152, 1154, 1156; Bar generator 1158; adder 1160; comparator 1162; -1166. LFO generator controller 1048 can be used for various control lines Therefore, it is connected to each of these circuit components. About the functions of these control lines Will be explained.   As shown, the data write from the local memory control module LDATOUT and LDATIN are connected to a data buffer 1150. Change The data buffer 1150 has a register 11 in addition to the accumulator 1164. It also has connections to 52, 1154, 1156. Register 1152, 115 4, 1156 are connected to the data buffer 1150 and the adder 1160. naan Bar generator 1158 is connected to adder 1160. The adder 1160 is a comparator Data 1162, register 1166, and by paths 1168 and 1174 Connected to accumulator 1164. Comparator 1162 is adder 11 60. Accumulator 1164 follows paths 1174 and 1168 To adder 1160, to register 1166 by path 1170, and 1172 connects to the data buffer 1150. Register 1166 Is connected to accumulator 1164 by path 1170.   As described above, various parameters for each LFO are stored in local memory. It is. These parameters are read from local memory on the line LDATOUT It is loaded into the data buffer 1150. Local memory control module Module (not shown) is connected to the control line LLFORD._Data buffer 11 by L Control the loading of data into 50. Data in data buffer 1150 Is the control line LLFOWR_L writes to local memory. B The local memory control module is the control line LLFOWR_By L Driving data from data buffer 1150 onto line LDATAN Control. Bits 14 and 15 from data buffer 1150 are the LFO waveform Determine quadrant and LFO generator controller -1148.   The data from the data buffer 1150 is stored in each control line LDCTRL, L The data is loaded into registers 1152 and 1154 by the DMC, The adder 116 from these registers by the control lines DRCTRL and DRMC. Moved to zero. Data from the data buffer 1150 is transferred to the control line LDMP. Is loaded into the register 1156. The data in register 1156 is By simultaneously activating the DRMP and SHFTMP control lines, the shift Can be When the control line DRMP is activated, the register All bits in 1156 are moved to adder 1160 while control line DRM When PHI is activated, eight MSBs are moved and control line DRM When the PLO is activated, eight LSBs are moved.   The number generator 1158 is activated when the control line DRZEROB is enabled. Move zero to adder 1160.   Adder 1160 adds the binary number on its B input to the binary number from its A input. The INVA control line causes the A input to go negative, while the INVB line Make the force negative. It is not possible to enable these control lines at the same time. No. When the control line ZEROA is enabled, the A input is zero. A input is Either zero or the value from path 1168. Enter B Force is the value on pass 1176.   The output of the adder 1160 is a comparator 1162 and an accumulator 1164 Can be sent to When the control line LDCMP is activated, the output data Data is loaded into the comparator 1162. The output value of the comparator 1162 is Is negative or positive, and according to this determination SLGM_ZERO or SLGM_Signal the LFO generator controller 1148 on the NEG line. When the control line LDACC is enabled, the accumulator 1164 The output data of the arithmetic unit 1160 is loaded. Control lines LDACC and SHFTA When CC is activated at the same time, data is stored by accumulator 1164 Shifted right.   Data in accumulator 1164 is buffered along path 1172 -1150. Control line LLRORD_L is the data of this data. Data buffer 1150 is controlled. Accumulator 116 The data from 4 can also be sent to register 1166. Control line LDO The FF controls the loading of this data into register 1166. register -1166 is also the line SSGA from the start generator_LN and SSGA_LT Data, each of which indicates an LFO number to be processed, Data is directed to the volume generator 1012 or the address generator 1000 Indicate if it is pointed.   The data in register 1166 is line SLGM_Move on DATA and add Register 1043 or volume generator of the sound generator 1000 (see FIG. 107). It is loaded into any of the registers 1065 at 1012 (see FIG. 109). Register 1166 is line SLGM_LNUM and SLGM_Data on LTYPE Data to the LFO generator controller 1148, which processes each And the register data is sent to the volume generator 1012. Or directed to the address generator 1000. System Control lines LDNFLFO and LDNVLFO store data in register 1043 or Controls which of 1065 is loaded. LFO voice match control line Are the address generator 1000 (see FIG. 107) and the volume generator 1012 (FIG. 109). ) To indicate the audio number associated with the LFO to be processed.   The PH1 line uses a clocking controller (Fig. Clocking signal (not shown) to the LFO generator controller 1148 I do. SSGA_The FSYNC line operates the LFO generator controller 1148 Supply a start pulse to start the operation. Line SGMI_Letter on GLFOE The signal is sent from the register SGMI and indicates whether all LFOs have been enabled. Show.     5. Signal path   FIG. 116 shows the signal path 1028 and the signal path and the local memory control mode. Module 8, volume generator 1012, address generator 1000, and storage logic 10 FIG. Signal path 1028: Signal path controller 1080; A Bus 1082 and B bus 1084; number generator 1088; adder / subtractor 10 90; S register 1092, S1 register 1096, and latch register 1098; data buffer 1104; shift logic 1094; bus transfer Logic 1100; multiplier bus 1086 and operand bus 1087; multiplier 110 2: Temporary register 1112; ROUT register 1114, LOUT register Star 1116, including EOUT register 1118.   As shown at the top of FIG. 116, the number generator 1088 is an adder / subtractor. 1090 and connected to B bus 1084; adder / subtractor 1090 generates number Unit 1088, connected to A bus 1082 and B bus 1084, and shift logic 1094 The S register 1092 has a junction with the A bus 1082 and shift logic 1094. Shift logic 1094 includes adder / subtractor 1090, S register -1092, connected to the latch register 1098, the S1 register 1096; S1 register 1096 is connected to shift logic 1094 and B bus 1084; Switch 1098 includes shift logic 1094, S1 register 1096 and A Connected to bus 1082; data buffer 1104 is connected to A bus 1082 Connected to the memory control module 8. Number generator 1088; Adder / subtractor 1090; S register 1092, S1 register 1096, And latch register 1098; data buffer 1104 and shift logic 109 4 is also connected to the signal path controller 1084 through various control lines described later Is done.   As shown at the bottom of FIG. 116, multiplier 1102 is a multiplier bus 1086, a sound bus. Connected to the quantity generator 1012 and the address generator 1000; 112 is connected to multiplier bus 1086; ROUT register 1114, LOU The T register 1116 and the EOUT register 1118 are connected to the multiplier bus 1086. Connected to product logic 1030. In addition, ROUT register, LOUT register The EOUT register is connected together at line 1106. Multiplier 11 02 and registers 1112, 1114, 1116, and 1118 Connected to the signal path controller 1080 through various control lines described later. It is.   The signal path controller 1080 connects to it through various control lines described below. It controls all the circuit components of the following signal path 1028. Various other control lines In this way, the signal path controller 1080 also controls the circuit components outside the signal path 1028. Connected. The functions of these control lines will be described.   The bus transfer logic 1110 transfers data from the A bus to the multiplier bus and vice versa. Send data. Transmission to A bus is possible by DRXFERUP control line While transmission to the multiplier bus is enabled by the DRXFERDN control line. Enabled.     The PHI1 line uses a clocking controller to clock the operation of its signal path. A clocking signal from a roller (not shown) is sent to a signal path controller 1028. To supply. Start Signal Pat from address generator 1000 The h line controls the start of operation of the signal path controller 1028. Start The Accumulation line controls the start of operation of the accumulation logic 1030.   The SMSI [ULAW] line is connected to bit ULAW of register SMSI. It is. The setting of this bit sets the signal path 1028 to 8-bit before interpolating the data. Control whether to extend the μ-law data of the default to 16-bit linear data .   Depending on whether control line DR0 or DR33 is activated, Bar generator 1088 moves a binary 0 or 33 to adder / subtractor 1090.   Adder / subtractor 1090 converts the binary number on A bus 1082 to the B bus 1084 Add or subtract by binary 33 or 0 from binary or number generator 1088 Calculate. The INVA and INVB control lines are respectively A bus 1082 and B bus 10 The data loaded from 84 into the adder / subtractor 1090 is made negative. These control lines cannot be enabled. The output of the adder / subtractor is a shift logic 10 94.   The S register 1092 temporarily stores data. Line LDS uses data While loading the S register from the A bus 1082, the line DRULAW Move to A bus on line 1108 and shift logic 1094 on line YYY You.   Shift logic 1094 shifts the data stored therein. Line SHY YY and SH2 are each: (i) a 3-bit binary number on line YYY; or (i i) whether the data has been shifted by 2 bits to multiply the data by 4 To determine   S1 register 1096 temporarily stores data from shift logic 1094 . Line LDS1 loads data from shift logic 1094 into S1 register , DRS1 lines move data from the S1 register to the B bus 1084.   Latch register 1098 also temporarily stores data. Line LDADDL AT loads data from shift logic 1094 into the latch register, The DLAT line moves data from the latch register to the A bus 1082.   The control line DRDATA is transmitted from the data buffer 1104 to the A bus 1082. Move the motion table data. This wave table data is stored in the address Data from the local memory control module 8 The buffer 1150 is loaded by the control line LDATOUT.   Multiplier 1102 converts the data on multiplier bus 1086 to volume generator 1012 or Multiply by the data from the address generator 1000. LDMULT line is data To the multiplier 1102, and the DRMULT line outputs the multiplication result to the multiplier bus 1010. Move to 86. The volume generator data is stored in the right volume buffer 1059 and the left volume buffer. Address from the buffer 1061 and the effect volume buffer 1063. The creature data is sent from the address fraction buffer 1041. Control line DR Which buffer is RVOL, DRLVOL, DREVOL, and DRADDFR It controls whether to move the data to the multiplier 1102. LDBUF system The control line is connected to the buffer 1041 in the address generator 1000, Connected to the buffers 1059, 1061, 1063 in the quantity generator 1012 Ensures that the data in these buffers is available to move to the signal path I do.   Temporary register 1112 temporarily stores data. LDTEMP1 rye Load data from multiplier bus 1086 into this register while The MP1 line moves data from this register to the multiplier bus.   Register ROUT 1114, LOUT 1116, EOUT 1118 Also temporarily store data. Data is stored in each control line LDROUT, LDL OUT, and these registers from multiplier bus 1086 by LDEOUT. Is loaded. As will be described later, data is transmitted through control lines DRROUT, DRLO UT, DREOUT driven from these registers to storage logic 1030 It is. See also FIG.   FIG. 117 shows during each of the set 12 clock cycles. FIG. 14 is a timing chart illustrating the operation performed by the signal path 1028. FIG. 117 For each of the twelve clock cycles: (i) which data is the multiplier bus, A bus (Ii) which buffer (address) (Fraction, right volume, left volume, or effect volume); (iii) if If so, what arithmetic operation is being performed on the data; (iv) what other The operation being performed; and (v) the formula for which arithmetic operation is being performed To indicate. "MULT" column and "ADD / SUB" column are signal path 1 028 reflects the general operations performed.     6. Accumulation logic   FIG. 118 shows the storage logic 1030, the storage logic 1030 and the address generator 100. 0, signal path 1028, and junction with synthesizer DAC 512. Accumulation The product logic 1030 includes: a storage controller 1120; a number generator 1122; And an accumulator register 1124.   As shown: number generator 1122 is adder / subtractor by path 1132 The storage controller 1 is connected to the 120; signal path 1028 is connected to adder / subtractor 11 by path 1134. 26; adder / subtractor 1126 generates number by path 1132 To the signal path 1028 via path 1134 and to paths 1136 and 1 138 is connected to the accumulation register 1124; 4 to adder / subtractor 1126 via paths 1136 and 1138 and path 1128 To the address generator 1000, and to the synthesizer DA by the path 1130. Connected to C 512. The accumulation register 1124 is controlled by the following control line Connected to the storage controller 1120:         LDSFT         DREACC7         DREACC6         DREACC5         DREACC4         DREACC3         DREACC2         DREACC1         DREACC0   As detailed below, through its control line, the storage controller 1120 controls all circuit components of the storage logic 1030 connected to it. other The storage controller 1120 passes through the signal line 1028, It is also connected to the SEASI and address generator 1000. These other controls The function of the line will also be described later.   When enabled by the DR0 control line, the number generator 1122 passes Move the zero on 1132 to adder / subtractor 1126.   ROUT register 1114, LOUT register 1 in signal path 1028 116, the data from the EOUT register 1118 is passed on adder / It is moved to the subtractor 1126. Control lines DRROUT, DRLOUT and D REOUT determines which of these registers will use that data as adder / subtractor 112. Decide whether to move to 6.   Adder / Subtractor 1126 passes data from pass 1132 or 1134 to pass 1 Add the data on 138. The result of this addition is the adder / subtractor 1 126 to the accumulation register 1124. When the sum exceeds the maximum value, Adder / subtractor 1126 may perform a rolling over or sign change instead of performing Clip data.   The accumulation register 1124 consists of ten 16-bit registers. This Two of these registers store left and right output data. The remaining 8 cash registers Stars accumulate effect data. By enabling the LSHFT control line And two steps occur: (i) data from path 1136 is stored Loaded into the top register of star 1124; and (ii) this data After the data is loaded, this data and the data previously existing in other registers To the next register or, if the bottom register, the register Is shifted to the top register. For example, before the shift, the data If arranged as shown at 118, after shifting, the data is arranged as follows Will be:     Top register → R. ACC.                           E. FIG. ACC. 7                           E. FIG. ACC. 6                           E. FIG. ACC. 5                           E. FIG. ACC. 4                           E. FIG. ACC. 3                           E. FIG. ACC. 2                           E. FIG. ACC. 1                           E. FIG. ACC. 0       Bottom register → L. ACC. Thus, both storage registers are implemented as 16-bit wide shift registers. To use. Shifting data accumulates appropriate data and corrects the data It is guaranteed to be stored in place.   When the control line LDED is activated due to the delay-based effect processing, Data is addressed on path 1128 from one of the top eight accumulation registers. The data is sent to the effect data buffer 1039 in the creature 1000. As aforementioned, Finally, under the control of the local memory control module 8, the effect data Is sent to the wavetable, where the address generated by the address generator 1000 is Written in.   Under the control of the start generator and the control line DRACC, the synthesizer module The left and right output data from the storage register 1124 on path 1130 Output to the column converter 1019 in parallel format. Then the data is serialized Transfer control block 540 or interface It is sent in series to the serial-to-parallel converter 1144 of Kitley 1025. Series-Normal The column converter 1144 converts the data in a parallel format into the synthesizer DAC 512. Send to After all possible numbers of speech in the frame have been processed, the DRACC control The start generator (not shown) causes this data to be Start output.   The lower three bits of the number of voices to be processed 120. The storage controller 1120 uses these three bits to It controls which data in the accumulation register 1124 is to be written.   Bits [7: 0] of register SEASI are stored by control line 1140 Connected to controller 1120. Based on the setting of these bits, The controller 1120 determines which of the accumulation registers 1124 stores the specific effect data. Control what you receive.         The PHI1 line uses a clocking controller to clock its accumulation operation. Clocking signal from roller (not shown) to storage controller 1120 Supply. Start Accumulation line from signal line 1028 The above signal controls the start of operation of the accumulation controller 1120.   FIG. 119 shows during each of the set twelve clock cycles. FIG. 9 is a timing chart illustrating operations performed by the accumulation logic 1030. FIG. Are arranged in a table and for each of the 12 clock cycles: (i) which (Ii) which operation is performed on the data (Iii) Indicate which arithmetic operation is being performed I do. The "expression" and "comment" columns are performed by the accumulation logic 1030 To reflect common operations.   FIG. 120 shows blocks and local memory controllers in the synthesizer module. FIG. 4 is a timing chart illustrating the overall timing of the operation of the troll module. . The timing diagram depends on the column, the following synthesizer module blocks: Start generator ("SSG"); Register array ("SRG"); Address generation Locomotive ("SAG"); volume generator ("SVG"); signal path ("SSP"); This reflects the timing of the storage logic ("SAC"). Local memory controller Roll module ("LMC") timing is listed in the last column .   The timing diagram shows that when the synthesizer module is powered up, Or various blocks and locals from the time the operation is started after a pause 5 shows the operation timing of the memory control module. Asterisk(* The operations in the columns SRG and SSP marked with) are issued after reset or power up. Do not live. In the column SAC, the timing and operation are controlled by the synthesizer module. Is in power-up / reset mode, indicated by line A, or Is the restart after the pause mode or the continuous operation mode indicated by line B Depending on what they have, they have different starting points. Timing diagram shows some audio synths Reflects the timing for processing of the user module. Those skilled in the art will see FIG. From 0 will easily recognize the timing that occurs for the processing of all audio .   The numbers after some operations in the timing diagram are which audio numbers are processed Indicates For example, "ADDfr (in) 31" in the column SSP is for audio 31 The address fraction value of The notation “(in)” or “(out)” refers to data Indicate if sent in / from a given block. For example, "ADDfr ( in) 31 "indicates that the address value for voice 31 is being sent to the signal path. .   In column SSG, “FSYNC” indicates that the synthesizer is operating in the uplift mode. Or operate in the frame extension mode. "LFSYNC" is Indicates that the mode has been set by the local memory control module. "AV" indicates whether a particular voice is active. "VN" is a specific voice number Indicates that processing for the bar has been completed.   In column SRG, read data from register array for specific voice There are two cycles to read (“RD”) and write data to the register array. There are two cycles to insert ("WR").   Those skilled in the art will appreciate the synthesizer module structure diagram and the timing diagrams described above, And section VI. From the local memory control module, Easily recognize the operations described in the SAG, SVG, SSP, SAC and LMC Will be.   System control module, CODEC module, local memory Things including control module and MIDI / game port module As a module formed on a lithic PC audio integrated circuit, I've been talking about a synthesizing table. However, instead, the system Control module, synthesizer DAC, and local memory control Form a wavetable synthesizer on a monolithic integrated circuit with Can be In another alternative, the wavetable synthesizer is With module module and local memory control module It can be formed on a circuit. Like the resulting alternative monolithic integrated circuit Can be used in various applications. For example, these integration times Any of the roads may use commercially available CODECs, storage devices and / or DACs, etc. , Along with other integrated circuits that support its operation, A sound card for use in a pewter can be formed. VI. Local memory control module   In FIG. 1, the circuit C includes a local memory control module 8. In this specification May refer to the local memory control module 8 as the LMC 8. L The MC 8 is connected to the MLC bus interface 250 and the block 252 in FIG. Includes a set of registers, latches, and logic circuits that are shown briefly. LMC 8 is off-chip Between the local memory device and the synthesizer module 6, The data is transferred between the interface 14 and the CODEC module 4. Turning to FIG. First, the DRAM circuit 110, the ROM circuit 86 and the IS A The serial EEPROM 78 that supports the Plug-n-Play standard is included.   A. Main function block   In FIG. 29, LMC 8 has a master state machine 254, a register data bus system. Control block 256, suspend mode refresh block 258, refresh request Block 260, priority encoder block 262 and memory interface Source block 264. In addition to these functional blocks, LMC 8 Includes multiple registers to be described.   The master state machine 254 and the priority encoder 262 provide a possible memory cycle. Determine which of the memory sources are allowed access and use that memory interface Source block 264 to generate the cycle. Also, LMC 8 has P lug-n-Play logic is included for Plug-n-Play access. Provides an interface to the serial EEPROM 78. Plug-n- The control of the Play compatible EEPROM 78 is performed by the PNPCS 76 and the PNPCS 76 shown in FIG. And executed on the PNP CON pin 265 (FIG. 29) corresponding to You.   Master state machine 254 receives input signals related to speech production via input 266. Take away. The audio input 266 has a register value SAVI (serial) indicating the number of audio to be processed. (See the description of the registers in the description of the sensor). Power down input Force 268 performs a general or modular stop, or Of several internally generated power-down signals to enter power-down mode Any one. These modes are described in the description of the system control module. This will be described in detail. Specifically, the power-down input 268 is a bit PWRL (local Active when power to memory changes from high to low I2L disables 16.9 Mhz clock to local memory control SUSRQ followed by I2LSUSRQ (see Figure 26) or ISUSP RG is immediately activated. All circuits are interrupted. Active in response to pin input. I2LSUSPIP (interruption continued). Logical sum of ISUSPRQ is taken Thus, 12 LSUSPIP is obtained. One time to activate I2LSUSRQ PPWRI [6 :: 1] is cleared by writing, and the above-described I2LSUSP Subsequent to this, the system enters the system stop mode.   The circuit activity signal provided on input 272 (FIG. 9) is at PUACT1 [0]. Generated in response to a condition. PUACT1 [0] is a voice function activation bit (system See the description of the system control register), which is low when all audio function Disable decoding of dress space, interrupts and DMA channels.   Output 72 is FRSYNC # generated at the beginning of each frame of audio processing, As described in the description of the system control module above, the priority encoder 262 The signal is multiplexed via a terminal 72 and output. ACSYNC♯ output signal 7 3 is one pulse representing the starting point of each 4-clock cycle memory access described below. This is a synchronization signal. Output 75 is 2 from state machine 254 to priority encoder 262. Bit MSM [1: 0] one-of-four memory cycle type signal.   1. Master state machine   The master state machine 254 has a frame length of 44.1 kHz samples. Count the game. Each frame has 32 sub-times, which is the time required to process each audio Consists of frames. Each subframe has three 4-clock accesses to local memory. Including Seth. SYNTH, EVEN, ODD and WAIT And each access type is described in the following priority encoder section. 3 illustrates different ways of prioritizing memory cycle requests. trout State machine 254 generates MSM [1: 0] specifying the current access type. You. The order in which these access types are generated is as follows. FIG. 30 is a state diagram showing the mode of MSM [1: 0].   The master state machine passes MSM [1: 0] to the priority encoder to allow for possible support. Cycle type (for example, synchronous patch access, CODEC, DMA, I / O , Refresh, etc.) to be performed.   a. Initialization Referring to FIG. 30, PCARST is active in state 287. , MSM [1: 0] = WAIT in state 290. PCA After RST # goes inactive, circuit C is activated by PUACTI [0]. Before the operation is completed, MSM [1: 0] = SYNTH in state 292 and the DRAM   Refresh to 110 is possible. After startup, master state machine 254 is in state Start the first SYNHTH access for subframe 0 at 275, and at that point To continue. The state machine 254 has eight clock syntheses for each subframe. Access type (states 275, 294) followed by four even clocks (state 2 96), eight synthesizers (states 298-300), and four odd clocks. (State 302). This pattern consists of all 32 subframes Repeated in states 304 and 306 until completed.   b. Frame extension mode This mode is Gravis Forte Ultra provided for obtaining compatibility with the asound GF-1. Frey As described in the description of the synthesizer module above, the SGMI [E [NH] can be used. In this mode, each frame Finally, a time delay of about 1.6197 microseconds x [SAVI-14] is added. . SAVI is a programmable register that specifies the number of active voices. The number of delay cycles is SAVI-14. This delay alternates with the first delay cycle. Wait for 27 clock cycles and the next delay cycle for 28 clock cycles. It is approximated by taking und. As shown in FIG. State in state 276 if the value of the file is set as SAVI-14. Enter extended mode. In state 278, four even numbers The cycle and four odd cycles are repeated three consecutive times. These 24 cycles Followed by a wait of three clocks in state 280, and an odd delay cycle Returning to the state 276, in the case of an odd delay cycle, further entering the waiting clock in the state 284 You. When all delayed clocks have ended in state 276, the subframe As long as the system number is reset and ISUSPRQ is not active in state 286. This process is restarted.   c. FRSYNC♯, EFFECT♯ and ACSYNC♯ As shown in FIG. As such, at the beginning of each new frame, the master state machine 254 has the RRSYNC { One clock pulse on ACSYNC and one clock pulse on ACSYNC A signal is issued indicating the beginning of each four clock cycle access time. EFFE CT # is clocked appropriately and the write (4 clock cycles) and read Active during the memory cycle of a set (8 clock cycles).   d. Suspend and stop mode ISUSPRQ from system control module Becomes active, master state machine 254 completes the current frame and state 28 Enter the WAIT mode at 6 and 290 (FIG. 30). LMC 8 is interrupt mode Any memory control when interfacing with the refresh cycle No signal is left.     As shown in FIG. 31, the interrupt mode continuing signal ISUSPIP # is activated. Then, the interrupt mode refresh cycle is executed at 32 Khz clock . When ISUSPIP is deactivated, the current suspend mode refresh Cycle ends on the next edge of the 32 Khz clock and all RAS # and C AS becomes inactive. Master status after ISUSPRQ goes inactive The state machine resumes operation for the next frame. Also, suspend mode refresh In the cycle, the circuit C enters the stop mode as described in the description of the system control module. Occurs at certain times.   2. Priority encoder   As shown in FIG. 29, priority encoder 262 includes an input 310 and a register. Respective outputs 31 from data bus control 256 and refresh control 260 Memory cycle requests are received via 2 and 314. MSM [1: 0], the priority encoder 262 will allow which cycle Is determined. The priority of the request is shown below. DMA cycle or SBI I / O cycle is every other ODD cycle There is a restriction that it is possible at least once. Therefore, the synthesizer module Rule is not allowed to assert an LFO access request in two consecutive ODD cycles. Not done. The local memory access mode output signal is output 316 and the memory The cycle specified by input 318 to interface 264 is generated. You.   3. Refresh request block   Refresh request module 260 is used when DRAM refresh is required RSHRQ # (refresh required) to priority encoder 262 via output 314 Request). The interval between refreshes is stored in the LMC configuration register (LMCFI). Therefore, it is set to 15, 62 or 125 microseconds. This value contains 2 bits. Input to refresh request module 260 via force 320. This block The refresh request counter (RSHRQCT [2: 0]. RSH after refresh interval elapses RQCT [2: 0] is incremented, and a refresh cycle to the DRAM is performed. Is executed, RSHRQCT [2: 0] is decremented. refresh Execution of the cycle is based on the ready signal provided at output 324 and input 326. Therefore, the refresh request mode is sent from the encoder 262. It is notified to Joule 260. When the counter is between 1 and 7, RSHRQ ♯ is active. RSHRRQT [2: 0] is in suspend mode (ISUSPIP ♯ is active) is set to 7.   4. Suspend mode refresh   Interrupt mode refresh block at input 330 due to power down condition An input to step 258 is generated. ISUSPI from system control module 2 After P $ is activated, it is provided by C32KHZ pin 70 (FIG. 5). The suspend mode refresh is operated using the 32 Khz clock. Input 32 8, the local memory control register (LMCI) is refreshed. Select type to be 62 or 125 microseconds or DRAM Choose to use self-refresh mode. All DRAM banks Refreshed at the same time. Suspend mode RAS and CAS outputs 332 and 3 34 is supplied to a memory interface 264 that generates the cycle. Figure 34 is a state diagram schematically showing a refresh cycle. FIG. 33 shows the suspend mode It is a timing diagram of a fresh cycle.   The C32KHZ clock signal remains inactive even after SUSPEND # goes inactive. Disconnect mode state machine works properly without RAS and CAS glitches Oscillation must be continued so as to end.   5. Register data bus control bank   As shown in FIG. 29, the register data control block 256 is connected via a system bus. Local memory registers that can be read and written by Needed to provide control of the system and system bus / register data bus interfaces A simple set of simple logics. Details of these registers and control functions Details will be described in other parts of this specification.   6. Plug-n-Play interface   After PCARST becomes non-linear, circuit C goes to PUACTI [0]. Therefore, before being activated, the LMC logic is in Plug-n-Play (PNP) mode. become. In this mode, MD [2: 1] is serialized from the system control module. Output to EEPROM 78 (MD [2] for SK, DI MD [1]), MD [0] is the serial returned to system control module 2. This is an input from an EEPROM (DO). System control for these attributes It is described in the module section and in FIG.   7. Memory interface   As shown in FIG. 29, the memory interface bus 264 has a maximum 10 banks, 4 banks of EPROM 86 and PNP serial Supports EEPROM 78 (FIG. 6). As described above, BKSEL [3: 0] is Multiplexed and used to select both RAM and ROM banks. RAS♯ , ROMCS}, and PNPCS are used for memory type selection. Local memory address Address used to access DRAM and ROM Are all linearly distributed from byte addresses or zero to the end of memory. Based on the address (RLA [23: 0]. Some of these 24 bits are shown in FIG. Depending on whether RAM or ROM is accessed, MA [10: 0] Or RA [21:11]. The table below shows the various registers (A Before the local memory address written in [23: 0]) becomes the real address The mode converted from the circuit C is shown. Some address registers in circuit C are (For example, all synthesizer address Real addresses are used for the other registers. Synthesizer patch ac For access, the access width is determined by SACI [2] and the DMA access The width is determined by the number of DMA request acknowledgments (channels 0, 1, and 2). 8 for bits 3 and 16 and 16 for channels 5, 6 and 7 is there). 16-bit access always assumes an even byte array, so that RLA [ 0] low specifies the LSB, and RLA [0] high specifies the MSB.   The four banks of DRAM 110 supported by DRAM circuit C There are several possible configurations specified by the register LMCFI. Each DRAM The width of the bank is 8 bits. Use each half of this data bus as two banks (For example, BKSELO # drives the CAS line corresponding to bits [7: 0]). BKSEL1} drives bits [15: 8]). Thus, a 16-bit DRAM can be used. Row address lines and The number of column address lines must be symmetric.   The following table shows the real addresses (RLA) on the rows and columns (MA [10: 0]). The multiplexing mode of [21: 0] is shown.   In systems with DRAM space required for 24-bit addressing The two most significant bits of the real address RLA [23:22] of the DRAM are encoded. And transferred from the circuit C via BKSEL [3: 0].   8-bit DRAM access FIG. 34a shows the timing of 8-bit DRAM access. FIG. The CLK in this timing diagram and the CLK below it are 16.9344.   Khz clock.   16-bit DRAM access FIG. FIG. High-speed page mode is used for 16-bit data access .   DRAM refresh FIG. 34c shows the timing of the DRAM refresh cycle. FIG. DRAM refresh cycle is CAS-before-RA The S method is used. 15, 62, 125 My when not suspended or stopped A microsecond refresh rate is supported (LMCFI).   ROM Each of the four 16-bit wide banks of ROM 86 (if any) B) must be the same size. The ROM size is specified in the LMCFI register. Is determined. Its value ranges from 128K × 16 (256 KB / bank) to 2M × 1 6 (4 megabytes / bank). A 16-bit ROM External latch 108 must be provided.   As described in detail above, a ROM access can carry 16 bits at a time Thus, the use of the address bus and the data bus is multiplexed. ROM access When an I / O write to the memory is performed, the MWE signal is active during the cycle. Be in a state. In the timing chart of FIG. 35, the real address (RA [23: 0]) is supplied from the circuit C. It shows the manner in which it is supplied. The width of the ROM bank is assumed to be 16 bits. From the above, RA [1] enters A [0] of the ROM, and points out that the same applies to the following. deep.   8. Local memory recording / reproducing FIFO   Local memory recording and playback FIFOs (LMRF and LMPF) are local This is a FIFO stored in the DRAM 110. In these FIFO registers This will be described in the description of CODEC. LMPF is from DRAM 110 Used for automatic data transfer to the CODEC playback FIFO 532 (FIG. 1). L The MRF reads from the CODEC recording FIFO 538 to the local DRAM 1 10 for automatic data transfer.   As shown in FIG. 36, the local memory recording and reproduction FIFO Provided within the FO control circuit 321, this circuit includes a programmable base address card. Counter 318, a 19-bit offset counter 320, and a programmable A FIFO size selection register 322 is included. FIFO size is offset cow By selecting a bit from the counter that resets the offset address to zero. Controlled. FIFO sizes range from 8 bytes to 256 Kbytes .   The output of offset counter 320 is output from register 318 at gate 324. It is logically ORed with the output base address and the real address of each access to the DRAM 110 is obtained. A dress is generated. The register 318 has LMRFAI and LM described below. The local memory record and playback FIFO address is supplied from the PFAI register. It is. Each byte transferred between DRAM 110 and CODEC 4 causes The offset counter 320 is incremented. Host CPU has normal I / O Writing LMPF data to DRAM 110 by access and DRAM The LMRF data is read from 110. Next LMBDR and LMS See the description of the BAI register. Local memory FIFO access is input In response to the FIFO access signal supplied to And is controlled by a controlled driver circuit 326 that supplies the data. Data transfer Signals and control signals are transmitted to the local memory FIFO via the register data bus 12. It is supplied to the control circuit 321.   CODEC sample counter CODEC record FIFO 538 to LMRF The CODEC sample counter is decremented by each sample transferred to It is. For each sample transferred from the LMPF to the CODEC playback FIFO 532 Therefore, the CODEC reproduction sample counter is decremented. CODEC F Point at which data is transferred to and from the IFO and the sample counter is decremented This will be described in detail in the CODEC part of this specification.   9. DMA data transfer   Two types of data transfer are possible between the system and the local memory. GF- The control of one compatible DMA is specified by LDMACI, The address is specified by LDSALI and LDSAHI. Inn The control of the starved DMA is specified by LDICI, and the base address is specified. Is specified by LDIBI. Use both types of DMA If done simultaneously, the results are unpredictable. LMC module 8 is a system The DMA logic described in the control module becomes the DRG signal output to the ISA bus. Becomes Similarly, the DAK # signal from the ISA bus is received by the DMA block. Is passed to the LMC module 8.   Local memory start address must be the same for all DMAs Absent.   TC interrupt TC signal from ISA bus is latched as soon as it becomes active. And remain active for the remainder of the DMA acknowledgment. The signal LLATT C is clocked into a flip-flop on the trailing edge of IOR # or IOW #. That Bit LTCIRQ is the output read into LDMACI [6]. Also this The bit is the AdLib-Sound Blast in the system control module. r is the bit written to LDMACI [6] before it is ORed with the interrupt, TC This is ANDed with the interrupt enable. Using the occurrence of TC, the Clear either LDMACI [5] or LDICI [9] depending on the type By doing so, the DMA transfer is stopped.   10. Interleaved DMA data mode   DMA allows local memory to be transferred from system memory to local DRAM 110. Transfer of interleaved data so that tracks are separated in memory. It is possible to To do this, the n of the interleaved audio data Are stored in the system memory (n is the register LDI Programmable in the range of 1 to 32 by CI [7: 3]. Each track The size of each track is also programmable by LDICI [2: 0]. The number of bytes in the loop is 2 ＾ (9 + LDDICI [2: 0]) (512 to 64 K range). The data transfer method is as shown in the table of FIG. Depends on the width of the DMA channel and the width of the sample.     As shown in FIG. 39, a local memory for the interleaved DMA function The address is obtained by ORing the base register and the offset counter 335. Obtained. The generated address is a real address, and the local DRAM 11 Indicates a byte in 0.     Further, as shown in FIG. 39, the offset counter is used for writing to the LDIBI. Each time, or PCA on line 332 via ORGATE 337_R Cleared when the ST signal is input. As shown in the figure, the LDIBI field Control the offset counter. LDICI [7: 3] is interleaved Specify the number of data tracks. This is shown simply as register 334. Tiger The clock size register 336 is controlled by LDICI [2: 0]. This service The MSB starting from the bit defined by the Incremented each time. The sample specified by the track register After the number LDICI [7: 3] is transferred, the LS is output by the track circulation output 368. B is incremented and MSB is cleared by the output 348 of the decoder 350 Is done. This DMA function is supported if the track register is set to zero. Operates in the same way as one-track transfer with the circulation point specified by the size register. You. LDIBI is added to the 5-bit down counter shown in the figure above The number of tracks is loaded each time data is written to LDI Is not loaded).   The 5-bit track register 334 is output on a 5-bit bus line 340, A number from 0 to 31 supplied to the down counter 342 is designated. Counter 3 42 is decremented on each DMA cycle via inputs 344 and 346; It is reset at count zero. Input from the counter 342 to the decoder 350 The enable output signal simply indicates the MSB of counter 335 on line 348. Cleared via the R [16: 9] output. The limit for clearing output 348 is MS A track that defines a boundary bit between B (number of tracks) and LSB (track size) Defined by input 352 from size register 336. Specified R input 348 activates OR gate 358 when enabled. The corresponding flip-flop 331 is supplied to the clear input of the corresponding flip-flop 331.   Similarly, size register 336 has three bits on line 354 to decoder 356. And the decoder provides a 3: 8 signal on the 8-bit bus 360. Provide the bit-decoded output S [16: 9]. The output signal on line 360 is The LSB of the counter 335 is incremented and the memory corresponding to the next track group is incremented. Address the next block of. The LSB of counter 335 is equal to line 360 It is incremented by the corresponding multiplexer 362.   B. Overview of local memory control pins   FIG. 7 shows an outline of external pins and functions of the local memory control module 8.   C. Overview of the local memory control register   1. LMC byte data register (LMBDR) Address: P3XR + 7 Read, write   This is retrieved by the LMALI and LMAHI I / O address counters. 8-bit port to local memory. LMCI [0] is auto increment The I / O address counter is set to the Increment by 1 for each set.   2. DMA control register (LDMACI) Index: P3XR + 5 read; Index IGIDXR = 41h Default: 00h   This register controls GF-1 compatible DMA access to local memory. Used for control. INV:   MSB inversion. When this bit is high, local memory The MSB of the DMA data to the memory is inverted. When low, this data Passed without change. Bit [6] of this register sets the MSB to bit [ 7] or bit [15]. This bit is a GF-1 compatible D Affects only MA and does not affect interleaved DMA. DMATC:   (DMATC for reading, IB15 for writing) End count. This bit separates the read and write functions. Logic 1 , This indicates that the DMA TC interrupt is active. This read also clears this interrupt bit (interrupt is When this bit is read for the first time after being set, its value returns to high and The rest is low. )   Bit 15 inversion (IB15). Writing this bit high clears the system memo. The data width of DMA data from the memory to the local memory is specified as 16 bits. Is written low, 8-bit data is specified. This is the cash register Only used for the INV bit of the star. Note: IB15 is LMCI [6] Can be read out via DIEN:   DMA IRQ enable. If this bit is high, the TC The function that interrupts at the end of a certain block in the memory-local memory DMA is Cable. This bit is set when LDMACI [0] is active or Is active when LDICI [9] is active, but the CODEC DM A is not active (this bit is free to drive the TC interrupt). The output of the AND gate is ANDed with the output of the flip-flop. Drive. DIV [1: 0]:   DMA rate divider. This is based on local memory and (internal DRQMEM signals) Controls the possible data rate to and from the system memory You. This bit only affects GF-1 compatible DMAs, It does not affect DMA.   At the given time, a new DMA request is set from the end of the DMA acknowledgment. Measured before However, when this time has elapsed, the previous DMA cycle If the local memory cycle corresponding to the file has not yet completed, this logic After the completion of the memory cycle, the DRQ signal is set. WID:     DMA width. This read-only bit is used between system memory and local memory. Specifies the data width of the DMA channel for transfer. UDCI [2: 0] requires DMA It is high when the request acknowledge signal 5, 6, or 7 is set. In other cases Are all low. DIR:     direction. If this bit is low, it indicates that the local memory DMA transfer is System memory read and local memory write RY. If this bit is high, this indicates a local memory DMA conversion. Transfer to local memory and write to system memory. It is specified. This bit only affects GF-1 compatible DMA. , Does not affect interleaved DMA. EN:   Enable GF-1 compatible DMA. If this bit is high, the system A DMA transfer occurs between the stem bus and local memory (this is a CODEC Does not affect DMA). First DMA request since this bit is set high There is a delay of 0.5 to 1.0 microseconds before is issued. This bit is reset by hardware when the TC line is asserted.   3. LMC DMA start address low register (LDSALI) Index: P3XR + (4-5) Write; Index IGI DXR = 42h Default: 0000h   This 16-bit register is a GF-1 compatible D indicating local memory. Designate the lower part A [19: 4] of the MA address counter. To this register A [3: 0] of the DMA address counter is automatically cleared by writing. You. Based on whether an 8-bit or 16-bit DMA channel is used Between the real address and the address programmed in the DMA register See LMC module memory interface section for details No.   4. LMC DMA start address high register (LDSAHI) Index: P3XR + 5 read / write; Index IGI DXR = 50h Default: 00h   This is via A [23:20] and A [3: 0] for the DMA cycle. GF-1 compatible DMA address counter pointing to local memory 110 Specify the upper and lower parts of. Is A [3: 0] a reason for compatibility? Is automatically cleared during writing to LDSALI. Odd byte address Starting a DMA transfer is not allowed. 8-bit or 16-bit DMA The real address and DMA registers are based on which channel is used. For conversion to and from the programmed address, refer to the memory See the interface section.     5. LMC address row (LMALI) Index: P3XR + (4--5) Write; Index IG IDXR = 43h Default: 0000h   This is via A [15: 0] for the programmed I / O cycle. Designates the lower part of the I / O address counter pointing to local memory 110 . The rest of this address is in LMAHI. The corresponding data port is LMBDR for site access and LMSBAI for 16-bit access is there. The LSB of this register is ignored for 16-bit accesses. 16 Writing of bit data cannot be started from an odd address. LMCI When [0] is set to the auto increment mode, the I / O address The counter increments by one for each access via LMBDR and the LMS Increment by 2 for each access via BAI.   6. LMC address high (LMAHI) Index: P3XR + 5 write; Index IGIDXR = 44h Default: 00h   This is via A [23:16] for the programmed I / O cycle. Designates the upper part of the I / O address counter pointing to local memory 110 . The rest of this address is in LMALI. The corresponding data port is LMBDR for site access and LMSBAI for 16-bit access is there. The LSB of this register is ignored for 16-bit accesses. LM If CI [0] is set to the auto increment mode, the I / O address The counter increments by one for each access via LMBDR and L Increment by 2 for each access via MSBAI. SGMI [E NH] is set to GF-1 compatibility mode In this case, A [23:20] is secured.   7. LMC 16-bit access register (LMSBAI) Index: P3XR + (4-5) read, write; index IGIDXR = 51h   This is retrieved by the LMALI and LMAHI I / O address counters. 16-bit port to local memory 110 to be accessed. LMCI [0] is automatic When set to the increment mode, the I / O address counter Increment by 2 for each access through the port. LMALI LS B is always treated as zero during access through this port.   5. LMC configuration register (LMCFI) Index: P3XR + (4-5) read, write; index Kusu IGIDXR = 52h Default: 0000h SR [1: 0] Suspend mode refresh rate (see table below) NR [1: 0] Normal mode refresh rate (see table below) RM [2: 0]:   ROM configuration. The size of the four ROM banks 86 is specified. 128K × 16 In the case (RM [2: 0] = 0), in the case of 256K × 16 (RM [2: 0] = 1), In the case of 512K × 16 (RM [2: 0] = 3), in the case of 1M × 16 (RM [2: 0] = 4) and 2M × 16 (RM [2: 0] = 5-7) is secured. DR [3: 0]: DRAM configuration (all values are bytes)     9. LMC control register (LMCI) Index: P3XR + 5 write; Index IGIDXR = 44h Default: 00h IB15:   Bit 15 inverted. This bit is read-only. This bit is LDMAC Provides CPU read access to I [6]. When this bit is high The width of DMA data from system memory to local memory is specified as 16 bits Is done. Writing this bit low specifies 8-bit data. this is Used only for LDMACI [INV]. ROMIO:     DRAM / ROM selection for I / O cycle. 0 = DRAM1; 1 = ROM AI:   Automatic increment. When this bit is low, this is via LMBDR. LMSBAI specifies I / O read and write to local memory Do not automatically increment the I / O address counter. This bit is high At this time, such an access causes the I / O address counter to access the address via the LMBDR. Access is incremented by 1 and access via LMSBAI is And then increment by two.   10. Local memory recording / reproducing FIFO base address (LMRFAI and LMPFAI) Index: P3XR + (4-5) read, write; read Index IGIDXR = 54h, Reproduction Index IGIDXR = 55h Default: 0000h   These registers store the base address of the local memory record and playback FIFO. The real (byte-oriented) address bits A [23: 8] are specified. To LMRFAI The LMRF offset counter is reset to 0 by writing. LMPF The writing to the AI resets the LMPF offset counter to zero.   11. Local memory FIFO size (LMFSI) Index: P3XR + (4-5) read, write; index SGIDXR = 56h Default: 0000h RE:   LMRF enable. When high, from LODEC recording FIFO 538 Are transferred to the LMRF.   RFSIZE. This is the circulation point of the LMRF offset counter 320. That is, the size of the FIFO is specified. FIFO size is 2 ＾ (RFSIZE + 3 ). This size ranges from 8 bytes to 256 Kbytes. PE:   LMPF enable. When high, the sample from the LMPF is CODEC The data is transferred to the reproduction FIFO 532. RFSIZE:   LMPF size. This is the circulation point of the LMPF offset counter 320. That is, the size of the FIFO is specified. FIFO size is 2 ＾ (RFSIZE + 3). This size ranges from 8 bytes to 256 Kbytes.   12. LMC DMA Interleave Control Register (LDICI) Index: P3XR + (4-5) read, write; index SGIDXR = 57h Default: 0000h IEN:   Interleaved DMA enable. When this bit is high, the interface Leaved DMA is enabled (ie, while this bit is high, A starved DMA cycle occurs). This bit is set to (terminal count pin T Terminal count reached (after DMA cycle corresponding to this function where C is active) Cleared by hardware when done. W16: The data width is 16 bits. When high, this bit is interleaved. Specifies that the width of each sampled sample is 16 bits. If low, 8 Specify the data of the bit width. ITRK [4: 0]:   Number of tracks interleaved. For example, 00h is 1 track, 01h Specifies two tracks. ISIZE [2: 0]:   The size of the interleaved track. The size of each track is 2 ＾ (9+ ISIZE) sample. The range is (8 bit DMA channel and 16 bit From the 512 bytes to 64 bytes, regardless of which DMA channel is selected). K bytes.   13. LMC DMA Interleave Base Register (LDIBI) Index: P3XR + (4-5) read, write; index SGIDXR = 58h Default: 0000h   This 16-bit register ORs with the offset controlled by LDICI. RLA [23: 8] to be specified. This register is set to the width of the DMA channel. The actual description in the memory interface part of the LMC module Specify an address. VII. MIDI and game port modules A. Game port overview   Referring now to FIG. 1 and FIG. 40, the game port module 10 of the circuit C It has features found in standard C game ports. These are generally up to Used to interface to two joysticks 372 and 374. Each joystick has potentiometers 376 and 3 in the X and Y directions, respectively. 78 and two function buttons 380 and 382. Joystick The inputs to circuit C from 372 and 374 are GAMIN [3: 0] pin group and G Four element input lines 384 and 386 to the AMIO [3: 0] pin group Done via The software uses a game port to control each joystick The X and Y positions of the buttons are determined, and the state of each button is determined. 1. GAMIN pin   The four GAMIN pins are 6K ohm (nominal: + or -2K ohm) resistors. The pins are internally lifted via a pin, and the state of these pins is described later and 1 via a register GGCR schematically included in block 390. Returned to the system control module. 2. GAMIO pin   Referring to FIG. 41, the software uses the GAMIO pin to (1) GAM Writing to the game port that the IO pin 392 has been set to the high impedance state To determine the joystick position and (2) the game port By polling the X potentiometer in the joystick Time used to charge an external capacitor via the Y potentiometer To determine. The measurement from time to voltage is performed by the differential amplifier 402 and the flip-flop. 404. The threshold voltage for the GAMIO bit is Joyce Joystick based on value stored in tick trim DAC register 398 It is controlled by a DAC 396, which is called a back trim DAC.   External potentiometers 376, 378 typically operate from 2.2K ohms to about 10 It varies in the range of 0K ohms. The external condenser 394 is usually 5600 picof Rad (pF).   The four GAMIO pins are connected to ground, high impedance, and There are three possible states: transfer state. These states are shown in FIG. 41a.   Ground: Most of the time, the GAMIO pin is grounded. In this state , Circuit C outputs logic level 0.   High impedance state: software writes to game control register 390 When writing, the GAMIO pin transitions to a high impedance state. this In the state, these pins are connected to the joystick trie via the differential amplifier 402. And internally compared with respect to the voltage level set by the DAC. To comparator The control level driven by the comparator 402 because the input of the To ensure that glitches are not sent to the On the output of 402 is a digitally synthesized hysteresis.   Ground transition state: This state is, for a certain GAMIO pin, the voltage of that pin Is started when the value exceeds the value of the joystick trim DAC 396. At this time At this point, the GAMIO control flip-flop 404 is cleared and the voltage on the pin is Becomes grounded. With a load of 5600 picofarads, the current on each pin Is limited to 18 mA or less during the transition (i = Cdv / dt). transition The time is less than 2 microseconds. At the end of the transition state, the GAMIO bit Is reported to the host CPU via the game control register 390. You.   Suspend mode: Suspend mode (refer to the power consumption mode of the system control module) ), The GAMIO pin 392 connects the joystick Is forced into a high impedance state so as not to be pulled out. The pin is medium After exiting the disconnect mode, the pins reach ground and the next The ground transition mode is set immediately until the writing of the data is completed. 3. Joystick trim DAC   The joystick trim DAC 396 is a 5-bit DAC that varies linearly. is there. The digital input to the joystick trim DAC 396 is static , It is called the joystick trim DAC register 398 and the SB114 Set by registers controlled by.   Suspend mode: When in suspend mode or when port module 10 is When disabled by PPWRI (power off in system control module) Cost mode), conventional register ladders used in DAC designs consume current Can not be done. B. MIDI port overview   MIDI (instrument digital interface) is a low-performance local area network Music industry including work (LAN) specifications and descriptions of data passed to the LAN Is a standard created by the world (this data is It is designed to be suitable for controlling the vessel). MIDI port on circuit C Can transmit and receive continuous data at the digital level. The external circuit uses these as MID It needs to interface to the ILAN.   Referring now to FIG. 42, the MIDI port 10a has a UART 4 for continuous transfer. 12 and a reception FIFO 414. Here, the merger for all purposes A group entitled Improved Universal Asynchronous Transceiver, assigned to Ming's common assignee U.S. Pat. No. 4,949,333 to Rick et al. Discloses a UART / FIFO configuration. One embodiment has been described. Software to send MIDI data Stores the bytes to be transmitted in the MIDI transmission data register 410 (GMTDR). Write. To read MIDI data received by UART 412 , It reads the MIDI receive data register 416 (GMDRD). UA 16 byte FIFO between RT 412 and MIDI receive data register 416 There is O414.   The circuit C receives data from the MIDI reception data register 416 or transmits Data that completes the process being performed, or as a result of either, Can be programmed to generate an interrupt. 1. MIDI UART   The MIDI interface 10a operates at 31.25 KHz +/- 1%, Based on Motorola MC6850 compatible UART 412. For sending and receiving data Is shown in FIG.   The UART 412 operates asynchronously. 2. MIDI receive FIFO and register   Referring again to FIG. 42, the 16-byte FIFO 414 includes the UART 412 and the M It interfaces with the IDI reception data register 416. MIDI reception When the communication data register 416 has data, an interrupt occurs ( If it is interruptible). An interrupt is generated by the system control module described above. This is explained at Register 416 is read by software The interrupt is cleared. Before this byte is read, When the MIDI data is received by the FIFO, the new data is stored in the FIFO 414. Can be put in. MIDI reception data register 416 reads If the FIFO 414 has more data after the Transferred from the FIFO 414 to the register 416, another interrupt occurs. This Thus, the IRQ pin to which the MIDI interrupt is assigned reads the data. Transitions from high to low, the data is transferred from FIFO 414 to register 4 When it is passed to 16, it transitions from low to high immediately. Including FIFO 414 Then the maximum allowed interrupt latency is about 320 microseconds to 5.44 millimeters Increase to the second. Data is directly transferred via software using GMRFAI. Later, it can be put in the MIDI reception FIFO. 3. MIDI loopback logic   Referring now to FIG. 42, the MIDI port 10a is connected to the MIDITX line 420 Provides the option of folding the above data directly to the MIDIRX line 422 For this purpose, a folding logic 418 is provided. This is described in the System Control section above. This is controlled by bits in the UMCR described above. Occasionally When in return mode, the MIDITX 424 pin is still folded Functions to transmit data to an external device. But the MIDIRX input 426 , Data cannot be received. C. MIDI and Game Port Pin Summary D. Overview of MIDI and gameport registers 1. Game control register (GGCR) Address: Write 201h   Writing any value to this register starts the capacitor charging cycle 4 GAMIOs to determine the XY position of the joystick All pins 392 go into a high impedance state. Address: 201h read Default: XXXX 0000 binary value GAMIN [3: 0] These bits indicate the state of the four GAMIN pins 392. To reflect. GAMIO [3: 0] Each of these GAMIO pins has a high impedance. -High in dance mode and ground transition mode, low in all other Read. 2. Joystick trim DAC register (GJTDI) Address: P3XR + 5 read, write; index IGIDXR = 4Bh Default: 1Dh TDAC [4: 0] The joystick trim DAC396 levels are as follows: Set as follows.   These values vary linearly with VCC. 3. MIDI control register (GMCR) Address: P3XR + 0 Write, Read (If IVERI [RRMD] Is active). Default: 0X0X XXX0 (reset by URSTI [RGF1] Note: When IVERI [RRMD] is active, this register Key is readable. If IVERI [RRMD] is not active, Readings from this address give the data in the GMSR. IVERI [RR MD] interrupt enable reading is performed in each of the MRST field and the TINT field. Give each one bit. Bits [6 and 1] are unknown for these reads Bit [0] indicates that the MRST is written in [1.1] (MIDI port). Bit [5] is low when TINT is reset to an active state). When it is written in [0.1] (IRQ is active), it is high. RINT Receive data interrupt enabled. 0 = Reception interrupt disabled. 1 = Receive interrupt Permission. TINT [1: 0] Transmission interrupt. 00 = IRQ disabled. 10 = IRQ disabled.           Interrupt enable bit. 01 = IRQ enabled. 11 = IRQ disabled.   This field contains one flip-flop, due to the combinational logic before combining the states. It is realized only by lop. MRST [1: 0] MIDI reset. 00 = normal operation. 10 = normal operation.           01 = normal operation. 11 = MIDI port reset.   The MIDI port reset command is used to reset all bits in the GMSR, receive FI The FO 414, the GMTDR, and the MIDI transmission / reception UART 412 are reset. This does not reset GMRDR. This command allows another I / O write Stay active until GMCR [1: 0] is changed to something other than [1: 1]. You. This field contains one flip, due to the combinational logic before combining the states. It is realized only by the flop. 4. MIDI status register (GMSR) Address: P3XR + 0 Read Default: 0X00 XX10   Note: When IVERI [RRMD] is active, the data in this register Data cannot be accessed. MIRQ MIDI interrupt request. This bit can be RDAT, TDAT, or Goes high when any one of MORERR is active. The equation is R   MIRO = GMCR [1] * (RDAT + MORERR) + (GMCR [6: 5] == (0,1) * TDAT; MOR ERR MIDI overrun error. This bit is the MIDI receive FIFO 41 4 goes full when an additional byte of MIDI data is received. You. This is cleared by reading GMRDR. MFRERR MIDI frame error. This bit is a stop bit (Fig. 3 ) Is read as other than the logic level 1, and becomes active. This is the MID The subsequent reception of a correctly framed byte in the I data It is reared. TDAT MIDI transmission data register (GMTDR) available Noh. This bit indicates that there is no data to be transmitted on MIDITX pin 424 , When the UART 412 is ready to accept another byte of data, Is set to a. This occurs when writing to GMTDR starts data transfer. , Cleared low. This means that the MIDI port reset (to (1,1) GMRDR [1: 0] write), goes low and returns high after reset. . RDAT MIDI receive data register (GMDRD) full. This bit is High when there is a valid byte of data in register 416 (GMDRR). Is set. This bit indicates that the byte is from register 416 (GMDRD). When read, it is cleared low. Data exists in the MIDI receive FIFO If present, this bit is read from register 416 (GMDRD). It goes high again about 2 microseconds after. 5. MIDI transmission data register (GMTDR) Address: P3XR + 1, write Pin group 1. 5 bolt specifications DC characteristics, VCC = 5 volts Maximum drive for Vol, Voh specification, VCC = 5 volts Note 1: The maximum drive capacity for these signals is PSEENI [ISAD R]. Note 2: There is no Ioh value for open collector output. Note 3: EFFECT # and FRSYNC # are SUSPEND # input and C32K Multiplexed by HZ input. CD-IRQ is output as ESPCLK. You can choose. 2. Voltage specifications DC characteristics, VCC = 3.3 volts Maximum drive for Vol, Voh specification, VCC = 3.3 volts Note 2: There is no Ioh value for open collector output. Note 3: EFFECT # and FRSYNC # are SUSPEND # input and C32K Multiplexed by HZ input. CD-IRQ is output as ESPCLK. You can choose.   The foregoing disclosure and description of the invention is illustrative and illustrative of the invention and Circuit elements, specifications, connections and implementation details, without departing from the spirit of The operation method can be variously changed.

────────────────────────────────────────────────── ─── Continuation of front page    (31) Priority claim number 08 / 333,460 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 333,467 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 333,536 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 333,564 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 334,461 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 334,462 (32) Priority date November 2, 1994 (33) Priority country United States (US) (31) Priority claim number 08 / 510,139 (32) Priority Date August 3, 1995 (33) Priority country United States (US) (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, M C, NL, PT, SE), JP, KR (72) Inventor Bramer, Jeffrey E             United States, Texas 78947, Les             Kisington, Box 30 Bebe 1 (72) Inventor Brown, Glen W.             United States, Texas 78748, Ohio             Austin, Boots Hill Drive             11414 (72) Inventor Caibler, Carlin Dru             United States, Texas 78737, Ohio             Austin, Corner Brook Pass             12101 (72) Inventor Famestar, Ryan             United States, Texas 78704, Ohio             Austin, Katherine Pass 2930 (72) Inventor Gesio, David             United States, Texas 78736, Ohio             Austin, Red Willow Drive               8005 (72) Inventor Garrick, Dale Y             United States, Texas 78748, Ohio             Austin, Festas Drive 3122 (72) Inventors Hogan, Michael             United States, Texas 78746, Ohio             Austin, Westlake Drive             4250 (72) Inventor Linz, Alfred Earl             United States, Texas 78739, Ohio             Austin, Rickerhill Lane 5925 (72) Inventor Norris, David             United States, Texas 78736, Ohio             Austin, Dawn Hill Circle             7504 (72) Inventor Schnitzline, Paul Gee             United States, Texas 78737, Ohio             Austin, Antler Bend Road               11410 (72) Inventor Sookes, Martin P.             United States, Texas 78735, Ohio             Austin, Fern Run 4702 (72) Inventor Spac, Michael E             United States, Texas 78640             Il, Box 170, Route 1 (72) Inventors Sagus, David N.             United States, Texas 78728, Ohio             Austin, Shoreline Drive             Number 311 3101 (72) Inventor Trok, Arantee             United States, Texas 78660             Hulgerville, Dunes Drive             2400

Claims (1)

[Claims] 1. Data and control signals within the central processing unit, system memory, and system Including a processor-accessible bus for transferring signal and address signals. For providing audio enhancements to personal computers A monolithic integrated circuit, wherein the monolithic integrated circuit comprises: A system control module that provides an interface to a bus accessible by the processor. Jules, Achieve analog-to-digital and digital-to-analog signal conversion. A coding and decoding module for coding, said coding and decoding module. But also An analog signal for transmitting and receiving analog signals between an external source and the destination. A log input circuit and an analog output circuit, Data for transmitting and receiving digital audio data to and from the system control module. A digital audio input circuit and a digital audio output circuit; Digital audio signal synthesizer module for creating digital audio signals When, A coding decoding module comprising: A monolithic integrated circuit comprising: 2. The integrated circuit according to claim 1, wherein the control module further comprises: Distribute data across the integrated circuit, communicating with each of the modules A register data bus for An integrated circuit comprising: 3. The integrated circuit according to claim 2, wherein the register data bus comprises: further, Provides data, control, and address connections to a processor-accessible bus Integrated circuit having an external bus interface circuit for the same. 4. The integrated circuit according to claim 1, wherein the system control module comprises: further, An interrupt circuit for creating and managing processor interrupt signals according to circuit requirements; An integrated circuit comprising: 5. The integrated circuit according to claim 1, wherein the system control module comprises: further, Request and acknowledge signals for direct memory access depending on circuit requirements A direct memory access circuit for creating and managing An integrated circuit comprising: 6. The integrated circuit according to claim 1, wherein the system control module comprises: further, Data bits, control bits and switches that reflect or control various circuit operations A plurality of integrated circuit control registers for storing status bits; An integrated circuit comprising: 7. The integrated circuit according to claim 1, wherein the system control module comprises: Further, an external oscillator for receiving an input signal and providing an output circuit clock signal. An integrated circuit having an internal clock circuit. 8. The integrated circuit according to claim 7, wherein the internal clock circuit further comprises: A clock stabilizing circuit, wherein the stabilizing circuit has a deteriorated external oscillator signal. A means for disabling the circuit clock signal during a period of time. Product circuit. 9. The integrated circuit according to claim 8, wherein the clock stabilizing circuit is an external circuit. Detects the state of the oscillator signal and creates a clock control signal that indicates the state of the external oscillator signal. An oscillator stabilizing circuit for The clock control to enable or disable a circuit clock signal. A clock control circuit adapted to respond to control signals, An integrated circuit comprising: 10. The integrated circuit according to claim 1, wherein said synthesizer module. But also Transferring the synthesized digital audio data to the coding / decoding module A digital signal transfer circuit for An integrated circuit comprising: 11. The integrated circuit according to claim 1, wherein the synthesizer comprises: Means for creating digital voice data for a plurality of voices; Means for combining the digital data of the audio into a composite digital audio signal; A plurality of programmable synthesizer audio control registers; To change the frequency of each audio in response to the state of the programmable register Means, An integrated circuit comprising: 12. The integrated circuit according to claim 1, wherein said synthesizer module. But also A data input circuit for obtaining audio signal data from an external source; An integrated circuit comprising: 13. 13. The integrated circuit according to claim 12, wherein the synthesizer module is And a memory circuit for temporarily storing digital audio data. Integrated circuit. 14. The circuit of claim 1, further comprising: A game port module, wherein the game port module has a game port module. An analog input circuit for receiving a frame control signal from an external device; Analog-to-digital converter for converting analog input signals to digital signals When, A circuit comprising: 15. The circuit of claim 1, further comprising a circuit between the circuit and an external device. Instrument digital interface module for providing data communication Circuit to do. 16. The circuit of claim 1, further comprising: Local memory for directly interfacing the integrated circuit with an external storage device A control module; A circuit comprising: 17. The circuit of claim 16, wherein the local memory control module is To enable data transfer between the integrated circuit and an external storage device. A memory interface circuit for creating address and control signals Circuit to be equipped. 18. The circuit according to claim 17, wherein the memory interface circuit is Interface between external random access storage and read-only storage A circuit comprising means for: 19. The circuit according to claim 18, wherein the local memory control module The independent storage cycle for random or read-only access. Logic circuit for defining, and the integrated circuit and the external storage device on a common conductor With control circuitry for multiplexing address, control, and data communication between Circuit. 20. The circuit according to claim 17, wherein the memory interface circuit is ,further, Serial data communication circuit for receiving serial data from external storage device And a logic circuit for generating a control signal in the external storage device. 21. The circuit of claim 17, wherein the local memory control module But also A selected module of the integrated circuit is allowed access to an external storage device. Circuit with a state machine to define and control the time period in which 22. The circuit according to claim 21, wherein said system control module comprises: Memory access mode control to create one or more memory mode control signals A control register and a mode control signal generating circuit, wherein the state machine has an extended mode. An extended time period of access to an external storage device in response to a load control signal Circuit with a logic circuit for creating a delay state for 23. The circuit according to claim 17, wherein the memory interface circuit is For generating a refresh signal on an external dynamic random access storage device A circuit with a path. 24. The circuit of claim 23, wherein the integrated circuit conserves energy. And a register-controlled power-down signal generation circuit, The power of the fresh circuit to provide a refresh signal at reduced speed A circuit including a logic circuit corresponding to the down signal; 25. The circuit according to claim 17, wherein the memory interface circuit is , Start address and end address of a block of memory provided in the external storage device. Address definition register to define the address and the beginning of the defined block Automatic address generation circuit for generating a continuous address signal from end to end circuit. 26. The circuit of claim 17, wherein the local memory control module Is An interrupt circuit for generating an interrupt request signal in the host system processor; , Means for receiving data from the host memory; Means for transferring the received data to an external storage device; A circuit comprising: 27. The circuit according to claim 26, wherein the local memory control module is Is Direct memory access request signal to the central processing unit of the host system Direct memory access means for creating the Data from host system memory under direct memory access control Means for receiving, Means for transferring data from the host system memory to the external storage device; A circuit comprising: 28. The circuit according to claim 27, wherein said direct memory access Means for storing data in the host system memory as the data is stored in the external storage device; A circuit comprising means for interleaving data received from the circuit. 29. The circuit according to claim 17, wherein the memory interface circuit is Enables 8-bit or 16-bit access to external storage A circuit comprising means for performing 30. The circuit of claim 17, wherein the memory interface circuit Address and signal to define the first-in / first-out register of the external storage device. And means for generating control signals. 31. The circuit of claim 2, wherein the register data bus comprises Comprising eight 8-bit data bus elements, wherein the system control module comprises 8-bit or 16-bit I / O access between the integrated circuit and the host system A circuit comprising means for enabling 32. The circuit according to claim 1, wherein an analog signal input / output terminal of the circuit. Is a circuit isolated from digital input / output terminals. 33. The circuit according to claim 1, wherein the system power input terminal and the system power input terminal. A circuit wherein a grounded input terminal is provided to a sensed analog signal terminal of the integrated circuit. 34. The circuit of claim 7, wherein the internal clock circuit is a digital circuit. A digital clock generation circuit for providing a first timing signal to circuit operation; And an analog clock for providing a second timing signal to analog circuit operation. A clock generation circuit, wherein the second timing signal is derived from the first timing signal. An independent circuit. 35. The circuit of claim 1, wherein the integrated circuit comprises a plurality of address fingers. The system control module includes an external processor or Is used to enable direct access to the circuit registers by the control circuit A circuit comprising: 36. The circuit according to claim, wherein said system control module comprises: Buffers input and output signals communicated between the integrated circuit and the processor accessible bus A circuit including a buffering circuit for storing the data in the buffer. 37. The circuit according to claim 36, wherein the buffering circuit comprises the integrated circuit. Subsequent I / O operations between the integrated circuit and the processor accessible bus are buffered. A circuit comprising means for delaying completion of an input / output operation. 38. A stereo audio encoder / decoder (codec) circuit, (a) an analog mixer circuit having a plurality of inputs and outputs, (b) a multi-stage interpolation filter circuit having at least one input and one output, Digital analog with noise shaper circuit and semi-digital FIR filter circuit A conversion circuit, whereby the at least one output is connected to the analog mixer. A digital-to-analog conversion circuit connected to the input of the mixer circuit; (c) a fourth-order sigma-delta modulation circuit having at least one input and one output. Circuit, multi-stage digital decision filter circuit and digital correction circuit A log-to-digital conversion circuit, whereby at least one input is said analog An analog-to-digital conversion circuit connected to the output of the log mixer circuit; (d) at least one input of the digital-to-analog conversion circuit; Data connected to the at least one output of the analog-to-digital conversion circuit A format conversion circuit; (e) a one-chip memory for storing digital audio signals, whereby The data format conversion circuit is connected to the one-chip memory; Data input to or output from the chip memory A one-chip memory for realizing the data compression / decompression operation of With The digital / analog conversion circuit and the analog / digital conversion circuit are independent. Can operate at up to programmable sample rates, Stereo audio encoder / decoder (codec) circuit. 39. The codec of claim 38, further comprising the one-chip memo. Codec having a serial transfer control circuit connected to the 40. The codec of claim 38, further comprising the digital analyzer. Controlling the sample rate at which the log circuit and the analog / digital circuit operate Clock to create an independent clock signal so that you can select Codec with circuit. 41. The codec according to claim 38, further comprising the analog mixer. Amplitude of a signal input to or output from the analog mixer circuit Codec having a zero-crossing detection circuit for controlling an audio signal. 42. The codec of claim 38, further comprising the one-chip memo. Interleave the data coming into the external system memory from the Alternatively, the external system may be used before the data is input to the one-chip memory. .Times. For interleaving interleaved data retrieved from memory A codec with a path. 43. The codec according to claim 39, wherein the serial transfer control circuit comprises an external For providing bi-directional serial data between the DSP and the one-chip memory Check. 44. The codec according to claim 38, further comprising an input and an output. A digital-to-analog conversion circuit, The output of the sizer data digital-to-analog conversion circuit is Codec connected to the input of the mixer. 45. The method of claim 38, further comprising off-chip local memory. A codec, wherein the local memory is connected to the on-chip memory. Codec. 46. The codec of claim 45, wherein the digital data path is Codec that exists between off-chip local memory and external DSP. 47. The codec according to claim 38, further comprising: A codec that provides control signals to an external CD-ROM interface. 48. The codec stored in claim 38, further comprising plugging in. Non-volatile serial memory interface to provide ready-to-use compatibility And the nonvolatile serial memory interface is connected to an external operating system. Codec that communicates with the operating system. 49. The codec of claim 45, wherein the off-chip local A memory providing data to the on-chip memory, the on-chip memory A codec configured as a PIFO to receive data from. 50. The codec of claim 45, wherein the off-chip local The memory is controlled by an on-chip data sample counter and the data Data sample counter has the ability to create system level interrupts. Check. 51. The codec according to claim 38, wherein the input to the mixer is The analog microphone signal is applied to a plurality of other analog inputs to the mixer. Codec summed by log signal. 52. The codec of claim 39, wherein the analog signal passes through the mixer. A path between the input from the digital / analog conversion circuit and the analog / digital Codec that exists between conversion circuits. 53. The codec of claim 38, wherein the analog mixer circuit is Output from the synthesizer digital-analog conversion circuit as an input signal Codec with analog signal. 54. The codec of claim 38, wherein the on-chip memory is a processor. It has a layback path FIFO and a recording path FIFO, each of said FIFOs Create system-level interrupts and / or DMA scheduling Codec with programmable I / O thresholds for 55. The codec of claim 38, wherein the analog mixer circuit is A control for controlling attenuation / gain of at least one of the plurality of mixer outputs. A codec equipped with a programmable master volume control circuit. 56. The codec of claim 41, wherein the zero crossing detection circuit further comprises: Then, a comparator circuit provided in the zero-crossing detection circuit is powered up. Comprising at least one fixed timer for controlling the length of time that it remains Codec. 57. The codec according to claim 40, wherein the clock generation circuit comprises a Selectable clocks for frequencies that change within the first and / or second frequency range A codec that creates a clock signal. 58. The codec of claim 39, wherein the serial data transfer control is performed. The control circuit is configured to control the off-chip local memory and the digital-to-analog conversion circuit. A first digital data loopback path between the off-chip local Between the digital memory and the analog / digital control circuit. Codec with loopback path. 59. The codec according to claim 39, wherein the serial transfer control circuit comprises an external Codec with bi-directional digital data path to external synthesizer DSP. 60. The codec of claim 38, wherein the analog to digital conversion is performed. Circuit, or the digital-to-analog conversion circuit, or both, may be independent A programmable sample rate, wherein said independent programmable sample rate comprises: Within one sample period, the analog-to-digital conversion circuit and the digital Changes can be made without disabling the operation of the analog circuit in the analog converter. Codec. 61. The codec of claim 59, wherein the digital-to-analog conversion is performed. The independent programmable sample rate of the circuit is variable and programmable in approximately 256 steps. A codec that is programmable. 62. The codec of claim 38, further comprising: Implement power management circuitry to allow power to be selected for at least some Codec to be equipped. 63. The codec of claim 45, wherein the off-chip local Local for controlling data transfer operation between a memory and the on-chip memory Codec including a memory control circuit. 64. The codec of claim 38, wherein the codec is 3.3. A slate on whether the unit is operating on volts or 5.0 volts. Equipped with a 3.3 / 5.0 volt detection circuit to provide status information to external systems Codec. 65. Multiple analog inputs and outputs, analog signal mixing, digital A voice control circuit provided with a log conversion circuit and an analog / digital conversion circuit Recording comprising a plurality of analog input signals and an analog-to-digital conversion circuit Signal path, digital input signal and playback signal with digital conversion circuit Route, transfer the converted analog signal from the digital / analog circuit to the output terminal And a playback signal path digital-to-analog conversion circuit Or the recording signal path analog / digital conversion circuit or both. Voice control circuit having a logic control circuit for independently controlling the pulling speed . 66. The codec of claim 59, wherein the digital If the independent programmable sample rate of the analog conversion circuit is more than one A codec that is variable and programmable in steps. 67. Analog input / output, analog signal mixing function, digital / analog conversion circuit, And a voice control circuit having an analog-to-digital conversion circuit. Recording signal path and data comprising an analog input signal of Playback signal path with digital input signal and digital-to-analog conversion circuit Digital audio data sample input to the digital-to-analog conversion circuit On-chip PIPO memory and off-chip local memory for storing And the playback signal path digital / analog conversion circuit and the recording signal Path to independently control the sampling rate of the analog-to-digital converter. An audio control circuit including a logic control circuit. 68. The noise shaper circuit according to claim 38, wherein the noise shaper circuit is a fifth-order sigma-delta transform. Codec with circuit. 69. A one-bit noise shaper circuit, 5th-order delta-sigma converter network with multiple feedback paths So that the n-bit digital signal input to said noise shaper circuit is Is converted to a 1-bit digital output signal, and n exceeds 1, and the noise shaper circuit The noise passband of the path is at least 0.20f, exceeding the signal bandwidth of the noise shaper circuit 1-bit noise shaper circuit. 70. The one-bit noise shaper circuit of claim 69, wherein the circuit comprises: Set the signal transfer function shown below, , In this case X (z) is the digital audio input signal, whereby , In this case, about Wk, A1-5 is the pole positioning feedback coefficient, and B1-2 is the zero positioning feedback coefficient. A 1-bit noise shaper circuit where the feedback coefficient is K1-5 and the digit shifter is K1-5. 71. The one-bit noise shaper circuit of claim 69, wherein the circuit comprises: The noise transfer function is set, Thereby, A1-5 is the pole positioning feedback coefficient, and B1-2 is the zero positioning feedback coefficient. A 1-bit noise shaper circuit where the feedback coefficient is K1-5 and the digit shifter is K1-5. 72. The one-bit noise shaper circuit of claim 69, wherein the one-bit output. A 1-bit noise shaper circuit wherein the signal has a phase variation not exceeding about 0.05 degrees. 73. The one-bit noise shaper circuit of claim 69, wherein the one-bit noise shaper circuit comprises The circuit has a sampling frequency of about 8 KHz for the n-bit digital input signal. When the passband noise edge of about 6 KHz and the n-bit digital input signal One bit with a passband noise edge of about 36 KHz when the sampling frequency is about 48 KHz Noise shaping circuit. 74. The one-bit noise shaper circuit of claim 69, wherein the one-bit noise shaper circuit comprises The circuit has the following zeros and poles, and in this case, and 1-bit noise shaper circuit. 75. The one-bit noise shaper circuit according to claim 70, wherein the digit shifters K1-5 and K1-5 And the following values are set for the feedback coefficient B1-2, k1 = 0.25, k2 = 0.5, k3 = 0.25, k4 = 0.5, and k5 = 0.125, and B1 = -0.039326867, B2 = -0.0149988 1-bit noise shaper circuit. 76. The one-bit noise shaper circuit of claim 71, wherein the digit shifter comprises: Value is set k = 0.5 and k4 = 0.5 1-bit noise shaper circuit. 77. The one-bit noise shaper circuit of claim 69, wherein the fifth-order delta 1-bit sigma conversion circuit network with noise gain factor less than about 1.85 Noise shaping circuit. 78. Noise control of the type with n-bit digital input signal and 1-bit output signal A shaper circuit, (a) a first integrator having an input and an output; (b) a first summing node having a plurality of inputs and outputs; An input of a one adder node is connected to the output of the first integrator and the first adder A first summing node having another input of the node connected to the first feedback signal path; , (c) a second summing node having a plurality of inputs and outputs, wherein said second summing node The output of the one addition node is connected to the input of the second addition node; A second feedback signal path connected to another of said inputs of said second summing node; Nodes and (d) a second integrator having an input and an output, whereby the input is the second A second integrator connected to the output of the two adding node; (e) a third summing node having a plurality of inputs and one output, whereby: The output of the second integrator is connected to one of the inputs of the third summing node; Another of the inputs of the third summing node is connected to a third feedback signal path A third addition node to be (f) a third integrator having an input and an output, wherein the input of the third integrator is Connected to the output of the third summing node, wherein the output of the third integrator is A third integrator connected to the two feedback signal paths; (g) a fourth summing node having a plurality of inputs and one output, whereby An input of the fourth summing node is connected to the output of the third integrator, Another input of the fourth addition node is connected to a fourth feedback signal path. And (h) a fifth summing node having a plurality of inputs and one output, whereby: An input of the fifth summing node is connected to the output of the fourth summing node; Another input of the fifth summing node is connected to a fifth feedback signal path. Arithmetic node, (i) a fourth integrator having an input and an output, whereby the fourth integrator comprises A fourth integrator having the input connected to the output of the fifth summing node; (j) a sixth summing node comprising a plurality of inputs and one output, wherein An input of the sixth summing node is connected to the output of the fourth integrator; Another input of the sixth summing node is connected to a sixth feedback signal path. An addition node, (k) a fifth integrator having an input and an output, whereby the input is the 6 is connected to the output of the summing node, and the output of the fifth integrator is connected to the fifth A fifth integrator connected to the feedback signal path and the one-bit signal output node; , (l) an input summing node having a plurality of inputs and one output, whereby One of the inputs of the input summing node is connected to the n-bit digital input signal. Connected, another input of the input summing node connected to a seventh feedback signal path Wherein the output of the input summing node is connected to the input of the integrator An addition node, A noise shaper circuit comprising: 79. The one-bit noise shaper circuit of claim 69, wherein the noise passband 1-bit noise shaper whose bandwidth exceeds 0.25f and the signal band of the noise shaping circuit circuit. 80.By converting an n-bit digital input signal to a 1-bit digital output So, in this case, n is greater than 1, (a) providing an n-bit digital input signal to a fifth-order sigma-delta conversion circuit; And (b) the noise passband of the sigma-delta network is Extending the signal band beyond at least 0.20f; (c) converting the n-bit input signal into a 1-bit digital output signal through the fifth network; Converting to an issue; How to configure. 81. (a) Multi-stage interpolation filter circuit with multi-bit input and multi-bit output Road and (b) a noise shaper circuit having a multi-bit input and a 1-bit output, The noise shaping input is the multi-bit output from the multi-stage interpolation filter circuit. A noise shaper circuit connected to the output, (c) A semi-digital FIR filter circuit having a digital input and an analog output. Wherein the FIR filter digital input is output from the noise shaper circuit. -A semi-digital FIR filter circuit connected to the bit, A digital-to-analog conversion (DAC) circuit comprising: 82. The DAC circuit according to claim 81, wherein a first stage of the multi-stage interpolation filter is A linear phase FIR filter with input, output, and 2N-1 taps, The first stage converts the frequency of the digital audio signal input to the first stage into the DAC circuit that oversamples the digital audio input signal at twice the sampling rate. 83. The DAC circuit according to claim 82, wherein a second stage of the multi-stage interpolation filter is Comprising a two-phase sinc5 interpolation second stage comprising an input and an output, said second stage input comprising: Connected to the output of the first interpolation stage so that the sinc5 stage Oversampling at 4 times the sampling rate of the digital audio signal input to the interstage The input of the second stage is connected to a first multiplier and a first delay block; An output of the first delay block is input to a second delay block and a second multiplier, An output of the second delay block is input to a third multiplier, and the first multiplier performs a first process. Path, the second multiplier is in a second processing path, and the third multiplier is in a third path. And the first processing path, the second processing path, and the third processing path operate in parallel. The output of the first processing path is the output of the second processing path in a first summing node. And the output of the third processing path and the output of the second processing path are The oversampler at the output of the second stage is summed at the Sampled selectively between the output of the summing node and the second summing node; A DAC circuit for outputting the sample thus selected to said output. 84. The DAC circuit of claim 83, wherein a third stage of the multi-stage interpolation filter is , A third stage of sinc2 interpolation with inputs and outputs, said third stage output comprising said sin c5 is connected to the output of the second stage so that the third stage of the sinc2 is The output is 64 times the sampling rate of the digital audio signal input to the first interpolation stage. Oversampled by a factor of two and the third stage input Input to the first summing node, and the output of the double delay block is negative. Is input to the first addition node, and the output of the first addition node is Input to the single delay block, input to the second addition node, and The output of the lock is input to the second addition node, and the output of the second addition node is Connected to an oversampler, wherein the oversampler is an output of the second summing node. Are sampled by a selection formula, and each of the selected samples is added to the third addition node. Input to the input of the third summing node at 16 times the clock speed of the third summing node. The output of the second independent delay block is input to the second independent delay block. The force is not only fed back to the input of the third DAC output from the third stage as a bar-sampled signal. 85. The DAC circuit according to claim 82, wherein the linear phase FIR filter first stage. Further comprises a two-phase filter, wherein the first-phase sub-filter is preceded by an odd number of coefficients. Create an odd number of signal samples by multiplying the digital audio input signal A second phase sub-filter multiplies the digital audio input signal by an even number of coefficients Thereby creating an even number of signal samples, whereby the sub-filters DAC circuit to run on. 86. The DAC circuit according to claim 81, wherein the noise shaper circuit is a fifth-order sigma. -A DAC circuit including a delta conversion circuit. 87. The DAC circuit according to claim 86, wherein said fifth-order sigma-delta converter circuit The following signal transfer function is set to , Where X (z) is the digital audio input signal, and , In this case Wk A1-5 is the pole positioning feedback coefficient and B1-2 is the zero positioning feedback coefficient. DAC circuit with feedback coefficient and K1-5 as digit shifter. 88. The DAC circuit according to claim 81, wherein the noise shaper circuit is an integrated circuit of the circuit. A DAC circuit that extends the noise passband to at least about 0.7f. 89. The DAC circuit according to claim 81, wherein the noise shaper circuit comprises a noise passband. A DAC circuit that extends the range to at least about 0.70f. 90. The DAC circuit of claim 81, wherein the noise shaper circuit comprises the shaper. DAC circuit that extends the noise pass band of the circuit to about 0.75f. 91. The DAC circuit according to claim 86, wherein the fifth-order sigma-delta conversion circuit is provided. The following noise transfer function is set, Thereby, , In this case Wk A1-5 is the pole positioning feedback coefficient, and B1-2 is the zero positioning feedback coefficient. A DAC circuit with the feedback coefficient and K1-5 as the digit shifter. 92.   82. The DAC circuit of claim 81, wherein the noise shaper circuit comprises five products. A fifth-order sigma-delta network comprising a divider, Two of the integrators have the same value as the other two digit shifter coefficients of the integrator. C circuit. 93.   83.The DAC circuit of claim 81, wherein the noise shaper circuit comprises about 1. 85 to 5th order sigma delta network with lower noise gain factor (K) set DAC circuit. 94.   The DAC circuit according to claim 81, wherein the semi-digital FIR filter comprises: (a) Clock input, 1-bit digital audio signal input, and multiple data output A shift register with a flip-flop; (b) a plurality of current sinks; (c) a plurality of DC offset current sources; (d) a first current adding operational amplifier and a second current adding operational amplifier, wherein the current Summing amplifier has voltage output node and positive and negative input nodes The negative input node for each of the current summing operational amplifiers is the DC offset current Connected to different nodes of source and selectively connected to one of the current sinks The positive input of each current summing operational amplifier. A node is connected to a reference voltage and a first resistor is connected to the first current summing operational amplifier. A second resistor connected between the current summing node and the voltage output node; 2 A connection is made between the current summing node and the voltage output node on the current summing operation amplifier. The voltage at each of the voltage output nodes of the current summing operational amplifier is The current selectively connected to the current summing node for each current summing operation amplifier; A first current adding operational amplifier and a second current adding operational amplifier related to the value of the sink; , (e) With a single-ended voltage output node and positive and negative voltage input nodes An operational amplifier, wherein said negative voltage input node is connected to said first and second terminals through a third resistor. Or the second current summing operational amplifier is connected to the voltage output node, and the positive voltage input Is connected to the voltage output node of the other current summing operation amplifier through a fourth resistor. A fifth resistor is connected to the reference voltage, and a sixth resistor is connected to the negative voltage input node. And the single-ended voltage output node. The voltage on the output node is the current for each of the current summing operational amplifiers. An operational amplifier related to the value of the current sink selectively connected to a summing node; DAC circuit comprising: 95.   A method of converting an n-bit digital signal to an analog signal, (a) inputting the n-bit signal to a multi-stage interpolation circuit filter circuit; (b) converting the input n-bit digital signal into a sample rate of the n-bit signal Interpolating 64 times of (c) outputting the interpolated signal to a noise shaper circuit; (d) converting the interpolated signal to a 1-bit output signal; (e) inputting the 1-bit output signal to a semi-digital FIR filter circuit; (f) converting the 1-bit signal to an analog output signal; How to configure. 96.   A method for converting an n-bit digital audio signal to an analog audio signal, , (a) inputting the n-bit audio signal to a three-stage interpolation circuit filter circuit; (b) converting the input n-bit digital signal of the first stage interpolation circuit to the n-bit Interpolating to twice the sample rate of the digital audio signal; (c) outputting the first-stage interpolation signal to a second-stage interpolation circuit; (d) the first-stage interpolation signal is four times the sampling rate of the n-bit digital audio signal Interpolating between (e) outputting the second-stage interpolation signal to a third-stage interpolation circuit; (f) The second-stage interpolation signal is set to 64 of the sample rate of the n-bit digital audio signal. Interpolating twice, (g) outputting the third stage interpolation signal to a 1-bit noise rectifier circuit; (h) converting the third stage interpolation signal to a 1-bit signal; (i) outputting the 1-bit signal to a semi-digital FIR filter circuit; (j) converting the 1-bit signal to an analog audio output signal; How to configure. 97.   The method of claim 96, wherein the first interpolator is a linear phase FIR filter. A method that includes ruta. 98.   97. The method according to claim 96, wherein the second stage interpolator is a sinc5 filter. A method comprising: 99.   97. The method according to claim 96, wherein the third interpolator includes a sinc2 filter. How to prepare. 100.   95. The DAC circuit according to claim 94, wherein a first capacitor is the first resistor. DAC connected in parallel with a resistor and a second capacitor connected in parallel with the second resistor circuit. 101.   The method of claim 96, further comprising: (k) low-pass filtering the analog audio output signal; How to configure. 102.   (a) a multi-bit digital input; (b) a first multiplexer having a plurality of inputs and one output, wherein the first multiplexer has A digital input signal is connected to one of the inputs of the first multiplexer. One multiplexer, (c) a first adder comprising a plurality of inputs and one output, wherein the first adder A first adder having a multiplexer output connected to one of the plurality of first adders; (d) a shift register having an input and an output, wherein the output of the first adder is A shift register whose input is connected to the shift register input; (e) a second adder having a plurality of inputs and one output, wherein A second adder having a register output connected to one of the plurality of second adder inputs; With The output of the second adder is provided to the output quantizer as a 1-bit digital output signal. Sigma-delta modulation circuit for digital-to-analog conversion (DAC) circuit provided. 103.   (a) output from the first serial configuration of the digital input circuit and the data register; A first device for selecting between signals to be selected, wherein the selected signal is a first adder. A first device provided to the calculator; (b) a field provided to the first adder that is summed with the selected signal. The feedback signal and the selection coefficient value, (c) an output of the first adder that is approximated before being provided to a second adder; (d) between one of the two signals output from the second serial configuration of the data register; A second selection device for selecting at one of the two signals, wherein one of the two selected signals is A second sum provided to the second adder summed with the estimated first adder output signal. A selection device; With A 1-bit output signal is output from the second adder; To convert a multi-bit digital input signal to a 1-bit digital output signal Digital sigma-delta modulation circuit. 104.   104. The modulation circuit of claim 103, wherein the output of the second adder is quantized. Modulation circuit provided to the instrument. 105.   The modulation circuit according to claim 104, wherein the quantizer is a flip-flop. A modulation circuit having a flip-flop. 106.   (a) a multi-bit input signal; (b) a first group of data registers connected in series; (c) a second group of data registers connected in series; (d) the multi-bit digital input signal and the serially connected data A first register for selecting between output signals from the last register of the first group of registers; A multiplexer, wherein the signal selected by the first multiplexer is a first multiplexer. A first multiplexer provided to the input of the adder; (e) the last register of the second group of the serially connected data registers Output signals and the serially connected data registers in the second group of data registers. A second multiplexer for selecting between output signals from the intermediate register, The signal selected by the second multiplexer is provided to an input of a second adder And The output of the first adder is approximated and then provided to another input of the second adder , The output of the second adder is output as a 1-bit digital output signal to an output quantizer. Provided, A second multiplexer; Oversampling digital sigma digital Luther modulation circuit. 107.   107. The sigma-delta modulation circuit according to claim 106, wherein the quantizer Is a sigma-delta modulation circuit having a flip-flop. 108.   The sigma-delta modulation circuit according to claim 106, further comprising: An input selectively connected to a first or second data register; Dell with coefficient decoding circuit having an output connected to another input of the detector Modulation circuit. 109.   107. The sigma-delta modulation circuit according to claim 106, wherein the second addition is performed. The output of the device is also the first in the second group of data registers connected in series. A sigma-delta modulation circuit provided in one register. 110.   107.The sigma-delta modulation circuit according to claim 106, wherein the 1-bit After the digital output signal is multiplied by the 1-bit signal by the first coefficient, A first multiplexer that provides the product of said multiplications as an input to a plexer Sigma-delta modulation circuit. 111.   The sigma-delta modulation circuit of claim 110, wherein the sigma-delta modulation circuit is connected in series. The output from the last register of a first group of data registers to be connected The sigma. Signal is also provided as another input to the third multiplexer. Delta modulation circuit. 112.   112. The sigma-delta modulation circuit according to claim 111, wherein the third multiplexer A sigma-delta modulation circuit whose output is provided as an input to a third adder. Road. 113.   107.The sigma-delta modulation circuit of claim 106, wherein the sigma-delta modulation circuit is connected in series. Each of the first and second groups of data registers to be A sigma data modulation circuit including three data registers. 114.   Multi-bit digital input signal is converted to 1- Converting to a bit digital output signal, (a) providing a set of cascaded integration stages; (b) a multi-bit digital input signal and a 1-bit digital Providing an output signal; (c) quantizing the 1-bit digital output signal; (d) multiplying the quantized 1-bit output signal by a plurality of filter coefficients. And (e) The nodes discarded between the individual collection stages in the set of integration stages Providing a plurality of calculated coefficients; How to configure. 115.   115.The method of claim 114, wherein said multiplying comprises 1-bit The method achieved by multiplication. 116.   Converts a multi-bit digital input signal to a 1-bit digital output signal Method (a) Multi-bit digital input signal, 1-bit digital output signal, and multiple A sigma-delta modulator circuit filter comprising a set of adders The set computing the sum of the two data terms; (b) the sum of two data terms calculated by each of the set of addresses; Estimating, (c) dividing the third data term by the approximation of each two data terms of the set of adders; Adding the calculated sum; How to configure. 117.   117. The method of claim 116, wherein the collection of at least one said adder. The step of estimating the sum by shifting the two data terms How to be. 118.   The method of claim 116, further comprising the 1-bit digital A method comprising the step of quantizing an output signal. 119.   119. The method of claim 118, further comprising at least one fill. The quantized 1-bit with at least one filter coefficient to create a data product. And multiplying the digital output signal by a digital signal. 120.   120. The method according to claim 119, wherein at least one of said set of adders. The data terms summed together form at least one of the filter products Way. 121.   The method of claim 116, further comprising: (d) providing at least one additional single adder; (e) adding the feedback filter coefficient to the sigma-delta modulation circuit filter Multiplying by the data feedback term output from the included integration stage Calculating the filter product with at least one additional single adder, How to configure. 122.   Using a digital sigma-delta modulator, multi-bit digital A method of converting an input signal into a 1-bit digital output signal, (a) inputting the multi-bit digital input signal; (b) output from the first group of data registers connected in series with the input signal; Selecting between the signals to be applied; (c) adding the selected signal to a feedback signal; (d) estimating the summed signal; (e) transferring the estimated signal to a second group of data registers connected in series; Adding with a first selection signal output from (f) the estimated signal and a first selection signal from the sigma-delta modulation circuit Outputting the sum of the two as a 1-bit digital output signal. how to. one two Three.   115. The method of claim 114, further comprising the serially connected data. A signal output from the data register and a signal in the second group of the data register. Selecting between signals output from an intermediate register of the Out of a second group of said serially connected data registers summed with signals. Providing the selected signal as the signal to be applied. Law. 124.   The method of claim 115, further comprising: selecting the selected coefficient value. A method comprising summing a selection signal and said feedback signal. 125.   126. The method of claim 125, wherein the estimating step comprises: A method achieved by shifting the measured select signal by a minimum of two bits. 126.   (a) a plurality of integration stages with a filter output, (b) a multi-bit digital input input to a first integration stage of the plurality of integration stages; A force signal, The filter output is input to a quantizer, the quantizer comprising an output, The quantizer output comprises a 1-bit digital output signal; After the 1-bit output signal is multiplied by a filter coefficient, the plurality of integration stages Feedback to each of the A multi-bit digital input signal, A digital sigma-delta modulation circuit filter comprising: 127.   Digital wavetable audio to create digital delay-based audio effects A method of using a synthesizer, (a) Create a first digital audio signal from data stored in an external wavetable memory Tep, (b) storing the first digital audio signal in the synthesizer; (c) writing the first digital audio signal from the synthesizer to the wavetable memory And the steps involved (d) upon selection after step (c), the first digital sound from the wavetable memory; Reading a voice signal; (e) from the first digital audio signal read from the wavetable memory, Creating a second digital audio signal representing a delayed version of the first digital audio signal Steps and how to configure. 128.   The method of claim 127, further comprising: The first digital audio signal, the second digital audio signal, or the first digital audio signal; Multiplying both the audio signal and the second digital audio signal by a volume component Steps and How to configure. 129.   The method of claim 127, further comprising: Repeating steps (a)-(e) as desired; How to configure. 130.   The method of claim 129, further comprising: Each time steps (a)-(e) are repeated, use LFO creation means to Changing the selection time; How to configure. 131.   Digital wavetable audio synth to create delay-based audio effects A method of using a sizer, (a) Create a first digital audio signal from data stored in an external wavetable memory Steps (b) storing the first digital audio signal in the synthesizer; (c) writing the first digital audio signal from the synthesizer to the wavetable memory; And the steps involved (d) upon selection after step (c), the first digital sound from the wavetable memory; Reading a voice signal; (e) a first delay from the first digital audio signal read from the wavetable memory; Creating a post-based digital audio signal; (f) storing the first delay-based digital audio signal in the synthesizer; And (g) the first delay-based digital from the synthesizer to the wavetable memory; Writing an audio signal; (h) upon selection after step (g), the first delay base from the wavetable memory; Reading an audio signal; (i) the first delay-based digital audio signal read from the wavetable memory; Generating a second delay-based audio signal from the signal; How to configure. 132.   132. The method of claim 131, wherein the first delay-based audio signal is Before being written to the wavetable memory, the delay-based audio signal is The method by which the components are multiplied. 133.   Digital wavetable synthesizer to create delay-based sound effects The method of using (a) Create a first digital audio signal from data stored in an external wavetable memory Steps (b) storing the first digital audio signal in the synthesizer; (c) writing the first digital audio signal from the synthesizer to the wavetable memory; And the steps involved (d) upon selection after step (c), the first digital sound from the wavetable memory; Reading a voice signal; (e) a first delay from the first digital audio signal read from the wavetable memory; Creating a post-base digital audio signal; (f) If the last step was step (e), the synthesizer Step of storing one-delay-based audio signal or repeating steps (f)-(i) If it has been created before the last time it was created in step (i) on the synthesizer. Storing a subsequent delay-based audio signal; (g) the synthesizer of step (f) from the synthesizer to the wavetable memory; Writing the delay-based digital audio signal stored in the (h) at the time of selection after step (g), from the wavetable memory, reading the delay-based audio signal stored in a wavetable memory; (i) from the delay-based audio signal read from the external memory of step (h) Creating a subsequent delay-based audio signal; (j) repeating steps (f)-(i) as desired; How to configure. 134.   A method according to claim 133, wherein prior to step (f), step (f) Wherein said delay-based audio signal stored in said synthesizer is a volume component Multiplied by. 135.   The method of claim 133, further comprising: Each time steps (f)-(i) are repeated, use LFO creation means to Changing the selection time; How to configure. 136.   (a) for storing a digital audio signal created by the synthesizer Storage device; (b) writing the digital audio signal stored in the storage device to an external wavetable Means for (c) the signal is written to the external memory by the writing means; After reading the digital audio signal from the external wavetable at the time of selection Means, Digital wavetable audio synth with the ability to create delay-based effects with Siza. 137.   139. The synthesizer according to claim 136, wherein the storage device is one or more. Wherein the means for writing comprises an accumulator from the accumulator. A synthesizer that writes digital audio signals to external memory. 138.   The synthesizer according to claim 136, further comprising: the storage device; To interface between the external wavetables and write to the external device, Temporarily storing said digital audio signal from said storage device of said means for writing Synthesizer with FIFO buffer to store. 139.   139. The synthesizer according to claim 138, wherein said storage device is one or more. Synthesizer comprising the accumulator of the above. 140.   139. The synthesizer according to claim 136, wherein said means for writing However, a synthesizer further having a function of clearing the storage device. 141.   140. The synthesizer according to claim 137, wherein said means for writing Has the function of clearing each of the one or more accumulators Synthesizer. 142.   139. The synthesizer according to claim 138, wherein said means for writing However, a synthesizer having a function of clearing the storage device. 143.   140. The synthesizer according to claim 139, wherein said means for writing. Has the function of clearing each of the one or more accumulators Synthesizer. 144.   (a) for storing digital audio signals created by the synthesizer One or more accumulators of (b) storing the digital audio signal accumulated by the one or more accumulators; A temporary storage device for (c) writing the digital audio signal stored in the temporary storage device to an external wavetable Means for (d) the signal is written to the external memory by the means for writing At a later time, for reading the digital audio signal from the external wavetable. Means and Digital wavetable audio synth that can create delay-based effects Siza. 145.   The synthesizer according to claim 144, wherein the temporary storage device is a FIFO. A synthesizer that is a buffer. 146.   148. The synthesizer according to claim 144, wherein said means for writing Has the function of clearing each of the one or more accumulators Synthesizer. 147.   148. The synthesizer according to claim 145, wherein said means for writing Has the function of clearing each of the one or more accumulators Synthesizer. 148.   (a) for storing digital audio signals created by the synthesizer Multiple accumulators, (b) storing digital audio signals accumulated by the plurality of accumulators; A temporary storage device for (c) writing the digital audio signal stored in the temporary storage device to an external wavetable Means for (d) the signal is written to the external memory by the means for writing At a later time, for reading the digital audio signal from the external wavetable. Means, Digital wavetable audio synth with the ability to create delay-based effects with Siza. 149.   The synthesizer according to claim 140, further comprising: Which one of the plurality of accumulators is created by the synthesizer Means for selecting whether to store a fixed digital audio signal, Synthesizer comprising: 150.   The synthesizer according to claim 148, wherein the temporary storage device A synthesizer that is a FIFO buffer. 151.   148. The synthesizer according to claim 148, wherein said means for writing Has a function of clearing each of the plurality of accumulators. The synthesizer. 152.   150. The synthesizer according to claim 149, wherein said means for writing Has a function of clearing each of the plurality of accumulators. The synthesizer. 153.   150. The synthesizer according to claim 150, wherein said means for writing Has a function of clearing each of the plurality of accumulators. The synthesizer. 154.   Low frequency oscillator (LFO) generator for digital wavetable speech synthesizer Wherein said synthesizer comprises: (i) at least a plurality of digital A digital audio signal is generated, and each of the plurality of digital audio signals is Created from wavetable data addressed by the synthesizer, (ii Waveform data addressing for each of the digital audio signals being created An address generator for setting, wherein the LPO generator comprises: (a) Reduce the wavetable addressing speed of the previous digital audio signal Used by the address generator to modulate for at least one Means for calculating the LFO variation value to be calculated; (b) means for providing the LFO change value to the address generator, (c) means for periodically updating the LFO fluctuation value in the previous period; A low frequency oscillator generator comprising: 155.   157. The LFO generator according to claim 154, wherein the LFO change value is in the previous period. Calculations and updates are based on depth, slope update speed, and frequency parameters. Data, LFO update speed parameter, current position parameter, and final position parameter LFO generator that depends on. 156.   157. The LFO generator according to claim 155, wherein the parameter is external. LFO generator stored in memory. 157.   With a low frequency oscillator (LFO) generator for digital wavetable voice synthesizers And the synthesizer is configured to (i) use a plurality of digital Audio signal (Ii) each of the digital audio signals being created has a volume Equipped with a volume generator that provides system components, Is (a) During at least one of the digital audio signals being created, the volume LF used by the volume generator to modulate components O means for calculating the variation value; (b) means for providing the LFO fluctuation value to the volume generator in the previous period; (c) means for periodically updating the LFO fluctuation value in the previous period; A low frequency oscillator generator comprising: 158.   157. The LFO generator according to claim 157, wherein the LPO change value is in the previous period. Calculations and updates are based on depth, slope update speed, and frequency parameters. Data, LFO update speed parameter, current position parameter and final position parameter LFO generator that depends. 159.   158. The LFO generator according to claim 158, wherein the parameter is external. Generator stored in memory. 160.   With a low frequency oscillator (LFO) generator for digital wavetable voice synthesizers And the synthesizer is configured to (i) transmit a plurality of digital signals for at least a frame time period. It is possible to create a digital audio signal, Each created from wavetable data addressed by the previous synthesizer (Ii) add a wavetable data address to each of the digital audio signals Address generator to set the specified speed, and (iii) A volume gage that provides a volume component for each of the digital audio signals Equipped with a generator, and the LPO generator (a) During at least one of the digital audio signals being created, the wavetable address Used by the address generator to modulate the specified speed. Of the digital audio signal during the To modulate the volume component during the first Means for calculating the tremolo LFO variation used by the generator; (b) The vibrato LFO fluctuation value calculated by the means for calculating Provided to the dress generator and calculated by the means for calculating the previous period Means for providing Moro LFO fluctuations and values to the volume generator in the previous period, (c) Vibrato LPO fluctuations calculated by the means for calculating Means for periodically updating the Moro LFO fluctuation value; A low frequency oscillator generator comprising: 161.   160. The LFO generator according to claim 160, wherein the vibrato LPO is Pre-calculation and update of variability and tremolo LFO variability are performed using depth parameter, slope Oblique update speed parameter, frequency parameter, LFO update speed parameter, current position LPO generator depending on parameters and final position parameters. 162.   164. The LFO generator according to claim 161 wherein the parameter is external. LFO generator stored in memory. 163.   With a low frequency oscillator (LPO) generator for digital wavetable voice synthesizers And the synthesizer is configured to (i) provide a plurality of data for at least a frame time period. Digital audio signals can be created. Each is created from a wavetable addressed by the synthesizer , (Ii) a wavetable data address for each of the digital audio signals being created Equipped with an address generator for setting the speed, the LFO generator (a) a wavetable ad for selecting one of the digital audio signals being developed; Address modulation during the previous time frame to modulate the specified speed. Means for calculating the LFO variation value used by the Nerator; (b) means for providing the previous term LFO fluctuation value to the previous term address generator; (c) means for periodically updating the LFO fluctuation value in the previous period; A low frequency oscillator generator comprising: 164.   164. The LFO generator according to claim 163, wherein the LFO variation value is The calculation and update in the previous period are the depth parameter, the slope update speed parameter, and the frequency parameter. Meter, LFO update speed parameter, current position parameter, and final position parameter LFO generator depending on data. 165.   164. The LFO generator according to claim 164, wherein said parameter is external. LFO generator stored in memory. 166.   A low frequency oscillator (LFO) for digital wavetable voice synthesizers, The synthesizer comprises: (i) at least a plurality of digital audio signals during a frame time period; (Ii) volume for each of the digital audio signals being created. Equipped with a volume generator that provides the Data (a) the volume structure for the selection of one of the digital audio signals being created; LFO used by the volume generator to modulate the component Means for calculating a modulation value during each said time frame; (b) means for providing the previous term LFO fluctuation value to the previous term volume generator; (c) means for periodically updating the LFO fluctuations and values in the previous term; A low frequency oscillator generator comprising: 167.   166. The LFO generator according to claim 166, wherein the LFO change value is in the previous period. Calculations and updates include depth parameters, ramp rate parameters, frequency parameters, LFO update speed parameter, current position parameter, and final position parameter LFO generator that exists. 168.   167. The LFO generator according to claim 167, wherein the parameter is external. LFO generator stored in memory. 169.   A low frequency oscillator for digital wavetable audio synthesizers, The synthesizer (i) outputs at least a plurality of digital audio signals during a frame time period. Each of the plurality of digital audio signals can be Created from wavetable data addressed by the synthesizer, and (ii) created Wavetable data addressing speed for each of the middle digital audio signals (Iii) the digital audio signal being created Volume components that provide volume components for each of the The LFO generator is equipped with a (a) the wavetable address for selecting one of the digital audio signals being created; Used by the address generator to modulate the specified speed Vibrato LFO variation or selection of one of the digital audio signals being created The volume generator to modulate the volume component for selection. At the specified frame, one of the tremolo LFO fluctuation values used by the Means for calculating during the interim period; (b) calculating the vibrato LFO fluctuation value calculated by the calculating means; A train provided to the dress generator and calculated by the means for calculating. Means for providing a Moro LFO variation to the volume generator; (c) the vibrato LPO fluctuation value and the train calculated by the calculating means; Means for periodically updating the Moro LFO fluctuation value; A low frequency oscillator generator comprising: 170.   The LFO generator according to claim 169, wherein the vibrato LFO Updating of the fluctuation value and the tremolo LFO fluctuation value is based on the depth parameter and the inclination update speed parameter. Meter, frequency parameter, LFO update speed parameter, current position parameter, LFO generator depending on and final position parameters. 171.   The LFO generator of claim 170, wherein the parameter is external. LFO generator stored in memory. 172.   Vibrato effect created by digital wavetable speech synthesizer A digital audio signal, wherein the synthesizer comprises at least (I) It is possible to create multiple digital audio signals during a frame time period. Each of the plurality of digital audio signals is addressed by the synthesizer. (Ii) The digital audio signal being created is created from the specified wavetable data. At the same time, it is possible to address wavetable data at some speed, (a) creating a low frequency oscillator (LFO) variation and value; (b) at least one of said wavetable elements of said digital audio signal being created; Modulating the dress designation speed to the LFO fluctuation value, (c) the LFO variation value used to modulate the wavetable addressing speed Steps to regularly update How to configure. 173.   172. The method of claim 172, wherein the LFO variation value is a depth parameter, a slope parameter. Oblique update speed parameter, frequency parameter, LFO update speed parameter, current position Method created from parameters and final position parameters. 174.   The method of claim 173, further comprising: Step (a) searching for the parameter from an external memory before, How to configure. 175.   Tremolo effect created by digital wavetable speech synthesizer Digital audio signal, wherein the synthesizer comprises: (i) at least ( i) it is possible to create multiple digital audio signals during the frame time period, and (ii) Providing a volume component for each of the digital audio signals being created Is possible, (a) creating a low frequency oscillator (LFO) variation parameter value; (b) the volume configuration of at least one of the digital audio signals being created Modulating an element with the LFO variation value; (c) periodically changing the LFO variation value used to modulate the volume component Updating to How to configure. 176.   175. The method of claim 175, wherein the LFO variation value is a depth parameter. , Tilt update speed parameter, frequency parameter, LFO update speed parameter A method created from the location parameters and the final location parameters. 177.   The method of claim 176, further comprising: Before step (a), retrieving the parameter from external memory; A method comprising: 178.   Digital audio signal created by digital wavetable audio synthesizer A method of adding a vibrato effect and a tremolo effect, wherein If the synthesizer has at least (i) more than one digital A plurality of digital audio signals. Created from wavetable data addressed by the synthesizer (Ii) for each digital audio signal being created, wavetable data at some speed (Iii) the digital audio signal being created It is possible to provide volume components for each, (a) Create a vibrato low frequency oscillator (LFO) fluctuation value and tremolo LPO fluctuation value Steps and (b) the wavetable addressing of at least one of the digital audio signals Velocity is at least one of the digital audio signals at the Vivrat LFO value. Modulating the two volume components with the tremolo LPO variation value; , (c) the vibler used to modulate the wavetable addressing speed The LFO variation value, and the value used to modulate the volume component Regularly updating the tremolo value; A method consisting of: 179.   178.The method of claim 178, wherein the Vivrat LFO variation value and The tremolo LFO fluctuation values are the depth parameter, the slope update speed parameter, Frequency parameter, LFO update speed parameter, current position parameter, and final Method created from location parameters. 180.   The method of claim 179, wherein Step (a) searching for the parameter from an external memory before, How to configure. 181.   Digital audio signal created by digital wavetable audio synthesizer A vibrato effect and a tremolo effect, wherein the synth The sizer must be able to (i) at least Generating a voice signal, wherein each of said plurality of digital voice signals is The wavetable data addressed by the synthesizer (Ii) wavetable at a certain speed for each digital audio signal being created. Addressing data '' and (iii) said digital sound being created. It is possible to provide a volume component for each of the voice signals, (a) Create a low-frequency oscillator (LFO) equivalency within a specified time frame period. Tep, (b) the wavetable addressing speed or volume of the digital audio signal being created; Modulating one of the system components with the LFO variation value; (c) modulating the wavetable addressing speed or the volume component; Periodically updating the LPO fluctuation value used for; How to configure. 182.   181.The method of claim 181, wherein the LPO variation value is a depth parameter, Tilt update speed parameter, frequency parameter, LFO update speed parameter, current position Method created from the position parameter and the final position parameter. 183.   The method of claim 182, further comprising: Before step (a), retrieving the parameter from external memory; How to configure. 184.   Central processing unit, system memory, and data and control within the system Signal and a host having a system bus for transferring address signals. Monolithic collection to provide audio enhancements to personal computers An integrated circuit, wherein the monolithic integrated circuit comprises: A system control module that provides an interface to the system bus. Thus, the control module further comprises: The entire integrated circuit communicates with the system bus decoding circuit to distribute data. A register data bus for Interrupt signal control, Plurality of integrated circuit control registers, and internal clock generation circuit and internal clock A control circuit; A system control module comprising: A digital output terminal for transmitting a digital signal to an external device, Digital wavetable audio synthesizer module for creating digital audio signals And, furthermore, Digital signal transfer for transferring a digital audio signal synthesized to the output terminal Circuit and A data input circuit for acquiring audio signal data from one or more external storage devices; , A digital wavetable audio synthesizer module comprising: Local memory control for interfacing the integrated circuit with an external storage device A memory control module comprising: the synthesizer module; Or data between the system bus interface and external storage. A local memory control module that communicates with the register data bus for transfer. Jules, A monolithic integrated circuit comprising: 185.   The circuit of claim 184, further comprising: An analog input circuit for receiving a game control signal from an external device; Analog-to-digital converter for converting analog input signals to digital signals When, Communication between the register data bus, the analog input circuit, and the conversion circuit An interface circuit for realizing A circuit comprising a game port module comprising: 186.   184. The circuit of claim 184, further comprising the data bus and an external Instrument digital interface module for realizing data communication between devices Circuit with a rule. 187.   184. The circuit according to claim 184, wherein said local memory control module is To enable data transfer between the integrated circuit and an external storage device. Memory interface circuit for generating address and control signals A circuit comprising: 188.   187. The circuit of claim 187, wherein the memory interface circuit Path interfaces with external random access storage and read-only storage. A circuit comprising means for installing 189.   Central processing unit, system memory, and data and control within the system Signal and a host having a system bus for transferring address signals. Monolithic collection to provide audio enhancements to personal computers An integrated circuit, wherein the monolithic integrated circuit comprises: A system control module to provide an interface to the system bus And the control module further comprises: Communicate with the system bus decoding circuit to distribute data throughout the integrated circuit A register data bus for Interrupt signal control, Multiple integrated circuit control registers, internal clock generation circuit and internal clock control circuit When, A system control module comprising: Synthesizer digital / analog for digital / analog signal conversion A conversion circuit, wherein the synthesizer digital-to-analog conversion circuit further comprises: To An analog output terminal for transmitting an analog signal to an external device, A digital audio signal input circuit for receiving a digital audio signal, A synthesizer digital-analog conversion circuit comprising: Digital wavetable audio synthesizer module for creating digital audio signals Wherein the synthesizer module further comprises: Synthesizer digital-to-analog signal conversion circuit for synthesized digital audio signal A digital signal transfer circuit for transferring the Data milk for obtaining audio signal data from one or more external memory devices Six circuits, A digital wavetable audio synthesizer module comprising: Local memory control for interfacing the integrated circuit with an external storage device Wherein the memory control module is a synthesizer module. The synthesizer digital-to-analog conversion circuit or the system bus The interface and the register for transferring data between the external storage device; A local memory control module in communication with the master data bus; A monolithic integrated circuit comprising: 190.   The circuit of claim 189, further comprising: An analog input circuit for receiving a game control signal from an external device; Analog-to-digital converter for converting analog input signals to digital signals When, Communication between the register data bus, the analog input circuit, and the conversion circuit An interface circuit for realizing A circuit comprising a game port module comprising: 191.   189. The circuit of claim 189, further comprising the register data To implement data communication between the bus and external devices, an instrument digital interface Circuit comprising a source module. 192.   199. The circuit of claim 189, wherein said local memory control module is To enable data transfer between the integrated circuit and an external storage device. Memory interface circuit for generating address and control signals A circuit comprising: 193.   199. The circuit of claim 192, wherein said memory interface circuit Interface with external random access storage and read-only storage A circuit comprising means for performing 194. (a) a register array that specifies control parameters for synthesizer operation; (b) wavetable addressing means, (c) volume creation means, (d) a signal path connected to the address creating means and the volume creating means Means, Digital wavetable speech synthesizer with 195.   A digital wavetale speech synthesizer according to claim 194, further, Storage means connected to the signal path means; Digital wavetable speech synthesizer with 196.   195. A digital wavetable audio synthesizer according to claim 194, wherein: In addition, Low frequency oscillator connected to the address creating means and the volume creating means Creation means, Digital wavetable speech synthesizer with 197.   199. A digital wavetable audio synthesizer according to claim 195, wherein In addition, Low frequency oscillator connected to the address creating means and the volume creating means Creation means, Digital wavetable speech synthesizer with 198.   195. A digital wavetable audio synthesizer according to claim 194, wherein: In addition, the digital wavetable audio synthesizer is interfaced to a synthesizer DAC. Digital wavetable speech synthesizer with circuitry for 199. (a) a register array that specifies control parameters for synthesizer operation; (b) wavetable addressing means, (c) volume creation means, (d) a signal path connected to the address creating means and the volume creating means Means, (e) at least one for storing data output from the synthesizer; A first accumulator, and for storing data written to the wavetable Connected to the signal path means, comprising at least one second accumulator Storage means, Digital wavetable speech synthesizer with 200.   199. A digital wavetable audio synthesizer according to claim 199, comprising: In addition, Low frequency oscillator connected to the address creating means and the volume creating means Creation means, Digital wavetable speech synthesizer with 201.   199. A digital wavetable audio synthesizer according to claim 199, comprising: In addition, the digital wavetable audio synthesizer is interfaced to a synthesizer DAC. Digital wavetable speech synthesizer with circuitry for 202.   (a) a first accumulator for accumulating data output from the synthesizer; Murator, (b) a second accumulator for accumulating data to be written to the wavetable; (c) Data is selectively stored in the first and second accumulators. Means for Storage logic for digital wavetable speech synthesizers with 203.   202. The storage logic of claim 202, wherein said data is stored selectively. Means for storing the data accumulated when the sum of the data is out of the range of values. Storage logic with the ability to delete. 204.   (a) a first algorithm for accumulating data output from the first synthesizer; An accumulator, (b) a second accumulator for storing data written to the wavetable; (c) selectively accumulating data in the first and second accumulators Means for Storage logic for digital wavetable speech synthesizers with 205.   204. The storage logic of claim 204, wherein the first accumulator is Left accumulator and stereo right output data for storing teleo left output data Storage logic with a right accumulator for storing data. 206.   204. The storage logic according to claim 204, wherein the data is selectively stored. Means for storing the accumulated data when the sum of the data is outside the range of values. Storage logic with the ability to delete data. 207.   (a) a first accumulator for accumulating data output from the synthesizer; Murator, (b) a second accumulator for storing data to be written to the wavetable; (c) selectively storing data in the first accumulator and the second accumulator Means for Storage logic for digital wavetable speech synthesizers with 208.   207. The storage logic of claim 207, wherein the first accumulator is a storage logic. Left accumulator for storing teleo left output data and stereo right output data Storage logic with a right accumulator for storing data. 209.   210. The storage logic of claim 207, wherein the data is stored selectively. The storage means deletes the accumulated data when the total of the data is out of the range of the value. Storage logic with the ability to remove 210.   210. The storage logic according to claim 208, wherein the data is stored selectively. The storage means deletes the accumulated data when the total of the data is out of the range of the value. Storage logic with the ability to remove 211.   (a) a first storage means for storing data output from the synthesizer; Steps and (b) second storage means for storing data to be written to the wavetable; (c) means for selectively storing data in the first storage means and the second storage means; Steps and Storage logic for digital wavetable speech synthesizers with 212.   220. The storage logic according to claim 211, wherein data is stored selectively. The storage means deletes the accumulated data when the total of the data is out of the range of the value. Storage logic with the ability to remove