JPH10320123A - Disk controller with built-in cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To freely set the data width of a buffer memory and to accelerate the transfer speed between the buffer memory and a disk controller without being limited by the number of pins of the disk controller by constituting the buffer memory in the same LSI with the disk controller LSI. SOLUTION: This disk controller with built-in cache memory 10 is incorporated with even an MPU 1, a work memory 2 and a program memory 3 (shown by 42) or not incorporated with them (shown by 41). Processing units (X) of the cache memory 10 can be made as long as physical block length ((n) times or 1/n a physical sector on a disk) on logical block length ((m) times or 1/m process block of a host). Check codes are added by the process units (X) and process numbers (Y) and when cache data are read out or written, an error is detected and corrected with both the check codes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk subsystem for controlling reading and writing of data between a host and a magnetic disk, and more particularly to a disk controller for increasing a transfer speed with a buffer memory.

[0002]

2. Description of the Related Art FIG. 1 shows the configuration of a conventional disk controller.

A disk controller that controls the reading and writing of data between a host and a magnetic disk is used to synchronize the transfer via a cache memory in order to absorb the difference between the data transfer speed from the higher order and the data transfer speed from the lower order. It is trying to make it.

For example, the transfer rate of the upper interface is 20 MB / S, and that of the lower interface is 20 MB / S.
In the case of S, the transfer speed between the disk controller and the buffer memory needs to be at least 20 MB / S + 20 MB / S = 40 MB / S.

The transfer speed of the upper interface is 100 MB / S, and that of the lower interface is 40 MB / S.
In the case of S, the transfer speed between the disk controller and the buffer memory needs to be at least 100 MB / S + 40 MB / S = 140 MB / S, and this transfer speed will be further improved in the future.

[0006]

However, if the buffer memory is mounted on a separate LSI from the disk controller, the transfer speed between the disk controller and the buffer memory is saturated, so that the transfer speed of the entire system is improved. It becomes difficult.

For example, in the case of 512 bytes per sector, 16
When buffer transfer is performed in bit units, 256 times of I
/ O occurs, hindering the improvement of the transfer speed, and
In order to make it 0 times, it is necessary to select either 10 times the performance of the memory or 10 times the byte width to be transferred. However, the performance of the buffer memory
Making it 0 times cannot be easily realized, and making data width / number of pins of the disk controller 10 times physically cannot be easily realized.

[0008]

The transfer rate of the system is as follows.
The transfer rate is determined by the R / W transfer speed for reading / writing serial data from / to the disk and the data transfer speed from the CPU to the / CPU. And the transfer rate between the buffer memory and the disk controller.

An object of the present invention is to increase the transfer speed between the buffer memory and the disk controller.

In the present invention, by configuring the buffer memory in the same LSI as the disk controller LSI,
The data width of the buffer memory can be freely set, and the transfer speed can be improved without being limited by the number of pins of the disk controller.

Therefore, in the disk subsystem according to the present invention, since the buffer memory and the disk controller exist in the same LSI, the I / O which controls the transfer performance is controlled.
The number can be reduced, and the transfer speed can be improved.

[0012]

FIG. 2 shows an embodiment of the configuration of the disk controller of the present invention.

1 is an MPU for controlling the controller, 2 is a work memory, 3 is a program memory for storing an MPU program, and each is connected to a bus 21. The controller with built-in cache memory
There are cases where the MPU 1, the work memory 2, and the program memory 3 are also built-in (shown by 42) and cases where they are not built-in (shown by 41). When no MPU or the like is incorporated, the controller 41 is connected to the bus 21.

The data read from the disk is
In a state where the serial data is read continuously into the iFo and the serial data becomes Full in the FiFo, the data is written into the internal buffer memory at once as parallel data. When the parallel data is sent to the CPU, the parallel data is transferred at once after reading the FIFO.

The processing unit (X) of the cache memory is a physical block length (n times or 1 / n times the physical sector on the disk) or a logical block length (m times the processing block of the host, or 1). / M times).

A check code is added for each processing unit (X) and each processing number (Y), and both check codes are used when reading / writing cache data.
Errors can be detected and corrected.

In general, a physical sector / logical block of a disk is 512 bytes. However, in order to add a check code, 512 + a bytes or blocking (logical block = 512 bytes × b) may occur in a customer system. Therefore, the processing unit (X) is M
Variable by PU.

In the case of a read / write command, data processing is performed a plurality of times longer than the physical sector length of the disk. However, in the case of a control command, data less than the processing unit (X) may be processed. Therefore, the processing unit (X)
A buffer Fifo for processing the minute is required.

[0019]

In the disk subsystem of the present invention, since the LSI constituting the disk controller has a built-in buffer memory, there is no I / O waiting time that occurs when the buffer memory is accessed by an external memory.
The I / O bottleneck is eliminated and the data bus bottleneck is eliminated.

The vertical and horizontal check codes enable high-speed and highly reliable data processing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a conventional disk controller.

FIG. 2 is a diagram showing a configuration of a disk controller according to one embodiment of the present invention.

[Explanation of symbols]

5 Host interface 6 Host side FIFO 7 Disk side FIFO 8 Disk interface 9 DMA 10 Cache memory 11 Buffer FIFO

Claims (4)

[Claims] 1. A disk controller which is connected to a host device and a storage device and has a built-in cache memory for storing data transferred between the host device and the storage device, wherein a processing unit of the cache memory is provided. A disk controller, wherein n is 1 or n times the physical block length, or m or 1 / m times the logical block length. 2. The disk controller according to claim 1, wherein a processing unit of said cache memory is variable. 3. A cache memory, wherein a check code is added for each processing unit and each processing number of the cache memory, and an error can be detected and corrected by both check codes when reading / writing cache data. The disk controller according to claim 1, wherein: 4. A cache memory pre-stage Fifo which takes out a processing unit (X) of the cache memory and partially reads / writes when a processing request less than the processing unit of the cache memory occurs. The disk controller according to claim 1, wherein