JPH1031648A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize the circuit of a DMA controller by preparing the address storage means, a write means, an address write means and a common address addition means in the DMA controller against every channel, setting only the requested address, and adding together the addresses of executed channels. SOLUTION: The flip-flops 107 to 109 are provided in a DMA controller as the address storage means serving as the registers which hold the addresses against every channel. An address set pulse generator 102 outputs an address set pulse to a selector 104 and also to an address ACK generation circuit 118. During the output of these pulses, the address information is sent to an address set bus. The address information functions to add together the value equivalent to the number of words which are accessed by a common adder 11 and adds only the added address information to an address register 107 to update the addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller for controlling direct memory access (DMA) from a device.

[0002]

2. Description of the Related Art Conventionally, in this type of DMA controller, an address counter is provided for each channel. Further, the setting of the address has been performed by a write of a CPU or the like.

[0003]

However, in the above-mentioned conventional example, there is a drawback that the circuit to be constituted becomes large-scale, and especially in the case of a multi-channel circuit, this is noticeable.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multi-channel DMA controller whose circuit can be made compact.

[0005]

In order to achieve the above object, according to the present invention, an address storage means, a writing means, a common address adding means, A writing means is provided for the channel so that only the requested address setting is set, and the address of the executed channel is added.

Further, arbitration means is provided for address setting and address addition so that memory access and address setting are not performed simultaneously.

Furthermore, a plurality of channels are divided into a plurality of groups, and the arbitration means is provided in each group, so that processing of different groups operates in parallel.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram of a DMA controller according to a first embodiment of the present invention. FIG.
2 is a circuit block diagram showing only one channel configuration in the circuit block diagram shown in FIG. 1 for convenience of explanation. In FIG. 1, 101 is an address set arbiter (arbiter), 1
02 is an address set pulse generator, 103 to 106 are selectors, 107 to 109 are flip-flops which hold the addresses of the respective channels, 110 is an address selector, 111 is an adder, 112 is a DREQ arbiter, and 113 is a latch circuit. , 114 are OR gates, 11
5 is an address write pulse generator, 116 is a timing generator, 117 is a data EN generation circuit, and 118 is an address ACK generator.

FIG. 2 is a circuit block diagram showing only one channel configuration in the circuit block diagram shown in FIG. 1 for easy understanding of the operation. In FIG. 1, elements existing for a plurality of channels are removed, but the other parts are the same as those in FIG. The DMA controller has two operating processes. The first is that the start address for performing DMA from an external device to be serviced is DM
This is a process of setting in an address register inside the A controller, and the second is a process of a memory access in which an external device to be serviced performs a DMA transfer.

First, the operation of the first process will be described. The external device to be serviced has the address REQ
Signal to request the DMA controller for an address set. The address REQ signal is input to the address set pulse generator 102. The address set pulse generator 102 first outputs a select signal to the selectors 103 and 104 and switches the input to the address set processing side (that is, the address set pulse generator 102). The selector 103 selects the address set bus from the address set bus and the input from the adder 111, and the selector 104 selects the address set pulse from the address set pulse and the address write signal.

Next, the address set pulse is supplied to the selector 1
04 and an address ACK generation circuit 118 at the same time.
Output pulse. The address ACK generation circuit outputs an address ACK signal, and the external device outputs the address ACK.
While the signal is being output, the address information to be set on the address set bus is driven. The address information is input to the address register 107 through the selector 103. On the other hand, the address set pulse input to the selector 104 is input to the EN input of the address register 107 to enable writing of the address register 107.

The address information is set in the address register 107 at the next rising edge of the CLK signal. At the rising edge of CLK at which the address information is set in the address register 107, the external device turns off the address REQ signal, and the operation process of the address set ends.

Next, the second process will be described.
External devices wishing to access memory access
The DMA request signal, that is, the DREQ signal is turned on, and a memory access is requested to the DMA controller.
The DREQ signal is output as it is to a memory controller (not shown) as a memory request signal,
The signal is input to the latch circuit 113. The latch circuit 113 is a transparent type latch and transmits an input signal when the memory ACK signal is in an off state and holds input data when the memory ACK signal changes to an on state. Therefore, the latch 113
The REQ signal is transmitted and the address write pulse generator 11
5 is input.

The memory controller turns on the memory ACK signal during the memory access if the memory access service is available. At this time, the DREQ signal is held in the latch circuit 113. On the other hand, the address information written in the address register 107 is input to the memory controller via the request address bus, and the memory controller accesses the memory at this address.

The address information is input to the adder 111, and the adder 111 adds the value of the number of words to be accessed. That is, 1 is added for word access, and 4 is added for 4-word access, and input to the selector 103. At this time, since the switching signal is not output to the selector 103, the added selector signal is input to the address register 107.

The timing generation circuit 116 sends a timing signal to the data EN generation circuit 117 at a predetermined timing according to the input memory ACK signal. Data E
The N generation circuit 117 outputs a data signal to the external device that has requested the service according to the timing signal.
The external device receives memory data from the memory controller according to the data signal. Alternatively, the write data is passed to the memory controller. At the same time, the DREQ signal is turned off.

The timing generation circuit 116 sends a timing signal to the address write pulse generation circuit 115 at the end of the memory access. The address write pulse generation circuit 115 outputs an address write signal to the EN input of the address register 107 through the selector 104. At the next rising edge of the CLK signal, the address information added by the adder 111 is written to the address register 107, and the address is updated. At the end of the memory service, the memory ACK signal is turned off, and the latch circuit 113 returns to the transparent state again.

The above first and second processes enable continuous DMA transfer with one address set.

Next, with reference to FIG. 1, the operation of a plurality of DMA controllers, that is, the DMA controller extended to n channels will be described with respect to the first process and the second process, respectively. For the first process, n sets of addresses are requested from n external devices through address REQ1, address REQ2, ^... Address REQn signals. The address set arbiter 101 transmits one of the n address REQ signals that has the highest priority among those input simultaneously, and masks (blocks) the others.
However, any method may be used for determining the priority. For the transmitted signal, an address signal is output at the same time when an address set pulse is generated for that channel, as in the case of one channel, and the address is set in the address register through the address set bus. .

[0021] For the second process, from the n-number of external devices, DREQ1, DREQ2, ^... DREQn
Each signal is input. DREQ Abita 112
Of the DREQ signals input at the same time, the signal with the highest priority is transmitted, and the others are masked. DREQ transmitted
The signal outputs a memory request signal to the memory controller through the OR gate 114. When the service of the memory is started and the memory ACK signal is input, the current DR signal transmitted through the DREQ arbiter 112 is output.
The EQ signal is held in the latch circuit 113. The output of the latch circuit 113 is input to the address selector 110,
The address information of the selected external device is output from the memory controller through the request bus, and the memory access of the address is serviced. Until the memory service ends, the latch circuit 113 is held, and the subsequent processing is the same as in the case of one channel, and operates only on the selected channel.

By the way, what should be considered in the case of multi-channel is an address set (that is, the first set).
And the memory access (ie, the second process) can occur simultaneously.

The present invention has the following arbitration means in order to avoid collision of the address write bus. That is, when the address REQ is output and the address set is executed, the address pulse generator 10
2, the mask signal is input to the DREQ arbiter 112,
All DREQ signals are masked. When the DMA access service is performed and the added address is set in the address register, a mask signal is output from the address write pulse generator 115 to the address set arbiter 101, and all the address REQ signals are masked. .

As described above, according to the present invention, a DMA controller can be realized efficiently and inexpensively for an external device having a plurality of DMA sources.

(Embodiment 2) FIG. 3 is a circuit block diagram of a DMA controller according to Embodiment 2 of the present invention. Example 2
In, the external devices that receive the DMA service are divided into two groups A and B to improve the operation efficiency. In FIG. 3, 301 is an address set arbiter A, 302 is an address set pulse generator A, 303 is an address ACK generator A, 304 is an address set arbiter B, 305 is an address set pulse generator B, 306
Is an address ACK generator B, 307 to 314 are selectors, 315 to 320 are address registers, 321 is an address selector, 322 is an adder, 323 is a mask A, 3
24 is a mask B, 325 is a DREQ abiter, 326 is an OR gate, 327 is a DREQ latch circuit, 328 is an address write pulse generator A, 329 is an address write pulse generator B, 330 is a timing generator, and 331 is a data EN generation circuit. It is.

In this embodiment, the basic operation is the first
Is similar to that of the first embodiment, except that the address set arbiters A and B 302 and 305 of the address set pulse generators A and B of the groups A and B respectively belong to the groups A and B.
And the selectors of the address ACK generators A, B, 307, and 311 of B, 303, and 306 are provided to enable address setting independently and simultaneously with address setting with other groups. Also, 323 and 324 masks A and B are applied to the DREQ input of each group, respectively.
8, 329 address write pulse generators A and B are provided, respectively, so that memory access and address setting can be performed without interference with each other outside the group. That is, when group A sets an address, 3
The 02 address set pulse generator outputs a mask signal, and masks only the DREQ of the group A with the mask A of 323. Similarly, when the address of the group B is set, the address set pulse generator 305 outputs a mask signal, and only the DREQ of the group B is entirely masked by the mask B 324.

On the other hand, while the group A is performing the memory transfer, 32
The address write pulse generator of No. 8 outputs a mask signal, and the address set arbiter A of 301 outputs the group A
Are masked. Similarly, during the memory transfer of the group B, the address write pulse generator 329 outputs a mask signal, and the address set arbiter B 304 masks all the addresses REQ of the group B.

FIG. 4 is a chart showing processing when a conflict occurs between an address set and a memory transfer in a group and outside a group. In the figure, A indicates that an arbitration is performed, and any one is executed, and ← → indicates that the arbitration is executed simultaneously without interfering with each other. As described above, in the present embodiment, the operation efficiency of the DMA controller can be dramatically improved. In the present embodiment, there are two groups, A and B. However, even if there are a large number of groups, the group can be similarly expanded. In addition, although there are a plurality of channels in the group, this may of course be only one channel.

[0029]

As described above, according to the present invention,
1. Since the address increment can be made common, a multi-channel DMA controller can be realized with a simple circuit configuration. Since each channel can independently reset the address, various applications are possible. 2,
External devices can use DMA without special intelligence
Service is available. 3. Efficient operation is realized by grouping.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a DMA controller according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram of only one channel of the DMA controller shown in FIG. 1;

FIG. 3 is a circuit block diagram of a DMA controller according to a second embodiment of the present invention.

FIG. 4 is a chart illustrating processing during a conflict according to the second embodiment;

[Explanation of symbols]

 Reference Signs List 101 address set arbiter 102 address set pulse generator 103-106 selector 107-109 address register 110 address selector 111 adder 112 DREQ arbiter 113 DREQ latch circuit 114 OR gate 115 address write pulse generator 116 timing generator 117 data EN generation circuit 118 Address ACK generator

Claims (17)

[Claims] In a DMA controller having a plurality of channels, for each of a plurality of channels provided inside the DMA controller,
Address storage means such as an address register,
Address writing means for externally setting a DMA address in the address storage means, address adding means for adding addresses by the number of words accessed to an access address of a channel being processed at the time of memory access by DMA; A DMA controller having address writing means for writing the address added by the addition means to address storage means of a channel which is processing. 2. The DMA controller according to claim 1, further comprising an arbitration means for arbitrating when a write to the address register by an external address writing means and a contention of the address added by said adding means conflict with the address writing means. A DMA controller, further comprising: 3. The DMA controller according to claim 1, wherein a plurality of channels are divided into a plurality of groups, and arbitration is performed for each group when a conflict occurs between an external address writing unit and an address writing unit from an adder. A DMA controller, further comprising arbitration means. 4. A DMA controller having a plurality of channels, comprising: an address set pulse generator for generating and outputting a select signal and an address set pulse in response to an external address set signal (REQ signal); A first selector configured to select one of the outputs of the adder, a plurality of address registers to which the output selected by the first selector is selectively input and temporarily held; An address selector for selecting and outputting the address value held in the address register; and adding the address value by the number of words of the memory accessed to the address value selected by the address selector, and adding the added address value to the first selector. According to the adder to be output and the memory access signal (DREQ signal) from outside An address write pulse generator for generating and outputting an address write pulse, and selecting and outputting the address set pulse input from the address set pulse generator and the address write pulse input from the address write pulse generator. And a plurality of second selectors for selectively enabling a corresponding one of the plurality of address registers, wherein the first selector receives the select signal from the address set pulse generator. When the address set bus is selected, the output of the adder is selected when there is no input, and the plurality of second selectors generate the address set pulse when the select signal is input from the address set pulse generator. Select the address set pulse from the DMA controller, wherein consists are, it to select the address write pulse from said address write pulse generator for. 5. The DMA controller according to claim 4, wherein when an address set signal of one channel is externally input, a select signal and an address set pulse are generated by said address set pulse generator, and said first selector Selects an address set bus, and one of the plurality of second selectors, to which the address set pulse is input, enables a corresponding one of the plurality of address registers. When an address value is held in an address register and a memory access signal of one channel is input from outside, an address write pulse is generated by the address write pulse generator, and an address write pulse among a plurality of second selectors is output. Is input to the second selector A DMA controller, wherein a corresponding one of a plurality of address registers is enabled to hold an address value obtained by adding the number of words of a memory accessed to the address value to the corresponding address register. 6. The DMA controller according to claim 4, wherein said address selector selects and outputs a corresponding one of a plurality of address registers in response to an externally input memory access signal of one channel. A DMA controller. 7. The DMA controller according to claim 4, wherein said address write pulse generator outputs an address write pulse at a predetermined timing from input of an external memory access permission signal (memory ACK signal). DMA controller to do. 8. The DMA controller according to claim 4, wherein one of the address set signals of a plurality of channels is selected and input to the address set pulse generator. And a DREQ arbiter for selecting one of the memory access signals of a plurality of channels and inputting the selected signal to the address write generator. 9. The DMA controller according to claim 8, wherein when an address set signal is inputted from outside, a DREQ arbiter mask means for masking said DREQ arbiter, and when a memory access signal is inputted from outside, A DMA controller further comprising address set arbiter mask means for masking the address set arbiter. 10. The DMA controller according to claim 9, wherein masking by said DREQ arbiter masking means is performed by inputting a mask signal generated by said address set pulse generator to said DREQ arbiter, and wherein said address set arbiter is masked. The DMA controller is characterized in that masking by the mask means is performed by inputting a mask signal generated by the address write pulse generator to the address set arbiter. 11. A DMA controller having a plurality of channels, the plurality of channels are divided into at least two groups, and each group is provided with a select signal and an address according to an external address set signal (REQ signal). An address set pulse generator for generating and outputting a set pulse, a first selector configured to select either an address set bus or an output of an adder, and selecting an output selected by the first selector A plurality of address registers that are temporarily input and temporarily held, an address write pulse generator that generates and outputs an address write pulse in response to an external memory access signal (DREQ signal), and an address set pulse generator The address set pulse input from the A plurality of second selectors for selecting an address write pulse input from a pulse generator and selectively enabling a corresponding one of the plurality of address registers by an output thereof. And an address selector for selecting and outputting the address values held by the plurality of address registers, and adding the address values by the number of words of the memory accessed to the address values selected by the address selector, and adding the added addresses. An adder for outputting a value to the first selector;
For each group, the first selector selects the address set bus when the select signal is input from the address set pulse generator, and selects the output of the adder when there is no input, The plurality of second selectors select the address set pulse from the address set pulse generator when the select signal is input from the address set pulse generator, and select the address set pulse from the address write pulse generator when there is no input. A DMA controller configured to select an address write pulse. 12. The DMA controller according to claim 11, wherein when an address set signal of one channel is externally input to each group, a select signal and an address set pulse are generated by said address set pulse generator. The first selector selects an address set bus, and one of the plurality of second selectors to which an address set pulse is input enables a corresponding one of the plurality of address registers. The address write pulse is generated by the address write pulse generator when a memory access signal of one channel is externally input, and a plurality of second selectors are provided. Of the address write pulses The one second selector enables the corresponding one of the plurality of address registers to hold an address value obtained by adding the number of words of the memory accessed to the address value to the corresponding address register. A DMA controller. 13. The DMA controller according to claim 11, wherein said address selector is common to each group and corresponds to one of a plurality of address registers corresponding to a memory access signal of one channel externally input. DMA characterized by selecting and outputting one
controller. 14. The DMA controller according to claim 11, wherein for each group, the address write pulse generator generates an address write pulse at a predetermined timing from the input of an external memory access enable signal (memory ACK signal). A DMA controller characterized by outputting. 15. The DMA controller according to claim 11, wherein one of an address set signal of a plurality of channels is assigned to each group.
And an address set arbiter for selecting one of a plurality of memory access signals of a plurality of channels and inputting the selected signal to the address write generator. DMA controller. 16. The DMA controller according to claim 15, wherein when an address set signal is input to each group from outside, a mask operating means for operating a mask means provided on an input side of said DREQ arbiter. And when a memory access signal is input from outside,
DM further comprising address set arbiter mask means for masking the address set arbiter.
A controller. 17. The DMA controller according to claim 16, wherein for each group, the operation of the mask operation means is such that a mask signal generated by the address set pulse generator is input to the mask operation means. The masking by the address set arbiter mask means is performed by inputting a mask signal generated by the address write pulse generator to the address set arbiter.
MA controller.