JPH10290437A - Digital transmission system for video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a digital processing circuit by allowing a transmitter to send consecutive video digital data with a code representing a data packet not added thereto and allowing a receiver to detect data of a video horizontal synchronizing signal thereby extracting a packet. SOLUTION: A digital modulation signal such as QPSK sent from a transmitter side is given to a digital demodulator 10, where the signal is demodulated into a serial signal and converted into a parallel signal in the unit of packets at a shift register 11. The shift register 11 provides the output of a parallel signal shifted one by one bit each in the timing of a shift clock generator 18 till a synchronization detector 16 detects a bit pattern of a horizontal synchronizing signal part, and when the synchronization detector 16 detects the bit pattern specific to the horizontal synchronizing signal part, the packet is confirmed and a succeeding serial signal is converted into an N-bit parallel signal and converted into a composite analog video signal by a code converter 12 and a D/A converter 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal transmission system for digitizing a composite video signal and transmitting high-quality video.

[0002]

2. Description of the Related Art There are an analog transmission system and a digital transmission system as a system for transmitting and receiving image data. In the case of the digital transmission system, conventionally, a code indicating the head position of a packet by packetizing the image data, an error correction code, etc. And processing such as data compression and decompression.

[0003]

As described above, conventionally, when a video signal is transmitted as digital data, a frame synchronization signal, an error correction code, and the like are added, and digital processing such as data compression and decompression is performed. Therefore, there has been a problem that the circuit configuration becomes complicated, and that codes other than image data are added, so that the data amount increases accordingly and the image transmission speed decreases.

SUMMARY OF THE INVENTION In view of the above problems, according to the present invention, when transmitting a video signal as digital data, the transmitting side transmits digital data consisting only of image data as continuous serial data, thereby implementing a digital processing circuit. It is an object of the present invention to simplify and to improve the efficiency of image transmission so that high-quality video signals can be easily digitally transmitted.

[0005]

According to the digital transmission system for video signals in the present invention, the transmitting side transmits digital data consisting of video data only as continuous serial data without adding a code indicating a data packet. ,
On the receiving side, video data packets are extracted from the continuous serial data by detecting the data of the horizontal synchronization signal portion of the video data.

Further, the phase of the timing clock for digital processing is matched with the phase of the color subcarrier frequency of the input composite video signal, and the data transmission speed is set to an integer ratio of the color subcarrier frequency of the composite video signal.

[0007] With this configuration, when digital transmission is performed, high-definition video can be transmitted without performing complicated digital processing. Therefore, the circuit can be simplified, and a faithful composite can be obtained on the receiving side. Reproduction of an analog video signal becomes possible.

[0008]

1 and 2 are block diagrams showing a first embodiment of a video signal digital transmission system according to the present invention. FIG. 1 shows a transmitting section, and FIG. 2 shows a receiving section. I have.

The A / D converter 2 converts the composite video signal input to the transmission unit 1 to a predetermined sampling frequency (f
s) is quantized to a natural binary code of N bits (N is a positive integer). The natural binary code signal obtained by the A / D converter 2 is further converted into a 2's complement Gray code by inverting the MSB in the code converter 3 and then serially converted by the P / S converter 4. Converted to a signal. This serial signal is converted into a digital modulation signal such as QPSK by the digital modulation section 5 and transmitted from the transmission antenna 7.

A / D converter 2, code converter 3, P / S
Each timing signal of the converter 4 and the digital modulator 5 is
The timing generation circuit 6 generates the input composite video signal based on a color subcarrier signal, a horizontal synchronization signal, and a vertical synchronization signal.

On the other hand, a receiving section 9 receives a spatially transmitted digital modulated signal such as QPSK by a receiving antenna 8 and a digital demodulator 10 demodulates a serial signal from the digital modulated signal. The demodulated serial signal is converted by the shift register 11 into a parallel signal in packet units. The parallel signal in packet units is converted from the 2's complement data into natural binary code data by the code converter 12, and the bit pattern of the horizontal synchronization portion of the composite video signal is detected by the synchronization detector 16 to reduce the bit pattern. Band pass filter (LPF) 15, AND circuit 1
7 to the shift register 11.

In the shift register 11, a synchronization detector 16
Outputs a parallel signal shifted by one bit at a time by the shift clock generator 18 until a bit pattern of the horizontal synchronization part is detected. After the determination, the serial signal is converted into an N-bit parallel signal, converted into a natural binary code by the code converter 12 and output to the D / A converter 13.

The shift register 11 and the code converter 1
2. The N-bit parallel signal in which the packet is determined is converted into an analog signal by the D / A converter 13 by the synchronization detector 16, the LPF 15, the AND circuit 16, and the shift clock generation circuit 18 and output as a composite video signal. You. The timing clock used in the receiver 9 is generated by the timing generator 14 using the symbol rate frequency sent from the transmitter.

FIGS. 3 and 4 are block diagrams showing another embodiment of the video signal digital transmission system of the present invention. This is applied when transmitting at a transmission rate. FIG. 3 shows a transmitting unit, and FIG. 4 shows a receiving unit.

In this embodiment, data of two frames of the NTSC signal is transmitted at 2.048 Mbits / sec.
Frame-by-frame transmission is performed at a transmission rate close to ond (bps). This 2.048 Mbps is the transmission speed of PCM sound of BS broadcast, and the modulation and demodulation circuit at the time of transmission can be shared by matching this.

Therefore, the A / D conversion sampling frequency of the input NTSC signal is set to four times (4 fs) the color subcarrier.
c = 14.318 MHz), the quantization is 8 bits (7 bits are used), and the memory capacity of 2 frames (for 2 * 525H) is 2 * 525 * 910 = 9555.
When the transmission bit rate is set to 00 bytes, the transmission bit rate of every 98 frames of the input NTSC signal is calculated as (95500
* 7 * 29.97) /98=2.045 (Mbps).

Therefore, the A / D conversion sampling frequency is 4 fsc, the quantization bit is 7 bits, and the input NT
A low-speed transmission method may be used in which two frames are transmitted every 98 frames of the SC signal.

In the transmitting section 43 in FIG. 3, the input composite video signal is sampled by the A / D converter 19 at a frequency (4 fsc ≒ 14.32 MHz) four times the color subcarrier frequency (fsc ≒ 3.58 MHz). And is quantized at a 7-bit quantization level. The digitally converted signal is stored in the frame memory 20 as data for two frames every 98 frames of the NTSC signal. The data stored in the frame memory 20 is about 290 Kbytes / sec by the next data fetch.
nd, and the P / S converter 21 converts the 7-bit parallel signal into a serial signal.
The data is output to the differential conversion circuit 22 as a data series of ps. The differential conversion circuit 22 generates 2-bit pair differential data (I and Q signals) in order to transmit the data sequence of about 2.045 Mbps by four-phase DPSK. The 2-bit pair differential data is phase-modulated by the QPSK modulation circuit 23, and transmitted as a 4-phase DPSK modulation signal.

As the timing signal on the transmitting side, a horizontal synchronizing signal and a vertical synchronizing signal of an input composite video signal are extracted by a synchronizing separation circuit 24, and a signal stabilized by an AFC circuit 25 and a color subcarrier of the input NTSC signal are also converted to an APC signal. The color subcarrier frequency 4 which is taken out by the circuit 26 and phase-locked to the horizontal synchronizing signal by the PLL circuit 27
The A / D converter 19 and the frame memory 2 are generated by the timing generation circuit 28 using the double frequency (4 fsc).
0, and are supplied to the P / S converter 21 and the differential converter 22.

On the other hand, the receiving section 46 shown in FIG.
The PSK-modulated data is received by the QPSK demodulation circuit 29 and subjected to QPSK demodulation to obtain I and Q signals. The I and Q signals are converted by the differential conversion circuit 30 to 2.045 Mbp.
The data is converted into s serial data and input to the packet phase adjustment circuit 31.

The packet phase adjusting circuit 31 shifts the serial data by one bit until a packet of the serial data is detected. The serial data whose phase has been adjusted by the packet phase adjustment circuit 31 is converted into a 7-bit parallel signal by the S / P conversion circuit 32. The 7-bit parallel signal is input to a switch (SW) 34 and a pattern detection circuit 33.

The pattern detection circuit 33 detects the bit pattern of the horizontal synchronization signal of the NTSC signal, and feeds back the detection result to the packet phase adjustment circuit 31. The 7-bit data determined by the packet by the packet phase adjustment circuit 31, the S / P conversion circuit 32, and the pattern detection circuit 33 is stored in the frame memory 35 or the frame memory 36.
Switch 3 as video data for two frames each.
4 and are alternately switched and written. That is, when two frames of video data are first written to the frame memory 35, the next two frames of video data are written to the frame memory 36, and this is alternately performed.

The time during which the video data for the two frames is written (the time for the 98 frames of the input NTSC signal) The video data for the two frames is 14.318 MHz (4f) from the frame memory not in the write mode.
The reading is repeated 49 times (for 98 frames) at a high speed of sc). The switching of the reading of the video data for the two frames is performed by the switch 37. 14.3 above
The data read at a high speed of 18 MHz (4 fsc) is converted into an analog signal by the D / A converter 38 to generate an original composite video signal.

The timing signal on the receiving side is obtained by comparing the Q signal frequency demodulated by the QPSK demodulation circuit 29 with the phase comparison circuit 39,
It can be easily generated by using a PLL circuit including the LPF 40, the timing generation circuit 41, and the VCO 42.

In the other embodiment, a memory having a memory capacity of 2 frames is used as the frame memory.
Two frames were transmitted every 98 frames of the input NTSC signal. However, as still another embodiment, data of one frame is fetched every 49 frames of the input NTSC signal using a memory having a memory capacity of one frame. One frame can be transmitted for each frame.

In this case, however, on the receiving side, the image data of the same frame is read 49 times in succession. Therefore, after reading the image data of one frame in order to match the phase of the color carrier signal, the image data of the next frame is read. When reading one frame, it is necessary to delay by 140 ns and invert the color carrier signal phase.

FIG. 5 is a block diagram of a receiving unit in a transmission system for transmitting data at a low-order transmission rate using a memory having a memory capacity of one frame. 3 except that the frame memory 20 is a memory having a memory capacity of one frame and one frame is transmitted every 49 frames.
Has the same configuration as the above configuration. The receiving unit also includes delay circuits 47 and 48 for delaying the output of each of the frame memories 35 and 36 by 140 ns and a switch 4 in that the frame memories 35 and 36 each have a memory capacity of one frame.
9 and 50 are connected and each frame memory 3
4 except that the image data for one frame written in the lines 5 and 36 are alternately read 49 times each.
It has the same configuration as.

That is, on the transmission side, the A / D converter 19 converts the input composite video signal to a frequency (4 fs) that is four times the color subcarrier frequency (fsc５８3.58 MHz).
c ≒ 14.32 MHz) and is quantized at a 7-bit quantization level. In the digitally converted signal, data for one frame is stored in the frame memory 20 every 49 frames of the NTSC signal. The data stored in the frame memory 20 is read out at about 290 Kbytes / second by the time of the next data fetch, and the 7-bit parallel signal is converted to a serial signal by the P / S converter 21 to obtain about 2.045 Mbps. The data is output to the differential conversion circuit 22 as a data series. The differential conversion circuit 22 generates 2-bit pair differential data (I and Q signals) in order to transmit the data sequence of about 2.045 Mbps by four-phase DPSK. The 2-bit pair differential data is phase-modulated by the QPSK modulation circuit 23,
It is transmitted as a four-phase DPSK modulated signal.

On the other hand, the receiving section 46 shown in FIG.
The PSK-modulated data is received by the QPSK demodulation circuit 29 and subjected to QPSK demodulation to obtain I and Q signals. The I and Q signals are converted by the differential conversion circuit 30 to 2.045 Mbp.
The data is converted into s serial data and input to the packet phase adjustment circuit 31.

The packet phase adjusting circuit 31 shifts the serial data by one bit until a packet of the serial data is detected. The serial data whose phase has been adjusted by the packet phase adjustment circuit 31 is converted into a 7-bit parallel signal by the S / P conversion circuit 32. The 7-bit parallel signal is input to a switch (SW) 34 and a pattern detection circuit 33.

The pattern detection circuit 33 detects the bit pattern of the horizontal synchronization signal of the NTSC signal, and feeds back the detection result to the packet phase adjustment circuit 31. The 7-bit data determined by the packet by the packet phase adjustment circuit 31, the S / P conversion circuit 32, and the pattern detection circuit 33 is stored in the frame memory 35 or the frame memory 36.
Switch 3 as video data for one frame.
4 and are alternately switched and written. That is, when video data for one frame is first written to the frame memory 35, video data for the next one frame is written to the frame memory 36, and this is performed alternately.

The time during which the video data for one frame is written (the time for 49 frames of the input NTSC signal) is obtained from the frame memory that is not in the write mode and the video data for one frame is 14.318 MHz (4f).
The reading is repeated 49 times (for 49 frames) at a high speed of sc).

At this time, after reading one frame of data to match the phase of the color carrier signal, when reading the next one frame, the switch 49 (or 50) is switched to read by the delay circuit 47 (or 48). The image data is delayed by 140 ns to invert the color carrier signal phase.

A switch 37 is used to switch the reading of one frame of video data from each of the frame memories 35 and 36.
Done by 14.318 MHz (4 fs
The data read at a high speed in c) is a D / A converter 38.
To generate an original composite video signal.

[0035]

According to the present invention, the transmitting side transmits only video data without adding a code indicating a data packet,
On the receiving side, packet extraction is performed by detecting data of the video horizontal synchronization signal portion, so that the digital processing circuit can be simplified.

The packet extraction on the receiving side is performed using a 2's complement data sequence when allocating a packet using the shift register, and is performed using a natural binary code when detecting a bit pattern. Extraction of the synchronization bit pattern becomes easy.

Further, since the phase of the digital processing timing clock is matched with the phase of the color subcarrier frequency of the input composite video signal and the data transmission speed is set to an integer ratio of the color subcarrier frequency of the composite video signal, Processing timing clock reproduction is easy and faithful reproduction of a composite analog video signal is possible.

Further, a video signal can be transmitted at low cost without employing a band compression technique represented by MPEG.

Further, the present invention can be easily applied to a digital transmission system in which a video signal is intermittently taken in and a still image is frame-advanced or transmitted as a quasi-moving image at a low transmission rate.

[0040]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a transmission unit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a receiving unit according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a transmission unit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a receiving unit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a receiving unit according to still another embodiment of the present invention.

[Explanation of symbols]

 1,43 Transmission unit 2,19 A / D converter 3 Code converter 4,21 P / S converter 5 Digital modulation unit 6,14,28,41 Timing generation circuit 7,44 Transmission antenna 8,45 Receiving antenna 9 , 46 receiving unit 10 digital demodulating unit 11 shift register 12 code converter 13, 38 D / A converter 15, 40 LPF 16 synchronization detector 17 AND circuit 18 shift clock generation circuit 20, 35, 36 frame memory 22 differential conversion Circuit 23 QPSK modulation circuit 24 Synchronization separation circuit 25 AFC circuit 26 APC circuit 27 PLL circuit 29 QPSK demodulation circuit 30 Differential conversion circuit 31 Packet phase adjustment circuit 32 S / P conversion circuit 33 Pattern detection circuit 34, 37, 49, 50 Switch 39 phase comparator 42 VCO 47,48 delay circuit

Claims (6)

[Claims] 1. A transmitting side transmits a composite video signal to an N
Means for converting into digital data of bits (N is a positive integer), and means for digitally transmitting the converted digital data as continuous serial data. A receiving side receives the composite video signal from the received serial data. A means for detecting an N-bit data packet by detecting a bit pattern of a horizontal synchronizing portion, and a means for converting the N-bit data detected as a packet into an analog signal. Digital transmission method. 2. The transmitting side transmits a composite video signal to N
Means for converting digital data of bits (N is a positive integer) to digital data as continuous serial data; and a receiving unit for receiving a digital transmission signal on a receiving side. A bit clock reproducing unit, a shift register for shifting received serial data one bit at a time, and a synchronization for detecting an N-bit data packet by detecting a bit pattern of a horizontal synchronization portion of the composite video signal from the digital data. A video signal digital transmission system, comprising: a detection unit; and means for converting N-bit data detected as a packet into an analog signal. 3. The transmitting side converts the composite video signal into N bits (N is a positive integer) at a predetermined sampling frequency (fs).
An A / D converter for quantizing to a natural binary code of
A code conversion unit for converting data obtained by the / D converter into a 2's complement Gray code; and a modulation unit for performing modulation for digital transmission, and a digital transmission signal is received at a receiving side. A receiving unit, a bit clock reproducing unit, a shift register for shifting transmission data one bit at a time, a code converting unit for converting a 2's complement Gray code into a natural binary code, and a video signal from the natural binary code. A video signal comprising: a synchronization detection unit for detecting an N-bit data packet by detecting a bit pattern of a horizontal synchronization portion of the above; and a D / A converter for converting the detected data into an analog signal. A digital transmission method for signals. 4. An A / D converter for converting a composite video signal into digital data on a transmission side, a frame memory for temporarily storing two frames of the converted digital data as a still image, A memory control unit that reads out as serial data that can be transmitted at a low speed, a transmission unit that performs modulation for performing digital transmission, a receiving unit that demodulates a digital transmission signal, and a phase of transmission serial data on the receiving side. , A packet detection unit that detects a horizontal synchronization portion of the video signal to extract a data packet, a frame memory unit that stores data, and data that has already been stored until the next two frames of data are received. A memory control unit for continuously reading data for two frames, and an analyzer for continuously reading data from the frame memory; A digital transmission system for a video signal, comprising: a D / A converter for converting a log signal; and transmitting a still image extracted from the composite video signal at a low speed. 5. An A / D converter for converting a composite video signal into digital data on a transmitting side, a frame memory for temporarily storing one frame of the converted digital data as a still image, and a digital memory for storing the stored digital data. A memory control unit that reads data at low speed and a transmission unit that performs modulation for digital transmission, and a receiving unit that demodulates a digital transmission signal and shifts the phase of transmission serial data to the receiving side A packet detector for detecting a horizontal synchronization portion of a video signal and extracting a packet of data, a frame memory for storing data, and continuously storing one frame data until receiving data for the next one frame. A memory control unit for reading, and a delay unit for delaying to match the phase of the color carrier when reading one frame continuously. And a D / A converter for converting continuously read data into an analog signal, and transmitting a still image extracted from the composite video signal at a low speed. 6. The method according to claim 1, wherein the phase of the timing clock when digitally processing the video signal is matched with the phase of the color subcarrier frequency of the input NTSC signal, and the data communication speed is an integer ratio of the color subcarrier frequency. A digital transmission system for a video signal according to claim 1, 2, 3, or 4.