JP3300178B2 - Receiver for performing oversampling analog-to-digital conversion for digital signals within a TV signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for recovering a digital signal which has been converted into an analog television signal.

[0002]

2. Description of the Related Art Relatively small (e.g., 3 to 5 IRE) signals that encrypt digital information often appear on television screens generated from composite video signals, provided that proper restrictions are imposed on the format of the digital signal. Instead, it can be mixed with a composite video signal. JI-A
N YANG is disclosed in US patent application Ser. No. 08 / 141,070.
No. "Apparatus for processing NTSC television signals having digital signals on a quadrature video carrier"
It describes a system for doing this. Like the invention described herein, the invention described in the patent application by JI-AN YANG may be issued to Samsung Electronics in accordance with a pre-existing Merchant Agreement to assign inventions made within the scope of employment. Assigned.

[0003] JI-AN YANG is an image carrier and frequency.
The same number is described for double phase shift key (BPSK) modulation of a suppressed carrier with a quadrature phase. JI-A
NYANG the comb filtering (comb fil
Regardless of tering, a TV receiver that separates luma and chroma (chroma) claims a BPSK signal that is limited by a bandwidth of about 2 MHz in order to avoid crosstalk into chroma. .

[0004] JI-AN YANG is more capable of transmitting data transmitted through a partial response filter to increase the correlation at corresponding points appearing along horizontal scan lines that are continuous in the composite video signal. Although it states that it is good, this is because line-comb filtering (line-comb f
iltering) .

[0005] JI-AN YANG also uses NTSC.
Claims to repeat BPSK frames in successive pairs of television signals in antiphase. The repetition of such data in a frame pair makes the composite video signal detected from the NTSC television signal less visible in the video generated from the composite video signal for BPSK to view on the screen.
Such repetition of data occurring in frame pairs can also result in a static portion of the continuous television image.
luminance part and BPSK of the composite video signal representing
To separate frame-comb filters in the digital signal receiver.
ering) .

[0006]

SUMMARY OF THE INVENTION JI-AN YANG
Are typically used to digitize composite video signals.
ter) is used, BPSK
Describes the problems that occur in digital signal receivers when digitized after detection. The remnant of the composite video signal of 750 kHz or more accompanies BPSK when BPSK is detected at the same time, but may sometimes be relatively large compared to BPSK.

[0007] If the digitization is performed immediately after the synchronization detection of BPSK and the quantization noise of the flash converter having only a resolution of about 8 bits, the relatively small BPSK is used.
If the K signal is improperly decomposed, the remnants of such a large composite video signal occupy a large part of the dynamic range provided by the flash converter to the analog input signal. Flash converters with as little as 12 bits can be made, but are too expensive for use in mass market electronics.

[0008]

Means for Solving the Problems JI-AN YANG
Asserts the use of line comb filtering of the BPSK signal before digitizing to reduce the relative magnitude of remnants of the composite video signal above 750 kHz with BPSK. The BPSK signal can then be broken down into a larger portion of the digital output range of the flash converter to reduce symbol errors.

[0009] While flash converters have increased in price fairly rapidly as their bit resolution has increased, the limitation on BPSK bandwidth that JI-AN YANG asserts is the price for bandwidth increases beyond 2 MHz. The increase is more appropriate. The 2 MHz limit on the BPSK bandwidth requires a 4 MHz sample rate for the maximum symbol rate to be properly sampled, an 8 bit flash conversion that can operate up to 16, 32 or even 64 times. The vessel is relatively reasonable in price.

Accordingly, the inventor points out that an oversampling conversion method can be used to obtain increased effective bit resolution from such an 8-bit flash converter. Since an effective resolution of about 12 bits can be obtained by oversampling at 16 times the 4 MHz sample ratio, the detected BPSK is compared with the composite video signal that occupies most of the dynamic range of the flash converter. Even if the BPSK is extremely small, the detected BPSK can be digitized without being lost by the quantization noise.

The present invention is embodied in a digital signal receiver for detecting a BPSK modulation of a suppression carrier orthogonal to a video carrier amplified and modulated by a composite video signal, wherein the detected BPSK is a residual composite video signal. BP from signal
SK is digitized before comb filtering. Preferably, the digitization of the detected BPSK is performed by an oversampling analog-to-digital converter.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS General equalization delays have been omitted from the drawings to simplify the drawings and to make them more understandable. Those of ordinary skill in the art of video signal processor design will be able to properly time-shift pixels or data affected by other delays on these other paths due to other processes performed on other paths. Align (time-ali)
gn) to recognize the need for such a delay. Anyone with ordinary knowledge in the field will need to know where such delays are, and understand how long each delay must be,
Such a delay will not be described below.

[0013] In a logic circuit, a person having ordinary knowledge in the relevant field is unsuitable for a “logic conflict (logic).
race) "condition, or shimming required to compensate for potential delays in performing logic operations.
A detailed description of the logic circuit design with respect to providing shimming delays will not be discussed below, as one can understand how to provide the delays. Furthermore, where analog-to-digital converters are shown and described herein, those having ordinary skill in the art will appreciate that anti-aliasing is not an option.
g) Since it is desirable to precede such a converter with a low-pass filter and how this can be implemented, it will not be described further below.

Also, if a digital-to-analog converter is shown or described herein, and is of ordinary skill in the art, then such a sample clock rejection low pass filter may be followed by such a converter. It is not further described below, as it can be appreciated that it is desirable to add and how this can be performed.

FIG. 1 shows a television transmitter 1 for transmitting a television signal in which a digital signal is hidden. The analog audio source 2 supplies one or more analog audio signals to the audio processing circuit 3. The audio processing circuit 3 supplies a modulation signal to the FM audio carrier carrier 4 for modulating the frequency of the audio carrier. The audio processing circuit 3 includes a delay necessary for synchronizing audio and a screen.

Also according to convention, the audio processing circuit 3 also includes a pre-emphasis network for the analog audio signal,
3D sound and secondary audio program (S) for inclusion in the modulated signal supplied to the M audio carrier transmitter 4.
AP) An apparatus for generating a sub-carrier may be included.

The frequency modulated (FM) audio carrier is
In-phase VSB AM video carrier and quadrature VSB B
In order to be frequency multiplexed with the PSK data carrier, it is usually supplied from an FM audio carrier transmitter 4 to a multiplexer 5. In the television transmitter 1 for wireless broadcasting, the multiplexer 5
Usually takes the form of an antenna coupling circuit, and the resulting frequency multiplexed transmission signal is broadcast from a transmission antenna 6.

A television transmitter for a radio relay station in a cable broadcasting system would not have the transmitting antenna 6 used for radio broadcasting. The multiplexer 5 has other forms, but the signal frequency multiplexed from the channel under consideration is further frequency multiplexed with the signal frequency multiplexed from the other channel, and the resulting signal is linear. It is applied to the trunk cable of the cable broadcasting system by the amplifier.

In FIG. 1, the analog video source 7 is
The basics of the modulation signal supplied to the VSB AM video transmitter 8 and
VSB AM video transmitter 8 analog composite video signal comprising
The VSB AM video transmitter 8 supplies the VSB AM video carrier to a multiplexer 5 from which it is frequency multiplexed with a frequency modulated (FM) audio carrier. The vertical synchronizing pulse, the horizontal synchronizing pulse, and the color burst of the analog composite video signal from the analog video source 7 are synchronized with the corresponding signals supplied by the station synchronizing signal generator 9.

The control connection 10 between the analog video source 7 of the composite video signal and the station synchronization generator 9 indicates the means used for such synchronization. Analog bidet
If Oh source 7 is urban studio or local television broadcasting station and the remote generator networked other composite video signal such as a television broadcasting station, the control connection 10
Would be a genlock connection to the station synchronization generator 9.

When the analog video source 7 is a regional camera, the regional camera receives synchronization information from the station synchronization generator 9 via the control connection 10. Various other types of synchronous designs, including those for video tape recorders and television cinema equipment, are familiar to those of ordinary skill in the art. Usually, time division multiplexer 11 is a vertical sync pulses, horizontal sync pulses, equalizing pulses, color burst and Pedesuto Le
Synchronous block information ( often referred to on the porch) may be replaced with VSB instead of the original synchronous block information.
It is used to insert into a composite video signal applied as a modulation signal to the AM video transmitter 8.

In the television transmitter 1 shown in FIG. 1, another VSB AM transmitter 12 has a residual band and an NTSC
In that for generating the binary phase shift key (VSB BPSK) suppressed carrier of VS B AM picture carrier and quadrature for the composite video signal, different from the transmitter currently used. This other VSB AM transmitter 12 can include a balanced modulator that balances the carrier and the BPSK modulated signal, receives the in-phase video carrier from the VSB AM video transmitter 8, and It may further include a 90 ° phase shift network that provides a carrier to the balanced modulator.

VSB A amplified and modulated by the NTSC composite video signal received from the VSB AM video transmitter 8
VS received from transmitter 12, such as M video carrier
The BBPSK signal is supplied to a multiplexer 5 from which it is frequency multiplexed with a frequency modulated (FM) audio carrier.

The serial bit digital source 13 converts the additional bits of the error correction code into a serial bit stream (serial-bit) applied to the frame repeater 15.
error correction coder 14 for insertion into the stream)
, A digital signal in the form of a serial bit. Frame repeater 15 provides each frame of received data to twice the input signal of the output signal. Frame repeater 1
5 is supplied to the partial response filter 16,
The partial response filter 16 inserts the correlation data in the appropriate points of the successive horizontal scanning lines. The digital response signal from the partial response filter 16 is supplied to a DAC 17 for conversion into an analog key signal.

The DAC 17 supplies a keying signal having a predetermined positive value corresponding to the digital 0 and a predetermined negative value corresponding to the digital 1 to the high frequency pre-emphasis and transfer shaping filter 18. It said predetermined negative level of the analog modulation signal has the same absolute value and the predetermined positive level of the analog modulation signal. The transfer shaping filter 18
Compensating for the loss in detection efficiency when simultaneously detecting VSB BPSK, this loss is from transmission, which is effectively a single sideband.

The response signal of the transfer shaping filter 18 is VS
The keying signal supplied to the balanced modulator at the BAM transmitter 12, which also receives the modulated quadrature video carrier. The VSB AM video transmitter 8 that supplies the VSB AM video carrier amplified and modulated by the NTSC composite video signal to the multiplexer 5 includes a VSB
The quadrature phase VSB BP transmitted from the AM transmitter 12
It is carefully designed and operated to avoid accidental phase modulation that can disturb the SK suppressed carrier.

Since the quadrature phase VSB AM carrier for PSK is suppressed, the phase of the combined VSB PSK and VSB AM signals is no different than can be sensed from the phase of the in-phase VSB AM video carrier. FIG. 1 shows a VSB AM video transmitter 8 and VSB separated from each other.
Shows the AM video transmitter 12, but actually, the same upper side band filter and the final amplifier stage, VSB AM video transmission <br/> Shin machine 8 and VSB AM video transmitter 8 and 12 can share.

FIG. 2 shows one form 160 in which the partial response filter 16 can be taken. Digital input signal serial bit form, via the input terminal 161 is applied to the first input terminal of the 2-input exclusive-OR (XOR) gate, the output of the 2-input XOR gate contact and the output terminal 163
Subsequently, the response signal of the partial response filter 160 is supplied thereto.

The second input of the XOR gate 162Terminal
Is the read output of the digital delay line 164ConnectionFrom
Write input for digital delay line 164ConnectionApplied to
Delay for the output signal from the multiplexer 165
Postponed responsesignalTo receive. Operate in read-write repeat mode
Created as a circular address line storage memory implemented as
The resulting digital delay line 164 is a single television
"1-H" delay equal to the horizontal scan line cycle
provide. The last data line of the data frame is
Filter 160 to indicate that it is being supplied to the filter 160.
Last row decoder supplied as a control signal to the
Excluding when the loading result is 1, the multiplexer 1
65 is a write input of the digital delay line 164Connection
Output terminal 163 to apply
160 responsessignalSelect

When the last row decoding result supplied as a control signal to the multiplexer 165 is 1, indicating that the last data row of the data frame is supplied to the partial response filter 160, the multiplexer 165
Applies the modulo 2 data frame count to the write input connection of the digital delay line 164. When the modulo 2 data frame count so applied is zero during the last row of the last frame of the pair,
A series of zeros are written to the digital delay line 164 so that during the first data row of the next paired frame, the data passes through the partial response filter 160 unchanged.

However, the digital delay line 16
A series of ones is applied to the digital delay line 1 when the modulo 2 data frame count selected by the multiplexer 165 is one during the last row of the first frame of the pair of data frames to be applied to the write input connection of the four.
64, during the first data row of the last frame of the data frame pair,
Passing through 60 results in a one's complement. This ensures that the data line next to the last frame in the data frame pair is the one's complement of the corresponding data line in the first frame preceding the data frame pair.

The digital filtering provided by the partial response filter 160 is to convert the digital responses 0 and 1 at the output terminal 163 with +1 and -1 amplification of the keying signal of the signal to control the generation of the BPSK signal. Suppresses the DC term in the analog signal generated by. This digital filtering shows that the response peaks at odd multiples of the half horizontal scanning line frequency fH, and that the response becomes zero at multiples of the horizontal scanning line frequency fH. This digital filtering causes the PSK signal for the data to have a comb-shaped frequency spectrum that complements the frequency spectrum of the comb-shaped luminance signal.

The luminance signal is a half horizontal scanning line frequency f
A response of 0 is represented by an odd multiple of H, and the horizontal scanning line frequency f
The peak of the reaction appears at a multiple of H. Partial response filter 16
0 shares the spectrum of PSK and passes through a 2-tap high-pass line comb filter with a single 1H delay line and a subtractor. Such a high-pass line comb filter has a digital signal receiver for suppressing a luminance signal having a friendly correlation between vertically arranged pixels and reducing it as a jamming signal 1 for PSK. Can be located.

FIG. 3 shows another form 166 in which the partial response filter 16 can be taken, which includes a final filtering section including the same elements 162 to 165 as the partial response filter 160. The partial response filter 166 further includes a first filtering unit similar to its own final filtering unit. This first filtering unit is a 2-input exclusive OR
A gate 167, but having a first input
The terminal is connected to the input terminal 161, and the output of the gate 167 is connected to the first input terminal of the XOR gate 162 rather than the input terminal 161 as in the partial response filter 160 shown in FIG.

The second input of the XOR gate 167Terminal
Is the read output of the digital delay line 168ConnectionFrom
Write input of digital delay line 168ConnectionApplied to
Delay for the output signal from the multiplexer 169
Postponed responsesignalTo receive. Digital delay line 168
Is a single TV like a digital delay line 164
Provide "1H" which is the same as the period of the John horizontal scan line.
Offer. The last data line of the data frame is
The multiplex, which indicates that the
Last row decoded supplied as a control signal to the
Excluding when the multiplexing result is 1, the multiplexer
169 is a write input of the digital delay line 168end
ChildResponse of XOR gate 167 to applysignalChoose
Select.

When the last row decoding result supplied as a control signal to the multiplexer 169 is 1, indicating that the last data row is being supplied to the partial response filter 166, the multiplexer 169 outputs the signal (w).
ired) 0 is applied to the write input connection of the digital delay line 164. This writes a series of zeros to the digital delay line 164 during the first row of each data frame. This series of zeros is provided to the XOR gate 167 during the first row of the next data frame, and the first zero of the data for selective interpolation, as described for the partial response filter 160 shown in FIG. Row is XOR gate 16
7 to the XOR gate 162.

The partial response filter 166 has a sharper toothbrush-like comb response than the partial response filter 160, but also exhibits a zero response at odd multiples of the half horizontal scan line frequency fH, The peak of the response appears at a multiple of the frequency fH. Digital signal receiver 3-
A tap high-pass line comb filter can be used to recover the PSK signal with a planar frequency spectrum and reduce the luminance signal of the jamming signal for the PSK.

FIG. 4 shows in more detail the structure for a portion of the television transmitter 1 shown in FIG. 1 used to digitally filter the digital data from which the phase shift keying signal is generated. The error correction coder 14 supplies a digital signal in the form of a serial bit to the rate buffer 20. Preferably, the error correction coder 14 is a type which generates a modified Reed-Solomon codes, the rate buffer 20 performs a dual role as the interleaver.

The interleaver operation of the rate buffer 20 is performed by the VS along with each horizontal scan line of the composite video signal transmitted by the VSB AM video transmitter 8.
The original order of the data scanning is arranged in columns lying over the rows of data finally transmitted by the BAM transmitter 12. The impulse noise and intermediate band frequencies of the composite video signal, which tend to couple horizontally, were mapped to rows appearing along the horizontal scan lines rather than on data mapped to columns lying over the horizontal scan lines. Than the modified Reed-Solomon code that operates on data,
The above operation is performed in order to less disturb the bits of the modified Reed-Solomon code.

In any event, the rate buffer 20 is a memory that provides a regularly adjusted base bit to a frame store memory 21 for writing during alternate data frames. A data frame is defined as a block of 525 rows of symbols occurring at a symbol rate that is a multiple of the data row scan rate, wherein the data row scan rate is similar to the horizontal scan line rate for an analog composite video signal. The BPSK symbol is a bit, but the symbol to which the modified Reed-Solomon code is applied is typically 2 @ N bits of data, where N is a small positive integer such as 3, 4, or 5.

The extended bit length of each modified Reed-Solomon code is selected to be less than 525 (for example, 256 or 512), and the impulse noise is reduced one or more times along its vertical axis by one of the modified Reed-Solomon codes. Upset one less. The relative phases of the data rows and the horizontal scan lines of the composite video signal are such that each data row coincides with each horizontal scan line of the composite video signal in time. The data frames appear in the same proportions as the frames of the analog composite video signal provided by the analog video source 7, but for reasons further disclosed herein, the data frames are represented by the composite video signal. It is convenient to delay the video signal frame by nine horizontal scan lines.

During each frame in a pair of consecutive data frames, the frame store memory 21 writes the first data frame after writing the first data frame to generate an output signal provided as an input signal to the partial response filter 16. Read and write it again before writing it again to the second data frame. Writing and reading of the rate buffer 20 and the frame storage memory 21 are controlled by a frame storage packing control circuit 22. During the selected vertical blanking interval (VBI) scan line, the transmitter 1 used to count eight frame cycles to control the insertion of the ghost cancellation reference signal into the composite video signal. The frame counter is one of its stages, the modulo 2 data frame used to time the read and read-write repeat operations of the frame store memory 21 between each frame of each successive data frame pair. A counter 23 is included. The frame
The memory storage and packing control circuit 22 also receives a data row count signal from the data row counter 24 and a symbol count signal from the eight-stage symbol counter 25, and performs row addressing on the received data row count signal and symbol count signal, respectively. And to the frame storage memory 21 as read addressing in a row. The data row count and the symbol count together constitute a completed addressing AD, and the frame storage packing control circuit 22 applies the completed addressing AD to the frame storage memory 21 shown in FIG.

Further, the frame storage packing control circuit 22 includes a write enable signal WE for the frame storage memory 21 and the completion addressing AD supplied to the frame storage memory 21 while writing the frame storage memory, together with the rate buffer 20. , And a write addressing WAD for the rate buffer 20 are generated. When digital data is selectively transmitted, the frame storage packing control circuit 22 also generates a read enable signal RE for the frame storage memory 21.

A more detailed operation mode is as follows.
Data frame count bits are supplied from the modulo-2 data off <br/> frame counter 23 to the frame storage packing control circuit 22, from which only when modulo 2 DATA FRAME COUNT bit is 0, with respect to the frame storage memory 21 Used to generate a write enable signal. The frame storage packing control circuit 22 supplies a read enable signal and a write enable signal for operating the frame storage memory 21 in a read-write repetition mode when the modulo 2 data count bit is 0. When the modulo 2 data frame count bit is 1, the frame storage packing control circuit 2
2 supplies only a readable signal.

The last row decoder 27 includes a data row counter 2
4 and a multiplexer 165 in the partial response filter 16 and a multiplexer 16 (if used for the filter 16).
9 to generate a control signal. The last row decoder 2
7 provides a zero output signal as a result of final row decoding in response to all values of the data row count, excluding the case where the last row is represented in the data frame, wherein the zero output signal is
Multiplexer 165 in partial response filter 16
(And, if multiplexer 169 is used, also 169) causes the partial response filter 16 to perform normal partial response filtering.

For the next data frame, the partial
To adjust the loading of the 1-H delay line 164 (and the 1-H delay line, if used) to match the initial state of the answer filter 16, the last row decoder 27 In response to the represented data row count, one response is provided to a multiplexer 165 in the partial response filter 16 (and 169 if multiplexer 169 is used). The modulo 2 data frame counter 23 supplies the multiplexer 165 with the modulo 2 data frame count as an alternative input signal, and when the last row decoder 27 supplies 1 to the multiplexer as a control signal, 1-H The write input connection of the delay line 164 is selected.

FIG. 4 includes, in addition to an eight stage symbol counter 25, a 256f _H voltage controlled oscillator (VCO) 31, a zero crossing detector 32, a 255 count decoder 33, and an automatic frequency and phase control (AFPC) detector 34. The symbol clocking circuit 30 is shown. The eight stage symbol counter 25 includes eight binary counting stages.

The zero-crossing detector 32, which may be more appropriately referred to as an average axis crossing detector, generates a pulse whenever the sine oscillation of the VCO 31 crosses its average axis in a predetermined direction. The zero-crossing detector 32 typically includes a limiter amplifier for generating a square wave for the sine oscillation of the VCO 31, a differentiating circuit for generating a pulse responsive to the transition of the square wave, and a frame storage packing control circuit 22 for timing purposes. Constitutes a clipper for separating the pulses of any pole supplied to. Also, such pulses are supplied to the 8-stage symbol counter 25 for counting on each successive line, and generate the symbol count supplied to the frame storage and packing control circuit 22.

The 255 count decoder 33 decodes the symbol count down to 255 to generate a pulse. Since the maximum count value is a power of two, each pulse from the 255 count decoder 33 is generated by the zero-crossing detector 32 in accordance with the 8-stage symbol < On the next pulse supplied to the counter 25, the 8-state
Since it may be used to reset the di symbol counter 25, returning the symbol count arithmetic zero. The 255 count decoder 33 supplies the pulse to the AFPC detector 34, and compares the pulse with the horizontal synchronization pulse H to develop the AFPC voltage supplied to the VCO 31. this is,
255 times originating Fushu wavenumber of VCO31 is horizontal scan line frequency, or 4, 027, to complete the regulation to negative feedback loop so as to 972Hz.

One method for synchronizing the counts with the modulo 2 data frame counter 23 and the data row counter 24 having a frame of the analog composite video signal will now be described. In the digital signal receiver for the system described herein, the data frame count is recovered at the beginning of line 9 of each frame of the analog composite video signal, immediately after the falling section of the vertical sync pulse in the initial field of each frame. It is desirable to synchronize the counters that do. In such a case, the counter that generates the data row count at the digital signal receiver is reset with a predetermined count value at the beginning of line 9 of each frame of the analog composite video signal.

Synchronizing the counts to the modulo 2 data frame counter 23 and the data row counter 24 in the transmitter 1 shown in FIG. 4 is compatible with a preferred receiver implementation. The output signal of the 255 count decoder 33 is supplied to a 2-input AND gate 36 as a first input signal.
Station sync generator 9 supplies vertical sync pulses V to the edge <br/> detector 35, the edge detector 35 is the edge line 9 of the composite video signal, and the line 271 of the composite video signal provides pulses at the midpoint, the output signal of the edge detector 35 is supplied as a second input signal to the aND gate 3 6.

[0052] The response signal of the AND gate 3-6, comprising the data frame end pulse edge line 9 of the composite video signal. Each such data frame tail pulse is applied as a trigger pulse to the modulo 2 data frame counter 23 to advance the data frame count signal, and the data pulse to reset the data row count to a predetermined initial value. Applied to the row counter 24. The You can either not 255 count decoder 33 actually, carry pulses from the final binary counting stage of the 8-stage symbol counter 25, the 255 mosquitoes
Instead of the output signal of the count decoder 33 may be supplied to the AFPC detector 34 and the AND gate 3 6.

The transmitting device described above with reference to FIGS. 1 to 4 is the same as that described by JI-AN YANG. The following digital signal receiver with reference to FIGS. 5 to 8 embodies the present invention.

FIG. 5 shows a digital signal receiver 37 for receiving a hidden digital television signal from a unit such as an antenna 42 and extracting the hidden digital signal. Tuner 43 selects a television channel detected by a first detector therein, the first detector converting the selected television signal to a set of intermediate frequencies and a set of video frequencies. Superheterodyne for conversion
a tunable down converter of the terodyne type.

The video intermediate frequency (IF) filter 44
The video intermediate frequency is selected for application as an input signal to the intermediate frequency amplifier 45, and the frequency of the video set is not selected. Following common practice, surface acoustic waves (SA
The W) filter can be used for the video IF filter 44 and for configuring the video IF amplifier 45 within a single integrated circuit (IC) of a multi-stage amplifier with no interstage tuning. The video intermediate frequency amplifier 45 supplies the amplified video intermediate frequency signal to the in-phase synchronous image detector 46 and the quadrature phase synchronous image detector 47. The oscillator 48 oscillating at the standard frequency of 45.75 MHz is
The oscillation is supplied to the in-phase synchronous video detector 46 without a phase shift. The oscillator 48 has an automatic frequency and phase control (AFPC) responsive to the output signal of the quadrature-phase synchronous video detector 47.

The in- phase synchronous image detector 46 and quadrature
The synchronous video detector 47 is usually provided with the video intermediate frequency amplifier 4.
5 and an oscillator 48 are included in the integrated circuit. The same
Phase synchronous image detector 46 and quadrature phase synchronous image detector 47
May be an enhanced carrier type or a true synchronization type. The in-phase modified composite video signal recovered by the in-phase sync video detector 46 is supplied to a horizontal sync separator 50 and a vertical sync separator 51, where the horizontal sync separator 50 and the vertical sync separator 5 are used.
1 recovers horizontal and vertical sync pulses from the in-phase modified composite video signal, respectively.

[0057] Preferably, also centered on a frequency filter 44 between middle 45.25MHz made of only approximately 3.5MHz width, the appearance of a digital signal receiver 37 described up to now, of the television receiver Those of ordinary skill in the design arts are generally familiar. this
Frequency filter 44 between the medium is quadrature-phase synchronous video detector 4
7 next without the need for filtering chroma rejection and in-channel rejection, providing chroma rejection and in-channel rejection (and the digital signal receiver 37 is configured with a television receiver, before Symbol in The inter-frequency filter 44 is
Chroma rejection and in-channel audio rejection provided by filtering after quadrature synchronous video detector 47 would be wide. ).

The bandwidth of the quadrature-phase synchronous image detector 47 must be slightly wider than the symbol rate in order not to reduce the upper frequencies in the "tail" of the BPSK response. The quadrature synchronous video detector 47 detects a keying signal with only such a part of the NTSC composite video signal at a frequency of 750 kHz or more.

In practice, the digital receiver 37 usually includes a ghost suppression circuit, which is not explicitly shown separately in FIG. It can be seen in the type described in detail in 08 / 108,311.

Each of the in-phase synchronous image detector 46 and the quadrature phase synchronous image detector 47 is arranged next to its own synchronous detector.
It includes respective ghost cancellation and equalization filters similar to those used next to the sync detector included in the other video detectors. The tunable parameters of the two ghost cancellation filters are adjusted horizontally in response to calculations performed by the computer, and the tunable parameters of the two equalization filters are also calculated by another computer. Adjusted horizontally in response to

When transmitted, the frequency is expanded to 4.1 MHz, but due to the limited intermediate frequency bandwidth in digital signal receivers, the frequency is expanded only to about 2.5 MHz Ghost Elimination Criterion (GCR) The signal is extracted from the selected vertical blanking interval (VBI) scan line of the video signal detected by the in-phase synchronous video detector 46.

The GCR signal is digitized and provided as an input signal to a computer for calculating adjustable parameters of the ghost cancellation and equalization filter. Alternatively or additionally, the DC or low frequency components of the response signal of the quadrature locked image detector 47 can be detected and used as a basis for calculating the adjustable parameters of the ghost cancellation filter.

[0063] In the digital signal receiver 37 shown in FIG. 5, the sample / symbol count signal is responsive to the sine oscillation received from the voltage controlled oscillator 105, and counts the pulses generated by the zero crossing detector 104 4
It is generated by the stage symbol counter 103. The symbol count signal is output from the 4-stage symbol counter 1
Generated by an 8-stage symbol counter 52 that counts the excess carrier from 03.

The 255 decoder 55 is connected to the zero-crossing detector 10
4 on the next pulse supplied to the 4-stage symbol counter 103 by the 4-stage symbol counter 1
To generate a pulse that resets the 03 and 8-stage symbol counter 52, the symbol count down to 255 is decoded and all sample / symbol counts and symbol counts are returned to arithmetic zero. 25 above
5 The pulse generated by the decoder 55 is fed to an AFPC detector 56 for comparison with the horizontal sync pulse H separated by the horizontal sync separator 50 and is adjustable to subdivide the symbol period by the control delay line 57 To be delayed.

The comparison result is low-pass filtered in the AFPC detector 56 to generate an automatic frequency and phase control (AFPC) voltage signal for application to the VCO 105. Such a device is a line-closed VCO1
05 is controlled to be 4,096 times or 64,44 times the horizontal scan line frequency fH.
The frequency is set to 7,545 Hz. The term "line closure" used in connection with a controlled oscillator means that the frequency of oscillation is one.
5,734,264 Hz is maintained at a fixed ratio to the scan line frequency, which is typically the AFP that compares the frequency of oscillations separated by the horizontal sync pulse by appropriate factors.
It means that it is performed by the C circuit.

The keying signal and accompanying portion of the NTSC composite video signal at a frequency of 750 kHz or more detected by the quadrature synchronous phase video detector 47
8, the matched filter 58 is responsive to a keying signal of a selected portion of the frequency element that is above 750 kHz of the composite video signal. The matched filter 58
Is sufficient to reduce the intersymbol interference
To expand the SK bandwidth, transition shaping of the roll-off transition shaping <br/> filter 18 in the transmitter (roll-o
ff) is provided.

The matched filter 58 also effectively progressively becomes a single-sided band beyond the frequency range between 0.75 and 1.25 MHz, and substantially over the frequency range above 1.25 MHz. To single side band VSB BPSK
Further, a peaking response is provided to compensate for the roll-off of the detection efficiency of the quadrature phase locked image detector 47 due to the following. However, the vestigial sideband filters of other television transmitters exhibit inter-variation, so the quadrature
The peaking response for compensating for the roll-off of the detection efficiency of the synchronous video detector 47 can be adjusted by modifying the transition shaping filter 18 to provide an appropriate peaking response in addition to the shaping transition. Perhaps even better on Machine 1. However, such additional peaking or pre-emphasis of the binary keying signal at the transmitter 1 would increase the high frequency content of BPSK above 0.75 MHz transmitted with the luminance signal.

The response from the matched filter 58 is applied as an input signal to, for example, an analog-to-digital converter 106 of a flash converter having an 8-bit resolution. The quadrature phase locked video detector 47 is substantially 75
Without recovering the frequency of the composite video signal below 0 kHz,
BPSK compounding has no zero frequency content. 750
The BPSK portion of the response of the quadrature-locked video detector 47 during transmission of the television video at frequencies above kHz and without much energy will alternate in polarity. Placing one of the decision thresholds for quantizing the input signal at the ADC 106 at a zero analog input level would result in A
Even if the bit resolution of the DC 106 is slightly lower than 8 bits, the BPSK part of the response of the quadrature-phase synchronous video detector 47 changes to the digital response of the ADC 106 during the transmission of the television video without any energy at a frequency of 750 kHz or more. Ensure triggering.

The right angle of the sync pulse to the constant frequency element
Due to the non-responsiveness of the phase-locked video detector 47, the moving area of the remnants of the composite video signal is reduced to 140 IRE units or less.
It must be rough in the dynamic area possible in the output, right-angled position
The phase synchronous image detector 47 responds to the moving area. If ADC 106 has an 8-bit resolution and BPSK
If the amplitude of is approximately 3 IRE units, five to six decision thresholds will be crossed by BPSK. Since this is sufficiently above the quantization noise, television images having some energy at frequencies above 750 kHz cannot place the BPSK portion of the response of the quadrature locked image detector 47 between close decision thresholds. There will be.

However, if the symbol determination circuit is to be replaced by the digital signal receivers 37 and 3 shown in FIGS.
As in the case of FIG. 8, when symbol determination for the ternary keying signal has to be performed, almost 16 determination thresholds are set to BPSK in order to guarantee a low symbol error.
Must be crossed by If the symbol decision circuit must make a symbol decision for the five-level keying signal, as in the case of the digital signal receivers 39 and 40 of FIGS. BPS to guarantee
It must be crossed by a K.

Accordingly, in a preferred embodiment of the present invention, A
The DC 106 is operated as an oversampling analog-to-digital converter so that the zero-crossing point is zero-crossing detector 10.
4 samples the response from the matched filter 58 each time it is detected. Therefore, the ADC 106 samples the symbol rate of 256 times the horizontal scanning rate fH 16 times, and the additional 4-bit resolution is 8 times through oversampling.
It can be obtained from the bit ADC 106.

The digital response signal of the ADC 106 is supplied as an input signal to a finite impulse response (FIR) digital low-pass filter 107. The filter 1
07 is a multi-tap digital delay line, the signal from its successive taps being symmetrically weighted according to the (sin x) / x function before adding to produce a low-pass filter response. The low-pass filter response from the filter 107 is B at 256 times the horizontal scanning rate fH.
It is provided to a 16 × sub-sampler or decimator 108 which provides a 12-bit analog-to-digital conversion response at the PSK symbol rate. 16
Decimation (deci) by the double sub-sampler 108
) reduces the storage power required in the subsequent digital comb filtering delay. Sampling from the sub- sampler 108 at the symbol rate having the optimal phase will vary at the symbol rate, but is a form of synchronous symbol detection that suppresses the response of quadrature composite video signals to elements. is there.

The sign bit (sign bit) of the digitized response signal of the ADC 106 is input by a line (wired taking). The sign bit and the sign bit delayed by one sample in the bit latch 110 are exclusive O
It is supplied to the R gate 111. The XOR gate 111
Detects the zero crossing of the digitized response signal from the ADC 106, and compares the detection result with a pulse phase discriminator 67.
To supply.

The pulse phase discriminator 67 determines the zero-crossing point of the oscillation signal of the control oscillator 105 detected by the zero-crossing detector 104 from the zero of the ADC 106 response signal detected by the XOR gate 111 from an appropriate phase relationship. The starting point of the intersection is selectively detected. The pulse phase discriminator 67 performs a low-pass filter on the sampled such selectively detected starting point and controls the control delay line 5.
7 generates a control signal for adjusting a delay provided to the horizontal synchronization pulse H applied to the AFPC detector 56. Such selective detection by the pulse phase discriminator 67 is performed by quadrature-phase synchronous image detection for a composite image signal.
This can be done during vertical blanking when the response value of the detector 47 is expected to be zero. Thus, during digitization, the phase of the ADC 106 input signal relative to the sample at the symbol rate is adjusted to minimize intersymbol interference.

An apparatus for adjusting the phase of a line-locked oscillator is of the form developed by the inventor's colleague, Jung-Wan Ko.
The AFPC loop which controls the frequency and phase of the oscillating signal of the control oscillator 105 with respect to the adjustable delay horizontal synchronizing pulse H supplied from the control delay line 57 causes the clocking of the ADC 65 to have a "rapid" period while adjusting the phase. And a filtering function for preventing occurrence of “glitch” or remarkable shortening. Such abrupt changes sometimes occur when adaptive phase adjustment is attempted in the ADC 65 clocking itself.

The vertical sync separator 51 supplies a "lossy" integrated response to the separated vertical sync pulse V to the threshold detector 68, the threshold voltage of which is 5 More than 1/2 scan line, 6 and 1/2
It is selected to be exceeded only when integrated below the scan line. It is 1 only when the input signal exceeds the threshold voltage, otherwise the output signal of the 0 threshold detector 68 is applied to the 2-input AND gate 69 for the first time.
Provided as an input signal (at the edge of a horizontal scan line).

The decoder 55, which generates 1 for the final value of the symbol count in each data row and generates 0 otherwise, outputs its output signal to the AND gate 6
9 as its second input signal. The one generated from the output of the AND gate 69 is responsive to the falling edge of the vertical pulse occurring at the beginning of the initial field of the composite video signal frame and provides a respective data frame end pulse for each such falling edge. Does not respond to the falling section of the vertical pulse that occurs between the initial and final fields of each frame.

To advance the reproduced data frame count signal obtained by subtracting one scan line from the data frame count signal at the transmitter, the AN
The data frame tail pulse in the response signal of D-gate 69 is provided to modulo 2 data frame counter 70 as a count input (CI) signal. As shown in US patent application Ser. No. 08 / 108,311, the best way of synchronizing the data frame counts in the television transmitter 1 and the digital data receiver 37 is four frames. The burst phase and Bessel chirp (Bessel chirp) on the 19th scan line
chirp) refers to a ghost cancellation reference (GCR) signal generated in a predetermined permutation of the phase. A single binary stage counter 70 that generates a modulo 2 data frame count is often a single stage in a multiple binary stage counter that generates a modulo 2N (N is an positive integer of at least 2) data frame count. Yes, the multi-stage counter is used to determine the accumulated time of a ghost cancellation reference (GCR) signal.

The data frame end pulse in response to the AND gate 69 is also applied as a reset signal to the data row counter 71 to reset the recovered data row count to its output signal with arithmetic zero. The output signal must be 524. The data row counter 71 is connected to count the horizontal synchronization pulse H supplied from the horizontal synchronization separator 50. The data row count is a circuit for acquiring data for a computer that calculates adjustable filtering parameters for the equalization and ghost cancellation filters included in the image detectors 46 and 47 (not explicitly shown in FIG. 5), GC
Used to control the selection of the VBI scan line containing the R signal.

The high-pass frame comb filter 72
The digital response of the desampler 108 is received as an input signal. A high-pass frame comb filter 72 includes a digital frame store 74 and a digital subtractor responsive to the signal samples for providing the signal samples applied at the input to the output for one frame scanning period, as appropriate. 73. The digital frame storage 7
4 is an R which is conveniently operated in a read-write repeat mode.
It is equipped with AM. The RAM receives the data row count from the counter 71 to line addressing (LAD) and receives the symbol addressing (SA) from the counter 52.
D) Receive the symbol count.

The subtractor 73 receives a sample of the digitized keying signal for the current frame from the resampler 108 as a minuend input signal, Is received as the decrement input progress. The difference signal of the subtracter 73 is a response signal of the high-pass frame comb filter 72, Zan'azuka luminance component representing the correlation of the frame-to-frame from this response signal <br/> is removed.

The high-pass line comb filter 120 receives this response signal as its input signal. The high-pass line comb filter 120 is a matched filter for the partial response filter 160 shown in FIG. 2 used for the partial response filter 16 in the transmitter 1 shown in FIG. The high-pass line comb filter 120 accompanies the detected keying signal, but the line-to-line change suppresses elements of the composite video signal that do not appear. The filter 12
0 will be further described herein in connection with FIGS. 9 and 10.

The analog signal, part of which is supplied as an input signal to the high-pass line comb filter 59, describes the binary coding of the keying signal, while the partial output signal from the high-pass line comb filter 59 is Describing the ternary encoding of the keying signal, the output signal is digitized by an ADC 65 to provide an input signal to a high-pass frame comb filter 72. Since the valid data frame combines two data frames of the same digital sample with the same amplification and opposite poles, the digitized signal provided as an output signal from the high-pass frame comb filter 72 is: Describes the ternary encoding of the keying signal in the alternative data frame of the valid data frame. Intervention of Invalid Data Frames In the alternative data frame, the digitized signal provided as output signal from the high-pass frame comb filter 72 is effectively five levels, but the symbol decision based on the invalid data frame is not important. .

The analog signal supplied as an input signal to a portion of the ADC 106 may be converted into a digital signal supplied to the high-pass frame comb filter 72 as an input signal in accordance with the description of the binary encoding of the keying signal. Describes the binary encoding of the keying signal. The digital response from the high-pass frame comb filter 72, supplied as an input signal to the high-pass line comb filter 120, describes the binary encoding of the keying signal in the alternative data frame of the valid data frame, The subtractor 73 differentially combines two data frames having the same digital samples with the same amplification and opposite polarities.

In the invalid data frame, the subtractor 73
Sometimes the amplification is the same and the poles are reversed, but at other times the amplification and the poles are all the same (this same pole may be the anode or the cathode) and there are two such digital samples. Since the data frames are differentially coupled, in such an intervening alternative data frame of an invalid data frame, the digital response from the high-pass line comb filter 72 provided as an input signal to the high-pass frame comb filter 120 is Is, in effect, ternary.

During such an invalid alternative data frame, the digital response from the high pass line comb filter 120 is effectively five levels, but the symbol decision based on the invalid data frame is not important. During the valid alternate data frame, the digital signal provided as an input signal to the high-pass line comb filter 120 may be a digital signal from the high-pass line comb filter 120 according to the description of the binary encoding of the keying signal. The response describes the ternary encoding of the keying signal.

Therefore, the high-pass line comb filter 1
The symbol decision circuit 75, which receives the twenty digital responses as input signals, has three comparator regions centered at -1, 0, +1 respectively. Symbol determination circuit 75
Includes an absolute value circuit 751 that generates a rectified digital response to the output signal from the high pass line comb filter 120. The rectified digital response from the absolute value circuit 751 describes the binary encoding of the keying signal and is provided to a threshold detector 752. The threshold detector 752 is one form of a symbol determination circuit that is well known in the digital communication field for performing a symbol determination regarding a binary coding of a keying signal. The threshold detector 752 receives the symbol stream from the absolute value circuit 751 and determines whether this symbol is 0 or 1. The threshold detector 752 typically includes a digital comparator arranged to operate as a threshold detector, and the threshold determination result indicates that the symbol is 1 depending on whether a threshold digital value is exceeded. Or 0 to control the decision.

The threshold detector 752 is preferably configured so that the threshold digital value for threshold determination is automatically adjusted according to the strength of the symbol. In such a case, the threshold detector 752 is coupled to a circuit for detecting the average peak level of the symbol stream provided by the absolute value circuit 751, or its average level, or all. There is a combined circuit for counting the digital value provided to the comparator from each detected level and defining a threshold for threshold detection. The detection nodes for determining the symbol decision threshold preferably include a quadrature phase
This is selectively performed during the vertical blanking period when substantially no energy is provided to the signal detected by the synchronous image detector 47 .

The symbol flow from the symbol determination circuit 75 is supplied as an input signal to a rate buffer 77. The rate buffer 77 outputs a luminance signal in which a keying signal is not erased by a data frame count and a frame-to-frame change does not appear. Elements are erased,
Input samples are received only from such alternate frames.

The digital samples are supplied to the rate buffer 77 at the symbol rate, and the error correction decoder 78
Is output from the rate buffer 77 at a 1/2 symbol rate. The decoder 78 receives the result of the decision by the symbol decision circuit 75 into the serial bit digital input data and corrects errors in the data to provide corrected serial bit digital data. Is output data of the digital signal receiver 37, and corresponds to serial bit digital data of the source 13 shown in FIG.

Designed to be used with a transmitter 1 that uses a modified Reed-Solomon code that operates on columns of data that lie on horizontal scan lines, rather than on data lines that appear along horizontal scan lines. In a preferred embodiment of the digital signal receiver 37, the rate buffer 77 operates as a deinterleaver for an error correction decoder 78. The write address generator for the rate buffer 77 is not shown in FIG. The read address generator includes a data row counter 71 for supplying a data row count and a symbol counter 52 for supplying a symbol count. At this time, each count is stored in the RAM (s) in the rate buffer 77, respectively. Provided for row addressing and column addressing.

FIG. 6 is a modification of the digital signal receiver 37 shown in FIG. 5, and also a digital signal receiver designed to be used with the transmitter 1 using the partial response filter 160 shown in FIG. Machine 38 is shown. When viewed in comparison with the digital signal receiver 37, the digital signal receiver 38 includes a high-pass frame comb filter 72.
And the order of serial connection of the high-pass line comb filter 120 and the high-pass line comb filter 120 is reversed.

FIG. 7 is a modification of the digital signal receiver 37 shown in FIG. 5, and shows the partial response filter 1 shown in FIG.
Shown is a digital signal receiver 39 designed to be used with the transmitter 1 using H.66. In the digital signal receiver 39, the other high-pass line comb filter 1 is placed next to the high-pass line comb filter 120.
30 comes. Such a serial connection of high-pass line comb filters 120 and 130 uses a digital delay line followed by 0, 1-H and 2-H delay periods to provide the input signal to the weighted addition network. Corresponding to
From there, to develop the filter response (-0.2
5): Weights are added at a ratio of 0.5: (− 0.25).

The partial response filter in the transmitter is shown in FIG.
When the digital signal receiver is of the same type as or equivalent to 165 shown in FIG. 7, and the digital signal receiver uses a three-scan line high-pass line comb filter as shown in FIG. When included, the digital response of the high-pass line comb filter 72 between valid data frames is essentially five levels rather than ternary with respect to describing the PSK signal. Therefore, the symbol decision circuit 7 shown in FIG. 5 or FIG. 6 having three comparator regions centered at -1, 0 and +1
5 is replaced by a symbol decision circuit 76 having five comparator regions centered at -2, -1, 0 + 1, and +2 shown in FIG.

The symbol determination circuit 76 includes an absolute value circuit 761 that generates a rectified digital response to the output signal from the high-pass frame comb filter 72. The rectified digital response of the absolute value circuit 761 describes a ternary encoding of the keying signal superimposed on the DC voltage pedestal rather than a binary encoding of the keying signal, and the rectified digital response is binary. It is supplied to a heavy threshold detector 762. The double threshold detector 762 receives the symbol stream from the magnitude circuit 761 and determines whether the symbol is 0, 1 or 2, where 2 is equal to 0.

The dual threshold detectors 762 are normally arranged to operate as respective single threshold detectors, but one comparator has twice the threshold of the other. Includes two digital comparators adapted to operate on the value digital value and some simple logic circuitry for determining the identity of the symbol depending on the threshold detection result. If no threshold digital value is exceeded, the logic indicates that the symbol is zero. If only the low threshold digital value is exceeded, the logic indicates that the symbol is one. If both the low threshold digital value and the high threshold digital value are exceeded, the logic circuit indicates that the symbol is two, which is identical to zero.

The double threshold detector 762 preferably adjusts the digital value provided to the comparator for determining the threshold for threshold detection automatically according to the strength of the symbol. It has become. In such a case, the double threshold detector 762 includes an absolute value circuit 76.
1 is coupled to a circuit for detecting the average level of the symbol stream provided by 1 or its average peak level, or the two levels. There is a circuit for counting the digital value supplied to the digital comparator from each detected level to determine a respective threshold for threshold detection. Detection section next to determine the symbol decision threshold is desirably a composite video signal is quadrature position
This is selectively performed during the vertical erase period when little energy is provided to the signal detected by the phase-locked video detector 47 .

FIG. 8 is a modification of the digital signal receiver 39 shown in FIG. 7, and a digital signal designed to be used with the transmitter 1 using the partial response filter 166 shown in FIG. The receiver 40 is shown. In the digital signal receiver 40, the high-pass frame comb filter 72 includes a high-pass line comb filter 1 connected in series like the digital signal receiver 39.
Instead of following before 20 and 130, it follows. The arrangement in which the high-pass frame comb filter 72 follows the high-pass line comb filter 120 but precedes the high-pass line comb filter 130 is another embodiment of the present invention.

The symbol determination circuit 75 in the digital signal receivers 37 and 38 shown in FIGS. 5 and 6 and the symbol determination circuit 76 in the digital signal receivers 39 and 40 shown in FIGS. A "hard" decision is made to provide a binary input signal to the decoder 78 in order to accomplish what data technicians refer to as "hard decision forward error correction." 76 may instead be a “soft decision” (soft-dec)
In order to perform what is called forward error correction of an input signal, a circuit for supplying an input signal having multiple levels to an appropriate decoder can be used.

FIG. 9 shows a high-pass line comb filter 1.
One possible form 121 of FIG. 20 is shown in detail.
An input terminal 122 for the filter 121 is connected to a non-inverting input connection of a differential input amplifier 123 having an output connection connected to an output terminal 124 of the filter 121. The inverting input connection of the differential input amplifier 123 receives the delayed response to the output signal from the multiplexer 126 from the output connection of the digital delay line 125, and the output signal of the multiplexer 126
Applied to 25 input connections.

The digital delay line 125 provides the same delay as the duration of one horizontal scan line. If such a "1-H" delay line is effectively analog, the delay line is typically comprised of a charge coupled device (CCD) shift register and the differential input amplifier 123
It is configured with a CCD shift register and its charge injection input circuit, and is included in the charge sensing output stage of the CCD shift register. The multiplexer 126 is conveniently configured in the same IC using field effect transistors operated as transmission gates.

The multiplexer 126 is connected to the decoder 6
The decoder 61 responds with a 1 to a data row count from the data row counter 71 which reaches a value associated with the last row of data in one data frame, Responds with 0 to all other values of the row count. In response to the output signal 1 of the decoder 61, the multiplexer 126 selects an analog zero for its output response. In response to the output signal 0 of the decoder 61, the multiplexer 126 outputs 1-H
The detected BPSK signal supplied to the input terminal 122 is selected for application to the input connection of the delay line 125.

FIG. 10 shows another form 127 which can be taken by the high-pass line comb filter 120 in detail.
This is an alternative to the configuration shown in FIG. 9 and does not include components 125 and 126. Multiplexer 1
28 is connected to the differential input amplifier 123 shown in FIG.
To the inverted input connection of The multiplexer 1
28 receives a control signal from a decoder 62, which responds with a 1 to a data row count from a data row counter 71 which is reset with a value associated with the last row of data in one data frame. And respond with 0 for all other values of the data row count.

In response to the output signal 1 of the decoder 61, the multiplexer 128 selects an analog zero for the output response. In response to the output signal of the decoder 61 being zero, the multiplexer 128 outputs 1-
An output signal is selected from the H digital delay line 129.
The output signal from the 1-H digital delay line 129 is a delay response to the signal provided to the input terminal 122 of the filter 120, the delay being the same as the duration of one horizontal scan line.

FIG. 11 shows in detail one possible form of the serial connection of the high-pass line comb filters 120 and 130. High-pass line comb filter 1
Reference numeral 21 is the same as that shown in FIG. The high-pass line comb filter 131 shown in FIG. 11 is a component 122 to 126 of the high-pass line comb filter 121.
And the components are similarly connected within the range of each filter.

FIG. 12 shows another example in which the high-pass line comb filters 120 and 130 can be connected in series. High-pass line comb filter 12
7 is the same as that shown in FIG. The high-pass line comb filter 137 shown in FIG.
9 and are similarly connected within each filter.

FIG. 13 shows the rate buffer 2 shown in FIG.
0 illustrates one possible form when used as an interleaver for the modified Reed-Solomon encoding supplied from the error correction coder 14. The data frame pair counter 80 inputs the carry-out (CO) signal supplied from the data frame counter 23 to its count input (C
I) Receive as a signal. The data frame pair counter 80 controls alternate writing and reading of two data frame storage RAMs 81 and 82 which are operated as a deinterleaver for error correction coding.

The RAMs 81 and 82 are written from the error correction coder 14 at a 1 / 2PSK ratio during the alternate frame pair period, and address scanning is performed by columns.
It is performed by symbols following the columns. RAM81
And 82 are read into the frame store memory 21 at the PSK ratio during each frame-period following the frame-period in which they were written, and address scanning is performed by rows and by symbols according to the rows. A "symbol" according to the rows referred to herein is, from a code perspective, a PSK symbol or bit rather than a 2N bit symbol associated with a modified Reed-Solomon code.

The address multiplexer 83 receives the data row count from the data row counter 24 and the symbol / row count from the symbol (eg, line-based symbol) counter 25 as read addressing. The address multiplexer 83 receives the data column count from the data column counter 84 and the symbol / column count from the column-based symbol counter 85 as write addressing. The zero-crossing detector 32 provides a triggered pulse at a PSK rate to a triggered flip-flop 86, which outputs an alternate transition of its output signal to a symbol counter 85 which follows the column. Count input by PSK ratio (C
Perform the function of a frequency separator to supply as I).

The decoder 87 outputs the maximum count (525 when processing the symbol count according to the column starting from 0).
) And provides 1 to the data string counter 84 as a count input (CI) signal. The output signal of the decoder 87 is a 2-input OR
Provided as a first input signal to a gate 88, the OR gate 88 resets a 1 to a column-based symbol counter 85 in response to a 1 from the decoder 87 to reset the symbol / column count to its initial value. Provide as a signal.

The second input signal supplied to the OR gate 88 and the reset signal supplied to the data string counter 84 are provided by an output response from a 3-input AND gate 89, and the output response is 1 At this time, this response is reset with the respective initial values of the symbol / column count and the data column count. Decoder 260 provides a logical one as the first input of AND gate 89 when the data row count indicates the arrival of the last row of the data frame.

If not, the decoder 260
Outputs a logical 0 as its output signal to the AND gate 89.
To supply. (If the partial response filter 160 is used for the transmitter 1 and the last row decoder 27 is designed to provide a logical one when the data row count indicates the arrival of the last row of the data frame, 4
Can be the decoder 27 shown in FIG. The output signal from the last symbol of the data row decoder 33 and the modulo 2 data frame count from the data frame counter 23 are applied to the AND gate 89 as the remaining two of the three input signals of the gate 89. You. The output response of the AND gate 89 is such that when any one selected in the RAMs 81 and 82 is read out to the frame storage memory 21 for each data row, the last symbol of the last data row is an odd number immediately before reaching an even frame. It is 1 only when a frame is reached.

If the modulo 2 data frame pair count from data frame pair counter 80 is one, then
The address multiplexer 83 selects the read addressing and sends it to the RAM 81, and selects the write addressing and sends it to the RAM 82. The modulo 2 data frame to count 1 from the data frame to counter 80 allows the RAM 81 to be read into the frame storage memory 21 for each data row, and the 0's complement of the count 1 indicates that the RAM 82 has an error correction code for each data column. 14
To be written from.

If the modulo 2 data frame pair count from data frame pair counter 80 is 0, then
The address multiplexer 83 selects the read addressing and sends it to the RAM 82, and selects the write addressing and sends it to the RAM 81. The modulo 2 data frame-to-count 0 from data frame-to-counter 80 allows the RAM 82 to be read into the frame storage memory 21 for each data row and the complement 0 of the count 0.
Allows the RAM 81 to be written from the error correction coder 14 for each data string.

FIG. 14 shows one possible form when the rate buffer 77 shown in FIGS. 5 to 8 is used as a deinterleaver for the modified Reed-Solomon coding supplied from the symbol decision circuit 75 or 76. ing. The data frame pair counter 90 receives the carry-out (CO) signal supplied from the data frame counter 70 as its count input (CI) signal. The data frame pair counter 90 controls the alternate writing and reading of the two data frame storage RAMs 91 and 92 operated as a deinterleaver for error correction coding.

The RAMs 91 and 92 are RAMs 9
Data for writing 1 and 92 is written only during alternate even frames supplied from the symbol decision circuit 75 or 76 in PSK ratio, and address scanning is performed by rows and by symbols according to the rows. A "symbol" according to the lines referred to herein is not a 2N bit symbol associated with a modified Reed-Solomon code from a code point of view, but a PSK symbol or bit. Each of the RAMs 81 and 82 is read into the frame store memory 21 at a 1/2 PSK ratio during the alternate frame pair period, and address scanning is performed by columns and by symbols according to columns.

The address multiplexer 93 receives the data row count from the data row counter 71 and the symbol / row count from the symbol (eg, symbol according to row) counter 52 as write addressing. The address multiplexer 93 receives the data column count from the data column counter 94 and the symbol / column count from the symbol counter 95 according to the column as read addressing. The zero-crossing detector 104 provides a triggered pulse at a PSK rate to a triggered flip-flop 96, which outputs an alternate transition of its output signal at a symbol counter 95 that follows a column at a 1/2 PSK rate.
Performs the function of a frequency separator to provide as a count input (CI) to the input.

The decoder 97 has a maximum count (525 assuming that the symbol count according to the column starts from 0).
) And provides 1 to the data string counter 94 as a count input (CI). The output signal of the decoder 97 is supplied as a first input signal to a 2-input OR gate 98, and the OR gate 9
8 responds to 1 from the decoder 97 to provide 1 as a reset signal to the column-based symbol counter 95 for resetting the symbol / column count to its initial value.

The second input signal supplied to the OR gate 98 and the reset signal supplied to the data string counter 94 are provided by an output response from a 3-input AND gate 99, and the output response is 1 At this time, this response is reset with the respective initial values of the symbol / column count and the data column count. The decoder 61 provides a logic one as a first input of the AND gate 99 when the data row count indicates that it is reaching the last row of a data frame.

Otherwise, the decoder 61 supplies a logical 0 to the AND gate 99 as an output signal. The output signal from the last symbol of the data row decoder 55 and the modulo 2 data frame count from the data frame counter 70 are applied to the AND gate 98 as the remaining two of the three input signals of the gate 98. The output response of the AND gate 98 is such that when one of the selected ones of the RAMs 91 and 92 is written from the symbol decision circuit 75 or 76 for each data row, the final data row before reaching the even frame is reached. 1 only when the last symbol reaches an odd frame
It is.

If the modulo 2 data frame pair count from data frame pair counter 90 is one, then
The address multiplexer 93 selects the read addressing and sends it to the RAM 91, and selects the write addressing and sends it to the RAM 92. The modulo 2 data frame pair count 1 from the data frame pair counter 90 allows the RAM 91 to be read into the error correction decoder 78 for each data column. The two-input AND gate 101 provides a one's complement of the data frame count and a zero of the data frame count from the counters 70 and 90.
And selectively supplies 1 to the RAM 92 as a write enable signal. This write enable signal enables the RAM 92 to be written from the symbol determination circuit 75 or 76 for each data row.

If the modulo 2 data frame pair count from data frame pair counter 90 is one, then
The address multiplexer 93 selects the read addressing and sends it to the RAM 92, and selects the write addressing and sends it to the RAM 91. The modulo 2 data frame pair count 0 from the data frame pair counter 90 allows the RAM 92 to be read into the error correction decoder 78 by data column. The 2-input AND gate 102 is responsive to the one's complement 0 of the data frame count and the data frame count 1 from the counter 90 to selectively supply 1 to the RAM 91 as a write enable signal. This write enable signal enables the RAM 91 to be written from the symbol determination circuit 75 or 76 for each data row.

When the substitute frame of the invalid signal generated from the frame comb filtering, which is a pair of frames, is removed, the rate buffering constituted by the digital signal receivers 37 to 40 to fill the remaining gap is performed by the frame comb. It can occur before the symbol decision circuit after filtering. Rate buffering is desirably performed after symbol determination, after which the frame store memory may be a single bit stream rather than a multiple bit stream.

[0124] Rate buffering with deinterleaving prior to error correction decoding is desirable to eliminate the need to separate the frame storage memory and rate buffering. If rate buffering is performed separately from deinterleaving, if this is a dual-ported RAM with a read-only port provided by a shift register, the serial stage of said register is accessed via a read / write port. Rate buffering can be performed with only one frame storage memory, if it can be loaded horizontally, one row at a time, from a dedicated RAM portion.

[0125]

The data transmission structure described herein provides a single, suitably wideband data transmission channel. A variety of different services can be provided through such a single data transmission channel using various types of time division multiplexing structures. For example, data can be transmitted in packet units, and header information for indicating the nature of the data service provided in each successive packet and the originator of the data service is provided. Television broadcasters and cable broadcasters can be the originators of various data services. The packet heading identifying the caller in a two-way data transmission structure can be used to select an appropriate data return channel, such as a dedicated channel in a telephone line or cable broadcasting system.

Having described embodiments of the present invention as proposed by the inventor, those of ordinary skill in the art of communication system, transmitter and receiver design will be familiar with the foregoing disclosure. Would. Thus, many alternative embodiments of the present invention could be designed. This fact must be kept in mind when interpreting the scope of the claims according to this specification.

[Brief description of the drawings]

FIG. 1 is an overall schematic diagram for a television transmitter for transmitting a television signal with a digital signal hidden therein, as described by JI-AN YANG.

FIG. 2 is a schematic diagram for a partial response filter, as described by JI-AN YANG, in which one of the two may be used in the television transmitter shown in FIG. 1;

FIG. 3 is a schematic diagram for a partial response filter, as described by JI-AN YANG, in which one of the two may be used in the television transmitter shown in FIG. 1;

FIG. 4 is a schematic diagram detailing a portion of the television transmitter shown in FIG. 1 used to digitally filter digital data to generate a phase shift key signal that modulates a suppressed, quadrature video carrier. is there.

FIG. 5 is a schematic diagram for each digital signal receiver embodying the present invention for receiving a hidden digital signal and extracting the hidden digital signal.

FIG. 6 is a schematic diagram for each digital signal receiver embodying the present invention for receiving a hidden digital television signal and extracting the hidden digital signal.

FIG. 7 is a schematic diagram for each digital signal receiver embodying the present invention for receiving a hidden digital television signal and extracting the hidden digital signal.

FIG. 8 is a schematic diagram for each digital signal receiver embodying the present invention for receiving a hidden television signal and extracting the hidden digital signal.

FIG. 9 is a schematic diagram illustrating in detail one of various possible forms of line-comb filtering in any one of the digital signal receivers of FIGS. 5 and 6;

FIG. 10 is a schematic diagram illustrating in detail one of various possible forms of line-comb filtering in any one of the digital signal receivers of FIGS. 5 and 6;

FIG. 11 is a schematic diagram illustrating in detail one of various possible forms of line comb filtering in any one of the digital signal receivers of FIGS. 7 and 8;

FIG. 12 is a schematic diagram illustrating in detail one of various forms that line comb filtering can take in any one of the digital signal receivers of FIGS. 7 and 8;

FIG. 13 is a schematic diagram for a rate buffer operated as a deinterleaver, which may be used in the portion of the television transmitter of FIG. 1 shown in FIG. 4, as described by JI-AN YANG.

FIG. 14 is a schematic diagram for a rate buffer operated as a deinterleaver, such as a digital signal receiver described by JI-AN YANG, that can be used in the digital signal receiver of FIGS.

[Explanation of symbols]

 37 Digital Signal Receiver 43 Tuner 44 Intermediate Frequency Filter 45 Intermediate Frequency Amplifier 46 In-Phase Synchronous Video Detector 47 Quadrature Phase Synchronous Video Detector 48 Oscillator 49 Shift Network 50 Horizontal Synchronous Separator 51 Vertical Synchronous Separator 52 Symbol Counter 55 decoder 56 AFPC detector 57 control delay line 58 matched filter 67 pulse phase discriminator 68 threshold detector 70 frame counter 71 data row counter 72 high-pass frame comb filter 74 digital frame storage 75 symbol decision circuit 751 absolute Value circuit 752 threshold detector 77 rate buffer 78 decoder 103 symbol counter 104 zero-crossing detector 105 voltage-controlled oscillator 106 ADC 107 low-pass filter 108 sub-sampler 120 high-pass line comb Filter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-76593 (JP, A) JP-A-5-260105 (JP, A) JP-A-60-153243 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 5/455 H04N 7/08

Claims (50)

(57) [Claims] 1. A system for combining and transmitting a video carrier amplitude-modulated by a composite video signal and a suppressed carrier amplitude-modulated by a binary phase shift keying signal so as to be in quadrature. A digital signal receiver for use with a system for transmitting digital information via a binary phase shift keying signal, the system comprising a residual component of the composite video signal from the suppressed carrier transmitted in combination with the video carrier by the system. A detector for detecting and outputting the binary phase shift keying signal; an analog-to-digital converter for receiving the detector output and digitizing the supplied detector output; Supplied with the detected detector output,
A digital comb filter for removing a residual component of the composite video signal from the advanced phase shift keying signal. 2. The digital receiver according to claim 1, wherein said digital comb filter is a high-pass digital frame comb filter. 3. An analog-to-digital converter according to claim 2, wherein said analog-to-digital converter is of an oversampling type.
Digital receiver as described. 4. The digital receiver according to claim 1, wherein said digital comb filter is a high-pass digital line comb filter. 5. The analog-to-digital converter according to claim 4, wherein the analog-to-digital converter is of an oversampling type.
Digital receiver as described. 6. The digital receiver according to claim 1, wherein said digital comb filter is a high-pass digital frame comb filter following a cascade connection of a high-pass digital line comb filter. 7. The analog-to-digital converter according to claim 6, wherein the analog-to-digital converter is of an oversampling type.
Digital receiver as described. 8. A symbol determining circuit for receiving a response signal from the high-pass digital line comb filter, determining a matching state of each digital symbol, and generating a bit serial digital response signal. Item 7. A digital receiver according to item 6. Wherein said digital comb filter, digital receiver of claim 1, wherein the high pass digital frame comb filter is high pass digital line-comb filter following the cascade. 10. The analog-to-digital converter according to claim 9, wherein the analog-to-digital converter is of an oversampling type.
Digital receiver as described. 11. A symbol determination circuit for receiving a response signal from the high-pass digital line comb filter, determining a matching state of each digital symbol, and generating a bit serial digital response signal. Item 10. A digital receiver according to item 9. 12. A digital system for use with a system that combines and transmits a video carrier amplitude-modulated by a composite video signal and a suppressed carrier amplitude-modulated by a binary phase shift keying signal so that they are in quadrature. A signal receiver for detecting and outputting the binary phase shift keying signal including a residual component of the composite video signal from the suppressed carrier transmitted by being combined with the video carrier by the system; and An output signal of a detector is supplied, an analog-to-digital converter for oversampling the output signal and digitizing the sampled data, and receiving the oversampled and digitized signal, A digital low-pass filter for removing high-mid frequency components of the Digital low-pass filter output signal, a sub-sampler for generating an output signal of a sub-sampler that samples the output signal of the detector, and receiving the output signal of the sub-sampler A cascade connection of a high-pass digital line comb filter and a high-pass digital frame comb filter for removing the residual component of the composite video signal, and determining a matching state of each digital symbol by an output signal of the cascade connection; A digital receiver comprising: a symbol determination circuit that outputs a bit serial digital signal. 13. The high-pass digital frame comb filter is located at the cascade in front of the high-pass digital line comb filter to receive the sub-sampler response signal. An input connection of a high-pass digital frame comb filter; and an output of the high-pass digital frame comb filter for supplying a response signal of the high-pass digital frame comb filter as an input signal to the high-pass digital line comb filter. A connection for delaying a response signal of the sub-sampler received from an input connection of the high-pass digital frame comb filter by a time interval corresponding to a connection time of frame scanning of the composite video signal; A frame digital delay line, and the one-frame digital delay A second input connection connected substantially no delay from the first and the input connection, the high frequency input connection of pass digital frame comb filter for receiving the delayed response signal from said first
And a first digital subtractor having an output connection for supplying a differential response signal to the signal at the second input connection to an output connection of the high-pass digital frame comb filter. The digital receiver according to claim 12, wherein 14. The one-frame digital delay line comprises:
14. A random access memory (RAM) operated in a read-write repetition mode.
Digital receiver as described. 15. The high-pass digital line comb filter, comprising: an input connection for the high-pass digital line comb filter for receiving a response signal of the high-pass digital frame comb filter; An output connection of the high-pass digital line comb filter for providing a response signal of the filter; and a response signal of the high-pass digital frame comb filter received from an input connection of the high-pass digital line comb filter. A 1-H digital delay line for delaying the composite video signal by a time interval corresponding to the duration of a horizontal scan line of the composite video signal; One input connection part and an input connection of the high-pass digital line comb filter And a second input connection connected without substantial delay to supply a differential response signal to the signals at the first and second input connections to an output connection of the high-pass digital line comb filter. 14. A digital receiver according to claim 13, comprising: a second digital subtractor having an output connection of: 16. An absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal, the symbol determination circuit comprising: An input connection for receiving the rectified response signal from an output connection of a value circuit; and a first state when the rectified response exceeds a threshold level, wherein the rectified response signal is at a threshold level. 16. The digital signal receiver according to claim 15, further comprising a threshold detector having an output connection for providing a bit of the digital signal in a second state when not exceeded. 17. The high-pass digital line comb filter, comprising: an input connection for the high-pass digital line comb filter for receiving a response signal of the high-pass digital frame comb filter; An output connection of the high-pass digital line comb filter for providing a response signal of the filter; and a response signal of the high-pass digital frame comb filter received from an input connection of the high-pass digital line comb filter. A first 1-H digital delay line for delaying the composite video signal by a time interval corresponding to a duration of a horizontal scanning line of the composite video signal; and receiving a response signal delayed from the first 1-H digital delay line. A first input connection for connecting the high-pass digital line comb filter; A second digital having a second input connection connected from the input connection without substantial delay, and an output connection for providing a differential response signal to the signals at the first and second input connections. A subtractor, and the differential response signal of the second digital subtractor is given a duration of 1
-H for delaying by a time interval corresponding to -H
-H digital delay line, a first input connection for receiving a delayed response signal from the second 1-H digital delay line, and no substantial delay from the output connection of the second digital subtractor. A connected second input connection, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. The digital receiver according to claim 13, further comprising: a third digital subtractor having: 18. An absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal, the symbol determination circuit comprising: An input connection for receiving the rectified response signal from an output connection of the value circuit; and a second threshold level wherein the rectified response signal exceeds a first threshold level and is higher than the first threshold level. Is not in the first state,
An output connection for providing a bit of the digital signal in a second state when the rectified response signal does not exceed the first threshold level or exceeds all of the first and second threshold levels; The digital signal receiver according to claim 17, further comprising a double threshold detector having a first threshold and a second threshold. 19. The high-pass digital frame comb filter, following the high-pass digital line comb filter in a cascade connection, for receiving a response signal from the high-pass digital line comb filter. An input connection of a high-pass digital frame comb filter; an output connection of the high-pass digital frame comb filter for providing a response signal of the combined comb filter; A one-frame digital delay line for delaying a response signal from the high-pass digital line comb filter received from an input connection by a time interval corresponding to a duration of frame scanning of the composite video signal; Delayed response from digital delay line A first input connection for receiving a signal; a second input connection connected without substantial delay from an input connection of the high-pass digital frame comb filter;
And a first digital subtractor having an output connection for supplying a differential response signal to the signal at the second input connection to an output connection of the high-pass digital frame comb filter. The digital receiver according to claim 12, wherein 20. The one-frame digital delay line comprises:
20. The digital receiver according to claim 19, wherein the digital receiver is a random access memory operated in a read-write repetition mode. 21. The high-pass digital line comb filter, comprising: an input connection of the high-pass digital line comb filter for receiving a response signal of the sub-sampler; and the high-pass digital frame comb filter. An output connection of the high-pass digital line comb filter to an input connection of the high-pass digital line comb filter; and the binary phase bias including a residual component of the composite video signal received from the input connection of the high-pass digital line comb filter. A 1-H digital delay line for delaying the shift keying signal by a time interval corresponding to the duration of a horizontal scan line of the composite video signal; and receiving a delayed response signal from the 1-H digital delay line. A first input connection for connecting the input signal to the input connection of the high-pass digital line comb filter. A second input connection connected to the first and second input connections, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. 20. The digital receiver of claim 19, comprising: a second digital subtractor having: 22. An absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for providing a rectified response signal, the symbol determination circuit comprising: An input connection for receiving the rectified response signal from an output connection of the value circuit; and a first state when the rectified response signal exceeds a threshold level, wherein the rectified response is at a threshold level. 22. A digital signal receiver according to claim 21, comprising: a threshold detector having an output connection for providing a bit of the digital signal that is in a second state when not exceeded. 23. The high-pass digital line comb filter, comprising: an input connection of the high-pass digital line comb filter for receiving a response signal of the sub-sampler; and the high-pass digital frame comb filter. An output connection of the high-pass digital line comb filter to an input connection of the high-pass digital line comb filter; and the binary phase bias including a residual component of the composite video signal received from the input connection of the high-pass digital line comb filter. A first 1-H digital delay line for delaying the transfer keying signal by a time interval corresponding to a duration 1-H of the horizontal scanning line of the composite video signal; and a delay line from the first 1- H digital delay line. A first input connection for receiving the response signal, and an input connection for the high-pass digital line comb filter. A second digital subtractor having a second input connection connected without substantial delay, and an output connection for providing a differential response signal to the signals at the first and second input connections. The differential response signal of the second digital subtractor has a duration of 1
-H for delaying by a time interval corresponding to -H
-H digital delay line, a first input connection for receiving a delayed response signal from the second 1-H digital delay line, and a substantial delay from an output connection of the second digital subtractor. A second input connection connected without connection, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. 20. The digital receiver according to claim 19, further comprising: a third digital subtractor having: 24. An absolute value circuit having an input connection for receiving the combined comb filter response signal and an output connection for providing a rectified response signal, the symbol determination circuit comprising: An input connection for receiving the rectified response signal from an output connection of the circuit; and a second threshold level, wherein the rectified response signal exceeds a first threshold level and is higher than the first threshold level. If not exceeded, it is in the first state,
An output for providing a bit of the digital signal in a second state when the rectified response signal does not exceed the first threshold level or exceeds all of the first and second threshold levels. The digital signal receiver according to claim 23, further comprising: a double threshold detector having a connection portion. 25. A digital system for use with a system for combining and transmitting a video carrier amplitude-modulated by a composite video signal and a suppressed carrier amplitude-modulated by a binary phase shift keying signal in quadrature. In the signal receiver, a high-frequency signal including the amplitude-modulated video carrier and a suppressed carrier amplitude-modulated by the binary phase shift keying signal is supplied, and the supplied high-frequency signal is converted into an intermediate frequency signal. A tuner that receives the intermediate frequency signal, amplifies the supplied intermediate frequency signal and outputs the amplified intermediate frequency signal, and a frequency and phase control function. A first control oscillation circuit that outputs a frequency signal obtained by delaying the frequency of the intermediate frequency by 90 °, and the amplified intermediate frequency signal is supplied, An in-phase video detector for detecting a composite video signal from the intermediate frequency signal using a predetermined frequency signal; and a frequency signal supplied with the amplified intermediate frequency signal and delayed by 90 degrees from the predetermined frequency. A quadrature-phase image detector for detecting a binary phase shift keying signal; a horizontal sync separator for separating a horizontal sync pulse from a composite video signal detected by the in-phase video detector; Controlled by a horizontal sync pulse,
A second control oscillator for generating a clock signal at a frequency and phase that is a multiple of the symbol rate for the advanced phase shift keying signal; and an output signal of the quadrature image detector, the output signal being supplied to the second An analog-to-digital converter that samples a clock signal supplied from a control oscillator and outputs a digital signal; and the digital signal is supplied from the analog-to-digital converter, and the symbol rate for the binary phase shift keying signal Means for outputting a digitized quadrature image detector response signal; and receiving a quadrature image detector response signal digitized by the symbol rate for the binary phase shift keying signal; Digital comb filter for removing residual components of composite video signals Receives the output signal from the digital comb filter, digital receiver, characterized in that it comprises, a symbol decision circuit for determining a transmitted symbol by the binary phase shift keying signal. 26. A symbol clock according to the clock signal.
Click oscillation, the analog - digital converter oversampling the response signal of the detector, to digitize each <br/> sample resulting in a predetermined number of bits of resolution
Made in frequency required, means for supplying the response signal of the digitized quadrature-phase video detector at the symbol rate for the binary phase shift keying signal, said analog - oversampled from the digital converter A digital low-pass filter for receiving a digital response signal of the detector and generating a digital low-pass filter response signal, and decimating the digital low-pass filter response signal .
And a sub-sampler for decimation to generate a response signal of the digitized quadrature image detector at the symbol rate to the binary phase shift keying signal. Item 29. A digital receiver according to item 25. 27. The digital receiver according to claim 25, wherein the digital comb filter comprises a cascade connection of a high-pass digital frame comb filter followed by a high-pass digital line comb filter. 28. The high-pass digital frame comb filter, comprising: an input connection of the high-pass digital frame comb filter for receiving a response signal of the sub-sampler; and the high-pass digital frame comb filter. The input signal of the high-pass digital frame comb filter for supplying the response signal as an input signal to the high-pass digital line comb filter, and the input signal of the high-pass digital frame comb filter. A one-frame digital delay line for delaying a response signal of the sub-sampler by a time interval corresponding to a duration of frame scanning of the composite video signal; and a delayed response signal from the one-frame digital delay line. A first input connection for receiving the high pass digital signal; A second input connection which is sustained substantially no delay from the input connection of the frame comb filter, the first
And a first digital subtractor having an output connection for supplying a differential response signal to the signal at the second input connection to an output connection of the high-pass digital frame comb filter. 28. The digital receiver according to claim 27, wherein 29. The high-pass digital line comb filter, comprising: an input connection of the high-pass digital line comb filter for receiving a response signal of the high-pass digital frame comb filter; An output connection of the high-pass digital line comb filter for providing a response signal of the filter; and a response signal of the high-pass digital frame comb filter received from an input connection of the high-pass digital line comb filter. A 1-H digital delay line for delaying the composite video signal by a time interval corresponding to the duration of a horizontal scan line of the composite video signal, and a second delay line for receiving a delayed response signal from the 1-H digital delay line. One input connection part and an input connection of the high-pass digital line comb filter And a second input connection connected without substantial delay to supply a differential response signal to the signals at the first and second input connections to an output connection of the high-pass digital line comb filter. 29. A digital receiver according to claim 28, comprising: a second digital subtractor having an output connection of: 30. An absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal, the symbol determination circuit comprising: An input connection for receiving the rectified response signal from an output connection of the value circuit; and a first state when the rectified response signal exceeds a threshold level, wherein the rectified response signal is at a threshold level. 30. A digital signal receiver as claimed in claim 29, comprising: a threshold detector having an output connection for providing a bit of the digital signal in a second state if not exceeded. 31. An output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver outputs a vertical synchronizing pulse from a composite video signal detected by the in-phase video detector. A vertical sync separator for separating the data, a data frame counter for counting the separated vertical sync pulses generated only in the initial field of the composite video signal frame to generate a data frame count, and an output connection of the symbol determination circuit. An input connection connected to receive the bit only when the data frame count modulo 2 has a predetermined one of two values upon receiving a bit from the unit, and At a rate and in a predetermined order, the output signal bits of the symbol decision circuit. Digital signal receiver according to claim 29, wherein further comprising a rate buffer and an output connection for supplying a. 32. A deinterleaver for supplying an output signal bit of the symbol determination circuit to an error correction decoder at a half symbol rate and in an order of a data string.
32. Digital signal receiver according to claim 31, operated as er). 33. The digital signal receiver counts the symbol clock oscillation to generate a row-wise symbol count, and in response to each of the separated horizontal sync pulses, a predetermined base count value for the symbol count. A symbol counter according to a row that resets the symbol count at each time; and a data counter is generated by counting each time the symbol counter according to the row is reset, and the data row counter is responsive to each of the separated vertical synchronization pulses. A data row counter for resetting the data row count with a predetermined base count value for the data frame count modulo 2 having the predetermined one of two values, and the symbol determination circuit only when output Is written specification between bit by individual time from the connection portion, for receiving both the symbol count in accordance with the data row count and row as the write addressing for the time of the individual, one also less included in the rate buffer The digital signal receiver according to claim 31, further comprising two random access memories. 34. The high-pass digital line comb filter, comprising: an input connection of the high-pass digital line comb filter for receiving a response signal of the high-pass digital frame comb filter; An output connection of the high-pass digital line comb filter for providing a response signal of the filter; and a response signal of the high-pass digital frame comb filter received from an input connection of the high-pass digital line comb filter. wherein the composite video signal a 1 1-H digital delay line for delaying a time interval corresponding to the duration of a horizontal scan line of a, receives a response signal delayed from said first 1 1-H digital delay line Input connection for inputting the signal to the input of the high-pass digital line comb filter. A second digital connection having a second input connection connected from the input connection without substantial delay, and an output connection for providing a differential response signal to the signals at the first and second input connections. A subtractor, and the differential response signal of the second digital subtractor is given a duration of 1
-H for delaying by a time interval corresponding to -H
-H digital delay line, a first input connection for receiving a delayed response signal from the second 1-H digital delay line, and no substantial delay from the output connection of the second digital subtractor. A connected second input connection, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. 29. The digital receiver according to claim 28, further comprising: a third digital subtractor having: 35. The symbol determination circuit comprising: an absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal; An input connection for receiving the rectified response signal from an output connection of the value circuit; and a second threshold level wherein the rectified response signal exceeds a first threshold level and is higher than the first threshold level. Is not in the first state,
An output for providing a bit of the digital signal in a second state when the rectified response signal does not exceed the first threshold level or exceeds all of the first and second threshold levels. 35. The digital signal receiver of claim 34, comprising: a dual threshold detector having a connection. 36. An output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver outputs a vertical synchronization pulse from a composite video signal detected by the in-phase video detector. A vertical sync separator for separating the data, a data frame counter for counting the separated vertical sync pulses generated only in the initial field of the composite video signal frame, and generating a data frame count, and an output connection of the symbol determination circuit. An input connection connected to receive the bit only when the data frame count modulo 2 has a predetermined one of two values, and only if so; At a rate and in a predetermined order, the output signal bits of the symbol decision circuit. Digital signal receiver according to claim 34, wherein further comprising a rate buffer and an output connection for supplying a. 37. The rate buffer is operated as a deinterleaver for supplying an output signal bit of the symbol determination circuit to an error correction decoder at a シ ン ボ ル symbol rate and in a data string unit order. The digital signal receiver according to claim 36, wherein: 38. The digital signal receiver counts the symbol clock oscillation to generate a row-wise symbol count, and in response to each of the separated horizontal sync pulses, a predetermined base count value for the symbol count. And a symbol counter according to a row that resets the symbol count at each time, counting each time the symbol count according to the row is reset to generate a data row count, and the data row count in response to each of the separated vertical synchronization pulses. A data row counter for resetting the data row count with a predetermined basic count value for the output of the symbol determination circuit when the data frame count modulo 2 has the predetermined one of two values, and only when so. Contact At least one random access included in the rate buffer, written by a bit from the continuation for a number of times, receiving both the data row count and the symbol count according to the row as write addressing during the time. 37. The digital signal receiver according to claim 36, further comprising: a memory. 39. The digital receiver according to claim 25, wherein the digital comb filter comprises a cascade connection in which a high-pass digital line comb filter is followed by a high-pass digital frame comb filter. 40. The high-pass digital frame comb filter, comprising: an input connection for the high-pass digital frame comb filter for receiving a response signal from the high-pass digital line comb filter; An output connection of the high-pass digital frame comb filter for providing a response signal of the comb filter; and an output connection from the high-pass digital line comb filter received from an input connection of the high-pass digital frame comb filter. A one-frame digital delay line for delaying the response signal by a time interval corresponding to a duration of frame scanning of the composite video signal; and a first for receiving the delayed response signal from the one-frame digital delay line. An input connection, and the high-pass digital frame A second input connection connected substantially no delay from the input connection of Mufiruta, the first
And a first digital subtractor having an output connection for supplying a differential response signal to the signal at the second input connection to an output connection of the high-pass digital frame comb filter. The digital receiver according to claim 39, wherein 41. The high-pass digital line comb filter, comprising: an input connection of the high-pass digital line comb filter for receiving a response signal of the sub-sampler; and the high-pass digital frame comb filter. An output connection of the high-pass digital line comb filter to an input connection of the high-pass digital line comb filter; and the binary phase bias including a residual component of the composite video signal received from the input connection of the high-pass digital line comb filter. A 1-H digital delay line for delaying the shift keying signal by a time interval corresponding to the duration of a horizontal scan line of the composite video signal; and receiving a delayed response signal from the 1-H digital delay line. A first input connection for inputting a signal and a substantial delay from an input connection of the high-pass digital line comb filter. A second input connection connected to the first and second input connections, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. 41. The digital receiver according to claim 40, further comprising: a second digital subtractor having: 42. An absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal, wherein the symbol determination circuit comprises: An input connection for receiving the rectified response signal from an output connection of the value circuit; and a first state when the rectified response signal exceeds a threshold level, wherein the rectified response is at a threshold level. 42. A digital signal receiver according to claim 41, comprising: a threshold detector having an output connection for providing a bit of the digital signal that is in a second state when not exceeded. 43. An output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver outputs a vertical synchronization pulse from a composite video signal detected by the in-phase video detector. A vertical sync separator for separating the data, a data frame counter for counting the separated vertical sync pulses generated only in the initial field of the composite video signal frame, and generating a data frame count, and an output connection of the symbol determination circuit. An input connection connected to receive the bit only when the data frame count modulo 2 has a predetermined one of two values, and only when receiving the bit from the unit; Output signal bits of the symbol decision circuit at symbol rate and in a predetermined order Digital signal receiver according to claim 41, wherein the further and a rate buffer and an output connection for supplying. 44. The rate buffer is operated as a deinterleaver for supplying an output signal bit of the symbol determination circuit to an error correction decoder at a シ ン ボ ル symbol rate and in a data string order. The digital signal receiver according to claim 43, wherein 45. The digital signal receiver counts the symbol clock oscillation to generate a row-wise symbol count, and in response to each of the separated horizontal sync pulses, a predetermined base count value for the symbol count. And a symbol counter according to a row that resets the symbol count at each time, counting each time the symbol count according to the row is reset to generate a data row count, and the data row count in response to each of the separated vertical synchronization pulses. A data row counter for resetting the data row count with a predetermined basic count value for the output of the symbol determination circuit when the data frame count modulo 2 has the predetermined one of two values, and only when so. Contact At least one random access included in the rate buffer, written by a bit from the continuation for a number of times, receiving both the data row count and the symbol count according to the row as write addressing during the time. The digital signal receiver according to claim 43, further comprising: a memory. 46. The high-pass digital line comb filter, comprising: an input connection for the high-pass digital line comb filter for receiving a response signal of the sub-sampler; and the high-pass digital frame comb filter. An output connection of the high-pass digital line comb filter to an input connection of the high-pass digital line comb filter; and the binary phase bias including a residual component of the composite video signal received from the input connection of the high-pass digital line comb filter. A first 1-H digital delay line for delaying the transfer keying signal by a time interval corresponding to a duration 1-H of the horizontal scanning line of the composite video signal; and a delay line from the first 1-H digital delay line. A first input connection for receiving the response signal, and an input connection of the high-pass digital line comb filter. A second digital subtractor having a second input connection maintained without substantial delay, and an output connection for providing a differential response signal to the signals at the first and second input connections; The differential response signal of the second digital subtractor is used for the duration 1
-H for delaying by a time interval corresponding to -H
-H digital delay line, a first input connection for receiving a delayed response signal from the second 1-H digital delay line, and substantially no delay from an output connection of the second digital subtractor. A connected second input connection, and an output connection for supplying a differential response signal to the signal at the first and second input connections to an output connection of the high-pass digital line comb filter. 41. The digital receiver according to claim 40, further comprising: a third digital subtractor having: 47. The symbol determination circuit, comprising: an absolute value circuit having an input connection for receiving a response signal of the combined comb filter and an output connection for supplying a rectified response signal; An input connection for receiving the rectified response signal from an output connection of the value circuit; and a second threshold level wherein the rectified response signal exceeds a first threshold level and is higher than the first threshold level. Is not in the first state,
An output for providing a bit of the digital signal in a second state when the rectified response signal does not exceed the first threshold level or exceeds all of the first and second threshold levels. 47. The digital signal receiver of claim 46, comprising: a dual threshold detector having a connection. 48. An output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver outputs a vertical synchronization pulse from a composite video signal detected by the in-phase video detector. A vertical sync separator for separating the data, a data frame counter for counting the separated vertical sync pulses generated only in the initial field of the composite video signal frame to generate a data frame count, and an output connection of the symbol determination circuit. An input connection connected to receive the bit only when the data frame count modulo 2 has a predetermined one of two values upon receiving a bit from the unit, and At a rate and in a predetermined order, the output signal bits of the symbol decision circuit. Digital signal receiver according to claim 46, wherein further comprising a rate buffer and an output connection for supplying a. 49. The rate buffer is operated as a deinterleaver for supplying an output signal bit of the symbol determination circuit to an error correction decoder at a half symbol rate and in an order of a data string. 49. The digital signal receiver according to claim 48, wherein 50. The digital signal receiver counts the symbol clock oscillation to generate a row-wise symbol count, and in response to each of the separated horizontal sync pulses, a predetermined base count value for the symbol count. A symbol counter according to the row that resets the symbol count, counting each time the symbol count according to the row is reset to generate a data row count, and responding to each of the separated vertical sync pulses. A data row counter for resetting the data row count with a predetermined basic count value for the count; and when the data frame count modulo 2 has the predetermined one of two values, and only when so, Out At least one random number included in the rate buffer, written by the bit from the power connection for a number of times, receiving both the data row count and the symbol count according to the row as write addressing during the time. 49. The digital signal receiver according to claim 48, further comprising: an access memory.