JPH10256383A - Semiconductor device and circuit constitution method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit constitution method for a semiconductor device of high performance in which a hardware is changed for each operation specification in optimum manner. SOLUTION: Using a control data flow graph S21 prepared from an operational describe, a data path circuit part 20A, corresponding to an initial circuit in higher order composition where a logical circuit is composed with the initial circuit as a nucleus, and a control circuit part 30 for controlling an operation of the data path circuit part 20A prepare a semiconductor device constituted with a reconfigurable circuit which can vary a circuit constitution. Based on circuit data as a result of the higher order composition, data path wire connection information as wire connection information of the data path circuit part 20A and control information for controlling the operation of the data path circuit part are generated, and the data path wire connection information and the control information is mapped on the reconfigurable circuit, and the data path circuit part 20A and the control circuit part 30 are circuit-constituted according to mapping information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as a system LSI used in the field of parallel processing and the like, and a circuit configuration method of a semiconductor device using a high-level synthesis technique.

[0002]

2. Description of the Related Art Conventionally, as a logic circuit design method,
2. Description of the Related Art A high-level synthesis technique for synthesizing a logic circuit from an operation description is known.

FIG. 3 is a functional block diagram showing an example of a conventional high-level synthesis technique disclosed in Japanese Patent Application Laid-Open No. 8-1011861.

[0004] In the figure, reference numeral 100 denotes an operation description graph in which operation specifications of hardware are described in an operation description language, and a control description graph creating means 200 creates a control description graph from the operation description graph 100. Further, the single flow extracting means 300 is provided with the control description graph creating means 2.
The control description graph created in 00 is classified according to control conditions, and a single flow including a subgraph or a closed loop is extracted.

[0005] An initial circuit input means 400 inputs an initial circuit. This initial circuit is not one corresponding to actual hardware but a virtual one. The high-level synthesis technique generates circuit data of a final logic circuit while editing (adding or deleting) the given initial circuit.

[0006] Thereafter, the scheduling means 500
The single flow extracted by the single flow extraction unit 300 is divided into execution steps, and the hardware allocation unit 6
00 assigns necessary hardware components to the initial circuit for each execution step divided by the scheduling means 500.

Then, the hardware sharing partial processing means 7
In the case of 00, among the assigned hardware components having the same function, components only used in different time zones are collected and shared, and the number of components is reduced. The finite state machine combining means 800 converts each step of the single flow allocated by the hardware allocating means 600 into a finite state machine 900, and converts the converted finite state machine into one.
Into two finite state machines.

As described above, in the above-described high-level synthesis technique, not a comprehensive search for a huge design space but a local partial region near an initial circuit is performed. Can be narrowed down to the vicinity of the initial circuit, so that not only can it be applied to a large-scale circuit, but also an optimal logic circuit closer to manual design can be designed.

[0009] The circuit data of the logic circuit obtained by synthesizing the logic circuit with the data path circuit obtained by the above-described high-level synthesis technique and further using the logic synthesis technique is represented by an FPGA (Field).
dProgrammable Gate Array)
Or a gate array. Note that this FPGA
Expresses circuit data by a method called a table lookup system in which a truth table of a logic circuit is tabulated and used.

After the logic circuit data is created in this way, a layout (automatic placement and routing) and a mask pattern are usually created to implement actual hardware.

[0011]

However, since a circuit realized by the above-described conventional logic circuit design method cannot dynamically change its circuit configuration, an operation description corresponding to each specific application program is required. Is not necessarily an optimal circuit configuration as a data path circuit for executing Therefore, an LSI having a sufficient performance cannot be realized.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a high-performance semiconductor device capable of optimally changing hardware for each operation specification and its circuit. It is to provide a configuration method.
It is another object of the present invention to provide a semiconductor device capable of reducing the circuit scale and a circuit configuration method thereof.

[0013]

In order to achieve the above object, a feature of a semiconductor device according to the first invention is that a data flow graph for each control condition is extracted from a control data flow graph created from an operation description. Then, scheduling is performed to divide this data flow graph into execution steps, and a data comprising a reconfigurable circuit corresponding to the initial circuit in high-level synthesis for synthesizing a logic circuit with the initial circuit as a core and capable of changing the circuit configuration. A semiconductor device having a path circuit unit, wherein data path connection information generated based on circuit data as a result of the high-level synthesis is mapped to the reconfigurable circuit, and the data path circuit is mapped in accordance with the data path connection information. The circuit configuration of the unit.

According to the first aspect, for example, when the semiconductor device is executed, the optimum data path connection information generated based on the circuit data as a result of the high-level synthesis is transferred to the reconfigurable device formed on the semiconductor device. By dynamically mapping to the circuit, an optimum data path circuit unit can be configured for each specific application program corresponding to the operation description.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the data path circuit section is arranged so as to correspond to a stage determined at the time of the scheduling.
A stage block is constituted by a register block, a bus unit, and an arithmetic unit block including a plurality of arithmetic units that can be executed simultaneously.

According to the second aspect of the present invention, the register block, the bus unit, and the operation unit block are formed in correspondence with the stage determined at the time of scheduling of the high-level synthesis. The simultaneous execution of arithmetic units can be maximized.

A third aspect of the present invention is a semiconductor device according to the second aspect, wherein an L-shaped bus is provided near the stage block, and the L-shaped bus forms a loop circuit of the stage block. It is in.

According to the third aspect, the intermediate operation result by the operation unit block can be fed back to the register block.

A semiconductor device according to a fourth aspect of the present invention is characterized in that, in the first to third aspects, the semiconductor device comprises a reconfigurable circuit capable of changing a circuit configuration and controls the operation of the data path circuit section. A control circuit unit is provided, wherein control information generated based on circuit data as a result of the high-level synthesis is mapped to the reconfigurable circuit, and the control circuit unit is configured according to the control information.

According to the fourth aspect, for example, when the semiconductor device is executed, the optimal control information generated based on the circuit data as a result of the high-level synthesis is transferred to the reconfigurable circuit formed on the semiconductor device. By dynamically mapping the data, the optimal control circuit for controlling the data path circuit can be appropriately configured.

The fifth aspect of the circuit configuration method of a semiconductor device according to the present invention is characterized in that a data flow graph for each control condition is extracted from a control data flow graph created from an operation description, and this data flow graph is executed. A data path circuit section corresponding to the initial circuit in high-level synthesis for synthesizing a logic circuit with an initial circuit as a nucleus, and a control circuit section for controlling the operation of the data path circuit section, A semiconductor device including a reconfigurable circuit capable of changing a circuit configuration is prepared, and based on circuit data as a result of the high-level synthesis, data path connection information that is connection information of the data path circuit unit and the data path. Control information for controlling the operation of the circuit unit, and the data path connection information and the control information are Mapped to down-configurable circuit is to the circuit constituting the data path circuit and the control circuit unit according to the mapping information.

According to the fifth aspect, the same effects as those of the first and fourth aspects are exhibited.

According to a sixth aspect of the present invention, there is provided a circuit configuration method for a semiconductor device according to the fifth aspect, wherein the data path circuit section includes a register block and a bus corresponding to the stage determined at the time of the scheduling. And a stage block composed of a plurality of operation units that can be executed simultaneously.

According to the sixth aspect, in the fifth aspect, an operation equivalent to that of the second aspect is exhibited.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a processing procedure diagram showing a circuit configuration method of a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a diagram for specifically explaining a part of the processing content in the present embodiment. FIG. 3 is a block diagram of a system LSI which is a semiconductor device of the present embodiment.

First, in FIG. 3, this system LSI
Reference numeral 10 denotes a reconfigurable LSI constituted by a reconfigurable circuit (dynamically programmable GA), which includes a data path circuit section 20, a control circuit section 30, a main bus 40, a processor, a DSP, and the like in the same LSI. The core unit 50 and the memory unit 60 are simultaneously integrated. The data path circuit section 20 includes a register block 21
A bus 21c and a computing unit block 21d are formed between a and 21b.

These integrated circuits are fixed circuit parts that cannot be changed. Data path allocation information and data generated by using a high-level synthesis technique described later are stored in storage elements scattered at connection points in the circuit. The path control information is written, a switch group directly connected to the storage element is operated to realize the connection, and the circuit configuration is changed. As the storage element, a memory element using a ferroelectric or a memory element such as a floating gate MOS may be used. The control circuit unit 30 has, for example, a PLA or FPGA configuration.

Next, a circuit configuration method according to the present embodiment will be described with reference to FIGS.

First, the operation specifications of the hardware for achieving the optimum performance for each specific application program are as follows:
It is described in the action description language (step S in FIG. 1).
10). This operation description language uses a software language “C”, and as shown at T10 in FIG. 2, sum (+) or product (*) operation is performed according to the condition value of the control variable p, and S = b + c Or it is shown by S = b * c.

The hardware information on the LSI for realizing this operation description is described as initial circuit data 20A. The above-described conventional initial circuit data is virtual and is added or deleted to obtain final circuit data. In the present embodiment, however, the initial circuit data 20A is a data path of an actual fixed circuit. One of the features is that the circuit section 20 is specified.

Based on this operation description, the initial circuit data 2
High-level synthesis for generating logic circuit data using 0A as a nucleus is performed (step S20).

More specifically, a parse tree is created by compiling (syntactic analysis) the above-described behavioral description language using a normal compiler technique, and the parse tree is organized and control data such as T21 shown in FIG. Flow graph (CDFG)
Is generated (step S21). Here, T21 in FIG.
"If" node 1 shown in (1) inputs a control variable "k" or "i" and selects a subgraph through branches 4 and 5 according to its true (T) and false (F), respectively. It is.

Subsequently, the control data flow graph thus created is re-analyzed to obtain control nodes, control variables, and values of conditional expressions (step S22). Then, the value of the variable is determined, and a data flow graph (DFG) which is a subgraph including a closed loop uniquely determined as shown at T23 in FIG. 2 is selected. The operating conditions are analyzed in this way, and a data flow graph is extracted for each operating condition (step S23).

Next, the extracted data flow graph is scheduled (step S24). That is, it is divided into execution steps according to the execution processing time of the arithmetic unit.
As a result, the data flow graph is shredded into pieces of the control data flow graph that are processed within the same time.

Then, a hardware component necessary for the processing, that is, the above-mentioned arithmetic unit block is allocated to each CDFG fragment (step S25). At this time, in this embodiment, a register is inserted. This is because, as described above, the initial circuit data 20A of the present embodiment corresponds to the data path circuit unit 20 which is an actual fixed circuit, and therefore, there is an upper limit to the number of arithmetic units that can be executed simultaneously, and the execution is performed. To change the steps, it is necessary to insert a register. Further, in the description of the present embodiment, the hardware components (arithmetic unit blocks) are described as those which are optimally designed and cannot be changed in order to suppress a decrease in performance.
By making the bit width and the like reconfigurable, the flexibility can be further increased. It is also effective to use an unchangeable arithmetic unit block and a reconfigurable glue logic.

The hardware components are allocated as described above,
Generates connection information that can be executed by the initial circuit. The connection information is output as data path assignment information, and the operation conditions for the DFG are output as data path control information (step S30).

The data path assignment information data and data path control information generated by using the above high-level synthesis are shown in FIG.
Is loaded at the time of execution into the LSI indicated by (step S4).
0). Since these pieces of information are cut out in accordance with the operation order, the circuits can be loaded in order, and are mapped to, for example, a table lookup system corresponding to PLA or FPGA.

The connection between the register blocks 21a, 21b, the bus 21c, and the arithmetic unit block 21d in each stage block 21 can be dynamically changed, and the data path circuit section 20 is determined by the data path assignment information.
That is, each block 21a of the register, the bus, and the arithmetic unit corresponds to the stage determined at the time of scheduling.
21d are combined to form the stage block 21.

Since the number of the stage blocks 21 can form a loop circuit with the L-shaped main bus 40,
Any number is acceptable.

This embodiment has the following advantages.

(1) Since the circuit data synthesized from the operation description can be dynamically mapped to the data path circuit unit 20 corresponding to the initial circuit and integrated on the LSI, the operation description is directly executed. An LSI that dynamically changes the circuit configuration of the data path circuit unit 20 can be realized. Further, this LSI can optimize the execution code in order to timely write the optimal circuit data to the application program.

(2) Since the arithmetic units in the data path circuit are integrated on an LSI with an optimal structure, a conventional AN
It is possible to realize a circuit faster than a functional block composed of a random circuit including basic cells such as D and OR.

(3) Since the arithmetic units to be executed simultaneously are utilized to the maximum extent so that the execution can be performed in the shortest execution step at the time of high-level synthesis, each stage is minimized and the program is executed with the minimum number of steps. LSI can be realized.

(4) Since the control circuit section 30 may be concerned with only the execution part of the operation description, it can be minimized.

Due to such advantages, the present embodiment is suitable for a system LSI used in a field that handles an enormous amount of calculation, such as image processing, search processing, recognition processing, and parallel processing by a multi-processor system. It is suitable for.

[0046]

As described above in detail, according to the semiconductor device of the first invention, data path connection information generated based on circuit data as a result of high-level synthesis is mapped to a reconfigurable circuit. Since the data path circuit section is configured according to the data path connection information,
It becomes possible to dynamically change the data path circuit section that directly executes the operation description. That is, since an optimal data path circuit section can be configured as appropriate for each specific application program, the execution code can be optimized, and a high-performance LSI can be realized.

According to the semiconductor device of the second invention, in the first invention, the data path circuit section is provided with a register block, a bus section, and a register block corresponding to the stage determined at the time of scheduling the high-level synthesis. Since the stage block is composed of an arithmetic unit block, an LSI which simultaneously executes arithmetic units so as to be executed in the shortest execution step can be utilized to the maximum, and each stage has the shortest and the program which executes the program with the shortest number of steps Becomes feasible.

According to the semiconductor device of the third aspect, in the second aspect, an L-shaped bus is provided near the stage block, and the L-shaped bus forms a loop circuit of the stage block. The intermediate operation result by the operation unit block can be fed back to the register block, and the number of stage blocks can be minimized.

According to the semiconductor device of the fourth aspect, in the first to third aspects, the control information generated based on the circuit data as a result of the high-level synthesis is mapped to the reconfigurable circuit. Since the control circuit section is configured in accordance with the control information, the same effects as those of the first to third aspects can be obtained, and the control circuit section for controlling the data path circuit section can be dynamically changed. Will be possible. In other words, since the optimal control circuit for controlling the data path circuit can be configured in a timely manner, the control circuit only needs to be related to the execution part of the operation description, and the circuit scale can be minimized. Will be possible.

According to the semiconductor device circuit configuration method of the fifth invention, the data path circuit corresponding to the initial circuit in the high-level synthesis and the control circuit for controlling the operation of the data path circuit are provided. Prepare a semiconductor device configured with a reconfigurable circuit that can change the circuit configuration,
Based on the circuit data that is the result of the high-level synthesis, generate data path connection information that is connection information of the data path circuit unit and control information for controlling the operation of the data path circuit unit,
Since the data path connection information and the control information are mapped on the reconfigurable circuit, and the data path circuit section and the control circuit section are configured according to the mapping information, the same effects as those of the first and fourth inventions can be obtained. it can.

According to the circuit configuration method for a semiconductor device of the sixth aspect, in the fifth aspect, the data path circuit section includes a register block and a bus section corresponding to the stage determined at the time of scheduling. In the fifth aspect of the present invention, there is provided a stage block including an operation unit block including a plurality of operation units that can be executed simultaneously.
An effect equivalent to that of the second invention can be obtained.

[Brief description of the drawings]

FIG. 1 is a processing procedure diagram showing a circuit configuration method of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram for specifically explaining a part of processing contents in the embodiment.

FIG. 3 is a block diagram of a system LSI that is a semiconductor device according to the embodiment;

FIG. 4 is a functional block diagram showing an example of a conventional high-level synthesis technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 System LSI 20 Data path circuit part 21a, 21b Register block 21c Bus 21d Operation unit block 30 Control circuit part 40 Main bus 50 Core part 60 Memory part

Claims (6)

[Claims] 1. A control system created from an operation description.
A data flow graph for each control condition is extracted from the data flow graph, scheduling is performed to divide the data flow graph into execution steps, and a logic circuit is synthesized using the initial circuit as a nucleus. A semiconductor device having a data path circuit section including a reconfigurable circuit whose configuration can be changed, wherein data path connection information generated based on circuit data that is a result of the high-level synthesis is mapped to the reconfigurable circuit. And a circuit configuration of the data path circuit section according to the data path connection information. 2. A stage comprising a register block, a bus unit, and an operation unit block comprising a plurality of operation units that can be executed simultaneously, corresponding to the stage determined at the time of the scheduling. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a block. 3. The semiconductor device according to claim 2, wherein an L-shaped bus is provided near said stage block, and said L-shaped bus forms a loop circuit of said stage block. 4. A control circuit comprising a reconfigurable circuit capable of changing a circuit configuration and controlling an operation of the data path circuit, wherein the control circuit is generated based on circuit data as a result of the high-level synthesis. 4. The semiconductor device according to claim 1, wherein the control information is mapped to the reconfigurable circuit, and the control circuit is configured according to the control information. 5. A control created from an operation description.
A data flow graph for each control condition is extracted from the data flow graph, scheduling for dividing the data flow graph into execution steps is performed, and data corresponding to the initial circuit in high-level synthesis for synthesizing a logic circuit with the initial circuit as a nucleus. A path circuit unit and a control circuit unit for controlling the operation of the data path circuit unit prepare a semiconductor device configured by a reconfigurable circuit capable of changing a circuit configuration, and are a result of the high-level synthesis. Based on circuit data, data path connection information that is connection information of the data path circuit unit and control information for controlling the operation of the data path circuit unit are generated, and the data path connection information and the control information are generated. The data path circuit section and the control circuit are mapped to a reconfigurable circuit according to the mapping information. Circuit design method of a semiconductor device, characterized in that the circuit configuration of the parts. 6. A stage comprising a register block, a bus unit, and an operation unit block comprising a plurality of operation units that can be executed simultaneously, corresponding to the stage determined at the time of the scheduling. 6. The method according to claim 5, wherein the circuit is a block.