JPH10254923A - Logic circuit verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform verification for time proportional to the change amount of circuit by verifying only a changed circuit section even in case of large scale circuit. SOLUTION: Concerning a logic circuit verifying device with which a whole circuit is provided with plural circuit diagrams and the respective circuit diagrams are equipped with circuit diagram files so as to verify a logic circuit, this device has a memory cell instance name extracting means 1 for reading all the instance names of memory cells provided in the changed circuit diagram file to become the object of verification, inter-memory cell partial circuit extracting means 2 for extracting a partial circuit for generating a signal to be inputted to the input terminal of read memory cell before and after the change, logic verifying means 3 for verifying the coincidence/non-coincidence of logic before and after the change of extracted partial circuit, and non- coincident part diagram display means 4 for displaying the noncoincident part and the input signal at that time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit design verification device, and more particularly to a logic circuit design verification device in which the entire circuit is defined by a plurality of circuit diagrams.

[0002]

2. Description of the Related Art As an example of conventional design verification of a logic circuit, there is an invention of a logic verification system described in Japanese Patent Application Laid-Open No. Hei 5-20383. The invention described in the above publication is
Verification of the logical equivalence of two logic circuits described in the same logic circuit and having different levels of detail of description
This is performed for the entire circuit.

[0003]

In the above-described conventional logic circuit verification apparatus, the whole circuit is verified even if a part of a large-scale circuit is corrected, so that it takes a lot of time to perform the verification. was there.

[0004] It is an object of the present invention, even for large-scale circuits,
The purpose of the present invention is to perform verification in a time proportional to the amount of circuit change by verifying only the changed circuit portion.

[0005]

In order to achieve the above object, a logic circuit verification apparatus according to the present invention comprises a plurality of circuit drawings, each of which has a circuit drawing file. A logic circuit verifying device for verifying a logic circuit that is present, wherein the first circuit diagram file in which the changed circuit diagram file is changed is read out from the plurality of circuit diagram files, and the read first circuit diagram file is provided. If the first instance name of the first storage element is extracted, and there is a first circuit connected to another second circuit drawing file without passing through the first storage element, The connection terminal between the first circuit drawing file and the second circuit drawing file and the connection terminal of the second circuit drawing file are connected to the first terminal.
A storage element instance name extracting means for extracting a second instance name of the second storage element via a second circuit up to a second storage element to which the circuit is connected; The circuit connected to the input terminal of the first or second storage element output from the storage element instance name extraction means is extracted from the circuit drawing file of Extracting the partial circuit before the change and the partial circuit after the change, which are obtained by tracing until reaching the output terminal of the storage element, and extracting the partial circuit between the storage elements. Logic verification means for verifying whether the partial circuit before the change and the partial circuit after the change logically match and outputting the result.

In the logic circuit verifying apparatus according to the present invention, the output result of the logic verifying means may be configured such that when a signal value is input to the partial circuit, the partial circuit before the change and the partial circuit after the change Inconsistency information indicating whether the output results are different.

Further, the above logic circuit verification device of the present invention
Based on the output result of the logic verifying unit, which part on the circuit diagram has a partial circuit that is logically inconsistent between before and after the change and what signal value is present at the input terminal of the partial circuit It is possible to have a non-coincidence portion drawing display means for displaying on a drawing whether or not a non-coincidence occurs when input is made.

That is, the storage element instance name extracting means reads all the instance names of the storage elements included in the changed circuit diagram file to be verified. The inter-storage-element partial circuit extracting means extracts a partial circuit that generates a signal to be input to the input terminal of the read storage element before and after the change. The logic verifying unit verifies a logic match / mismatch between the extracted partial circuit before and after the change. The mismatched portion drawing display means displays the mismatched portion and the input signal at that time.

With this configuration, even if the entire circuit is a large-scale circuit defined by a plurality of circuit drawings, a flip-flop, a latch, or the like can be connected between the circuit before change and the circuit after change. When the number of storage elements (hereinafter, simply referred to as storage elements) can be made to correspond to each other, the verification as to whether they are logically equivalent is input to the storage elements included in the changed drawing and the storage elements. Since only the partial circuit that generates the signal is verified, the verification time can be reduced as compared with the case where the entire circuit is verified.

[0010]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a logic circuit verification device according to an embodiment of the present invention. The logic circuit verification device shown in FIG.
And inter-storage element partial circuit extraction means 2 and logic verification means 3
And the mismatched part drawing display means 4.

The entire circuit diagram to be verified has a plurality of drawings. The circuit diagram file is a circuit diagram file a before modification in which a plurality of drawings are one file for each drawing.
And a circuit diagram file a * after change, a storage element instance name list file b, a partial circuit file c before change, and a partial circuit file c * after change, in which only the changed partial circuit of the circuit diagram file is used as a file. , And a verification result file d. Also, the changed circuit diagram file a * is created only for the changed drawing,
For a drawing that is not changed, the circuit diagram file a before change is not updated and is kept as it is.

The storage element instance name extracting means 1 reads the changed circuit diagram file a * and reads the flip-flop (hereinafter referred to as FF) included in the changed drawing file.
), All the instance names of storage elements such as latches are extracted, and storage element instance name list file b
Is output. At this time, for a net connected to another drawing without passing through the storage element in the changed drawing file, the connection destination in the other drawing is traced until the storage element or the external input / output terminal is reached. Is also output to the storage element instance name list file b.

The inter-storage element partial circuit extraction means 2 reads the storage element instance name list file b. Then, a partial circuit, which is a combinational circuit of gate elements generating a signal to be input to the input pin of the storage element, is extracted from the circuit diagram file a before change and the circuit diagram file a * after change, and the partial circuit file before change is extracted. c and the changed partial circuit file c *. The partial circuit is a combination circuit of gate elements formed when the input pin of the storage element is traced in a direction opposite to the direction in which a signal flows to reach the output pin of the storage element. The output terminal of this partial circuit becomes the input pin of the storage element. The partial circuits are output by the number of input pins of the storage element output to the storage element instance name list file b.

The logic verification means 3 verifies whether or not the pre-change partial circuit file c and the post-change partial circuit file c * logically match, and outputs the verification result as a verification result file d. Logical match / mismatch determination
For example, if the order of appearance of the variables is the same, a matching BDD (binary decision diagram) may be used if they have the same logic. Further, a Boolean comparison method, a comparison simulation method, or the like as disclosed in JP-A-3-29868 may be used.

The mismatched circuit diagram display means 4 reads the verification result file d, and if there is a mismatched portion, reads the drawing corresponding to the mismatched portion from the circuit diagram file a before change and the circuit diagram file a * after change and displays the drawing. I do.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the logic circuit verifying apparatus of FIG. 1 described in the embodiment of the present invention will be further described with reference to a circuit diagram example.

FIG. 2 is a diagram showing a part of the circuit diagram file before change shown in FIG. The circuit to be verified is composed of a plurality of drawing files for each drawing. In FIG. 2, FIG. 2 (a) shows a part of the drawing file 1, and FIG. 2 (b) shows a part of the drawing file 2. Is shown.

FIG. 3 is a diagram showing a part of the modified circuit diagram file shown in FIG. 1. FIG. 3 (a) is a diagram obtained by modifying the drawing file 1 shown in FIG. 2 (a). 3
(B) is a modification of the drawing file 2 shown in FIG. 2 (b).

The partial circuit is changed between the pre-change circuit shown in FIG. 2 and the post-change circuit shown in FIG. 3 so that the number of storage elements corresponds. Specifically, there are cases where FFs or latches correspond, and cases where FFs and latches correspond. Between FIG. 2 and FIG. 3, a circuit for generating a signal to be input to the input pin D of the instance name FF2 is changed, and although the number of gate elements constituting a partial circuit is different, it is a storage element. The number of FFs is the same.

The storage element instance name extracting means 1 reads the modified circuit diagram of FIGS. 3A and 3B,
The instance name of the changed storage element in the drawing is extracted.

FIG. 4 is a diagram showing a part of the storage element instance name list file shown in FIG. 1, in which a changed drawing file name and an extracted instance name are described.

The inter-storage element partial circuit extraction means 2 reads the storage element instance name list file of FIG. 4 and outputs a partial circuit that generates a signal to be input to the input pin of each FF.

FIG. 5 is a diagram showing the partial circuit file before change shown in FIG. 1, and shows a partial circuit that generates a signal to be input to the input pin D of the instance name FF2 before the change. FIG. 6 is a diagram showing the changed partial circuit file shown in FIG. 1, and shows a partial circuit that generates a signal to be input to the input pin D of the changed instance name FF2.

The logic verifying means 3 verifies the partial circuit before the change shown in FIG. 5 and the partial circuit after the change shown in FIG. 6 to generate a signal to be input to the input pin D of the FF2. Verify that the logical match before and after the change.

FIG. 7 is a diagram showing the BDD of the partial circuit shown in FIG. 5, and shows the BDD of the input pin D of the FF2 before the change. FIG. 8 is a diagram showing the BDD of the partial circuit shown in FIG. 6, and shows the BDD of the input pin D of the FF2 after the change. FIG. 9 is a diagram showing the verification result file shown in FIG. 1, and shows an output display state of a mismatched portion in the verification result between FIG. 7 and FIG.

Since the two BDDs shown in FIGS. 7 and 8 do not match, it can be seen that they do not match logically. Therefore, as shown in FIG.
Regarding the above, the fact that the logic of the input pin D does not match before and after the change and the combination of the input signals that do not match are output as a verification result file.

FIG. 10 is a diagram showing a drawing display state of the mismatched portion shown in FIG. 9. The mismatched portion output from the mismatched circuit diagram display means 4 based on the verification result of FIG.
The drawing is displayed. In the drawing, a mark “☆” is displayed for a net that does not match, and a combination of input signals to the storage element that does not match is also displayed.

[0029]

As described above, according to the present invention, even if the entire circuit is a large-scale circuit defined by a plurality of circuit drawings, the number of storage elements between the circuit before change and the circuit after change is reduced. If it can be made to correspond, the verification as to whether or not they are logically equivalent has been changed by verifying only the storage element of the changed drawing and the partial circuit that generates the signal input to the storage element. By verifying only the circuit portion, the verification can be performed in a time proportional to the amount of change of the circuit, and the verification time can be reduced as compared with the case where the entire circuit is to be verified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a logic circuit verification device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a part of a circuit diagram file before change shown in FIG. 1;

FIG. 3 is a diagram showing a part of the circuit diagram file after the change shown in FIG. 1;

FIG. 4 is a view showing a part of a storage element instance name list file shown in FIG. 1;

FIG. 5 is a diagram showing a partial circuit file before change shown in FIG. 1;

FIG. 6 is a diagram showing a partial circuit file after the change shown in FIG. 1;

FIG. 7 is a view showing a BDD of the partial circuit shown in FIG. 5;

FIG. 8 is a diagram showing a BDD of the partial circuit shown in FIG. 6;

FIG. 9 is a view showing a verification result file shown in FIG. 1;

FIG. 10 is a view showing a drawing display state of a mismatched portion shown in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Storage element instance name extraction means 2 Inter-storage element partial circuit extraction means 3 Logic verification means 4 Mismatch point drawing display means a Circuit diagram file before change a * Circuit diagram file after change b Storage element instance name list file c Partial circuit before change File c * Modified partial circuit file d Verification result file

Claims (3)

[Claims] 1. A logic circuit verification apparatus for verifying a logic circuit having a plurality of circuit drawings and each of the plurality of circuit drawings including a circuit drawing file, comprising: The first change was made
And extracts the first instance name of the first storage element included in the read first circuit drawing file, and extracts the other instance name without passing through the first storage element. The first connected to the second schematic drawing file
If there is a circuit, the connection terminal between the first circuit drawing file and the second circuit drawing file and the second terminal
The second instance name of the second storage element is extracted via the second circuit between the connection terminal of the circuit drawing file of the first embodiment and the second storage element to which the first circuit is connected. A storage element instance name extracting means for connecting to the input terminal of the first or second storage element output from the storage element instance name extracting means from the circuit diagram file before change and the circuit diagram file after change Means for extracting a partial circuit before change and a partial circuit after change, obtained by tracing the circuit being performed until the output terminal of the first or second storage element is reached; Logic verification means for verifying whether the pre-change partial circuit extracted by the inter-storage-element partial circuit extraction means and the post-change partial circuit are logically identical, and outputting the result; Characterized by having , The logic circuit verification device. 2. The output result of the logic verification means indicates what kind of signal value is input to the partial circuit and the output result of the partial circuit before the change is different from the output result of the partial circuit after the change. The logic circuit verification device according to claim 1, further comprising mismatch information. 3. Based on an output result of the logic verifying means, which part of a circuit in the circuit diagram is logically inconsistent between before and after the change and which input terminal of the partial circuit 3. The logic circuit verification device according to claim 1, further comprising a mismatched portion drawing display means for displaying, on a drawing, whether or not there is a mismatch when such a signal value is input.