JP4559519B2 - Logical equivalence verification device - Google Patents

Description

  The present invention displays only portions where the logic of the pre-change circuit and the post-change circuit does not match after the logic equivalence verification between the pre-change circuit and the post-change circuit when the circuit under design is changed. The present invention relates to a logical equivalence verification apparatus that analyzes a common mismatch cause, which is an element that causes a common logic mismatch in a pre-change circuit and a post-change circuit, when a large number of locations are detected.

  The logic equivalence verification technique is one of CAD techniques for performing logic design verification of a large scale integrated circuit (LSI) or the like. LSI development begins with a specification study and involves a number of processes until the final LSI is manufactured. In order to develop a high-quality LSI, it is very important that no logic design errors are mixed in during the design process.

  In the design process, even after the logical specifications are finalized, the logic specifications are not changed in the mounting design process for actual manufacturing, such as adjusting the timing of signals and inserting scan circuits for manufacturing tests. Many changes are made to the implementation configuration. This operation is called an implementation process. There is a high possibility of mistakes that change the logic in this implementation process. Therefore, it is necessary to improve the logic design quality by verifying whether the logic specifications of the logic circuit before the implementation process and the logic circuit after the implementation process match. The technology for that is the logic equivalence verification technology. Hereinafter, the logic circuit before the implementation process is referred to as a specification, and the logic circuit after the implementation process is referred to as an implementation.

  Before performing logical equivalence verification, first, a plurality of verification points are selected in the logic circuit. As the verification point, a point at which the circuit is easily cut, such as an external terminal of an LSI or a flip-flop (FF), is usually selected. Next, a part having a certain verification point as an output point is extracted as a logic cone. The logic cone is a portion that is backtraced from a verification point that is an output point to another verification point that is an input point.

  FIG. 23 is a diagram illustrating an example of a logic cone. As shown in FIG. 23, the logic cone 51 is a part that is back-traced from a verification point 52 that is an output point to verification points 53 and 54 that are input points. The verification points 53 and 54 are output points of other logic cones. Although each logic cone is usually not so large, thousands to tens of thousands and hundreds of thousands of logic cones are cut out from one LSI, and logical equivalence verification is performed. When the logic of all logic cones matches, the two logic circuits, Impli and Spec, are considered equivalent for the first time. In the case of mismatch, the logic of a plurality of logic cones often does not match, which makes analysis difficult. For example, as shown in FIG. 23, when the logic cone 51 and the logic cone 55 overlap, if a design error is mixed in the overlapping portion, both logic cones are verified to be inconsistent.

  The spec and implementation logic are expected to match, but if the verification results do not match due to a mistake in the correction of the logical structure, etc., it is necessary to analyze the cause and correct the logic to the correct one. .

  As a logic equivalence verification device that performs logical equivalence verification of the pre-change circuit and post-change circuit and displays the result, when the logic of the pre-change circuit and post-change circuit does not match, the part that does not match is displayed There is. (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 10-254923 (page 3-4, FIG. 1)

  However, as described above, the number of logic cones constituting one LSI is enormous, and there is a problem that it takes much time and time to specify the cause of inconsistency after the logic equivalence verification. In addition, after the logic equivalence verification, the user selects a spec / implement pair from a plurality of logic cones that have a logic mismatch, and checks the difference between the spec and the implementation on the circuit diagram to investigate the cause of the mismatch. In this case, it is not known from which disagreement cause it is efficient, and the number of investigations for the disagreement cause becomes very large.

  The present invention has been made in view of the above-described problems, and provides a logical equivalence verifying apparatus that can reduce the trouble of analyzing the cause of inconsistency after logical equivalence verification and reduce design / verification TAT (Turn-around Time). With the goal.

  In order to solve the above-described problem, the present invention is a logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays the result of the logical equivalence verification, and the two circuits correspond to each other. A first identifier recording means for performing structure matching for determining whether or not there is a corresponding portion of the circuit structure in each logic cone, and recording the result of the structure matching as an identifier for each element; Subcone extraction means for extracting a group of elements having the same identifier connected to each other as a subcone, verification means for performing logical equivalence verification of the two circuits for each subcone extracted by the subcone extraction means, and the logical equivalent Based on the verification result, the subcone in which the logical equivalence verification result is inconsistent and the logical equivalence verification result are It is made of a display control means for displaying to distinguish between matches subcone.

  According to such a configuration, a subcone can be easily extracted using the result of the structure matching performed before the logical equivalence verification of the two circuits. Also, after verifying the logic equivalence of the two circuits, the subcones with the same logic and the subcones with the wrong logic are displayed separately, thereby reducing the time and effort of analyzing the cause of the mismatch and shortening the design period. can do. Note that the first identifier recording means in the present embodiment is the internal DB 5 and the preprocessing means 7.

  Further, the present invention is a logical equivalence verification apparatus that performs logical equivalence verification of predetermined two circuits and displays a result of the logical equivalence verification, in each of the logic cones corresponding to each other in the two circuits. Second instance recording means for performing instance name matching to determine whether or not the instance names match, and recording the result of the instance name matching as an identifier, and elements connected to each other from the logic cone and having the same identifier Subcone extraction means for extracting a group as a subcone, verification means for performing logical equivalence verification of the two circuits for each subcone extracted by the subcone extraction means, and the logical equivalence verification based on the result of the logical equivalence verification The subcone that does not match the result of the It is made of a display control unit that displays.

  According to such a configuration, a subcone can be easily extracted using the result of the instance name matching performed before the logical equivalence verification of the two circuits. Also, after verifying the logic equivalence of the two circuits, the subcones with the same logic and the subcones with the wrong logic are displayed separately, thereby reducing the time and effort of analyzing the cause of the mismatch and shortening the design period. can do. In the present embodiment, the second identifier recording means is the internal DB 5 and the preprocessing means 7.

  Further, the present invention provides a logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification. In the logic cones corresponding to each other in the two circuits, By applying an external input to the predetermined part and setting the output of the predetermined part to a constant value, sub-cone extraction means for extracting the sub-cone by removing the predetermined part from the logic cone, and for each sub-cone extracted by the sub-cone extraction means A verification means for performing logical equivalence verification of the two circuits, and a subcone in which the logical equivalence verification result does not match and a subcone in which the logical equivalence verification result matches based on the logical equivalence verification result. And display control means for displaying separately.

  In the logical equivalence verification apparatus according to the present invention, when a logical cone is divided into a plurality of parts by the predetermined part, the sub-cone extraction means extracts the plurality of parts as sub-cones. it can.

  According to such a configuration, before the logical equivalence verification of the two circuits, it is possible to easily extract the sub-cone by excluding the part that is not the verification target such as the test circuit. In addition, after the logic equivalence verification of the two circuits, the parts that are not subject to verification are not displayed, and the subcones with the same logic and the subcones with the mismatched logic are displayed separately. Can be reduced, and the design period can be shortened.

  Further, the present invention provides a logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification. In each logical cone corresponding to each other in the two circuits, An internal verification point associating means for selecting an internal verification point for viewing the output and associating the internal verification point; a sub-cone extraction means for extracting a sub-cone from the logic cone using the internal verification point; Verification means for performing logical equivalence verification of the two circuits for each sub-cone extracted by the sub-cone extraction means, and based on the result of the logical equivalence verification, the sub-cone in which the result of the logical equivalence verification is inconsistent with the logical equivalent Display control means for distinguishing and displaying the sub-cones with the matching verification results is provided.

  According to such a configuration, it is possible to easily extract the subcone using the internal verification point set before the logical equivalence verification of the two circuits. Also, after verifying the logic equivalence of the two circuits, the subcones with the same logic and the subcones with the wrong logic are displayed separately, thereby reducing the time and effort of analyzing the cause of the mismatch and shortening the design period. can do. The internal verification point associating means in the present embodiment is the preprocessing means 7.

  In the logical equivalence verification apparatus according to the present invention, the display control means displays only the sub-cones in which the logical equivalence verification results are inconsistent based on the logical equivalence verification results. it can.

  According to such a configuration, after the logic equivalence verification of the two circuits, only the subcone whose logic does not match is displayed, thereby reducing the time and effort for analyzing the cause of the mismatch and shortening the design period. be able to.

  The present invention also provides a logic equivalence verification for analyzing the cause of a logic mismatch when a plurality of mismatched logic cones are detected that are logic mismatches as a result of the logic equivalence verification of two predetermined circuits. A storage unit for storing elements constituting the inconsistent logic cone, and an element constituting the logic cone selected as an analysis target among the inconsistent logic cones is extracted as an analysis element, and includes the analysis element The disagreement logic cone is extracted for each analysis element as the corresponding logic cone, the analysis means for calculating the number of the corresponding logic cone for each analysis element, and the display for displaying the corresponding number for each analysis element And a control means.

  According to such a configuration, the user views the corresponding number for each analysis element, and determines that the analysis element with a large number of hits is likely to be a common cause of the logic mismatch between the two circuits. can do. Note that the storage unit in the present embodiment is the DB 101.

  In the logical equivalence verification apparatus according to the present invention, the display control means displays only the analysis elements whose corresponding number is in a predetermined range.

  According to such a configuration, the user narrows down analysis elements that are likely to be a common cause of the logic mismatch between the two circuits by browsing only the analysis elements whose number is within a predetermined range. Can do.

  In the logical equivalence verification apparatus according to the present invention, the display control means may further display an identifier of the corresponding logical cone for each analysis element.

  According to such a configuration, the user may browse the corresponding logic cone and the corresponding number for each analysis element, and may be a common cause of logic mismatch between the logic cone including the analysis element and the two circuits. It is possible to know an analysis element having a high value.

  In the logical equivalence verification apparatus according to the present invention, the display control means highlights an output point that is affected by modification of an element.

  According to such a configuration, the user can reduce unnecessary circuit changes and re-verifications by displaying the effect of the element correction on the logic cone that has become a logic mismatch in the logic equivalence verification. .

  In the logical equivalence verification apparatus according to the present invention, the display control means highlights an output point affected by an input restriction for excluding a predetermined circuit.

  According to such a configuration, the user can reduce unnecessary circuit changes and re-verifications by displaying the influence of input restrictions on the logic cones that have become logic mismatches in the logic equivalence verification. .

  In the logical equivalence verification apparatus according to the present invention, the predetermined two circuits may be a pre-change circuit and a post-change circuit when the circuit under design is changed.

  According to such a configuration, after the logic equivalence verification between the pre-change circuit and the post-change circuit, only the sub-cone with the logic mismatch is displayed, thereby reducing the labor of analysis of the cause of the mismatch. The period can be shortened.

  According to the present invention, there is provided a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification, wherein each logic cone corresponding to each other in the two circuits is displayed. Performing a structure matching for determining whether or not there is a corresponding part in the structure of the circuit, and recording the result of the structure matching as an identifier for each element, and having the same identifier connected to each other from the logic cone Extracting a group of elements as sub-cones, performing logical equivalence verification of the two circuits for each sub-cone, and a sub-cone in which the result of the logical equivalence verification is inconsistent based on the result of the logical equivalence verification; Logical equivalence verification comprising the step of distinguishing and displaying subcones that match the logical equivalence verification result The law can be provided.

  Further, according to the present invention, there is provided a logical equivalence verification method for performing logical equivalence verification of predetermined two circuits and displaying a result of the logical equivalence verification, wherein the logic cones corresponding to each other in the two circuits are: Performing instance name matching for determining whether or not the instance name matches for each element, and recording the result of the instance name matching as an identifier; and a set of elements connected to each other and having the same identifier from the logical cone Extracting as a sub-cone, performing a logical equivalence verification of the two circuits for each sub-cone, and based on a result of the logical equivalence verification, a sub-cone in which the result of the logical equivalence verification is inconsistent with the logical equivalence verification A logical equivalence verification method comprising the step of distinguishing and displaying subcones that match the results of It is possible to provide.

  Further, according to the present invention, there is provided a logical equivalence verification method for performing logical equivalence verification of predetermined two circuits and displaying a result of the logical equivalence verification, wherein the logic cones corresponding to each other in the two circuits are: A step of extracting a sub-cone from the logic cone by applying an external input to a predetermined part of the logic cone and setting the output of the predetermined part to a constant value, and the two circuits for each sub-cone. And a step of distinguishing and displaying a subcone in which the result of the logical equivalence verification does not match and a subcone in which the result of the logical equivalence verification matches based on the result of the logical equivalence verification. A logical equivalence verification method can be provided.

  In addition, according to the present invention, there is provided a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification, wherein each logic cone corresponding to each other in the two circuits is displayed. Selecting an internal verification point for viewing the output of the part, associating the internal verification point, extracting a sub-cone from the logic cone using the internal verification point, and for each sub-cone The logical equivalence verification of the two circuits is distinguished from the subcone in which the logical equivalence verification result is inconsistent from the subcone in which the logical equivalence verification result is in agreement based on the logical equivalence verification result. It is possible to provide a logical equivalence verification method comprising the step of displaying.

  Further, according to the present invention, when a plurality of mismatched logic cones that are logic mismatches in the result of the logic equivalence verification of two predetermined circuits are detected, a logic for analyzing the cause of the logic mismatch is detected. An equivalence verification method, the step of storing elements constituting the inconsistent logic cone, and extracting the elements constituting the logic cone selected as the analysis target from the inconsistent logic cones as analysis elements, Including the mismatched logic cone including the corresponding logic cone for each analysis element, calculating the number of the corresponding logic cones as the corresponding number for each analysis element, and displaying the corresponding number for each analysis element It is possible to provide a logical equivalence verification method comprising:

Further, according to the present invention, a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification is stored in a computer-readable medium in order to cause the computer to execute. A logical equivalence verification program,
In each logic cone corresponding to each other in the two circuits, performing a structure matching to determine whether there is a corresponding portion for the structure of the circuit, and recording the result of the structure matching as an identifier for each element; Extracting a set of elements connected to each other and having the same identifier for each element from the logic cone as a subcone, performing a logical equivalence verification of the two circuits for each subcone, and a result of the logical equivalence verification A logical equivalence verification program is provided that causes a computer to execute a step of distinguishing and displaying a subcone in which the logical equivalence verification result is inconsistent and a subcone in which the logical equivalence verification result is identical based on can do.

Further, according to the present invention, a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification is stored in a computer-readable medium in order to cause the computer to execute. A logical equivalence verification program,
In the logical cones corresponding to each other in the two circuits, performing instance name matching for determining whether or not the instance name matches for each element, and recording the result of the instance name matching as an identifier; Extracting a group of elements connected to each other having the same identifier as a subcone, performing a logical equivalence verification of the two circuits for each subcone, and based on a result of the logical equivalence verification, the logical equivalence verification It is possible to provide a logical equivalence verification program that causes a computer to execute a step of distinguishing and displaying a sub-cone in which the result of the above is inconsistent and a sub-cone in which the result of the logical equivalence verification is identical.

  Further, according to the present invention, a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification is stored in a computer-readable medium in order to cause the computer to execute. In the logic equivalence verification program, in the corresponding logic cones in the two circuits, an external input is given to a predetermined part of the logic cones, and the output of the predetermined part is set to a constant value. Excluding the predetermined portion, extracting a subcone, performing a logical equivalence verification of the two circuits for each subcone, and based on a result of the logical equivalence verification, the result of the logical equivalence verification is inconsistent And a step of distinguishing and displaying a sub-cone having the same logical equivalence verification result It is possible to provide a logical equivalence verification program, characterized in that.

Further, according to the present invention, a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying the result of the logical equivalence verification is stored in a computer-readable medium in order to cause the computer to execute. A logical equivalence verification program,
In each of the logic cones corresponding to each other in the two circuits, selecting an internal verification point for viewing the output of a portion and associating the internal verification point; from the logic cone, the internal verification point Extracting a subcone, performing a logical equivalence verification of the two circuits for each subcone, and based on a result of the logical equivalence verification, the subcone and the logical It is possible to provide a logical equivalence verification program that causes a computer to execute a step of distinguishing and displaying subcones whose equivalence verification results match.

  Further, according to the present invention, when a plurality of mismatched logic cones that are logic mismatches in the result of the logic equivalence verification of two predetermined circuits are detected, a logic for analyzing the cause of the logic mismatch is detected. A logical equivalence verification program stored in a computer-readable medium for causing a computer to execute the equivalence verification method, the step of storing elements constituting the mismatch logic cone, and analysis of the mismatch logic cone The elements constituting the logic cone selected as the target of the extraction are extracted as analysis elements, the mismatched logic cone including the analysis element is extracted as the corresponding logic cone for each analysis element, and the number of the corresponding logic cones is determined as the corresponding number. The step of calculating for each analysis element and the step of displaying the corresponding number for each analysis element are calculated. Be performed it is possible to provide a logical equivalence verification program characterized.

  As described above in detail, according to the present invention, logical equivalence verification is performed on a sub-cone basis, and only the sub-cone in which the cause of inconsistency is displayed is displayed, thereby reducing the time and effort of analyzing the cause of inconsistency performed by the user. -Verification TAT can be shortened. In addition, when a large number of logic mismatch sub-cones appear, it is possible to analyze a plurality of logic mismatches at the same time, and it becomes easy to analyze the cause of the common mismatch. Therefore, the analysis time is significantly reduced as compared with the method of analyzing all the logic mismatch subcones one by one. Further, by taking into account the common cause of the logic mismatch, it is possible to prevent the number of correction points from being generated or to generate another new mismatch cause, thereby optimizing the correction.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
In this embodiment, a part in the logic cone is extracted as a sub-cone using a plurality of internal verification points set in the logic cone before the logic equivalence verification, and the verification result does not match for each sub-cone. Display only sub-cones.

  First, the configuration of the logical equivalence verification apparatus will be described. FIG. 1 is a block diagram showing an example of the configuration of the logical equivalence verification apparatus. As shown in FIG. 1, the logical equivalence verification apparatus includes a storage unit 1, a control unit 2, a display unit 3, and an input unit 4. The storage unit 1 stores a database (DB) related to circuit information, a verification control program, and the like. The control unit 2 performs display on the display unit 3 in accordance with the verification control program in the storage unit 1 and the instruction from the input unit 4. The user uses the input unit 4 to input / change a circuit, instruct logical equivalence verification, and the like.

  Next, functions of the logical equivalence verification apparatus will be described. FIG. 2 is a functional block diagram illustrating an example of functions of the logical equivalence verification apparatus. As shown in FIG. 2, the function of the logical equivalence verification apparatus includes a DB 100 and a verification control program 200. The DB 100 includes an internal DB 5 that records information related to circuits, and a verification DB 6 that records information related to logical equivalence verification. The internal DB 5 includes a cell library 51, a specification design 52, and an implementation design 53. The cell library 51 records cell names, cell circuit information, and the like. The cell name is expressed by, for example, AND2 (2-input AND), AND3 (3-input AND), or the like. The specification design 52 records instance information, cell names, circuit connection information, etc. in the specification. Instance information is information consisting of an instance name and an instance terminal name. The instance name is a name given to each element. Similarly, the implementation design 13 records instance information, cell names, circuit connection information, and the like in implementation. The verification DB 6 records information related to sub-cones and verification information that is the verification result for each sub-cone as a verification table.

  As shown in FIG. 2, the verification control program 200 includes a preprocessing unit 7, a sub-cone extraction unit 8, a verification unit 9, and a display control unit 10. FIG. 3 is a flowchart showing an example of the flow of the verification control program.

  First, the pre-processing means 7 performs pre-processing for logical equivalence verification using information on the circuit of the internal DB 5 (S1). First, the preprocessing means 7 associates hierarchical instances between specifications and implementations. Here, for example, the association is performed using the instance name of the hierarchy. Next, verification points are selected and associated in specifications and implementations. Further, a portion having the verification point as an output point is extracted as a logic cone. Next, the preprocessing means 7 selects and associates internal verification points in the logic cone in the specification and implementation. The internal verification point is a point for viewing a partial output in the logic cone.

  Next, the sub-cone extraction unit 8 extracts a sub-cone from the logical cone using a plurality of internal verification points, and records information on the extracted sub-cone in the verification table of the verification DB 6 (S2). The sub-cone in the present embodiment is a portion backtraced from an internal verification point that is an output point to another internal verification point that is an input point.

  Next, the verification means 9 performs logical equivalence verification for each corresponding subcone between the specification and the implementation (S3), and records the result as verification information in the verification table of the verification DB 6 for each subcone. The verification information includes, for example, information such as “mismatch”, “unverified”, and “match”.

  Further, in the present embodiment, the internal verification point that is the input point of the first sub-cone with the matching verification information is the internal verification point that is the output point of the second sub-cone with the matching verification information. In this case, those internal verification points are not retained, and the verification table of the verification DB 6 is updated with the first sub-cone and the second sub-cone as one sub-cone.

  Next, the display control means 10 reads information on the specification and the implemented circuit from the internal DB 5 in accordance with the verification information in the verification table of the verification DB 6, and only the sub-cone whose logic does not match in the circuit diagram of the specification and the circuit diagram of the implementation. It displays on the display part 3 (S4). Here, subcones whose verification information is “match” are not displayed, and subcones whose verification information is “mismatch” or “unverified” are displayed.

  FIG. 4 is a diagram illustrating an example of a sub-cone extracted using an internal verification point. FIG. 4A shows a logic cone in the specification, and FIG. 4B shows a logic cone in the implementation. These two are the corresponding logic cones. White circles indicate verification points, and black circles indicate internal verification points.

  In the logic cone of FIG. 4A, since the verification information of the sub cone having the internal verification point 21 as the output point is “mismatch”, this sub cone is displayed. Similarly, in the logic cone of FIG. 4B, since the verification information of the sub cone having the internal verification point 22 as the output point becomes “mismatch”, this sub cone is displayed. It is determined according to the verification information whether or not the sub-cones whose output points are other internal verification points are displayed.

Embodiment 2. FIG.
In this embodiment, using the result of the structure matching automatically executed before the logical equivalence verification, the part in the logical cone is extracted as a sub-cone, the verification is performed for each sub-cone, and only the sub-cones where the verification results do not match. Is displayed.

  In this embodiment, the logical equivalence verification apparatus shown in FIG. 1 is used to perform the logical equivalence verification process according to the flow shown in FIG. 3, but the preprocessing and subcone extraction process in the present embodiment are performed. This is different from the processing in the first embodiment. Hereinafter, pre-processing and sub-cone extraction processing in the present embodiment will be described.

  In the present embodiment, the preprocessing unit 7 extracts a portion having the verification point as an output point as a logic cone, and then performs structure matching between corresponding logic cones between the specification and the implementation. The structure matching is a process for determining whether or not there is a corresponding part in the circuit structure by comparing the instance name, the connection relation between instances, a logical expression, and the like between the specification and the implementation. The sub-cone extraction means 8 extracts the sub-cone from the logical cone using the result of the structure matching, and records information on the extracted sub-cone in the verification table of the verification DB 6 (S2). The logical equivalence verification (S3) and the sub-cone display (S4) are the same as those in the first embodiment.

  Next, sub-cone extraction processing in the present embodiment will be described. First, the result of the structure matching by the preprocessing means 7 is recorded in the specification design 52 and the implementation design 53 as an identification flag for each instance. For example, 1 is recorded as an identification flag in an instance where the structures do not match. In addition, 0 is recorded as the identification flag in the instance having the matched structure. Next, the sub-cone extraction means 8 extracts the sub-cone using the identification flag recorded in the specification design 52 and the implementation design 53.

  FIG. 5 is a block diagram illustrating an example of a sub-cone extraction process in the logic cone according to the first embodiment. First, a verification point that is an output point of a logic cone is searched, and the verification point is set as the first trace source (S11). Next, in accordance with the connection information between the instances, a trace process for searching for a trace destination instance connected in the direction of the input point of the logic cone from the trace source instance is performed (S12). Next, in the trace processing, the identification flag of the trace source instance is compared with the identification flags of all trace destination instances (S13).

  As a result of the comparison of the identification flags, when the identification flag of any instance of the trace destination is equal to the identification flag of the trace source instance (S13, No), the process returns to the process S12, and the instance having the same identification flag is set as a new trace source. Continue the trace process.

  On the other hand, as a result of comparison of the identification flags, if the identification flags of all trace destination instances are different from the identification flags of the trace source instances (S13, Yes), the traced range is extracted as a subcone, and the extracted subcone is verified. Register in DB6 (S14). A new trace source instance in the logic cone is searched (S15).

  When an instance that can be a trace source remains in the logic cone without being traced (S16, No), the process returns to S12. On the other hand, if there is no instance that can be a trace source in the logic cone (S16, Yes), this flow ends. With the above flow, all the sub-cones in the logic cone are extracted. This flow is performed for all logic cones.

  FIG. 6 is a diagram illustrating an example of a sub-cone extracted using the result of the structure matching. FIG. 6A shows a logic cone in the specification, and FIG. 6B shows a logic cone in the implementation. These two are the corresponding logic cones. In addition, each portion surrounded by a dotted line is an extracted sub-cone.

  In the logic cone of FIG. 6A, the trace process is performed from the verification point 11. First, assuming that a2 connected to a1 has an identification flag equal to a1, a trace process is performed from a1 to a2. Next, if a5 connected to a2 has an identification flag different from a2, the trace processing is not performed. Furthermore, if a3 connected to a1 has an identification flag different from a1, there are no instances to be traced. As a result, a1 and a2 are extracted as sub-cones 12.

  Next, a3 becomes a new trace source, and the same trace processing is started. If a4, a5, and a6 connected to a3 have an identification flag equal to a3, the trace processing is performed from a3 to a4, a5, and a6. Next, there are no instances to be traced. As a result, a3, a4, a5, and a6 are extracted as sub-cones 15. Accordingly, in the logic cone of FIG. 6A, two sub-cones 12 and 15 are extracted.

  Similarly, in the logic cone of FIG. 6B, the trace processing is performed from the verification point 13. First, assuming that a2 connected to a1 has an identification flag equal to a1, a trace process is performed from a1 to a2. Next, if a8 and a9 connected to a2 have an identification flag different from a2, the trace processing is not performed. Further, if a7 connected to a1 has an identification flag different from a1, there are no instances to be traced. As a result, a1 and a2 are extracted as sub-cones 14.

  Next, a7 becomes a new trace source, and similar trace processing is started. If a8 connected to a7 has an identification flag equal to a7, the trace processing is performed from a7 to a8. Next, assuming that a9 connected to a8 has an identification flag equal to a8, the trace processing is performed from a8 to a9. Next, there are no instances to be traced. As a result, a7, a8, and a9 are extracted as sub-cones 16. Accordingly, in the logic cone of FIG. 6B, two sub-cones 14 and 16 are extracted.

  As described above, a collection of instances connected to each other and having the same identification flag is extracted as a subcone, and verification is performed for each subcone corresponding in the specification and implementation. In FIG. 6, the corresponding sub-cones 12 and 14 are subjected to logical equivalence verification. For example, if the verification results match, they are not displayed. Corresponding sub-cones 15 and 16 are subjected to logical equivalence verification. For example, if the verification results do not match, they are displayed. As described above, only the subcones whose logics do not match are displayed on the display unit 3, so that the trouble of analyzing the cause of the mismatch can be reduced and the design period can be shortened.

Embodiment 3 FIG.
In the present embodiment, a part in a logical cone is extracted as a sub-cone by using the result of instance name matching automatically executed before logical equivalence verification, and verification is performed for each sub-cone. Display only.

  In this embodiment, the logical equivalence verification apparatus shown in FIG. 1 is used to perform the logical equivalence verification process according to the flow shown in FIG. 3, but the preprocessing and subcone extraction process in the present embodiment are performed. This is different from the processing in the first embodiment. Hereinafter, pre-processing and sub-cone extraction processing in the present embodiment will be described.

  In the present embodiment, the preprocessing means 7 extracts a portion having the verification point as an output point as a logical cone, and then performs instance name matching in the corresponding logical cone between the specification and the implementation. The instance name matching is a process for determining whether or not there is a corresponding part for the instance name by comparing the instance name between the specification and the implementation. The sub-cone extraction means 8 extracts the sub-cone from the logical cone using the instance name matching result, and records information on the extracted sub-cone in the verification table of the verification DB 6 (S2). The logical equivalence verification (S3) and the sub-cone display (S4) are the same as those in the first embodiment.

  Next, sub-cone extraction processing in the present embodiment will be described. First, the result of the instance name matching by the preprocessing unit 7 is recorded in the specification design 52 and the implementation design 53 as an identification flag and link information for each instance.

  For example, when the instance name with the spec does not match any instance name of the implementation, the identification flag is recorded as 1 in the instance in the spec design 52 and the link information is not recorded. Similarly, when an instance name with an implementation does not match any instance name in the specification, an identification flag is recorded as 1 in an instance in the implementation design 53, and link information is not recorded.

  On the other hand, when the instance name with the specification matches the instance name with the implementation, the identification flag is recorded as 0 in the instance in the specification design 52, and the link information to the corresponding implementation instance is displayed. In a certain instance in the implemented design 53, the identification flag is recorded as 0, and the link information to the instance of the corresponding specification is recorded.

  The sub-cone extraction means 8 extracts a sub-cone using the identification flag recorded in the spec design 52 and the implied design 53. The sub-cone extraction process in the present embodiment is performed in the same flow as the flowchart shown in FIG. 5 except that the identification flag is based on the instance name matching result. This sub-cone extraction process is performed for all logic cones.

  FIG. 7 is a diagram illustrating an example of a sub-cone extracted using the result of instance name matching. FIG. 7A shows a logic cone in the specification, and FIG. 7B shows a logic cone in the implementation. These two are the corresponding logic cones. B1 to b6 indicate instance names.

  In the logic cone of FIG. 7A, assuming that b1, b2, and b3 have the same identification flag, b1, b2, and b3 are extracted as the sub-cone 31. If b4, b5, and b6 have the same identification flag, b4, b5, and b6 are extracted as the sub-cone 32.

  Similarly, in the logic cone of FIG. 7B, assuming that b1, b2, and b3 have the same identification flag, b1, b2, and b3 are extracted as sub-cones 33. If b4, b5, and b6 have the same identification flag, b4, b5, and b6 are extracted as the sub-cone 34.

  As described above, a collection of instances connected to each other and having the same identification flag is extracted as a subcone, and verification is performed for each subcone corresponding in the specification and implementation. In FIG. 7, the corresponding sub-cone 31 and sub-cone 33 are subjected to logical equivalence verification. For example, if the verification results match, they are not displayed. Corresponding sub-cone 32 and sub-cone 33 are verified for logical equivalence. For example, if the verification results do not match, they are displayed. As described above, only the subcones whose logics do not match are displayed on the display unit 3, so that the trouble of analyzing the cause of the mismatch can be reduced and the design period can be shortened.

Embodiment 4 FIG.
In the present embodiment, before the logical equivalence verification, a predetermined portion that is not to be verified is excluded from the logic cone, subcones are extracted, verification is performed for each subcone, and only subcones whose verification results do not match are displayed.

  In this embodiment, the logical equivalence verification apparatus shown in FIG. 1 is used to perform the logical equivalence verification process according to the flow shown in FIG. 3, but the preprocessing and subcone extraction process in the present embodiment are performed. This is different from the processing in the first embodiment. Hereinafter, pre-processing and sub-cone extraction processing in the present embodiment will be described.

  First, parts that are not subject to verification will be described. Examples of parts that are not verified include a test circuit (scan circuit) used for a manufacturing test, a logic change portion by cutting a loop circuit, and the like. The part that is not to be verified is usually excluded from the circuit diagram by a user instruction or preprocessing before the logical equivalence verification.

  In this embodiment, the part that is not to be verified in the specification and implementation includes an external input, and when a predetermined value is input to the external input, the value of the output point is the same regardless of what value is input to other input points. It is designed in advance to always output a constant value. By inputting a predetermined value to the external input of the non-verified part in the spec and implementation before the logical equivalence verification, the output point values are equalized, and the process of extracting the non-verified part is realized. .

  Next, sub-cone extraction processing in the present embodiment will be described. In the present embodiment, after the preprocessing means 7 extracts a portion having the verification point as an output point as a logic cone, the sub-cone extraction means 8 performs external input to the corresponding logic cone of the specification and the implementation, and performs verification. Extraction of a non-target portion is performed (S21). This non-verified portion is registered in the verification DB 6 as a non-displayed sub-cone. When the logic cone is not divided into a plurality of parts due to the part not to be verified (S22, No), the remaining part is registered in the verification DB 6 as a sub-cone (S23), and this flow is finished. On the other hand, when the logic cone is divided into a plurality of parts that are not to be verified (S22, Yes), the divided parts are registered in the verification DB 6 as sub-cones (S24), and this flow is terminated. The sub-cone extraction process according to the above flow is performed for all the logic cones having a portion that is desired to be excluded from verification.

  The sub-cone extraction means 8 extracts the sub-cone from the logical cone according to the above flow, and records information on the extracted sub-cone in the verification table of the verification DB 6 (S2). The logical equivalence verification (S3) and the sub-cone display (S4) are the same as those in the first embodiment.

  FIG. 9 is a diagram illustrating an example of a sub-cone extracted by excluding a portion not to be verified. FIG. 9A shows a logic cone in the specification, and FIG. 9B shows a logic cone in the implementation. These two are the corresponding logic cones. In addition, each shaded portion is a portion that is not subject to verification.

  In the logic cone of FIG. 9A, the output point 41 in the shaded area always outputs a constant value by performing external input. Thereby, the hatched portion can be excluded from the verification target. Here, since the logic cone is divided into two parts by extracting the parts not to be verified, the parts divided into two parts are extracted as sub-cones 42 and 43.

  Similarly, in the logic cone of FIG. 9B, the output point 44 in the hatched portion always outputs a constant value by performing external input. Thereby, the hatched portion can be excluded from the verification target. Here, since the logic cone is divided into two parts by extracting the parts not to be verified, the parts divided into two parts are extracted as sub-cones 45 and 46.

  As described above, sub-cones are extracted except for portions not to be verified, and verification is performed for each corresponding sub-cone in the specification and implementation. In FIG. 9, the hatched portion is not displayed. Corresponding sub-cones 43 and sub-cones 46 are subjected to logical equivalence verification. For example, if the verification results match, they are not displayed. Corresponding sub-cones 42 and sub-cones 45 are subjected to logical equivalence verification. For example, if the verification results do not match, they are displayed. As described above, only the subcones whose logics do not match are displayed on the display unit 3, so that the trouble of analyzing the cause of the mismatch can be reduced and the design period can be shortened. In the present embodiment, a portion that is not subject to verification is not displayed, but low luminance display may be performed.

  In the first to fourth embodiments, both the specification circuit diagram and the implementation circuit diagram are displayed on the display unit 3 as the verification results. However, only one circuit diagram may be displayed. good. Further, in the present embodiment, the portion where the verification results match is not displayed, but low luminance display may be performed.

Embodiment 5 FIG.
In the present embodiment, when the spec-implemented logical equivalence verification is performed using any one of the first to fourth embodiments, a large number of inconsistent sub-cones, which are sub-cones that have a logical inconsistency, are detected. In addition, the cause of the common mismatch, which is a common cause of the logic mismatch between the specification and the implementation, is analyzed.

  In designing a multi-stage logic circuit, it is possible to design a logic circuit with all possible sharing by performing logic synthesis with the goal of sharing elements and creating a circuit with as few elements as possible. ing. The shared element belongs to a plurality of sub-cones. If there is an error in an element belonging to many sub-cones even in one place in the implementation, there may be a logic mismatch in many sub-cones. That is, if a plurality of logical mismatches are detected and a plurality of related portions are logical mismatches, there is a high possibility that a common cause exists. For this reason, in this embodiment, elements that exist in common in the mismatched sub-cones are set as common mismatch cause candidates.

  First, the function of the logical equivalence verification apparatus in the present embodiment will be described. In this embodiment, a DB 101 is provided instead of the DB 100, and a verification control program 200 is provided instead of the verification control program 201. Further, a verification DB 63 is provided instead of the verification DB 6, a display control means 62 is provided instead of the display control means 10, and an analysis means 61 is further added. The verification DB 63 includes an analysis table and an analysis result table in addition to the verification table. The display control means 62 displays a logic mismatch list screen, an analysis condition setting screen, a common mismatch cause analysis result screen, a mismatch cause influence analysis screen, an influence propagation range screen, and a verification constraint setting screen, which will be described later, in addition to the display function of the mismatch subcone. It has a function. The analysis means 61 performs common mismatch cause analysis.

  Hereinafter, the common mismatch cause analysis will be described with reference to the flowchart of FIG. In the present embodiment, the specification shown in FIG. 12 and the implementation shown in FIG. 13 will be described as examples. The spec shown in FIG. 12 includes elements represented by instance names L1 to L10, and includes input points A, B, C, and D and output points S, T, U, and V. Further, the implementation shown in FIG. 13 includes elements represented by instance names M1 to M10, and includes input points A, B, C, and D and output points S, T, U, and V. FIG. 14 shows a sub-cone whose output point is S in the specification. Subcones whose output points are S, T, U, and V in the specification and implementation are extracted in the same manner as in FIG. Here, the logic equivalence verification and the common inconsistency cause analysis are performed in units of subcones, but a logic cone may be used instead of the subcone.

  First, the spec shown in FIG. 12 and the implementation shown in FIG. 13 are logically verified for each sub-cone, and sub-cones whose verification results do not match are displayed. In the first to fourth embodiments, the display control means 62 displays the mismatched subcone on the circuit diagram in the specification and implementation, but in this embodiment, the output of the mismatched subcone is displayed as a logical mismatch list. (S31).

  FIG. 15 is a diagram illustrating an example of a logical mismatch list screen. On the logic mismatch list screen, output points of mismatched sub-cones in the spec and implementation are displayed as a list. On the logic mismatch list screen, the user uses the input unit 4 to check the output points of the mismatched sub-cones to select analysis sub-cones. The analysis sub-cone is a sub-cone targeted for common non-coincidence cause analysis among the non-matching sub-cones. Here, as shown in FIG. 15, it is assumed that the user selects the analysis subcone by checking the output points S, T, U, and V in the specification and implementation. Regarding the selection of analysis sub-cones, a function may be provided in which all output points or a fixed number of output points are automatically selected by selecting output points as initial settings on the logic mismatch list screen. .

  After selecting the analysis subcone, when the user clicks the analysis condition setting button 71 on the logic mismatch list screen, the analysis unit 61 stores the analysis subcone selected on the logic mismatch list screen in the analysis table of the verification DB 63 for display control. The means 62 displays the analysis condition setting screen (S32). FIG. 16 is a diagram illustrating an example of the analysis condition setting screen. Here, the user uses the input unit 4 to set conditions for performing a common mismatch cause analysis. On the analysis condition setting screen, the analysis gate type, analysis element connection status, and number of appearances can be set.

  With the analysis gate type, it is possible to limit the types of elements to be subjected to common mismatch cause analysis. For example, as shown in FIG. 16, when AND and OR are turned ON, only AND and OR elements are subjected to common mismatch cause analysis. Here, as an example, only AND and OR are ON, but other analysis gate types may be selected.

  In the analysis element connection status, it is possible to limit the connection status of elements to be subjected to common mismatch cause analysis. The minimum number of inputs indicates the minimum value of the input to the element, the maximum number of inputs indicates the maximum value of the input to the element, the minimum number of output branches indicates the minimum number of branches of the output of the element, and the maximum number of output branches indicates the number of output of the element Indicates the maximum number of branches. For example, as shown in FIG. 16, if the minimum number of inputs is 2, the maximum number of inputs, the minimum number of branches, and the maximum number of branches are not limited, only elements having two or more inputs are subjected to common mismatch cause analysis.

  With the number of appearances, it is possible to limit the appearance status of elements that are the target of common mismatch cause analysis. For example, as shown in FIG. 16, if the number of appearances is one or more, only the elements that have appeared one or more times are subjected to common mismatch cause analysis.

  Here, it is assumed that the user sets analysis conditions as shown in FIG. After setting the analysis conditions, when the user clicks the analysis execution button 72 on the analysis condition setting screen, the analysis unit 61 stores the analysis conditions set on the analysis condition setting screen in the analysis table of the verification DB 63. Next, the analysis means 61 performs common mismatch cause analysis using information and analysis conditions regarding the analysis sub-cone of the DB 101 (S33).

  Here, the common mismatch cause analysis will be described. First, the analysis means 61 extracts an analysis element that is an element that matches an analysis condition from the elements constituting the analysis subcone in the specification and implementation. Next, each analysis element is compared with the elements constituting each non-matching sub-cone to extract the corresponding sub-cone that is a non-matching sub-cone including the analysis element, and the corresponding number that is the number of the corresponding sub-cones is calculated. Next, for each analysis element, the corresponding sub-cone and the corresponding number are associated and stored in the analysis result table.

  Next, the display control means 62 displays a common mismatch cause analysis result screen according to the analysis result table (S34). FIG. 17 is a diagram illustrating an example of a common mismatch cause analysis result screen. As shown in FIG. 17, on the common mismatch cause analysis result screen, for each of the spec and the implementation, the row label is the instance name of the analysis element and the column label is the output point name of the mismatch sub-cone, corresponding to the corresponding sub-cone for each analysis element. In addition to displaying the matrix with the position checked, the corresponding number for each analysis element is displayed.

  Here, in the common mismatch cause analysis result of the spec shown in FIG. 17, among the elements constituting the analysis sub-cone, the analysis elements that satisfy the analysis condition of AND or OR, two inputs or more, and the number of appearances one or more times are L1 to L10. The analysis elements L1 to L10 are displayed as row labels. For example, the discordant sub-cone represented by the output point S includes L1, L2, L4, L6, and L7, and therefore corresponds to the analysis elements L1, L2, L4, L6, and L7 in the column corresponding to the output point S. A check is displayed at the line position. Similarly, a check is displayed at a position corresponding to all the analysis elements and the corresponding sub-cone, and the corresponding number of analysis elements L1 is displayed as 4.

  In addition, the lower limit of the number of hits may be specified, and only analysis elements that are common to more logical mismatch subcones than the lower limit may be displayed. This makes it easier for the user to browse when the number of analysis elements is large. . Here, the analysis elements are displayed in order of numbers, but they may be displayed in order of decreasing number of hits. By browsing such a common mismatch cause analysis result screen, the user can determine an analysis element having a large number of hits as a common mismatch cause candidate with a high possibility of being a common mismatch cause.

  Next, the user re-verifies the common mismatch cause candidate by correcting the element or setting a verification constraint. Here, reducing the number of unnecessary circuit changes and re-verifications by displaying how much the circuit change affects the mismatched subcone in the previous logical equivalence verification by modifying the elements and setting verification constraints. Can do.

  In the common mismatch cause analysis result screen, when the user desires to display the influence of the element correction (S35, Yes), the display control means 62 displays the influence propagation range accompanying the element correction (S36). End the flow. When the user desires to display the influence due to the setting of the verification constraint (S37, Yes), the display control unit 62 displays the influence propagation range associated with the verification constraint (S38), and ends this flow. Further, when the user does not wish to display the influence of the modification of the element and the setting of the verification constraint (No in S37), this flow is finished.

  Here, the display of the influence propagation range accompanying the change of the element will be described. After browsing the common mismatch cause analysis result screen, when the user selects a common mismatch cause candidate by double-clicking the element M1, for example, in FIG. 17, the display control means 62 displays a mismatch cause influence analysis screen as shown in FIG. Display. In the example of FIG. 18, the circuit diagram is displayed on the mismatch cause influence analysis screen, and the element M1 in the circuit diagram is highlighted. Further, when the user selects by clicking on the element M1, “invert logic”, “change logic”, and “exchange input” are pop-up displayed as candidate correction methods for the element.

  Next, when the user selects, for example, “invert logic” from the correction method candidates, the display control means 62 displays the influence propagation range screen as shown in FIG. A circuit diagram is displayed on the influence propagation range screen, and the range affected by the selected correction is highlighted. The example of FIG. 19 represents that the influence of the logic inversion of the element M1 extends to M4, M6, M7, M8, M9, M10, S, T, U, and V. Further, on the logic mismatch list screen, output points affected by the logic inversion of the element M1 may be highlighted.

  From the influence propagation range screen of FIG. 19, it can be seen that the user has an influence on the output points S, T, U, and V by correcting the element M1, and it is meaningful to perform re-verification. If the influence due to the logic inversion of the element M1 does not propagate to any of the output points S, T, U, V on the influence propagation range screen, the user does not need to correct the element M1, and other common mismatch cause candidates You can find out if you investigate.

  Next, the display of the influence propagation range accompanying the setting of the verification constraint will be described. When the user inputs an instruction to display the verification constraint setting screen after browsing the common mismatch cause analysis result, the display control unit 62 displays a verification constraint setting screen (not shown). Verification constraint setting means setting a fixed value to the input of the part that is not subject to verification when a part that is not subject to verification, such as a test circuit, is added to only one of the specifications and implementations Thus, a portion that is not subject to verification is excluded. For example, when the logic equivalence verification of the specification shown in FIG. 20 and the implementation shown in FIG. 21 is performed, the output points X, Y, and Z are inconsistent in logic, and the input E that causes the inconsistency is added as a test circuit. Suppose it is a thing. Therefore, in order not to make this test circuit function, the input E is set to High as a verification constraint.

  The verification constraint setting screen includes verification constraint setting items and an effect confirmation button. In the example of FIG. 21, after the user sets the input E to High in the verification constraint setting item, the display control means 62 displays the influence propagation range screen as shown in FIG. I do. A circuit diagram is displayed on the influence propagation range screen, and the range affected by the setting of the verification constraint is highlighted. The example of FIG. 22 represents that the influence by the input E reaches P7, P8, P9, X, Y, and Z. Further, on the logic mismatch list screen shown in FIG. 15, the output points affected by the input E may be highlighted.

  From the influence propagation range screen of FIG. 22, it can be seen that the user has an influence on the output points X, Y, and Z by setting the verification constraint, and it is meaningful to perform re-verification. If the influence due to the validation constraint setting does not propagate to any of output points X, Y, or Z on the influence propagation range screen, the user does not need to set the validation constraint and investigate other common mismatch cause candidates. I understand that

(Supplementary note 1) A logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification,
A first identifier that performs structure matching for determining whether or not there is a corresponding portion of the circuit structure in each corresponding logic cone in the two circuits, and records the result of the structure matching as an identifier for each element Recording means;
Sub-cone extraction means for extracting as a sub-cone a group of elements connected to each other and having the same identifier from the logical cone;
Verification means for performing logical equivalence verification of the two circuits for each sub-cone extracted by the sub-cone extraction means;
Display control means for distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification apparatus comprising:
(Appendix 2) A logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification,
Second identifier recording means for performing instance name matching for determining whether or not the instance name matches for each element in the logic cones corresponding to each other in the two circuits, and recording the result of the instance name matching as an identifier;
Sub-cone extraction means for extracting as a sub-cone a group of elements connected to each other and having the same identifier from the logical cone;
Verification means for performing logical equivalence verification of the two circuits for each sub-cone extracted by the sub-cone extraction means;
Display control means for distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification apparatus comprising:
(Supplementary Note 3) In a logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification,
In the logic cones corresponding to each other in the two circuits, an external input is given to a predetermined portion of the logic cone and the output of the predetermined portion is set to a constant value, so that the predetermined portion is removed from the logic cone and a sub-cone is extracted. Subcone extraction means to perform,
Verification means for performing logical equivalence verification of the two circuits for each sub-cone extracted by the sub-cone extraction means;
Display control means for distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification apparatus comprising:
(Supplementary note 4) In the logical equivalence verification apparatus according to supplementary note 3,
The logical equivalence verification apparatus according to claim 1, wherein when the logic cone is divided into a plurality of parts by the predetermined part, the sub-cone extraction means extracts the plurality of parts as sub-cones.
(Supplementary Note 5) In a logical equivalence verification apparatus that performs logical equivalence verification of two predetermined circuits and displays a result of the logical equivalence verification,
In each of the logic cones corresponding to each other in the two circuits, an internal verification point for selecting an internal verification point for viewing the output of a part and correlating the internal verification point; and
Subcone extraction means for extracting a subcone from the logic cone using the internal verification point;
Verification means for performing logical equivalence verification of the two circuits for each sub-cone extracted by the sub-cone extraction means;
Display control means for distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification apparatus comprising:
(Supplementary note 6) In the logical equivalence verification apparatus according to any one of supplementary notes 1 to 5,
The display control means displays only a sub-cone in which the logical equivalence verification result is inconsistent based on the logical equivalence verification result.
(Supplementary Note 7) A logical equivalence verification apparatus for analyzing the cause of a logic mismatch when a plurality of mismatched logic cones, which are logic mismatches in the result of logic equivalence verification of two predetermined circuits, are detected. There,
A storage unit for storing elements constituting the inconsistent logic cone;
An element constituting a logic cone selected as an analysis target among the mismatch logic cones is extracted as an analysis element, and the mismatch logic cone including the analysis element is extracted as a corresponding logic cone for each analysis element, and the corresponding logic is extracted. An analysis means for calculating the number of cones as a corresponding number for each analysis element;
Display control means for displaying the corresponding number for each analysis element;
A logical equivalence verification apparatus comprising:
(Supplementary note 8) In the logical equivalence verification apparatus according to supplementary note 7,
The logical equivalence verification apparatus, wherein the display control means displays only the analysis elements whose corresponding number is within a predetermined range.
(Supplementary note 9) In the logical equivalence verification apparatus according to supplementary note 7 or supplementary note 8,
The display control means further displays an identifier of the corresponding logic cone for each analysis element.
(Supplementary note 10) In the logical equivalence verification apparatus according to any one of supplementary notes 7 to 9,
The display control means highlights an output point that is affected by an element modification.
(Supplementary note 11) In the logical equivalence verification apparatus according to any one of supplementary notes 7 to 10,
The display control means highlights an output point that is influenced by an input restriction for excluding a predetermined circuit.
(Supplementary note 12) In the logical equivalence verification apparatus according to any one of supplementary notes 1 to 11,
The predetermined two circuits are a pre-change circuit and a post-change circuit when a circuit under design is changed.
(Supplementary note 13) A logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In each logic cone corresponding to each other in the two circuits, performing a structure matching to determine whether there is a corresponding portion for the structure of the circuit, and recording the result of the structure matching as an identifier for each element;
Extracting a set of elements connected to each other and having the same identifier as sub-cones from the logic cone;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification method comprising:
(Supplementary note 14) A logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In the logic cones corresponding to each other in the two circuits, performing instance name matching to determine whether or not the instance name matches for each element, and recording the result of the instance name matching as an identifier;
Extracting a set of elements connected to each other and having the same identifier as sub-cones from the logic cone;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification method comprising:
(Supplementary Note 15) A logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In the logic cones corresponding to each other in the two circuits, an external input is given to a predetermined portion of the logic cone and the output of the predetermined portion is set to a constant value, so that the predetermined portion is removed from the logic cone and a sub-cone is extracted. And steps to
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification method comprising:
(Supplementary Note 16) A logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In each logic cone corresponding to each other in the two circuits, selecting an internal verification point for viewing the output of a portion, and associating the internal verification point;
Extracting a sub-cone from the logic cone using the internal verification point;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification method comprising:
(Supplementary Note 17) A logical equivalence verification method for analyzing the cause of a logic mismatch when a plurality of mismatched logic cones are detected as a result of logic mismatch in the result of logic equivalence verification of two predetermined circuits. There,
Storing the elements comprising the inconsistent logic cone;
An element constituting a logic cone selected as an analysis target among the mismatch logic cones is extracted as an analysis element, and the mismatch logic cone including the analysis element is extracted as a corresponding logic cone for each analysis element, and the corresponding logic is extracted. Calculating the number of cones as the corresponding number for each analysis element;
Displaying the number of hits for each analysis element;
A logical equivalence verification method comprising:
(Supplementary Note 18) A logical equivalence verification program for causing a computer to execute a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In each logic cone corresponding to each other in the two circuits, performing a structure matching to determine whether there is a corresponding portion for the structure of the circuit, and recording the result of the structure matching as an identifier for each element;
Extracting from the logic cone a set of elements connected to each other and having the same identifier for each element as a sub-cone;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification program that causes a computer to execute.
(Supplementary note 19) A logical equivalence verification program for causing a computer to execute a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In the logic cones corresponding to each other in the two circuits, performing instance name matching to determine whether or not the instance name matches for each element, and recording the result of the instance name matching as an identifier;
Extracting a set of elements connected to each other and having the same identifier as sub-cones from the logic cone;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification program that causes a computer to execute.
(Supplementary note 20) A logical equivalence verification program for causing a computer to execute a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In the logic cones corresponding to each other in the two circuits, an external input is given to a predetermined portion of the logic cone and the output of the predetermined portion is set to a constant value, so that the predetermined portion is removed from the logic cone and a sub-cone is extracted. And steps to
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification program that causes a computer to execute.
(Supplementary note 21) A logical equivalence verification program for causing a computer to execute a logical equivalence verification method for performing logical equivalence verification of two predetermined circuits and displaying a result of the logical equivalence verification,
In each logic cone corresponding to each other in the two circuits, selecting an internal verification point for viewing the output of a portion, and associating the internal verification point;
Extracting a sub-cone from the logic cone using the internal verification point;
Performing logical equivalence verification of the two circuits for each sub-cone;
Distinguishing and displaying a subcone in which the result of the logical equivalence verification is inconsistent and a subcone in which the result of the logical equivalence verification is identical based on the result of the logical equivalence verification;
A logical equivalence verification program that causes a computer to execute.
(Supplementary Note 22) A logical equivalence verification method for analyzing the cause of a logic mismatch when a plurality of mismatched logic cones, which are logic cones that resulted in a logic mismatch in the result of the logic equivalence verification of two predetermined circuits, is detected. A logical equivalence verification program to be executed by a computer,
Storing the elements comprising the inconsistent logic cone;
An element constituting a logic cone selected as an analysis target among the mismatch logic cones is extracted as an analysis element, and the mismatch logic cone including the analysis element is extracted as a corresponding logic cone for each analysis element, and the corresponding logic is extracted. Calculating the number of cones as the corresponding number for each analysis element;
Displaying the number of hits for each analysis element;
A logical equivalence verification program that causes a computer to execute.

It is a block diagram which shows an example of a structure of the logical equivalence verification apparatus in this Embodiment. FIG. 10 is a functional block diagram illustrating an example of functions of the logical equivalence verification apparatus according to the first to fourth embodiments. It is a flowchart which shows an example of a process of a verification control program. It is a figure which shows an example of the subcone extracted using the internal verification point. FIG. 10 is a block diagram illustrating an example of sub-cone extraction processing in a logic cone according to the second and third embodiments. It is a figure which shows an example of the subcone extracted using the result of structure matching. It is a figure which shows an example of the subcone extracted using the result of instance name matching. FIG. 10 is a block diagram illustrating an example of sub-cone extraction processing in a fourth embodiment. It is a figure which shows an example of the subcone extracted except the part which is not verification object. FIG. 10 is a functional block diagram illustrating an example of functions of a logical equivalence verification apparatus in a fifth embodiment. It is a flowchart which shows an example of a process of common mismatch cause analysis. It is a figure which shows an example of a specification. It is a figure which shows an example of an implementation. It is a figure which shows the subcone which made S the output point in a specification. It is a figure which shows an example of a logic mismatch list screen. It is a figure which shows an example of an analysis condition setting screen. It is a figure which shows an example of a common mismatch cause analysis result screen. It is a figure which shows an example of a mismatch cause influence analysis screen. It is a figure which shows an example of an influence propagation range screen. It is a figure which shows another example of a specification. It is a figure which shows another example of an implementation. It is a figure which shows another example of an influence propagation range screen. It is a figure which shows an example of a logic cone.

Explanation of symbols

  1 storage unit, 2 control unit, 3 display unit, 4 input unit, 100, 101 DB, 5 internal DB, 51 cell library, 52 spec design, 53 implement design, 6,63 verification DB, 200, 201 verification control program, 7 Pre-processing means, 8 Sub-cone extraction means, 61 Analysis means, 9 Verification means, 10, 62 Display control means, 11, 13 Verification points, 21, 22 Internal verification points, 12, 14, 15, 16, 31, 32, 33, 34, 42, 43, 45, 46 Subcones.

Claims (1)

A logic equivalence verification device for analyzing the cause of a logic mismatch when a plurality of mismatched logic cones, which are logic cones resulting in a logic mismatch in the result of logic equivalence verification of two predetermined circuits, are detected,
A storage unit for storing elements constituting the inconsistent logic cone;
An element constituting a logic cone selected as an analysis target among the mismatch logic cones is extracted as an analysis element, and the mismatch logic cone including the analysis element is extracted as a corresponding logic cone for each analysis element, and the corresponding logic is extracted. An analysis means for calculating the number of cones as a corresponding number for each analysis element;
Display control means for displaying the corresponding number for each analysis element;
A logical equivalence verification apparatus comprising:

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