JPH10214058A - Driving method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving method for a plasma display panel which is reduced in power consumption. SOLUTION: This method drives the plasma display panel which has column electrodes and row electrode couples crossing the column electrodes to form pixels at respective intersection parts and makes a gradational display by dividing an image of one frame into subframes having light emission periods corresponding to bit digits of pixel driving data. At this time, at least one of the row electrode couples is divided into row electrode groups, whether or not there is an illuminating pixel in a specific subframe is decided by the row electrode groups according to pixel driving data, and the supply of a driving pulse to a row electrode group having no illuminating pixel in the specific subframe is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix display type alternating current (AC) type plasma display panel (P).
DP).

[0002]

2. Description of the Related Art In recent years, as display devices have become larger, thinner display devices have been required, and various thin display devices have been provided. ACPDP is known as one of them. Pertaining A
The CPDP is provided with a row electrode pair which is orthogonal to the column electrode and the column electrode and constitutes one row (one scan line) by a pair (row electrode X, Y). Each of the column electrode and the row electrode pair is a discharge space. , And a discharge cell is formed at each intersection of the column electrode and the row electrode pair.

As one of the methods of displaying such a PDP in gray scale, a display period of one frame (one field) is divided into N sub-frames (light emission) for a time corresponding to the weight of each bit digit of N-bit display data. There is a method (so-called sub-frame method) in which the image is divided into sub-fields and displayed.

In the subframe method, as shown in FIG. 4, for example, when the pixel drive data is 6 bits, the display period of one frame is divided into six subframes SF1, SF2,..., SF6. . At this time, each subframe S
In F1 to SF6, for example, once, twice, four times, eight times
The sustain discharge light emission is performed 16 times and 32 times.

Each subframe includes, for example, a simultaneous reset period (black portion in FIG. 4), an address period, a sustain discharge period (hatched portion in FIG. 4), and a wall charge erasing period (not shown).
And various drive pulses are applied as shown in FIG.

FIG. 5 is a diagram showing the timing of applying various driving pulses of the conventional ACPDP. In the figure, first, a reset pulse RPy of negative polarity is applied to all the row electrodes Y1 to Yn, and a reset pulse RPx of positive polarity is applied to all of the row electrodes X1 to Xn. By the application of the reset pulse, a discharge is generated in all the discharge cells, charged particles are generated, and after the discharge is completed, wall charges are accumulated and formed in each discharge cell (simultaneous reset period).

Next, pixel data pulses DP1 to DPn corresponding to pixel data of each row are sequentially applied to column electrodes D1 to Dm.
Is applied. A scanning pulse (selection erasing pulse) SP is sequentially applied to the row electrodes X1 to Xn in synchronization with the application timing of each of the pixel data pulses DP1 to DPn. At this time, discharge occurs only in the discharge cells (light-off pixels) to which the pixel data pulse DP and the scan pulse SP are simultaneously applied to the column electrodes and the row electrodes, respectively, and the wall charges formed during the simultaneous reset period are erased. You.

On the other hand, in a discharge cell (lighting pixel) to which the scanning pulse SP is applied but the pixel data pulse DP is not applied, the above-described discharge does not occur, and thus the wall charges formed during the simultaneous reset period remain as they are. . As described above, the wall charges of each discharge cell are selectively erased according to the pixel data, and the lit pixel and the unlit pixel are selected (address period).

Then, a positive sustaining pulse IPy is applied to each of the row electrodes Y1 to Yn, and a positive sustaining pulse IPx is applied to the row electrodes X1 to Yn at a timing different from the application timing of the sustaining pulse IPy. Xn. As described above, the discharge sustaining pulses IPx and IPy are alternately applied to the row electrode pair, and the discharge cells (lighting pixels) in which the wall charges remain repeat discharge emission while the discharge cells (light-out pixels) in which the wall charges have disappeared. No discharge light emission (sustain discharge period).

Next, an erase pulse EP is applied to all the row electrodes X1 to Xn all at once to erase the wall charges of all the discharge cells (wall charge erase period). As described above, the simultaneous reset period, the address period, the sustain discharge period, and the wall charge erase period
Image display is performed by repeatedly performing this as one display cycle (one subframe).

[0011]

In the above-described sub-frame method, the reset pulse, the discharge pulse (display) or not during the sustain discharge period of each sub-frame is used.
Driving pulses such as a scanning pulse, a sustaining pulse, and an erasing pulse have been applied to the row electrode pairs.

However, depending on the contents of the video, discharge emission (display) may not be required for a screen corresponding to one of the sub-frames in one frame. When the screen corresponding to one sub-frame is divided into a plurality of areas instead of the entire screen corresponding to one sub-frame, discharge light emission (display) is performed for any of the areas.
If it is not necessary to perform the above, the possibility is further increased. Therefore, in such a case, useless power is consumed for application of the drive pulse.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide a method of driving a plasma display panel with reduced power consumption.

[0014]

According to the first aspect of the present invention,
A plurality of column electrodes, and a plurality of row electrode pairs arranged so as to intersect the column electrodes and form pixels at respective intersections, and emits one frame image corresponding to each bit digit of the pixel drive data. A method of driving a plasma display panel that performs gradation display by dividing into a plurality of sub-frames, wherein at least one of the row electrode pairs is divided into a plurality of row electrode groups, and each row electrode group is It is characterized in that the presence or absence of a lighting pixel in a predetermined sub-frame is determined every time, and the supply of a driving pulse to a row electrode group having no lighting pixel in the predetermined sub-frame is stopped.

According to a second aspect of the present invention, in the method for driving a plasma display panel according to the first aspect,
The predetermined subframe includes a subframe corresponding to the heaviest bit digit.

[0016]

According to the present invention, the above-described driving method is used. Therefore, the lighting pixel discriminating unit uses the bit data (pixel driving data) supplied to the row electrode group corresponding to each subframe to turn on the lighting pixel for each row electrode group. Is determined in a predetermined sub-frame, and if there is no illuminated pixel during the display period of the predetermined sub-frame, a control signal for stopping the supply of the driving pulse to the corresponding row electrode group is generated. By supplying to the control circuit, during the display period, the control circuit supplies a drive pulse (reset pulse, scan pulse, sustain pulse, erase pulse) unnecessary for lighting display to the row electrode group of the corresponding sub-frame. , Power consumption during driving of the plasma display panel can be reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a structure of a three-electrode reflective ACDP which is driven by a driving method of a plasma display panel according to an embodiment of the present invention. As shown in FIG.
A pair of row electrodes (sustain electrodes) X, Y and row electrodes X, Y arranged adjacent to each other in parallel with each other on the inner surface of the glass substrate 1 on the display surface side of the pair of glass substrates 1, 2 opposed to each other via Dielectric layer 5 for covering wall charge, MgO covering dielectric layer 5
Are provided respectively. The row electrodes X and Y are each composed of a transparent electrode 4 made of a wide band-shaped transparent conductive film and a bus electrode (metal electrode) 3 made of a narrow band-shaped metal film laminated to supplement the conductivity. It is composed of

On the other hand, barriers 10 are provided on the inner surface of the glass substrate 2 on the back side in a direction intersecting with the row electrodes X and Y and partition the discharge space 7. A column electrode (address electrode) D arranged in a direction intersecting X and Y, and a phosphor layer 8 of a predetermined emission color that covers each column electrode and the side surface of the barrier 10 are provided. The discharge space 7 is filled with a discharge gas obtained by mixing a small amount of xenon with neon. A discharge cell (pixel) is formed at each intersection of the above-mentioned column electrode and row electrode pair.

Next, a method of driving the plasma display panel according to the present invention, which is performed using the PDP 11 of FIG. 1, will be described. FIG. 2 is a diagram illustrating a configuration of a driving device that performs panel driving by the driving method of the present invention. Here, a case is shown in which one of the row electrode pairs (row electrode X) is vertically divided into two row electrode groups, and one frame is composed of two subframes.

In FIG. 2, an A / D converter 21 samples input video signals in accordance with a clock signal supplied from a control circuit 22 to obtain N-bit pixel data corresponding to one pixel. , Which are sequentially supplied to a pixel data processing circuit.

The image data processing circuit 23 includes a control circuit 22
Clock signal, horizontal and vertical synchronization signals,
And a dither processing circuit for performing data processing according to a selection signal and the like, a false contour correction data conversion circuit, and the like. These dither processing circuits and false contour correction data conversion circuits reduce the number of bits of pixel data to realize pseudo halftone display,
In addition, pixel data in which false contours are compensated is generated and supplied to the frame memory 24.

The frame memory 24 sequentially writes pixel data output from the image data processing circuit 23 in response to a write control signal supplied from the control circuit 22. Further, the frame memory 24 reads the written pixel data according to a read control signal supplied from the control circuit 22, and supplies the read pixel data to the column electrode driver 26. Here, bit data of a bit digit corresponding to each sub-frame is sequentially read from the frame memory 24 in accordance with the display order of the sub-frames.

The control circuit 22 generates a reset timing signal, a scan timing signal, a sustain timing signal, and an erase timing signal in accordance with the input horizontal and vertical synchronization signals, and generates a reset timing signal, a scan timing signal, a sustain timing signal, Erasure timing signals are sent to row electrode groups X11 to X1n and X21 to X corresponding to two subframes.
2n, a row electrode driver (row electrode X driver) 25a, 25b, a reset timing signal,
The sustain timing signal is supplied to a row electrode driver (row electrode Y driver) 25c.

Plasma display panel (PDP) 1
In FIG. 1, one of the row electrodes X and Y (row electrode X) is divided into two row electrode groups X11 to X1n and X21 to X2n.
Row electrode drivers (row electrode X drivers) 25a and 25b are provided corresponding to the two row electrode groups X11 to X1n and X21 to X2n. On the other hand, a row electrode driver 25c (row electrode Y driver) is provided corresponding to the other of the row electrodes X and Y (row electrode Y).

Row electrode driver (row electrode X driver) 25
Reference numerals a and 25b denote reset pulses for simultaneously initializing the wall charge amounts of all the discharge cells in accordance with the various timing signals, and selectively form or erase wall charges in accordance with pixel data to illuminate pixels ( A scan pulse (selective write pulse or selective erase pulse) for selecting a cell) and a light-off pixel (cell), and maintain the light-on pixel and the light-off pixel (ie,
A sustain pulse for maintaining a discharge light emission state) and an erase pulse for erasing wall charges of all discharge cells are generated, and these are supplied to the row electrode groups X11 to X1n and X21 to X2n. At this time, the scanning pulse is sequentially applied by scanning from the row electrode X11 to the row electrode X2n.

Row electrode driver (row electrode Y driver) 25
c is a reset pulse for simultaneously initializing the wall charges of all the discharge cells in accordance with the various timing signals,
Sustain pulses for maintaining the lit pixels and the unlit pixels (that is, maintaining the discharge light emitting state) are applied to the row electrodes Y11 to Y2n.
To supply. At this time, a reset pulse and a sustain pulse are applied to the row electrodes Y11 to Y2n at the same timing.

The column electrode driver 26 converts the voltage values corresponding to the logical values "1" and "0" of the bit data (pixel drive data) of the bit digit corresponding to each sub-frame sequentially supplied from the frame memory 24. A pixel data pulse is generated and supplied to the column electrodes D1 to Dm of the PDP 11.

The first lighting pixel discriminating section 27a responds to the bit data (pixel driving data) of the bit digit corresponding to each sub-frame sequentially supplied from the frame memory 24, and sets the row electrode groups X11 to X11 to The presence / absence of a lit pixel in the display area (upper half of the screen) Sa corresponding to X1n is determined. If there is no lit pixel in the display period of each subframe, a drive pulse (reset pulse) for the row electrode groups X11 to X1n is determined. , A scan pulse, a sustain pulse, and an erase pulse), and supplies it to the control circuit 22.

Similarly, the second lighting pixel discriminating section 27b responds to the bit data (pixel driving data) of the bit digit corresponding to each sub-frame sequentially supplied from the frame memory 24, and outputs the row electrode in each sub-frame. Group X21 ~
The presence / absence of a lit pixel in the display area (lower half of the screen) Sb corresponding to X2n is determined. If there is no lit pixel in the display period of each subframe, the drive pulse (reset pulse) for the row electrode groups X21 to X2n is determined. , And a second control signal for stopping the supply of the sustain pulse is supplied to the control circuit 22.

The control circuit 22 responds to the first and second control signals supplied from the first and second illuminated pixel discriminating sections 27a and 27b to control the row electrode driver (row electrode X driver) 2.
The supply of the reset timing signal, the scan timing signal, the sustain timing signal, and the erase timing signal to 5a and 25b is stopped (controlled).

When one or more illuminated pixels are present in the display areas Sa and Sb during the display period of each subframe, the above control signal is not generated, and as a result, a drive pulse is applied to each row electrode group. Supplied.

Next, the operation of the driving device will be described.
Here, the pixel drive data is 4 bits. In FIG. 2, the first lighting pixel determination unit 27a includes lines 11 to 1n (row electrode groups X11 to X11) sequentially supplied from the frame memory 24.
X1n), the bit data (pixel driving data) for the pixels in the display area (upper half of the screen) Sa corresponding to X1n) is determined for each subframe, and, for example, as shown in FIG.
.. 1n (the upper half of the screen) corresponding to the row electrode groups X11 to X1n (ie, the upper half of the screen) when all the bit data of the bit digit with the heaviest weight for all the pixels are non-light emission logical values (that is, the display area). If all the pixels in Sa are all unlit pixels, the subframe corresponding to the bit digit with the heaviest weight (the subframe SF with the longest light emission period)
In the display period of 4), a first control signal for stopping the supply of the driving pulse to the row electrode groups X11 to X1n is generated and supplied to the control circuit 22. FIG. 3 is a diagram showing a lighting state of a pixel in one frame of the PDP being driven by using the driving method of the present invention for each sub-frame corresponding to each display area. A sub-frame when there is one or more illuminated pixels is shown, and a blank portion shows a sub-frame when there is no illuminated pixel in the display period.

In FIG. 2, the second lighting pixel discriminating section 27b includes a display area (lower half of the screen) corresponding to the lines 21 to 2n (row electrode groups X21 to X2n) sequentially supplied from the frame memory 24. Bit data (pixel drive data) for the pixels in Sb is determined for each sub-frame, and for example, as shown in FIG.
X2n) corresponds to the second heaviest bit digit when the bit data of the second heaviest bit digit for all pixels in the display area (lower half of the screen) Sb corresponding to X2n) is a non-emission logical value During the display period of the sub-frame (the sub-frame SF3 having the second longest light emission period), a second control signal for stopping the supply of the drive pulse to the row electrode groups X21 to X2n is generated.
To supply.

The control circuit 22 includes a first lighting pixel determination unit 27
In response to the first control signal supplied from a, supply of drive pulses to the row electrode groups X11 to X1n in the display period of the subframe corresponding to the heaviest bit digit (subframe SF4 having the longest light emission period) To stop (control) the supply of the reset timing signal, the scanning timing signal, the sustain timing signal, and the erasing timing signal to the row electrode driver (row electrode X driver) 25a so that the second lighting pixel determination unit 27b supplies the reset signal. Second
In response to the control signal, the supply of the drive pulse to the row electrode groups X21 to X2n is stopped in the display period of the subframe (subframe SF3 having the longest light emission period) corresponding to the second heaviest bit digit. The supply of the reset timing signal, the scan timing signal, the sustain timing signal, and the erase timing signal to the row electrode driver (row electrode X driver) 25b is stopped (controlled).

With the above configuration, the driving device of the PDP is
During the display period of one frame of the driving PDP, the row electrode group corresponding to the sub-frame in the case where there is no illuminated pixel is driven so that the supply of the driving pulse is stopped during the display period. In addition, generation of a drive pulse that does not contribute to discharge is suppressed, and accordingly, power consumption during PDP driving is reduced accordingly.

FIG. 2 shows an example in which one of the row electrode pairs (row electrode X) is vertically divided into two row electrode groups.
However, the present invention is not limited to this. For example, one of the row electrode pairs (the row electrode X) may be divided into an odd line and an even line and divided into two row electrode groups.

Further, one of the row electrode pairs (row electrode X) can be divided into three or more row electrode groups. When the number of divisions of the row electrode group is increased as described above, the suppression of the generation of the drive pulse that does not contribute to the discharge becomes more effective.

In the above-described embodiment, the other (row electrode Y) of the row electrode pair is applied with a common drive pulse in all lines (rows), and is not divided and the supply of the drive pulse is not restricted. However, it is also possible to limit the supply of the drive pulse by dividing the same as one of the row electrode pairs (row electrode X).

In this case, for example, one of the row electrode pairs (row electrode X) is divided into four row electrode groups, and the other (row electrode Y) of the row electrode pair is divided into two row electrode groups to display each subframe. In the period, the presence or absence of the illuminated pixel may be determined for each display region corresponding to the four row electrode groups, and the supply of the driving pulse to each row electrode group may be selectively limited.

Further, in the above-described driving method, an example using a reflection type ACPDP having a three-electrode structure has been described. However, the present invention is not limited to this, and another type of PDP such as a DC (direct current) type PDP is used.
Also applicable to

[0041]

According to the present invention, the above driving method is used.
The lighting pixel determination unit determines the presence / absence of a lighting pixel for each row electrode group in a predetermined subframe based on bit data (pixel driving data) supplied to the row electrode group corresponding to each subframe. If there is no illuminated pixel during the display period, a control signal for stopping the supply of the driving pulse to the corresponding row electrode group is generated and supplied to the control circuit, so that the control circuit Stops supplying drive pulses (reset pulse, scan pulse, sustain pulse, erase pulse) unnecessary for lighting display to the row electrode group of the corresponding sub-frame, so that power consumption when driving the plasma display panel is reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a structure of a reflective ACDP with a three-electrode structure driven by a method of driving a plasma display panel according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a driving device that performs panel driving by the driving method of the present invention.

FIG. 3 shows one PDP being driven using the driving method of the present invention.
FIG. 3 is a diagram illustrating a lighting state of a pixel in a frame for each sub-frame corresponding to each display region.

FIG. 4 is a diagram illustrating various drive pulses applied to each sub-frame during a display period of one frame of a PDP being driven using the sub-frame method.

FIG. 5 is a diagram showing application timings of various conventional driving pulses of the ACPDP.

[Explanation of symbols]

 1 ... Glass substrate 2 ... Glass substrate 3 ... Bus electrode (metal electrode) 4 ... Transparent electrode 5 ... Dielectric layer 6 ... Protection layer 7 Discharge space 8 Phosphor layer 10 Barrier 11 PDP 21 A / D converter 22 Control circuit 23 ····· Image data processing circuit 24 ··· Frame memory 25a ··· Row electrode driver (row electrode X driver) 25b ··· Row electrode driver (row electrode X driver) 25c ··· Row electrode driver (row Electrode Y driver) 26... Column electrode driver 27a... First lighting pixel determination unit 27b.

Claims (2)

[Claims] 1. A plurality of column electrodes, and a plurality of row electrode pairs arranged so as to intersect with the column electrodes and form a pixel at each intersecting portion. A method of driving a plasma display panel that performs gradation display by dividing into a plurality of subframes having a light emission period corresponding to the above, wherein at least one of the row electrode pairs is divided into a plurality of row electrode groups, Determine the presence or absence of a lighting pixel in a predetermined sub-frame for each row electrode group according to the drive data,
A method for driving a plasma display panel, comprising: stopping supply of a driving pulse to a row electrode group having no illuminated pixels in the predetermined subframe. 2. The method according to claim 1, wherein the predetermined sub-frame includes a sub-frame corresponding to a heaviest bit digit.