JPH11265163A - Driving method for ac type pdp - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of addressing while avoiding the prolongation of a required time. SOLUTION: In an address term TA for forming a charge distribution corresponding to display contents through a linear scanning voltages Ppx and Ppy are impressed for generating priming discharging to a pair of electrodes X and Y for each line and afterwards, voltages Pax, Pay and Pa are impressed for generating address discharging only to a cell requiring change of a charging state. Simultaneously with the impression of voltages Pax, Pay and Pa to the cell of the row of i-th selection priority, the voltages Pax, Pay and Pa for generating priming discharging are impressed to a pair of electrodes of (i+2)th row or following row. In this case, (i) is an integer from 1 to n-2 (n: number of rows of selection object).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface discharge AC
The present invention relates to a method for driving a PDP (Plasma Display Panel).

2. Description of the Related Art PDPs are self-luminous thin display devices using a substrate pair as a support, and have been widely used in applications such as television images and computer monitors with the practical use of color screens. . As the market expands, so does the demand for operational reliability.

[0003]

2. Description of the Related Art As a color display device, an AC type PDP having a three-electrode surface discharge structure has been commercialized. This is a matrix display in which a pair of main electrodes (first and second electrodes) for maintaining lighting are arranged for each row (line) of the matrix display, and an address electrode (third electrode) is arranged for each column. It is. Partition walls for preventing discharge interference between cells are provided in a stripe shape. Since the display is of the AC type, the memory function of the dielectric layer covering the main electrode is used for display. That is, addressing for forming a charged state according to display contents is performed in a line scanning format, and thereafter, a lighting sustaining voltage Vs having an alternating polarity is simultaneously applied to all the main electrode pairs. This allows
Only in the cell where the wall charge exists, the effective voltage (also referred to as cell voltage) Veff exceeds the firing voltage Vf, and a surface discharge occurs along the substrate surface. By shortening the application period of the lighting sustaining voltage Vs, an apparently continuous lighting state can be obtained.

When displaying a time-series image such as a television image, the charged state of the entire screen is changed during the period from the end of maintaining the lighting of one image to the addressing of the next image in order to prevent display disturbance. Preparation for addressing to make uniform is performed. For example, in the case of a write address format in which wall charges are formed only in cells to be turned on, reset processing for erasing charges on the entire screen is performed prior to addressing.

[0005]

As described above, in the structure in which the discharge space is divided for each column by the stripe-patterned partition walls, space charges which produce a priming effect occur only within each column. Therefore, the electric charge which contributes to the priming effect of each cell in the address period in which the discharge is generated in the unit of a row is caused by the remaining space charge generated by the discharge in preparation for the addressing and the cell on the upstream side of the row selection (scan). Is the space charge generated by the address discharge. When the upstream cell is a cell that does not need to generate an address discharge (for example, a non-lighting cell in a write address format), only the space charge generated in the addressing preparation stage contributes to the priming effect. For this reason,
In particular, in the row selected at the end of the address period, since the elapsed time from the addressing preparation is long and the residual amount of space charge is small, the discharge delay becomes remarkable, and the scanning time for one row defined by the scan pulse width ( There is a serious problem that an address discharge does not occur within an address cycle and a display defect occurs.

As a means for avoiding this problem, there has been proposed a method of causing a priming discharge for forming space charges in a row to be selected immediately before application of a scan pulse for selecting a row (Japanese Patent Laid-Open No. 9-6280). issue). Priming discharge occurs in all cells in a row regardless of display contents,
The address discharge surely occurs.

However, in the conventional driving method, since a pulse for generating a priming discharge and a pulse for generating an address discharge are applied for each row, the time required for addressing the entire screen is reduced. There is a problem that the length is extended more than twice as much as the case where it is not performed. In moving image display, faster addressing is desirable.

An object of the present invention is to increase the reliability of addressing while avoiding an increase in required time.

[0009]

According to the present invention, a priming discharge is generated for each row at the time of addressing, thereby reliably generating an address discharge. Then, the drive voltage application timing is selected so that an address discharge is generated in a certain row and a priming discharge is generated in another row that is not adjacent to the row. As a result, the time required for addressing can be prevented from being greatly extended, and interference between the priming discharge and the address discharge is prevented.

In the method according to the first aspect of the present invention, a plurality of first and second main electrodes are arranged so as to form an electrode pair for generating a surface discharge for each row of the matrix display, and the first and second main electrodes are arranged for each column. This is a method of driving an AC-type PDP in which three electrodes are arranged and a discharge space is continuous over the entire length of the screen in a column direction, and forms a charge distribution according to display contents in a line scanning format in which each row is selected in the order of arrangement. During the address period,
For each row, after applying a voltage for generating a priming discharge to the electrode pair, a voltage for generating an address discharge is applied to only the cells whose charge state needs to be changed. Simultaneously with the application of the voltage for causing an address discharge to the cells in the i-th row, the voltage for causing a priming discharge to the electrode pairs in the (i + 2) -th or later row is generated. To be applied. i is 1 to (the number of rows to be selected-
It is an integer up to 2).

According to a second aspect of the present invention, in the driving method, at least one of the same configuration as the electrode pair is provided outside the screen in the column direction.
A pair of auxiliary electrode pairs are provided, and in the address period, before applying the voltage for causing a priming discharge to the electrode pair of the first row in the selection order, the auxiliary electrode pair is The voltage for generating a priming discharge is applied.

In a driving method according to a third aspect of the present invention, in the address period, the first main electrodes in the odd-numbered rows are electrically shared and the first main electrodes in the even-numbered rows are electrically shared. When applying the voltage for causing an address discharge to the cells in the odd-numbered rows by electrically commonizing them, the first main electrodes in the odd-numbered rows are biased to a first potential. And when biasing the first main electrode of the even-numbered row to the second potential and applying the voltage for causing an address discharge to the cells of the even-numbered row, Biasing a first main electrode to the second potential and biasing the first main electrodes in even-numbered rows to the first potential.

In the driving method according to the present invention, in the address period, a row is divided into an odd-numbered group and an even-numbered group, and a charge distribution according to display contents is formed for each group in a time-division manner. Between the formation of the first set and the formation of the second set,
The voltage for generating a priming discharge is applied to the auxiliary electrode pair near the first row selected in the subsequent set.

According to a fifth aspect of the present invention, in the address period, the first application time of the voltage for causing the priming discharge is longer than the second and subsequent application times.

In the driving method according to a sixth aspect of the present invention, in the address period, the time for applying the voltage to the auxiliary electrode pair is reduced by applying the voltage to the electrode pair in a row belonging to the subsequent set. This is to make the time longer than the application time.

According to a seventh aspect of the present invention, in the driving method, a plurality of first and second main electrodes are arranged so as to form an electrode pair for generating a surface discharge for each row of the matrix display. A method for driving an AC-type PDP in which a third electrode is arranged and a discharge space is continuous over the entire length of a screen in a column direction, wherein a row is divided into an odd-numbered set and an even-numbered set, and After performing the charging state, uniforming, and forming the charge distribution according to the display contents, performing the charging state, uniforming, and forming the charge distribution according to the display contents for the other set, and performing charging of the one set. A first address period forming a distribution, and a second address period forming the other set of charging distributions.
In each of the address periods, a voltage for generating a priming discharge is applied to the pair of electrodes for each row, and thereafter, an address discharge is performed for only the cells whose charge state needs to be changed. (J + 2) at the same time as applying the voltage for applying the voltage to cause the address discharge to the cells of the j-th row in the selection order.
And applying the voltage for causing a priming discharge to the electrode pairs in the third or subsequent row. j is an integer from 1 to (the number of rows to be selected-2).

In the driving method according to the present invention, in each of the first and second address periods, the first application time of the voltage for causing the priming discharge is longer than the second and subsequent application times. Is what you do.

[0018]

FIG. 1 is a configuration diagram of a plasma display device 100 according to a first embodiment. Plasma display device 100
Is an AC type P which is a flat type color display device.
DP1 and a drive unit 80 for selectively lighting vertically (horizontally and horizontally) cells (display elements) C constituting a screen (screen) ES as a display area,
It is used as a wall-mounted television receiver and a monitor of a computer system.

The exemplary PDP 1 comprises a pair of first and second
Are arranged in parallel, and in each cell C, the main electrode X, Y and the address electrode A as a third electrode cross each other to form a "3-electrode surface discharge structure" PDP. Main electrode X,
Y both extend in the row direction (horizontal direction) of the screen, and one main electrode Y is used as a scan electrode for selecting a cell C in a row unit at the time of addressing. The address electrode A extends in the column direction (vertical direction), and is used as a data electrode for selecting a cell C in a column unit. The area where the main electrode group and the address electrode group intersect is the screen ES.

The drive unit 80 includes a scan controller 81, a common driver controller 82, a data processing circuit 83, a power supply circuit 84, an X scan driver 85, an X common driver 87, a Y scan driver 86, a Y common driver 88, and an address driver 89. have. To the drive unit 80, pixel-based field data DF indicating the luminance level (gradation level) of each color of R, G, and B is input together with various synchronization signals from an external device such as a TV tuner or a computer.

The field data DF is temporarily stored in the frame memory 830 of the data processing circuit 83, and is then divided into a predetermined number of subfields to form subfield data Dsf for gradation display, as described later. Is converted. The subfield data Dsf is stored in the frame memory 830 and transferred to the address driver 89 at a predetermined timing. The value of each bit of the subfield data Dsf is information indicating the necessity of lighting of the cell in the subfield, more specifically, information indicating the necessity of the address discharge.

The X scan driver 85 and the scan driver 86 are provided for individually applying a drive voltage to each of the main electrodes X and Y at the time of addressing. The X common driver 87 and the Y common driver 88 collectively apply a drive voltage to the main electrode pairs corresponding to each row of the screen when the lighting is maintained. The address driver 89 simultaneously applies a drive voltage to the address electrodes A corresponding to each column. These drivers are supplied with predetermined power from a power supply circuit 84 via a wiring conductor (not shown). The common driver controller 82 is provided with a drive waveform ROM that stores data that defines the timing of control signals to be supplied to the X common driver 85 and the Y common driver 88. The drive unit 80 is arranged on the back side of the PDP 1, and each driver and the electrodes are electrically connected by a flexible cable (not shown).

FIG. 2 is a perspective view showing the internal structure of the PDP 1 according to the present invention. In the PDP 1, a pair of main electrodes X and Y are arranged in each row on the inner surface of a glass substrate 11 which is a base material of a front-side substrate structure. A row is a horizontal cell column on the screen. The main electrodes X and Y each include a transparent conductive film 41 and a metal film (bus conductor) 42, and are covered with a dielectric layer 17 made of low melting point glass and having a thickness of about 30 μm. Magnesia (Mg) is formed on the surface of the dielectric layer 17.
An O) protective film 18 having a thickness of several thousand angstroms is provided. The address electrodes A are arranged on an inner surface of a glass substrate 21 which is a base material of the rear-side substrate structure, and are covered with a dielectric layer 24 having a thickness of about 10 μm. On the dielectric layer 24, one partition wall 29 having a height of 150 μm and having a linear band shape in plan view is provided between each address electrode A. The discharge space 30 is formed by these partition walls 29.
Are defined in the row direction for each sub-pixel (unit light-emitting area), and the gap size of the discharge space 30 is defined. Then, phosphor layers 28R, 28G, and 28B of three colors of R, G, and B for color display are provided so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29. ing. The discharge space 30 is filled with a discharge gas in which xenon is mixed with neon as a main component, and the phosphor layers 28R, 28G, and 28B are locally excited by ultraviolet rays emitted by xenon during discharge to emit light. One pixel (pixel) of the display is composed of three sub-pixels arranged in the row direction. The structure within each subpixel is cell C. Since the arrangement pattern of the partition walls 29 is a stripe pattern, a portion corresponding to each column in the discharge space 30 is continuous in the column direction across all the rows L. In order to prevent surface discharge interference in the column direction, the arrangement interval of the main electrode pairs is set to a value sufficiently larger than the surface discharge gap.

Hereinafter, P in the plasma display device 100 will be described.
The driving method of DP1 will be described. First, the outline of the gradation display and the driving sequence will be described, and then the addressing process to which the present invention is applied will be described in detail.

FIG. 3 is a diagram showing an outline of a first example of the driving sequence, and FIG. 4 is a diagram showing an outline of a second example of the driving sequence. The first example is a write address format, and the second example is an erase address format.

For example, in the display of a television image, in order to reproduce a gradation by binary lighting control, for example, eight fields f (a suffix of a code represents a display order) of each field f of a time series which is an input image. Subfield sf1,
sf2, sf3, sf4, sf5, sf6, sf7, s
Divide into f8. In other words, each field f forming the frame F is divided into eight subfields sf1 to sf8.
Replace with the set of However, when reproducing a non-interlaced image such as a computer output, each frame is divided into eight. And these subfields
The relative ratio of luminance at f1 to sf8 is 1: 2: 4:
Weights are set so as to be 8: 16: 32: 64: 128, and the number of sustain discharges in each of the subfields sf1 to sf8 is set. Since 256 levels of luminance can be set for each of the RGB colors by a combination of lighting / non-lighting in units of subfields, the number of colors that can be displayed is 256 ³ . It is not necessary to display the subfields sf1 to sf8 in the order of luminance weight. For example, optimization such as placing the subfield sf8 having a large weight in the middle of the display period can be performed.

The sub-field period Tsf assigned to each of the sub-fields sf1 to sf8 includes an addressing preparation period TR for making the charge distribution uniform, an address period TA for forming the charge distribution according to the display content, and a luminance according to the gradation level. , A sustain period TS for maintaining the lighting state in order to secure the lighting state. Of these, the address period TA
The present invention is deeply related to the present invention. In each subfield period Tsf, the length of the addressing preparation period TR and the address period TA is constant regardless of the luminance weight, but the length of the sustain period TS increases as the luminance weight increases.
That is, the total length of eight subfield periods Tsf corresponding to one field f is different from each other.

In the addressing preparation period TR,
A voltage pulse Prx1 of positive polarity is applied to the main electrode X, and a voltage pulse Pry1 of negative polarity is applied to the main electrode Y at the same time to forcibly generate a strong surface discharge over the entire screen. At the falling of the voltage pulses Prx1 and Pry1, self-discharge occurs due to excessive wall charges, and most wall charges disappear. After that, voltage pulses Prx2 and Pry2 having polarities opposite to those before are applied to the main electrodes X and Y to generate a surface discharge to form an amount of wall charges suitable for the address format.

In the address period TA, rows are selected line-sequentially, and priming pulses Ppx, Ppy and scan pulses Pax, Pay are sequentially applied to the main electrode pairs of the selected row. The priming pulse Ppx and the scan pulse Pax have a positive polarity and are applied to the main electrode X, and the priming pulse Ppy and the scan pulse Pay have a negative polarity and are applied to the main electrode Y. The pulse application timing is determined by the scan pulses Pax, P for the i-th row.
The application of the ay and the application of the priming pulses Ppx and Ppy to the (i + 2) -th row are delayed by a fixed time for each row so that they are simultaneously performed.

For example, in the case of a write address format, a priming discharge is generated to erase wall charges to such an extent that a sustain discharge does not occur, and to form a space charge contributing to priming. This space charge facilitates the occurrence of an address discharge in the cell where it occurs and a priming discharge in an adjacent cell. Subsequent to the priming discharge, an address discharge is generated only in the cells to be lit (the currently lit cells). The address discharge occurs only in the cells to which the address pulse Pa is applied to the address electrode A at the same time as the scan pulses Pax and Pay. By the address discharge, an amount of wall charges suitable for the sustain discharge is formed. In the case of the erase address format, unnecessary wall charges are erased by generating an address discharge only in cells to be turned off (currently non-lighted cells), and an amount of wall charges necessary for sustain discharge is left in the currently lighted cells. To

The priming discharge of the first selected row utilizes the space charge generated by the discharge in the addressing preparation period TR. Therefore, the addressing preparation process and the addressing process must not be separated from each other in time.

In the sustain period TS, all the address electrodes A are biased to a positive potential in order to prevent unnecessary discharge. In the case of the write address format shown in FIG. 3, a sustain pulse Ps2 having a positive polarity and a long pulse width is first applied to all the main electrodes Y. After that, a sustain pulse Ps is alternately applied to the main electrode X and the main electrode Y. The final sustain pulse Ps is applied to the main electrode Y. By applying the sustain pulses Ps2 and Ps,
Surface discharge occurs in the currently lit cell in which wall charges are formed in the address period TA. In the case of the erase address format shown in FIG. 4, the sustain pulse Ps2 is applied to all the main electrodes X first, and then the sustain pulse Ps is applied to the main electrodes Y and the main electrodes X alternately. The final sustain pulse Ps is applied to the main electrode Y. Sustain pulse P
Due to the application of s2 and Ps, surface discharge occurs in the cell where the wall charge remains in the address period TA.

Next, the voltage applied during the address period TA will be described in detail. FIG. 5 is a drive voltage waveform diagram of the first embodiment. In this figure, alphanumeric characters representing line numbers 1 to n are added to X and Y as signs of the main electrodes. In the following drawings, when it is necessary to distinguish individual electrodes, reference numerals are given in a similar manner.

At the start of the address period TA, wall charges of opposite polarity are present in substantially the same amount near the main electrode X and near the main electrode Y. [In the case of a write address type] A priming discharge is generated between the main electrodes. At this time, the priming pulse Pp
The voltage between the main electrodes (Vpx−Vpy + Vxyi) in consideration of the wall voltage at the time of applying x and Ppy exceeds the discharge start voltage between the main electrodes, and becomes a voltage for erasing the wall charges on the main electrodes X and Y. To Here, Vxyi is a wall voltage between the main electrodes due to wall charges. On the other hand, when an unnecessary discharge (counter discharge in the thickness direction of the panel) occurs between the address electrode A and the main electrode X or between the address electrode A and the main electrode Y,
Since a large amount of wall charges are formed on the address electrode A and hinder the address discharge, the voltage between the address electrode A and the main electrode X and the voltage between the address electrode A and the main electrode Y start discharging. Do not exceed voltage. Therefore, the maximum voltage (Vpx−Vba + Vaxi) applied between the address electrode A and the main electrode X during the priming discharge, and
The maximum voltage (V) applied between the address electrode A and the main electrode Y
aa−Vpy + Vayi) should not exceed the firing voltage. Here, Vba is a bias voltage of the address electrode A, Vaxi is a wall voltage between the address electrode A and the main electrode X, and Vayi is a wall voltage between the address electrode A and the main electrode Y. Further, by setting the potential of the address electrode A at the time of the priming discharge to a value close to the neutral potential of the main electrode pair, accumulation of wall charges on the address electrode A can be suppressed. Here, the value of Vpx + Vpy and Va
It is set so that the value of b + Va is close. Va is the peak value of the address pulse Pa.

The address discharge is generated between the address electrode A and the main electrode Y of the currently lit cell. Therefore, the applied voltage (Vaa-Vay) to the currently lit cell must be equal to or higher than the discharge starting voltage, and the applied voltage (Vab-Vay) to the non-lit cell this time must be equal to or lower than the discharge starting voltage. The voltage between the main electrodes (Vax-Vay) must be equal to or lower than the surface discharge start voltage, but is set to a value as large as possible. This is to increase the wall voltage between the main electrodes after the address discharge as much as possible.

In order to generate an address discharge, the applied voltage (Vaa-Vay) must be equal to or higher than the discharge starting voltage as described above. However, if the applied voltage is too high, an adjacent cell separated from the address electrode A by the partition 29 can be used. Discharge occurs with the main electrode Y. In order to avoid this address defect, the voltages Vaa and Vay must be set to such an extent that no discharge occurs between cells adjacent in the row direction. Further, the bias voltages Vxab and Vyab of the main electrodes X and Y are set to values at which unnecessary discharge does not occur, and are adjusted so that the spread of the discharge in the column direction becomes appropriate. [Erase address format] Priming pulse Pp
The voltage between the main electrodes at the time of applying x and Ppy (Vpx-
Vpy + Vxyi) is set such that a discharge having such an intensity that a wall charge required for the sustain discharge remains between the main electrodes. The potential setting between the address electrode A and the main electrodes X and Y is the same as in the case of the write address format.

To generate an address discharge, the voltage (V) between the address electrode A and the main electrode Y of the currently lit cell is used.
aa−Vay + Vayp) is equal to or higher than the firing voltage,
The voltage (Vba-Vay + Vayp) between the address electrode A and the main electrode Y of the non-lighting cell this time must be equal to or lower than the discharge starting voltage. Here, Vayp is a wall voltage between the address electrode A and the main electrode Y remaining after the priming discharge. The voltage between the main electrodes (Vax-Vay +
Vxyp) must be less than or equal to the starting voltage of surface discharge,
In addition, it is necessary to sufficiently reduce the wall voltage between the main electrodes after the address discharge. Vxyp is a wall voltage between the main electrodes remaining after the priming discharge.

FIG. 6 is a schematic diagram of a main electrode arrangement according to the second embodiment. In the structure in which the partition walls 29 are arranged in a stripe shape as described above, since the discharge space 30 is continuous in the column direction, the discharge in a row adjacent to the discharge in each row affects. Screen E
When the same number of main electrode pairs as the number of rows of S are arranged, other main electrode pairs exist only on one side in the first row and the last row, and therefore, other main electrode pairs exist on both sides. Lines and operating conditions are slightly different. Therefore, it is preferable to provide at least one or more main electrode pairs outside the screen ES to make the operating conditions of each row of the screen ES uniform. In the example of FIG. 6, auxiliary main electrodes DY1 and DX1 are arranged outside the main electrodes Y1 and X1 in the first row, and auxiliary main electrodes DY2 and DX2 are arranged outside the main electrodes Yn and Xn in the last row.

FIG. 7 is a drive voltage waveform diagram of the second embodiment. In the address period TA, the auxiliary main electrodes DY1, D
X1, DY2, DX2 are regarded as the main electrodes X, Y, and the priming pulses Ppx, Ppy and the scan pulses Pax,
Pay is applied. That is, first, the auxiliary main electrode DY
1 and DX1, a priming discharge is generated, and the main electrodes X1 and Y1 in the first row and the main electrodes X2 and
In the order of Y2, between the main electrodes in each row and the auxiliary main electrodes DY2, DX
A priming discharge occurs between the two. Application of scan pulses Pax and Pay to the i-th row and (i +
2) Priming pulses Ppx, Pp for the second row
It is the same as in the first embodiment that the pulse application timing is delayed by a fixed time for each row so that the application of y is performed at the same time.

Auxiliary main electrodes DY1, DX1, DY2, DX
If the wall charges remain in 2, erroneous lighting occurs in the subsequent sustain period TS. Therefore, in the case of the write address format, when the scan pulses Pax, Pay are applied to the auxiliary main electrodes DY1, DX1, DY2, DX2, regardless of the currently lit cell and the currently non-lit cell, as shown in FIG. The address pulse Pa is not applied to the address electrode A. Conversely, in the case of the erase address format, the address pulse Pa is applied regardless of the currently lit cell and the currently non-lit cell.
Is applied to erase the wall charges.

The auxiliary main electrodes DY1, DX1, DY
2. When a plurality of pairs DX2 are provided on both sides of the screen ES, the application timings of the priming pulses Ppx and Ppy and the scan pulses Pax and Pay may be common to the auxiliary main electrode groups on each side.

FIG. 8 is a drive voltage waveform diagram of the third embodiment. According to the driving method of the present invention, if the first priming discharge in the address period TA does not occur, the subsequent priming discharge may not occur continuously over a plurality of rows. Therefore, it is extremely important to ensure that the first priming discharge occurs. In order to increase the reliability of the minimum priming discharge, the pulse width w2 of the priming pulses Ppx2 and Ppy2 to be applied first should be longer than the normal width w1 as shown in FIG. The reason why the discharge does not occur is that the discharge delay is larger than the pulse width w2, so that the longer the pulse width w2, the more reliably the discharge occurs.

Incidentally, as in the second embodiment, the auxiliary main electrode D
When Y1, DX1, DY2, and DX2 are provided and the first priming discharge is generated between the auxiliary main electrodes DY1 and DX1, the pulse width w2 of the priming pulses Ppx2 and Ppy2 applied to the auxiliary main electrodes DY1 and DX1 is increased. I just need.

FIG. 9 is a configuration diagram of a plasma display device 100b according to the fourth to sixth embodiments. In the figure, components having the same functions as in the example of FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the description thereof will be omitted or simplified.

The plasma display device 100b is an AC type P
It is composed of DP1 and a drive unit 80b. The drive unit 80b includes a scan controller 81b, a common driver controller 82b, a data processing circuit 83,
A power supply circuit 84, two X common drivers 87A and 87B,
It has a Y scan driver 86, a Y common driver 88, and an address driver 89.

In the plasma display device 100b, the main electrode X
Are divided into a set of odd-numbered rows and a set of even-numbered rows, and are electrically shared for each set. Electrical commonization of the main electrode X is performed by wiring on the panel, internal wiring of the X common drivers 87A and 87B, or wiring on a connection cable. The X common driver 87A applies a drive voltage to the odd-numbered main electrodes X at a time, and the X common driver 87B applies a drive voltage to the even-numbered main electrodes X at a time.

By sharing the main electrode X, the drive circuit can be simplified. That is, in the X scan driver 85 in the example of FIG. 1, several hundreds of rows are selectively selected, so that the circuit scale is inevitably increased. Usually LS
However, even if an LSI is used, the mounting area is large and the circuit cost is high. Therefore, if only one of the main electrode pairs can be driven by the common driver, circuit cost can be reduced.

FIG. 10 is a drive voltage waveform diagram of the fourth embodiment. The potential of each main electrode X in the address period TA is
Any value may be used except when a discharge is generated in the corresponding cell and when a discharge is generated in a cell adjacent in the column direction. That is, any period other than the period from one address cycle before the priming discharge to one cycle after the address discharge can be set arbitrarily. Therefore, the main electrode X
If the potential (Vpx) at the time of priming discharge and the potential (Vax) at the time of address discharge can be made equal to each other, FIG.
Driving by applying a voltage having a waveform such as 0 is possible. With this drive waveform, the potentials of the odd-numbered main electrodes Xodd are equal and the potentials of the even-numbered main electrodes Xeven are equal in the address period TA, so that the scan driver that selects each main electrode X It becomes unnecessary.

When an auxiliary main electrode is provided, a drive voltage having the same waveform as that of the even-numbered main electrode Xeven is applied to all auxiliary main electrodes on the side adjacent to the main electrode pair in the first row of the screen.
A drive voltage having the same waveform as that of the odd-numbered main electrode Xodd is applied to all auxiliary main electrodes adjacent to the main electrode pair in the last row.

FIG. 11 is a drive voltage waveform diagram of the fifth embodiment. With the driving waveform of the above-described fourth embodiment, the potential of the main electrode X changes for each address cycle, so that the reactive power due to charging and discharging of the floating capacitance of the cell increases. Therefore, the address period TA is divided into a first half TA1 and a second half TA2, and priming pulses Ppx, Ppy and scan pulses Pax, Pay to odd-numbered main electrode pairs are applied in the first half TA1, and even-numbered main electrode pairs are applied. The application of the priming pulses Ppx, Ppy and the scan pulses Pax, Pay to the second half TA2 can reduce the number of potential changes of the main electrode X.

In the example of FIG. 11, the first half TA1 and the second half T
A priming period TP is provided between A2 and A2, and a priming discharge is generated in the auxiliary main electrode pair on the first row side during the priming period TP. In other words, a discharge is generated in the auxiliary main electrode pair near the second row selected first in the second half TA2 to form space charges that contribute to priming for the first priming discharge in the second half TA2.

The priming discharge in the auxiliary main electrode pair is caused by the voltage pulse P in the addressing preparation period TR.
It is generated by the same pulse as rx, Pry. Thus, the sustain period TS after the wall charge is erased
To prevent unnecessary discharge at

FIG. 12 is a drive voltage waveform diagram according to the sixth embodiment. In the example of FIG. 12, not only the addressing but also the addressing preparation is performed in a time-division manner by dividing into odd rows and even rows. That is, first, the first addressing preparation period T
In R1, for example, the charge distribution is made uniform for the odd-numbered rows, and then the odd-numbered rows are addressed in the first address period TA1. Next, in the second addressing preparation period TR2, the charge distribution is made uniform in the remaining rows (for example, even rows), and then the second address period TA
In step 2, the addressing of the even-numbered rows is performed.

[0054]

According to the first to eighth aspects of the present invention,
Addressing reliability can be improved while avoiding an increase in required time.

According to the second aspect of the present invention, it is possible to make the operating conditions of each line in the screen uniform and to improve the display quality. According to the third, fourth, seventh, or eighth aspect of the present invention, it is not necessary to individually control one of the main electrode pairs, so that the drive circuit can be simplified.

According to the fifth or sixth aspect of the present invention, a space charge that produces a priming effect can be reliably formed, and the reliability of addressing can be further improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a plasma display device according to a first embodiment.

FIG. 2 is a perspective view showing an internal structure of a PDP according to the present invention.

FIG. 3 is a diagram illustrating an outline of a first example of a driving sequence.

FIG. 4 is a diagram showing an outline of a second example of the driving sequence.

FIG. 5 is a drive voltage waveform diagram of the first embodiment.

FIG. 6 is a schematic diagram of a main electrode arrangement according to a second embodiment.

FIG. 7 is a drive voltage waveform diagram of the second embodiment.

FIG. 8 is a drive voltage waveform diagram of the third embodiment.

FIG. 9 is a configuration diagram of a plasma display device according to fourth to sixth embodiments.

FIG. 10 is a drive voltage waveform diagram of the fourth embodiment.

FIG. 11 is a drive voltage waveform diagram according to a fifth embodiment.

FIG.

[Explanation of symbols]

1 PDP X, Y Main electrode A Address electrode (third electrode) 30 Discharge space ES screen TA Address period TA1 First address period TA2 Second address period Ppx, Ppy Priming pulse Pax, Pay scan pulse Pa Address pulse DX1, DX2 , DY1, DY2 Auxiliary main electrode (auxiliary electrode) Ppx2, Ppy2 Priming pulse

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenji Awamoto 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kenji Ishiwatari 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Koichi Sakita 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Limited (72) Inventor Kunio Takayama 4, Kami-Odanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 1-1 1-1 Fujitsu Co., Ltd. (72) Inventor Kazu Inoue 4-1-1 1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Seiichi Iwasa 4 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Chome 1-1 Fujitsu Limited

Claims (8)

[Claims] 1. A plurality of first and second main electrodes are arranged so as to form an electrode pair for generating a surface discharge for each row of a matrix display, and a third electrode is arranged for each column. And a method of driving an AC-type PDP in which a discharge space is continuous over the entire length of a screen in a column direction. After applying a voltage for causing a priming discharge to the electrode pair, applying a voltage for causing an address discharge only to the cell whose charge state needs to be changed, and selecting the ith selection order. Simultaneously with the application of the voltage to cause an address discharge to the cells of a row, (i +
2) A method of driving an AC-type PDP, wherein the voltage for generating a priming discharge is applied to the electrode pairs in a row on or after the first row. 2. An at least one auxiliary electrode pair having the same configuration as the electrode pair is provided outside the screen in the column direction, and in the address period, the auxiliary electrode pair in the first row is selected in the first order in the address period. The AC type P according to claim 1, wherein the voltage for generating a priming discharge is applied to the auxiliary electrode pair before the voltage for generating a priming discharge is applied.
Driving method of DP. 3. In the address period, the first main electrodes of odd-numbered rows are electrically shared with each other, and the first main electrodes of even-numbered rows are electrically shared with each other. When applying the voltage for causing an address discharge to the cells of the odd-numbered rows, the first main electrodes of the odd-numbered rows are biased to a first potential, and the first main electrodes of the even-numbered rows are biased. When the first main electrode is biased to a second potential and the voltage for causing an address discharge to be applied to the cells in the even-numbered rows is applied, the first main electrodes in the odd-numbered rows are connected to the second main potential. 3. The method of driving an AC type PDP according to claim 1, wherein the bias is biased to two potentials and the first main electrodes in the even-numbered rows are biased to the first potential. 4. In the address period, a row is divided into an odd-numbered group and an even-numbered group, and a charge distribution according to display contents is formed for each group in a time-sharing manner. 3. The voltage for generating a priming discharge to the auxiliary electrode pair near the first selected row of the subsequent set between the formation and the formation of the subsequent set.
The driving method of the AC type PDP described in the above. 5. The AC type according to claim 1, wherein in the address period, the first application time of the voltage for causing the priming discharge is longer than the second and subsequent application times. Driving method of PDP. 6. The address period, wherein a time for applying the voltage to the auxiliary electrode pair is longer than a time for applying the voltage to the electrode pair in a row belonging to the subsequent set. The driving method of an AC type PDP according to claim 4 or 5. 7. A plurality of first and second main electrodes are arranged so as to form an electrode pair for generating a surface discharge for each row of the matrix display, and a third electrode is arranged for each column. A method of driving an AC-type PDP in which a discharge space is continuous over the entire length of a screen in a column direction, wherein a row is divided into an odd-numbered group and an even-numbered group, and one of the groups is charged, uniformed, and displayed. After the formation of the charge distribution according to the first set, the charge distribution and uniformization of the other set and the formation of the charge distribution according to the display content are performed. The first address for forming the charge distribution of the one set In each of the period and the second address period forming the other set of charge distribution, a voltage for causing a priming discharge to be applied to the electrode pair is applied to each row, and thereafter, the charge state is changed. Cells that require Applying a voltage for generating the address discharge in only, simultaneously with the application of the voltage to the selection order cause an address discharge for j th of said cell line, (j +
2) A method of driving an AC-type PDP, wherein the voltage for generating a priming discharge is applied to the electrode pairs in a row on or after the first row. 8. The AC type according to claim 7, wherein in each of the first and second address periods, the first application time of the voltage for causing a priming discharge is longer than the second and subsequent application times. Driving method of PDP.