JPH10200783A - Frame synchronizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the frame synchronizer that generates no surpass noise with a small memory capacity even when prediction of surpass is difficult in the case that an interlace input image signal is outputted with a synchronization frequency different from the input frequency. SOLUTION: An address comparison section 33 detects surpass due to write and prevent a surpass noise due to write by stopping the write. Furthermore, a write control section 31 stores at least one complete odd number field image and read of an odd field is conducted by the complete odd number field image and an interpolation image generating section 35 interpolates the image of the odd number field, and even when a complete even number field image is not available, the odd number field image is used in place of the even number field image so as to prevent occurrence of surpass due to read and then the required memory size is suppressed into a size for three fields.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronizer for outputting an interlaced image signal at a synchronization frequency different from that of an input signal.

[0002]

2. Description of the Related Art A frame synchronizer outputs an input image signal at a phase independent of the input, and is used for the purpose of outputting an image signal at a synchronization frequency different from the input.

When an image signal is output at a synchronous frequency different from that of an input image signal, the writing and reading speeds are different. Therefore, the same output can be obtained by overwriting the read address or by overwriting the write address. Images of different frames are output to the screen, and passing noise occurs at the boundaries. Here, a frame is an image composed of two fields, and it is assumed that a field which is one image transmitted by one vertical scan includes an odd field and an even field.

As a method of preventing this overtaking, there is a method of controlling reading and writing by using an image memory for four fields so as to read from a memory (one field) where writing is not performed. The method was as shown in the proceedings 7-7 of the National Assembly of the Society.

There is also a method of predicting the occurrence of overtaking from the phase difference between the input and output vertical synchronization signals and the synchronization frequency, and stopping the writing at the frame where the occurrence of overtaking is predicted. For example, Japanese Patent Laid-Open No. 7-203383 discloses a method. The method was as disclosed.

[0006]

However, the method of using a memory for four fields (two frames) in the above-mentioned prior art has a problem that it requires a large amount of memory and is costly.

In the method of predicting the overtaking, if the writing interval is not constant or if the synchronization frequency of the input image signal fluctuates, the occurrence of the overtaking cannot be predicted. There was a problem that it could not be prevented.

First, the principle of generating passing noise will be described. FIG. 11 shows an example in which writing overtakes reading. In the case of FIG. 11, since writing is fast, the n-th frame before overtaking and the (n + 1) -th frame after overtaking are simultaneously displayed on the same screen, and as shown in FIG. Different frame boundaries are displayed. This is overtaking noise.

Next, FIG. 12 shows an example in which an overtaking that is difficult to predict occurs due to a change in the input synchronization frequency. While there is no change in the input synchronization frequency, overtaking can be predicted from the relationship between the input and output synchronization frequencies, but after the fluctuation, prediction is performed using a value different from the actual synchronization frequency, so that it is difficult to predict overtaking. Similarly, when writing to the memory after performing image processing, the speed of writing,
It is also difficult to predict the overtaking even when the speed is caused by the processing.

The inventor of the present invention has focused on the fact that, when reading is not performed from a field in which writing has already been performed and writing is about to overtake reading, if writing is interrupted, overtaking does not occur. I decided to take the method. In addition, by using the interpolated image as a substitute image for the even field, the above method can be performed with a memory size for three fields.

The present invention has been made in view of the above problems, and its object is to
An object of the present invention is to provide a frame synchronizer in which the memory size is reduced to three fields (1.5 frames) and no overtaking noise is generated even when it is difficult to predict the occurrence of overtaking.

[0012]

According to the present invention, the above-mentioned problems are solved by the following means.

In the frame synchronizer according to the first aspect of the present invention, an image memory size is reduced by providing an interpolated image generation unit, an address comparison unit detects the occurrence of overtaking, and a field memory read out by the write control unit based on the detection. The overtaking is prevented by determining the area and controlling the writing.

More specifically, the frame synchronizer according to claim 1 compares an image memory having a field memory area for storing input image data in units of fields with a read address and a write address for the image memory. An address comparison unit that detects overtaking of the read address by the write address;
An image data output from the image memory is input, an interpolated image generating unit for generating interpolated image data based on the input image data, and outputting the interpolated image data, and a field memory area of the image memory for reading out And outputs an output select signal for instructing which of the image data and the interpolated image data is output. When the overtaking is detected, the writing operation to the image memory is interrupted. A write control unit, a read control unit that controls a read operation on the field memory area specified by the read area signal, an input of the image data and the interpolated image data, and selection of an output based on the output select signal And an output selector unit for outputting output image data. It is intended.

According to a second aspect of the present invention, in the frame memory, the write control unit has an odd field flag and an even field flag for each area of the image memory, and by reading and writing these, the determination of the field memory area to be read is simplified. Hardware.

[0016]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG.

First, a method of controlling a frame synchronizer that does not generate overtaking noise even when it is difficult to predict overtaking will be described below.

FIGS. 5 to 7 are diagrams showing a state of control for overtaking noise prevention. The image memory 30 shown in FIG. 1 is divided into three areas of field memory areas 60, 61 and 62 (each of which has a capacity of one field). FIG. 5 is a diagram showing a state of a temporal change of a write address 41 and a read address 42.

As for reading, it is necessary to display the screen continuously, so that it cannot be delayed or interrupted. Therefore, as there is no guarantee that the writing will be completed before the completion of the reading, it is not possible to read the field that is already being written because it leads to overtaking.
Therefore, in the case where the next memory area cannot be read due to writing being performed in the memory area corresponding to the field to be read next, the present embodiment deals with the following.

(I) If the next field to be read is an odd field, the field is read from the one in which the complete picture of the odd field (not being written) is stored in each memory area. FIG. 5 shows a diagram corresponding to this case. Here, even if reading of the field memory area 61 is completed, since writing is performed in the next field memory area 62, the odd field flag 52
Is read out next.

It is to be noted that control is performed so that even if the writing of the even field is interrupted, the next memory area is not written even if the writing of the even field is interrupted. Prevent writing to the memory area where the next complete odd field screen is stored.

(Ii) If the next field to be read is an even field, the even field screen of the same frame as the field just read (usually an odd field) must be read. If this even field is completely written in the memory area to be read next, it will be read. If not,
If some memory area has a complete even-numbered field screen, a total of four fields of memory is required. Therefore, instead of the screen of the even field, a screen obtained by line interpolation of the odd field screen of the same frame is used, and a total of three fields (1.5
(Frames) of memory, and reduce the memory size.

FIG. 6 shows a corresponding example. Here, the even-numbered field of the n-th frame corresponding to the already-read odd-numbered field of the n-th frame of the field memory area 61 is still being written to the field memory area 62 and cannot be read. Therefore, the field memory area 61 is read out again, interpolated and output.

Regarding writing, there is no particular problem even if the writing is interrupted, since only the input data is lost. Therefore, it is possible to start writing to a memory area that has already been read (preceding the read address). However, if the write address overtakes the read address, noise is generated. Therefore, when this overtake is detected, it is necessary to stop the write there. Beginning of the next frame (start of the odd field) since the complete odd field screen must be left
When writing is restarted from the beginning, the address needs to be set at the head of this area before writing is restarted in order to write in the same area where the writing was interrupted and read it out.

FIG. 7 shows a corresponding example. Here, the writing of the even-numbered field of the n-th frame is performed in the field memory area 60, but the reading of the odd-numbered field of the (n-1) -th frame is overtaken, so that the writing is stopped. Then, when the odd-numbered field of the (n + 1) th frame is input, the address is returned to the field memory area 60 and writing is resumed.

In the following, a configuration of the frame synchronizer for performing the above-described control and details of control using the configuration will be described.

The read area signal, an output dot clock for timing readout from the image memory and the output vertical synchronizing signal are inputted, and the read address and read control for the field memory area specified by the read area signal are input. A read control unit that outputs a signal; and an output selector unit that receives the image data and the interpolated image data as input, selects an output based on the output select signal, and outputs output image data. Frame synchronizer.

FIG. 1 shows a configuration diagram of a frame synchronizer of the present invention. The frame synchronizer 10 includes an image memory 30, a write control unit 31, a read control unit 32,
It comprises an address comparison unit 33, an interpolation image generation unit 35, and an output selector unit 36.

The image memory 30 stores the input image data 11. Here, a configuration using a two-port memory is shown. The image memory 30 only needs to have a capacity of 1.5 frames, and control is performed by dividing this into three areas of one field (0.5 frame).

The read control section 32 outputs a read address 42 and a control signal 44 such as a read enable signal to the image memory 30 to control reading. The read control unit 32 sets the read address 42 so as to read from the area of the image memory 30 designated by the read area signal 46, and reads one image data from the image memory 30 at every rising of the output dot clock 17, Each time the read address 42 is incremented.

The address comparing section 33 compares a read address and a write address with respect to the image memory 30, and
When the write address 41 and the read address 42 are addresses in the same memory area of the image memory 30 and the write address 41 has a value equal to or larger than the read address 42, the write control unit 31
5 is output to notify the occurrence of overtaking.

The interpolation image generator 35 generates a line interpolation image of the image data read from the image memory 30.
Specifically, the line memory 70, the adder 71, and the shifter 7
It consists of two. The read image data is added to an adder 71.
And the line memory 70 at the same time. The adder 71 and the shifter 72 calculate the average of the image data read directly and the image data delayed by one line through the line memory 70, and output the average.

The output selector 36 selects the image data read from the image memory 30 and the interpolated image output from the interpolated image generator 35 by the output select signal 47 from the write controller 31. Data 1
Output as 5.

The write controller 31 controls the writing by outputting a write address 41 and a control signal 43 such as a write enable signal to the image memory 30. Also,
With respect to the three areas of the image memory 30, which area of the image data is read is also determined.

A read area signal 46 for designating the field memory areas 60 to 62 of the image memory 30 to be read is output, and an output select signal 47 for instructing which of the image data and the interpolated image data is to be output is output.

Based on the write reset signal 45, the address is returned to the head of the field memory area being written, and the write operation to the image memory 30 is interrupted.

The write control section 31 includes an input even / odd signal 14 indicating whether the input image data is data of an even field or an odd field, and an input vertical synchronization signal 12.
An output even / odd signal 18 indicating whether the output image data is data of an even field or an odd field;
An output dot clock 17, an output vertical synchronization signal 16,
A write reset signal 45 is input, and a read area signal 46, an output select signal 47, and a write control signal 43
And the write address 41 are output.

FIG. 2 shows the configuration of the write control unit 31.
The write control unit 31 includes a write area register 50, an input even / odd register 51, a read area register 54, an output even / odd register 55, a flag control unit 70, a write area control unit 71, a read area control unit 72, and a memory control unit 7.
3. It is composed of a field flag section 74, and the field flag section 74 is composed of an odd field flag 52 and an even field flag 53.

FIG. 3 shows a flowchart relating to the writing control. When the start of each field is detected by the input vertical synchronization signal 12 (step 100), the process proceeds to step 101.

In step 101, it is checked whether or not the writing of the even-numbered field is repeated. The write area control unit 31 has an input even-odd register 51 in which the value of the input even-odd signal 14 at the time of writing is stored, and even-number fields are repeated from the beginning for some reason. When there is such an input, when the next area is reached, the input even-odd signal 14 and the value of the input even-odd register 51 are recognized as an even number, and this is recognized.

If an even number of consecutive shots is not detected in step 101, the process proceeds to step 102, where data is written to the image memory. The memory control unit 31 sets the input image data 11
Is written to the image memory 30, and the write address 41 is incremented each time.

The write control section 31 has an odd field flag (OF) 52 and an even field flag (EF) 53 for each of the three areas of the image memory 30, and controls based on these.

The odd field flag 52 and the even field flag 53 have an odd field,
This is a flag indicating that a complete screen of an even field is stored.

Each time writing is performed in step 102, the flag control unit 70 outputs a flag control signal 82 to clear the odd field flag 52 and the even field flag 53.

In step 103, 1 is set in step 102.
Each time a dot is written, it is checked whether writing for one field has been completed. More specifically, the completion of the write is determined by the flag control unit 70 when the input even / odd signal 14 indicates an odd number and the input vertical synchronization signal 12 is in a blanking period.

The write control section 31 has a write area register (WA) 50 indicating which area is currently being written, and the write area control section 71 reads and writes the write area register 50. . Basically, when the writing of one field is completed, the writing area control section 71 increments the writing area register 50 and proceeds to step 107.

In step 107, the input even-odd register 5
1 determines whether the field written is even or odd, and outputs a flag control signal 82. If the field is odd, the flag control unit 70 sets the odd field flag 52 (OF = 1). If there is, the even field flag 53 is set (EF = 1).

The write area control section 71 outputs the contents of the write area register 50 as a write area signal 80. When the write area changes, the memory control section 73 outputs the write address 41 based on the change of the write area signal 80. Is set at the beginning of the memory area indicated by the write area signal 80, and then writing to the next area is started.

If it is determined in step 103 that writing for one field has not been completed, step 104
Then, the relationship between the write address 41 and the read address is checked. The write area control unit 71 permits the start of writing to an area from which reading has already been performed in order to avoid unnecessary stoppage of writing.
However, the address comparison unit 33 determines that the write address 41
Detects that the data passes the read address 42 (the addresses match in the same area) and outputs the write reset signal 45. If the write reset signal 45 is output, the process proceeds to step 105; Done.

If an even number detects a continuous fire in step 101 or an overtaking is detected in step 104,
In step 105, the control of writing is stopped until the beginning of the next frame (the start of the odd field). For this purpose, the write area control unit 71 stops the write control of the memory control unit 73 by the write stop signal 81, and the memory control unit 73 sets the write address 41 to the area where the write is currently performed (pointed by the write area pointer). Area).

Then, in step 106, when the beginning of the next frame comes, the write area control unit 71 releases the output of the write stop signal and restarts the write. this is,
This is to ensure that a complete odd field remains in the image memory 30.

The writing control is completed as described above. Next, a control flowchart for determining the read area is shown in FIG.

When the start of reading of each field is detected by the output vertical synchronization signal 16 (step 110),
Move to step 111.

In step 111, it is checked whether or not the reading of the even or odd field is repeated. The read area control section 72 has an output even-odd register 55, and detects a continuous fire in the same manner as in the case of an even write.

The read area control section 72 has a read area register (RA) 54 indicating which area is currently being read, and the read area control section 72 reads the read area signal 46 in accordance with the read area register (RA) 54. Output to the control unit 32. The read area register 54 takes a value from 0 to 2 similarly to the write area register 50, and is returned to 0 after 2.

If the continuous reading of the even field is detected in step 111, the reading area register 5
4 is left as it is, and if no value is detected, the value is incremented (RA = RA + 1), and the process proceeds to step 112.

In step 112, the output even-odd signal 1
8 is used to determine whether to output as an even field or an odd field.

If it is determined in step 112 that the field is an odd field, the value of the read area register 54 is decremented in step 118 until an area in which the odd field flag 52 is set is found. If the odd field flag 52 is set in the area indicated by the read area pointer 54, the write control unit 31 outputs a read area signal 46 having the same contents as the read area register 54 to the read control unit 32. Thus, the read control unit 32 reads the image data in the area indicated by the read area signal 46.

If the field to be read is an even field, the read area register 5
It is checked whether the even-numbered field flag 53 of the area indicated by 4 is set.

If set, a read area signal 46 having the same contents as the read area pointer 54 is output to the read control unit 32. If it is not set, it means that the complete even field that was being read has not been completed, so the read area register 54 is decremented to the area just read (corresponding to the odd field), and step 116 Move on to Then, the read area signal 4 having the same content as the read area register 54
6 is output to the read control unit 32, and an output select signal 47 for selecting the output of the interpolation image generation unit 35 is output to the output selection unit 36. This is because an image of an odd field is interpolated because a necessary even field image does not exist, and is used instead.

The read area control unit 72 determines the end of reading of one field based on the input indicating the retrace period of the output vertical synchronization signal 16.

By performing the above control, data can be output without generating passing noise even when it is difficult to predict passing, such as when the input synchronization frequency fluctuates or the interval between input data is not constant. The required memory size can be reduced to three fields.

Further, the frame synchronizer according to the present invention does not require a hardware change or a setting change corresponding to the change even when a different combination is used for the input / output synchronization frequency. However, there is an advantage that a single frame synchronizer can cope with various systems.

FIG. 9 shows a frame synchronizer using PAL-NT.
FIG. 3 shows a configuration diagram in a case where the present invention is used for an up (down) converter for converting an input / output synchronization frequency like an SC.

The up-converter includes, for example, an A / D converter 1 relating to an input image signal such as PAL, an input sync separation unit 2, an input dot clock generation unit 3, an input even / odd determination unit 4, and an output image such as NTSC. Related to signal
It comprises a D / A converter 5, an output synchronization generator 6, an output dot clock generator 7, an output even / odd signal generator 8, and a frame synchronizer 10.

The input image signal is A / D converted by the A / D converter 1 and input to the frame synchronizer 10 as input image data 11. In addition, an input vertical synchronizing signal 12, an input dot clock 13, and an input even / odd signal 14 are respectively generated by an input sync separation unit 2, an input dot clock generation unit 3, and an input even / odd determination unit 4 based on an input image signal, and the frame synchronizer 10 Is input to

The output vertical synchronizing signal 16, the output dot clock 17, and the output even / odd signal 18 are output from the output synchronizing generator 6, the output dot clock generating unit 7, and the output even / odd generating unit 8, respectively.
Is generated and input to the frame synchronizer 10.

The output image data 15 output from the frame synchronizer 10 is D / A converted by a D / A converter, mixed with an output vertical synchronization signal 16 as an output image signal, and output.

The frame synchronizer 10 outputs the input image data 11 as output image data 15 in synchronization with the output vertical synchronization signal 16. For example, in the case of a PAL-NTSC up converter, the synchronous frequency is converted from 50 Hz to 60 Hz and output. In this case, naturally, the input image is insufficient, so that the frame synchronizer 10
Uses the whole frame or a part (one field) of the same frame repeatedly. Conversely, 60Hz with down converter
In the case where the input image is converted to 50 Hz, the input image is left over, and the frame synchronizer thins out the input image.

FIG. 8 is a block diagram showing the case where the frame synchronizer of the present invention is used in a system for performing image processing such as mapping. The difference from the example of FIG. 9 is that the input image data 11 and the input dot clock 13 are output from the image processing unit 20 in that the input dot clock generation unit 3 has the image processing unit 20. Is gone. Here, the interval at which the image processing unit 20 outputs the input image data 11 is not constant because it depends on the processing. In such a case, overtaking may occur even when the synchronization frequency is the same for input and output, which is one of the cases where it is difficult to predict the overtaking. Even in such a case, the frame synchronizer of the present invention can prevent passing noise.

[0071]

According to the frame synchronizer of the present invention, the address comparing unit detects overtaking due to writing and interrupts the writing to prevent overtaking noise due to writing. In addition, the writing control unit stores one complete odd field screen, so that the reading of the odd field is performed only for the complete odd field screen, and the interpolation of the odd field screen by the interpolation image generation unit is performed. Even when there is no complete even-numbered field screen, it replaces the even-numbered field screen, prevents overtaking by reading, and reduces the required memory size to three fields. As a result, there is an effect that no overtaking noise is generated even when it is difficult to predict the overtaking, and a large memory size is not required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frame synchronizer of the present invention.

FIG. 2 is a configuration diagram of a writing control unit.

FIG. 3 is a control flowchart for writing.

FIG. 4 is a control flowchart for reading.

FIG. 5 is a diagram showing an address flow at the start of reading of an odd field.

FIG. 6 is a diagram showing a flow of addresses when using an interpolated image;

FIG. 7 is a diagram showing an address flow when writing is stopped due to overtaking detection.

FIG. 8 is a configuration diagram of an image processing system using a frame synchronizer of the present invention in the embodiment.

FIG. 9 is a configuration diagram of an up (down) converter using the frame synchronizer of the present invention.

FIG. 10 is a diagram showing an example of occurrence of passing noise

FIG. 11 is an explanatory diagram of the cause of overtaking noise.

FIG. 12 is a diagram showing an example in which it is difficult to overtake prediction

[Description of Signs] 10 frame synchronizer 11 input image signal 12 input vertical synchronization signal 13 input dot clock 14 input even / odd signal 15 output image data 16 output vertical synchronization signal 17 output dot clock 18 output even / odd signal 30 image memory 31 write control unit 32 Read control unit 33 address comparison unit 35 interpolation image generation unit 36 output selector unit 41 write address 42 read address 43 write control signal 44 read control signal 45 write reset signal 46 read area signal 47 output select signal 50 write area register 51 input even-odd register 52 Odd field flag 53 Even field flag 54 Reading area register 55 Output even / odd register 60, 61, 62 Field memory area 70 Flag control unit 71 Write area control unit 72 Read area control unit 73 Memory control unit 80 Write area signal 81 Write stop signal 82 Flag control signal

Claims (2)

[Claims] 1. An image memory having a field memory area for storing input image data in field units, an address comparing unit for comparing a read address and a write address with respect to the image memory, and detecting an overtake of the read address by the write address. An interpolated image generating unit that receives interpolated image data from the image memory, generates interpolated image data based on the input image data, and outputs the interpolated image data; A read area signal specifying a memory area is output, an output select signal indicating which of the image data and the interpolation image data is output is output, and when the overtaking is detected, a write operation to the image memory is performed. A write control unit to suspend, A read control section for controlling the read operation for the field memory area specified by the area signal out as input the interpolated image data and the image data, performs a select output on the basis of the output select signals,
A frame synchronizer comprising an output selector unit for outputting output image data. 2. The image processing apparatus according to claim 1, wherein the writing control unit has an odd field flag and an even field flag for each of the field memory areas of the image memory, and when the input image data is written to the image memory. Clears the odd field flag and the even field flag corresponding to the written field memory area, sets the odd field flag when writing the entire odd field, and finishes writing the entire even field. At time, the even field flag is set, and (i) when shifting the reading of the even field from the odd field,
If the even field flag has been set in the area next to the field memory area that has been specified until now, the area is specified by a read area signal, and an output select signal that specifies the output of the image data is output. If it is not set, the designated area is designated again, and an output select signal for designating the output of the interpolated image data is output. (Ii) When the reading of the odd field is started, the odd flag is set. 2. The frame synchronizer according to claim 1, wherein an output select signal for designating the output of the image data is designated by designating the field memory area in which is set.