JPH10178334A - Matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain precise synchronizing removal by small circuit constitution or processing by successively adding a product sum data group successively obtained between with an inverse spread code group concerning over sampling data by a product sum arithmetic means at a prestage by an adding arithmetic means at a poststage. SOLUTION: SR1 to SR8 are shift registers on each m(8) stage. Then, SR1 to SR8 time-sequentially store (delay) n×m (8×8) number of each revere spread data over-sampled by the 1/8 chip frequency of input. A product sum circuit consisting of residual constitution successively obtains product sums (correlated output) between n(8) number of each reverse spread data of every m(8) number of SR1 to SR8 and a reverse spread code C. In an arithmetic circuit 2 on a poststage, RG1 to RG8 time-sequentially store m-number of product sum data Σ1 with the timing of each 1/8 chip period of input. Each remaining adder circuit adds each product sum data RG1 to RG8 to obtain correlated data Σ2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a matched filter (M
and more particularly to a matched filter for obtaining the despread synchronization in a communication system for despreading a signal sequence spread with n spread code sequences with the same despread code sequence as the spread code sequence. .

2. Description of the Related Art In recent years, in mobile communication systems such as car phones and mobile phones, a conventional TDMA (Time Division Multipl
e-Access), DS-CDMA (Direct Spre) which is superior in fading countermeasure and can accommodate more subscribers.
Ad-Code Division Multiple Access) mobile communication systems have been actively researched and developed.
The present invention relates to an improvement in a matched filter (matched filter) suitable for use in cell synchronization acquisition and demodulation synchronization acquisition in a DS-CDMA mobile communication system.

[0003]

2. Description of the Related Art FIGS. 11 to 18 are diagrams (1) to (8) for explaining a conventional technique. FIG. 11A shows DS-CDMA.
FIG. 11B shows a partial configuration of a transmitter according to this method, and FIG. 11B shows a partial configuration of a receiver. In FIG. 11A, reference numeral 11 denotes a code generator (CG) for generating a spread code sequence C (t) having an n-chip period, 12 a multiplier (×), and 13 a D / A converter (D / A). , 14 are a modulation unit (MOD) by BPSK or the like, 15 is a transmission amplifier (TXA), and 16 is a transmission antenna.

The input transmission data is multiplied (primary modulation) by a spreading code sequence C (t) by a multiplier 12 and converted into spread data having an n-fold frequency. The spread data is subjected to D / A conversion by the D / A converter 13, secondarily modulated by the modulator 14, and transmitted via the transmission amplifier 15 and the transmission antenna 16. In FIG. 11B, 21 is a receiving antenna, 2
2 is an RF amplifier (RXA), 23 is a demodulation unit (DEM) using BPSK or the like, 24 is an A / D conversion unit (A / D), 25
Is a matched filter (MF), 26 is a peak detector (P
D) and 27 are code generators (CG) for generating the same despread code sequence C (t) as the above spread code sequence, and 28 is a multiplier (x).

The signal received by the receiving antenna 21 is RF-amplified by an RF amplifier 22, and second-order demodulated by a demodulation unit 23 by, for example, a synchronous detection method. This demodulated signal is supplied to the A / D converter 2
4 is subjected to A / D conversion to become despread data,
And the matched filter 25. The matched filter 25 performs a correlation operation between the input despread data and the despread code C, and outputs a correlation value sequence. Peak detector 2
6 detects a maximum peak of the correlation value sequence and generates a trigger signal TG at a corresponding timing. The code generator 27 generates a despread code sequence C (t) in synchronization with the trigger signal TG. Then, the multiplier 28 multiplies the input despread data by the despread code sequence C (t), and thus the same received data as the transmission data is reproduced.

FIG. 12 shows a timing chart of the code spreading / despreading process. The transmission delay from the transmitter to the receiver is ignored. The spreading code sequence C (t) is composed of a PN sequence having a 1 / n period (that is, a chip period Δt) sufficiently shorter than the symbol period T of the transmission data. In the transmitter, when the transmission data is multiplied by the spreading code sequence C (t) (corresponding to the addition of exclusive OR / mod2), the spreading data as shown is obtained. In the receiver, when the input despread data is multiplied by a synchronized despread code sequence (corresponding to the addition of exclusive OR / mod2), the same received data as the transmitted data is reproduced. However, if the input despread data is multiplied by a despread code sequence delayed in phase by, for example, one chip period Δt, the received data becomes a substantially random signal.

Therefore, in order to correctly demodulate the received data, it is necessary to match the phases of the despread data and the despread code sequence. The specification of this phase is called synchronization acquisition and utilizes the autocorrelation characteristics of the spread code sequence. It is done. FIG. 13 is a diagram for explaining the autocorrelation characteristics of the spreading code sequence. In general, PN (Pse
udorandom Noise) sequence is used. The PN sequence has the following properties. (A) Equilibrium: The difference between the appearance frequencies of "0" and "1" in one cycle is 1 or less. (B) Connectivity: One of the number k of "0" and "1" in one cycle is 1 / 2 ^k is present in a proportion of (c) correlation: when comparing each term by cyclically shifting the code sequence, the difference between the number of terms that do not match the match the number of terms to be 1: Figure 13 (a) is The table shows the autocorrelation output of an example spread code sequence.

[0008] This series "00011101" is a complete P
Although it is not an N-sequence, it has a short period and substantially satisfies the properties (a) to (c) of the PN-sequence, and is therefore adopted in the specific description of this specification for simplicity. The autocorrelation characteristics of this series “00011101” are as follows. Here, the calculation of the autocorrelation value is performed by converting the code “0” to the signal “−”.
1 ". The autocorrelation value of the series “00011101” is (−1 × −1) + (− 1 × −1) + (− 1)
× -1) + (1 × 1) + (1 × 1) + (1 × 1) + (−
1 × −1) + (1 × 1) = 8. The series "00011
101 ”and a sequence“ 001110 ”whose phase is shifted by ８ cycle
10 ”is (−1 × −1) + (− 1 × −
1) + (− 1 × 1) + (1 × 1) + (1 × 1) + (1 ×
−1) + (− 1 × 1) + (1 × −1) = 0. The same applies hereinafter.

FIG. 13B is a graph of the autocorrelation output of FIG. This series "00011101"
Then, a high autocorrelation output is obtained for each cycle in which the phases of the codes are aligned =
Although “8” is obtained, the autocorrelation output is “0” or less in each of the other phases. Therefore, it is possible to perform synchronization acquisition using this property, and a device that performs a cross-correlation operation required for the synchronization acquisition (that is, a correlation operation between a despread data sequence and a despread code sequence) is implemented by a matched filter. is there.

FIG. 13C shows an autocorrelation function of the M series. M (Maximum-length sequence) sequence is a typical PN sequence commonly used today. M
In the sequence, a large autocorrelation peak value is obtained in one cycle of the code as shown in the figure, and the correlation output of the other portions is substantially flat. In an actual apparatus, such an M-sequence is used, but in the case of description, if this sequence is long, the calculation of numerical examples becomes enormous. Therefore,
In this specification, description will be made using a spreading code sequence “00011101”.

FIG. 14 shows the configuration of a conventional matched filter, in which FF1 to FF8 are flip-flop circuits, x is a multiplier, and + is an adder. F
F1 to FF8 store (delay) each despread data sampled (A / D converted) at the input chip period Δt in time series. The sum-of-product circuits having the remaining configurations are FF1 to
Each despread data of the FF8 and the despread code C “000111”
01 ”(correlation output).

FIG. 15 is an operation timing chart of the matched filter of FIG. Each input despread data is shifted into each FF in synchronization with the chip clock signal CHCK. When the eighth chip clock signal CHCK is generated, the first despread data sequence “00011101” is input to FF1 to FF8. The correlation output at this time is (-1 × -1) + (-1 × -1) + (-1 ×
-1) + (1 × 1) + (1 × 1) + (1 × 1) + (− 1
× -1) + (1 × 1) = 8, and the value is set in a register (not shown) by the next chip clock signal CHCK. At this timing, the despread data sequence of FF1 to FF8 is shifted by one to “00111011”, and the correlation output at this time is (−1 × −1) + (−).
1 × -1) + (1 × −1) + (1 × 1) + (1 × 1) +
(−1 × 1) + (1 × −1) + (1 × 1) = 2.
Thereafter, the process proceeds in the same manner, and the correlation output (correlation signal) as shown in the figure.
Is obtained. Here, the maximum correlation output ± 8 is obtained at the timing of each data cycle (= code cycle). Therefore, if the code generation unit 27 generates the despread code sequence C (t) in synchronization with this timing, the received data can be reproduced in the same manner as the transmitted data.

Although the above description is based on the principle of a matched filter, the following description will be given in consideration of more realistic characteristics of a communication device. FIG. 16 shows a more detailed relationship between the despread data sequence and the despread code sequence. Generally, after secondary demodulation (A /
The despread signal (before D conversion) is affected by the band limiting filter on the transmitting side and the noise removing filter on the receiving side (inter-symbol interference, etc.), and the signal locus transits on the eye pattern (shown by the dotted line) as shown Becomes The figure shows the despread signal “0001110”.
"1" is indicated by a thick line. There is an A / D conversion sampling point at the center of each eye pattern, and when the signal level of the despread signal ≧ threshold TH, despread data = 1, and when the signal level <threshold TH, despread data = −1. I do.

Considering the case of synchronously capturing with such despread data, the despread code a whose phase is exactly the same as the original,
It can be easily understood that synchronization can be obtained with the despreading code b whose phase is advanced by ψ and the despreading code c whose phase is ψ delayed.
That is, this synchronization acquisition has an ambiguity of approximately the chip period Δt. In this case, it is sufficient if the phase of the despreading code happens to be a. However, in the case of b or c, not only the maintenance of synchronization becomes unstable due to the influence of noise or the like, but also the reproduction (despreading) of the received data tends to be erroneous. Become.

Therefore, conventionally, the input despread signal is oversampled (A / D converted) at a period of 1 / m (for example, m = 8) sufficiently shorter than the chip period Δt, and the obtained oversampling data is obtained. There is known a matched filter which enables more precise synchronization acquisition based on the above. FIG. 17 is a diagram showing a configuration of a matched filter according to a conventional oversampling method. In FIG.
(8) A stage shift register.

Here, SR1 to SR8 are 1/8 of the input.
N × m (8 ×
8) Each of the despread data is stored (delayed) in time series.
The sum-of-products circuit having the remaining configuration is each m of SR1 to SR8.
(8) The product sum (correlation output) between every n (8) pieces of despread data and the despread code C “00011101” is sequentially obtained.

FIG. 18 is an operation timing chart of the matched filter of FIG. Here, there is a sampling point for A / D conversion at the center of each 1/8 chip cycle.
The input despread signal is 0, ± 1,
It is assumed that the data is quantized into ± 2 despread data. Also,
Each of the correlation outputs shown in the figure is actually obtained with a delay of one data period T, however, here, the correlation outputs are further advanced by one data period T due to space limitations.

Each input despread data is shifted into each SR in synchronization with an oversampling clock signal OSCK having a 1/8 chip cycle. 64th clock signal O
When the SCK occurs, despread data having a signal level as shown is input to SR1 to SR8. The correlation output at this time is (0 × −1) + (− 2 × −1) + (− 2 × −)
1) + (0 × 1) + (2 × 1) + (2 × 1) + (0 × −
1) + (0 × 1) = 8. Next clock signal OSC
When K occurs, the despread data sequences of SR1 to SR8 are each shifted by one, and the correlation output at this point is (-1 × -1) + (-2 × -1) + (-2 × -1). +
(1 × 1) + (2 × 1) + (2 × 1) + (− 1 × −1)
+ (1 × 1) = 12. Thereafter, the process proceeds in the same manner, and a correlation output as shown in the figure is obtained.

[0019]

However, each of the above m
(8) In the method of sequentially obtaining correlation outputs based on every n (8) oversampling data, not only the amplitude of the correlation peak value is low, but also the attenuation of the correlation output adjacent to the peak value becomes slow, Cannot distinguish peak values. Further, since each correlation operation is based on n pieces of oversampling data for every m data, the input signal waveform is not accurately reflected in the correlation operation, and a position shift occurs at a correlation peak detection point.

This displacement can be easily understood from the fact that the cross-correlation calculation outputs a correlation peak at a phase in which the signal patterns of the despread data and the despread code are most similar. That is, since the pattern of the despreading code sequence is “-1-11-1111-11”, the pattern of the n-th despreading data “m” that is most similar to this pattern is set to “−2-2−11”. 2222-2-11 "appears with a delay of about 3/8 chip period from the head position of the signal.

Therefore, according to the above-described conventional matched filter, ambiguity and instability still remain in the synchronization acquisition.
Therefore, it is conceivable to obtain a highly accurate correlation output using all oversampled data of n × m (64). FIG. 18 also shows the correlation output in this case. Even if the input despread signal waveform is dull as shown in the figure, if a correlation operation is performed using all the oversampled data,
It can be easily understood that as a result of the input signal waveform being accurately reflected in the correlation calculation, a correlation peak value can be obtained at the head position of the input signal that best matches both signal patterns.

However, for this reason, the number of multipliers and adders in FIG. 17 simply becomes m (8) times, which is not practical. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the related art, and an object of the present invention is to provide a matched filter capable of acquiring a highly accurate synchronization with a small number of circuit configurations or processes.

[0023]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the matched filter of the present invention (1) is for obtaining the despread synchronization in a communication system for despreading a signal sequence spread by n spread code sequences with the same despread code sequence as the spread code sequence. A first delay means for delaying at least n × m signal sequences oversampled at a period of 1 / m of a chip period, and every mth n signals in said first delay means Sum calculating means for calculating the sum of products of the delayed signal sequence and n despreading code sequences, and a second means for delaying M (M ≦ m) product sum sequences output from the product sum calculating means. A delay unit; and an addition operation unit for obtaining a sum of the M delay product-sum sequences in the second delay unit.

According to the present invention (1), the product-sum data sequence sequentially obtained between the despread code sequence and the m-th oversampling data by the product-sum operation means at the preceding stage is used for the subsequent stage. According to a configuration in which the addition operation means sequentially adds M (1 <M ≦ m), correlation outputs are sequentially obtained for all n × m oversampling data with a circuit configuration that is less than twice the conventional configuration. It is possible to obtain a similar highly accurate and highly stable correlation output (and, consequently, synchronization acquisition).

Preferably, in the present invention (2), in the above-mentioned present invention (1), as shown in FIG. 4, for example, the addition number M of the product-sum sequence is fixed to an integer of 1 <M ≦ m. For example, assuming that the number of additions of the product-sum sequence is M = 2, the input signal waveform has M M more than the conventional matched filter of FIG.
(2) The correlation information reflects the doubled waveform information, and the calculation accuracy is improved accordingly. If the number of additions M of the product-sum series is 3 to m, the accuracy of the correlation operation is further improved.

Preferably, in the present invention (3),
In the present invention (1), for example, as shown in FIG. 7, the addition number M of the product-sum sequence is variably configured in the range of 1 ≦ M ≦ m. By variably configuring the addition number M of the product-sum sequence, a flexible correlation operation according to the input signal waveform or the like can be performed.

Note that each product-sum sequence used in the correlation operation is m
M series may be continuously extracted from the series, or M
Individuals may be extracted intermittently. This applies to the present invention (2). Preferably, in the present invention (4), in the present invention (1) to (3), for example, as shown in FIG. 1 (or FIG. 9), an intervening means is provided between the second delay means and the addition operation means. And a coefficient multiplying means for multiplying each of the M delay product-sum sequences in the second delay means by a predetermined tap coefficient and providing the result to the addition calculating means.

According to the present invention (4), the distortion (dullness) of the input signal waveform is equalized (shaped) by the configuration in which the M delay product-sum sequences in the second delay means are each multiplied by a predetermined tap coefficient. Then, the same effect as when the post-correlation calculation is performed can be obtained. Therefore, highly accurate and stable synchronization acquisition can be obtained. The features of the present invention will be more apparent from the following description of embodiments of the present invention.

[0029]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing the configuration of the matched filter according to the first embodiment. In FIG.
Is an arithmetic circuit in the subsequent stage, and RG1 to RG8 are registers.
Note that the configuration of a receiver using this matched filter may be the same as that in FIG.

The operation circuit 1 at the preceding stage may be the same as the conventional matched filter shown in FIG. In the arithmetic circuit 2 at the subsequent stage, RG1 to RG8 store (delay) m sum-of-product data # 1 obtained at the timing of each input 1/8 chip cycle in a time series. The remaining addition circuits are RG1 to R
G8 each product-sum data are added, and finally the correlation data Σ2
Ask for.

FIG. 3 is a diagram for explaining the operation of the matched filter according to the first embodiment. FIG. 18 is referred to as an operation timing chart of the matched filter. A certain oversampling clock signal OS
At the timing t0 of CK, the product-sum data Σ1 (t0) = (D11 × C1) + (D21
× C2) + (D31 × C3) + (D41 × C4) + (D
51 × C5) + (D61 × C6) + (D71 × C7) +
(D81 × C8) is obtained. Here, the despread data D
11 represents the first oversampling data in the first chip period Δt in FIG. Despread data D
21 represents the first oversampling data in the second chip period 2Δt. The same applies hereinafter.

At the next timing t1 of the clock signal OSCK, the contents of the product-sum data # 1 (t0) obtained above are set in the RG8 of the succeeding-stage arithmetic circuit 2, and at the same time, the output of the preceding-stage arithmetic circuit 1 is # 1 ( t1) = (D12 × C1) +
(D22 × C2) + (D32 × C3) + (D42 × C
4) + (D52 × C5) + (D62 × C6) + (D72
× C7) + (D82 × C8). Here, the despread data D12 is the first chip period Δt in FIG.
Represents the second oversampling data in. The despread data D22 is the second in the second chip period 2 △ t.
Of oversampling data.

In the same manner, the timing t8 of the eighth clock signal OSCK is based on all the oversampling data of 64 corresponding to one cycle of the despreading code in RG1 to RG8 of the arithmetic circuit 2 at the subsequent stage. Product-sum data # 1
(T0) to $ 1 (t7) are set. The arithmetic circuit 2 at the subsequent stage supplies the total product sum data Σ1 (t
0) to # 1 (t7) are output as sum data # 2 (t8) = 92. When the next clock signal OSCK is generated, R
The sum-of-products data series of G1 to RG8 is shifted by one, and at this timing, the subsequent operation circuit 2 outputs the total sum-of-products data {1}
Addition data of (t1) to $ 1 (t8) $ 2 (t9) = 9
2 is output. Thereafter, the process proceeds in the same manner, and the correlation output shown in FIG. 18 is obtained.

Thus, according to the first embodiment,
In spite of a small circuit configuration less than twice the conventional matched filter shown in FIG. 17, a highly accurate correlation output accurately reflecting the input despread signal waveform can be obtained. When the correlation output according to the first embodiment is compared with the conventional correlation output, a large amplitude (9
2) is obtained, and a large inclination (amplitude attenuation) characteristic around the peak value is obtained. Therefore, the peak value of the correlation is easily distinguished (detected). Moreover, since the input despread signal waveform is precisely reflected, the peak value (92) of the correlation is obtained in synchronization with the leading end of the input despread signal waveform. Therefore, synchronization acquisition with less ambiguity is obtained.

In this example, the peak value of the correlation (92)
Are arranged side by side, but this can be improved by reducing the quantization width of the A / D conversion. If an M-sequence is used as the spreading code, the correlation output between the peaks becomes flat, and a sharper correlation function can be obtained. FIG. 4 is a diagram showing a configuration of a matched filter according to the second embodiment, in which the number M of data to be added in the arithmetic circuit 2 at the subsequent stage is an integer within a range of 1 <M <m (for example, M = 3). In the case where it is fixed to.

FIGS. 5 and 6 are diagrams (1) and (2) for explaining the operation of the matched filter according to the second embodiment. In FIG. 5, the operation transition table of FIG.
The operation transition table shown in FIG. 5 is obtained by terminating the operation for three G6s. The operation transition at the timing of t0 to t2 is the same as in FIG. At the next timing t3, the oversampling data (D11 to D81), (D12 to D82), (D1
3-D83) based on sum-of-products data # 1 (t0)-$ 1
(T2) is set.

The arithmetic circuit 2 at the subsequent stage outputs the sum data Σ2 (t3) = 32 of the product-sum data Σ1 (t0) to Σ1 (t2) at the timing of t3. Next clock signal OS
When CK occurs, the sum-of-products data series of SR6 to SR8 is shifted by one. As a result, at the timing of t4, the subsequent arithmetic circuit 2 outputs the sum-of-products data Σ1 (t1) Σ１1 (t
3) The added data Σ2 (t4) = 38 is output. Thereafter, the process proceeds in the same manner, and the correlation output of FIG. 6 is obtained.

The position of the matched filter according to the second embodiment is intermediate between the conventional matched filter shown in FIG. 17 and the matched filter according to the first embodiment shown in FIG. Even in the case of the conventional matched filter shown in FIG. 17, a correlation function that reflects the input signal waveform to some extent was obtained by sequentially using every mth oversampling data for the correlation operation. According to the second embodiment, three consecutive oversampling data in each chip period are used for the correlation operation, so that the input signal waveform is more effectively reflected. As a result, not only can a relatively large correlation amplitude be obtained, but also a relatively sharp attenuation characteristic of the amplitude can be obtained around the correlation peak value by using three consecutive oversampling data.

Thus, according to the second embodiment,
Although the circuit configuration is smaller than that of the first embodiment, the ambiguity of synchronization acquisition (position shift, etc.) is effectively improved. FIG. 7 is a diagram showing a configuration of a matched filter according to the third embodiment. FIG. 7 shows a case where the number M of data to be added in the subsequent-stage arithmetic circuit 2 is variably configured within the range of 1 ≦ M ≦ m. Is shown.

In the arithmetic circuit 2 at the subsequent stage, each R of this example is
G1 to RG8 each have an enable terminal for setting input data. Focusing on RG8, when the enable signal E8 = 1, input data is set in the RG8. When the enable signal E8 = 0, the RG8 is set.
Is not set to the input data. In this case, the output of RG8 is reset to data "0" by a reset signal (not shown). The same applies to the other RG1 to RG7.

FIG. 8 is a diagram for explaining the operation of the matched filter according to the third embodiment. There are, for example, eight operation modes of the matched filter, and each operation mode 1 to 8 is selected by external enable signals E1 to E8. FIG. 8 shows a truth table for mode selection. In the operation mode 1, E8 = 1 (H) and E7 to E1 = 0 (L)
Thus, only the content of RG8 is valid (addition target). The correlation calculation in this case is similar to that of the conventional matched filter of FIG. In the operation mode 3, since E8 to E6 = 1 and E5 to E1 = 0, only the contents of RG8 to RG6 are valid (addition targets). The correlation operation in this case is similar to that of the matched filter according to the second embodiment in FIG. Then, in the operation mode 8, by E8 to E1 = 1,
All contents of RG8 to RG1 are valid (addition target). The correlation operation in this case is similar to that of the matched filter according to the first embodiment in FIG. Other operation modes 2, 4 to 7
Can be similarly considered.

According to the third embodiment, the number of oversampling data used for the correlation operation can be flexibly set according to the input signal waveform or the like, and efficient correlation operation can be performed. The truth table of the operation mode is not limited to the one shown in FIG. For example, as operation mode 4, E1, E3, E
5, E7 = 1 (H) and E2, E4, E6, E8 = 0
(L) can be set. However, in this case, the enable signals E1 to E8 are not the inputs of RG1 to RG8 in FIG.
1 (1) to 1 (8) are added for input control of each adder + to which the input is made. That is. For example, if E1 = 1, the added data = product sum dataΣ1 (1), and if E2 = 0, the added data = 0.

In such a configuration, the arithmetic circuit 2 at the subsequent stage outputs the odd-numbered product-sum data # 1 (1), # 1 (3), # 1 out of the delayed product-sum data # 1 (1) to $ 1 (8) at each time point.
(5) and Σ1 (7) are extracted and added. In this case, four times oversampling data contributes to each correlation operation as compared with the conventional matched filter of FIG. 17, and the input signal waveform is more faithfully reflected in each correlation operation.

FIG. 9 is a diagram showing the configuration of a matched filter according to the fourth embodiment.
A multiplier x is interposed in each output line of G1 to RG8, and a predetermined tap coefficient TC
1 to TC8 are shown. By the way, in the first embodiment, the correlation operation was performed on all 64 oversampling data, but the peak value of the obtained correlation was “92” smaller than the theoretical maximum value “128”. . This is because the input despread signal waveform is dull due to the influence of band limitation as shown in FIG. If the input despread signal waveform maintains a substantially perfect pulse signal waveform, a substantially perfect pattern match with the despread code pattern "-1-1-1111-11" is obtained. The correlation peak value in this case should be the theoretical maximum value 2 × 64 = 128.

Therefore, in the fourth embodiment, the correlation calculation is performed by substantially equalizing (shaping) the input despread signal waveform. This will be described with reference to FIG. FIG. 10 is a diagram illustrating the operation of the matched filter according to the fourth embodiment. Generally, to equalize (shape) an input despread signal waveform, it is conceivable to separately provide a frequency equalizer, a transversal filter, or the like.

However, according to the fourth embodiment, the tap coefficient multiplying means can be provided in the subsequent operation circuit 2 as shown in FIG. 9 without separately providing a frequency equalizer, a transversal filter, and the like. Thus, the same effect as that obtained by substantially equalizing the input despread data can be obtained. To explain this more specifically, in the fourth embodiment, as shown in FIG.
Each of the delay product-sum data sequences G1 to RG8 is multiplied by a predetermined tap coefficient TC1 to TC8. In this case, for example, focusing on the seventh chip period 7 in FIG. 10, at a certain timing during the correlation operation process, the product-sum data Σ1 (1) = D11 + D21 + D31 + D41 + D51 is stored in RG1.
+ D61 + D71 + D81 are set, and the product-sum data Σ1 (2) = D12 + D22 + D32 + D is stored in RG2.
42 + D52 + D62 + D72 + D82 are set. The same applies to RG3 to RG8. That is, this state indicates a part of the phase at which the maximum correlation value is obtained.

The values of the predetermined tap coefficients TC1 to TC8 are preferably the input signal waveform of a dull eye pattern as shown in this portion (that is, a portion where a signal change with the highest frequency occurs) (shown by a thick dotted line in the figure). ) Is shaped (equalized) into a rectangular pulse signal waveform (shown by a thick solid line in the figure). Now, for example, assuming that the tap coefficient TC = 2, the product-sum data of RG2Σ1 (2) × 2 = 2 (D12 +
D22 + D32 + D42 + D52 + D62 + D72 + D
82). This is because each oversampling data D12, D22, D32, D42, D5
This is equivalent to multiplying 2, D62, D72, and D82 by 2. In this case, preferably, each multiplier ×
Is set to a threshold value, and the magnitude of the multiplication result is | 2 × 8 | =
When | 16 | is exceeded, the magnitude of the multiplication result is clipped to | 16 |.

When a specific calculation is performed according to this method, the product-sum data Σ1 (2) = ｛(− 1 × −
1) + (− 2 × −1) + (− 2 × −1) + (1 × 1) +
(2 × 1) + (2 × 1) + (− 1 × −1) + (1 ×
1) Where｝ = 12, the product-sum data {1 (2) × 2 = 2} (− 1 × −1) + (− 2 × −1) in the configuration of FIG.
+ (− 2 × −1) + (1 × 1) + (2 × 1) + (2 ×
1) + (− 1 × −1) + (1 × 1)｝ = 24 ≧ 16 = 1
It becomes 6.

In the configuration of FIG. 2, D12 is (-1) → (-2), D42 is (1) → (2), D72
Is calculated as (-1) → (-2), and D82 is changed as (1) → (2), and the product-sum data Σ1 (2) = ｛(− 2 × −1)
+ (− 2 × −1) + (− 2 × −1) + ( 2 × 1) + (2
× 1) + (2 × 1) + (− 2 × −1) + ( 2 × 1)｝ =
The result is the same as 16.

In other words, according to the fourth embodiment, by multiplying the product-sum data Σ1 (2) by the tap coefficient TC = 2, the signal waveform of the input signal is previously equalized in the configuration of FIG. This shows that the same result as that of obtaining the product-sum data Σ1 (2) after conversion (shaping) is obtained. The other tap coefficients TC1, TC3 to TC8 can be similarly considered.

FIG. 10 shows the correlation output obtained by the configuration of FIG. 2 and the correlation output ′ obtained by the configuration of FIG. 9 together. According to the fourth embodiment, the maximum correlation value = 120 is obtained at the tip of the input signal waveform. Moreover, the maximum correlation value “120” is one, which is sufficiently larger than the adjacent correlation value “112”. Therefore, according to the fourth embodiment, high-accuracy and high-stable synchronization acquisition can be easily obtained with a small circuit configuration.

Although a threshold value is provided for the output of each of the multipliers X, it is needless to say that a correlation peak value can be obtained at a correct position without providing such a threshold value due to the nature of the correlation operation. There is no. Further, in each of the above embodiments, a matched filter having a hardware configuration has been described. However, the matched filter according to the present invention is implemented by software processing using a DSP (Digital Signal Processor) or a general-purpose CPU according to the above-described arithmetic algorithms. Is also feasible.

Although the operation in each of the above embodiments has been described using specific numerical examples, the present invention is not limited to these numerical examples. In addition, although a plurality of embodiments suitable for the present invention have been described, it goes without saying that various changes in the configuration, control, and combinations thereof can be made without departing from the spirit of the present invention. .

[0054]

As described above, according to the present invention, the product-sum data sequence obtained by the preceding product-sum operation means for each of every n m oversampling data and the despread code sequence is calculated. And M (1 <M.ltoreq.m) are sequentially added by the addition operation means at the subsequent stage, so that the correlation output is sequentially performed for all oversampled data of n.times.m with a circuit configuration less than twice the conventional one. , It is possible to obtain a highly accurate and stable correlation output (and, consequently, synchronization acquisition) similar to that obtained in the above, which greatly contributes to cell synchronization in spread spectrum communication, improvement in the performance of a demodulator, and reduction in circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a configuration of a matched filter according to the first embodiment.

FIG. 3 is a diagram illustrating an operation of the matched filter according to the first embodiment.

FIG. 4 is a diagram illustrating a configuration of a matched filter according to a second embodiment.

FIG. 5 is a diagram (1) illustrating an operation of the matched filter according to the second embodiment;

FIG. 6 is a diagram (2) illustrating the operation of the matched filter according to the second embodiment.

FIG. 7 is a diagram illustrating a configuration of a matched filter according to a third embodiment.

FIG. 8 is a diagram illustrating an operation of the matched filter according to the third embodiment.

FIG. 9 is a diagram illustrating a configuration of a matched filter according to a fourth embodiment.

FIG. 10 is a diagram illustrating an operation of the matched filter according to the fourth embodiment.

FIG. 11 is a diagram (1) for explaining a conventional technique;

FIG. 12 is a diagram (2) for explaining a conventional technique;

FIG. 13 is a diagram (3) illustrating a conventional technique.

FIG. 14 is a diagram (4) for explaining a conventional technique;

FIG. 15 is a diagram (5) for explaining a conventional technique;

FIG. 16 is a diagram (6) explaining a conventional technique;

FIG. 17 is a diagram (7) for explaining a conventional technique;

FIG. 18 is a diagram (8) explaining the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Code generation part (CG) 12 Multiplier (x) 13 D / A converter (D / A) 14 Modulation part (MOD) 15 Transmission amplifier (TXA) 16 Transmission antenna 21 Receiving antenna 22 RF amplifier (RXA) 23 Demodulation Unit (DEM) 24 A / D conversion unit (A / D) 25 matched filter (MF) 26 peak detection unit (PD) 27 code generation unit (CG) 28 multiplier (×) FF flip-flop circuit RG register SR shift Register + adder

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Koji Matsuyama 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Masahiko Shimizu 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Inside Fujitsu Limited

Claims (4)

[Claims] 1. A matched filter for obtaining despread synchronization in a communication system for despreading a signal sequence spread by n spread code sequences with the same despread code sequence as said spread code sequence, wherein: First delay means for delaying at least n × m signal sequences oversampled at a period of 1 / m; n every n delayed signal sequences in the first delay means; A product-sum operation means for obtaining a product sum with a despread code sequence; a second delay means for delaying M (M ≦ m) output product-sum sequences of the product-sum operation means; A matched filter comprising: an addition operation means for obtaining a sum of M delayed product-sum sequences in the delay means. 2. The matched filter according to claim 1, wherein an addition number M of the product-sum sequence is fixed to an integer of 1 <M ≦ m. 3. The matched filter according to claim 1, wherein the addition number M of the product-sum sequence is variably set within a range of 1 ≦ M ≦ m. 4. An intervening means between the second delay means and the addition operation means, multiplying each of the M delay product-sum sequences in the second delay means by a predetermined tap coefficient, and The matched filter according to any one of claims 1 to 3, further comprising a coefficient multiplying means for providing the matched filter.