JPH10161580A - Crt display device and method for preventing image persistence - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obviate the occurrence of image persistence on a fluorescent surface even if the same patterns are displayed for a long time on a CRT. SOLUTION: The position of the video to be displayed on the CRT is set at a position (1) at the time of power on. The position of the video to be displayed on the CRT is set at the one position randomly selected from (2) to (9) after lapse of a prescribed time (for instance 2 hours). Further, the number of the position of the video to be displayed on the CRT is incremented (but (2) next to (9)) after lapse of a prescribed time. The setting of the position of the video to be displayed on the CRT is embodied by setting the timing of the synchronizing signal separated from video signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cathode ray tube (CRT).
The present invention relates to a display device, and more particularly, to means for preventing burn-in of a CRT.

[0002]

2. Description of the Related Art CRTs are widely used as display devices for displaying images on televisions, personal computers and the like. In a CRT, when light is emitted with an abnormally high luminance or when light is concentrated in one place, the fluorescent screen in that part is burned, and the light emission luminance in that part is significantly reduced. Therefore, in the conventional CRT display device, a video amplifier is provided with a peak drive amount limiting circuit.

[0003]

However, by providing this limiting circuit, it is possible to prevent burn-in due to an abnormal input signal, but it is not possible to prevent burn-in due to long-time light emission. Accordingly, it is an object of the present invention to provide a CRT display device capable of preventing image sticking due to long-time light emission and a method for preventing image sticking.

[0004]

A CRT display device according to the present invention uses a CRT, a first means for supplying a video signal to the CRT, and a timing of a synchronizing signal of the video signal.
A second means for generating a deflection signal to be supplied to the RT, and a third means for changing the position of the image displayed on the CRT by changing the relationship between the timing of the video signal and the timing of the synchronization signal by a predetermined algorithm. And characterized in that:

A method for preventing burn-in of a CRT display device according to the present invention supplies a video signal to a CRT and controls the deflection timing of the CRT using the timing of a synchronizing signal of the video signal to display a video. By changing the relationship between the timing of the video signal and the timing of the synchronization signal by a predetermined algorithm, the position of the video displayed on the CRT is changed.

According to the present invention, when a video signal is supplied to a CRT to display a video, the position of the video changes according to a predetermined algorithm. As a result,
When displaying the video of the same pattern for a long time, the display position of the video changes according to a predetermined algorithm, so that the burn-in of the CRT can be prevented.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a CRT projection type color television receiver to which the present invention is applied (hereinafter, referred to as a projection type television receiver).

[0008] This projection type television receiver has an antenna AN.
A TV tuner 1 for selecting a video signal of a desired channel from a TV broadcast signal received at T, a video input terminal 2 for inputting an external video signal, and a video signal or video input terminal 2 selected for the TV tuner 1 An input switching circuit 3 for switching and outputting an input video signal.

The projection type television receiver generates R, G, and B color signals from the video signal output from the input switching circuit 3, separates the horizontal synchronizing signal HS and the vertical synchronizing signal VS, and adjusts the timing thereof. A signal processing block 4 for performing
Video amplifier 5 for individually amplifying each color signal of R, G, B
R, 5G, 5B, CRTs 6R, 6G, 6B for displaying the outputs of the video amplifiers 5R, 5G, 5B, and a deflection circuit 7 for supplying the horizontal deflection signal HD and the vertical deflection signal VD to the CRTs 6R, 6G, 6B. ing.

Further, the projection type television receiver has a microcomputer (hereinafter referred to as a microcomputer) 8 and a power supply circuit 9.
And The microcomputer 8 controls the signal processing block 4 via the data bus. The power supply circuit 9 supplies a power supply voltage to each circuit, block, and the like.

FIG. 2 is a block diagram showing the internal configuration of the signal processing block 4 of FIG. As shown in this figure, the signal processing block 4 performs Y / C separation, R, G,
A video signal processing circuit 41 for generating B, etc., a synchronization separation circuit 42 for separating the horizontal synchronization signal HS and the vertical synchronization signal VS from the video signal, and adjusting the timing of each of the horizontal synchronization signal HS and the vertical synchronization signal VS. And the horizontal synchronizing signal HS '
And a variable delay circuit 43 for generating a vertical synchronization signal VS ′,
44. Here, the delay amounts of the variable delay circuits 43 and 44 are controlled by the microcomputer 8. In addition, there is a delay associated with signal processing between the input and output of the video signal processing circuit 41.

FIG. 3 is a flowchart showing an example of the processing of the microcomputer 8. FIG. 4 is a diagram showing how the positions of the images displayed on the CRTs 6R, 6G, 6B change under the control of the microcomputer 8, and FIG.
6B and Variable Delay Circuits 43 and 44
FIG. 6 is a diagram showing the timing of the input and output signals of the signal processing circuit 4. Hereinafter, the operation of the television receiver to which the present invention is applied will be described with reference to FIGS.

First, when a power switch of the television receiver is turned on, a power supply voltage is supplied from the power supply circuit 9 to each circuit, block, and the like. Then, a video signal received by the antenna ANT and selected by the television tuner 1 or a video signal input from the video input terminal 2 is input to the signal processing block 4 through the input switching circuit 3.

The signal processing block 4 generates R, G, and B color signals from the input video signal, and
R, 5G, 5B. Further, after separating the horizontal synchronizing signal HS and the vertical deflection signal VS from the input video signal, the timing is adjusted to provide the horizontal synchronizing signal HS ′ and the vertical deflection signal VS ′, which are supplied to the deflection circuit 7. The video amplifiers 5R, 5G, and 5B convert the R, G, and B color signals into C signals.
Amplify to drive RT6R, 6G, 6B,
Output. The deflection circuit 7 outputs the horizontal deflection signal HD at the timing of the horizontal synchronization signal HS ′ and the vertical deflection signal VS ′.
And a vertical deflection signal VD, and CRTs 6R, 6G, 6
B.

As described above, CRTs 6R, 6G, 6
B displays three-color images of R, G, and B. These images are synthesized on a screen via a projection optical system (not shown).

At this time, as shown in step S1 of FIG. 3, the positions of the images displayed on the CRTs 6R, 6G and 6B are set to the positions shown in FIG. Hereinafter, the position shown in FIG. 4 is referred to as a center position. Then, in order to set the positions of the images displayed on the CRTs 6R, 6G, 6B to the center position, the microcomputer 8 gives a delay of “0” to the variable delay circuits 43, 44. The delay of “0” refers to the variable delay circuit 4
The timings of the horizontal synchronizing signals HS 'and VS', which are the outputs of the
This is to match the timing of the G and B color signals.
For example, as shown in FIG. 6, since the R, G, and B color signals are delayed from the original video signal by the time td, the horizontal synchronization signal HS is delayed by the time td to be the horizontal synchronization signal HS ′, and thus the two are synchronized. Match the timing. The same applies to the vertical direction.

Next, as shown in step S2 of FIG. 3, a predetermined time tw (for example, two hours) is waited. That is, step S
Set the center position with 1 and operate the counter at the same time.
Wait for tw to elapse. Then, after tw has elapsed, FIG.
The position of the image is set by randomly selecting one of the positions (1) to (4). Hereinafter, the positions indicated by in FIG. 4 are referred to as peripheral positions. Here, the process of randomly selecting one of the peripheral positions is performed using the output of a random signal generation unit (not shown) in the microcomputer 8. If the power is turned off before elapse of tw in step S2, the process ends.

Here, a control signal given to the variable delay circuits 43 and 44 by the microcomputer 8 when executing step S3 will be described. As shown in FIG. 4, for example, the position is A to the right in the horizontal direction with respect to the center position, A to the top in the vertical direction,
It has been shifted. Therefore, by shifting the timing of each of the R, G, and B color signals at the center position by a time corresponding to A in the horizontal and vertical directions, the position of the image is shifted from the center position. Can be done. In this embodiment, R,
Instead of shifting the timings of the G and B color signals, the timings of the horizontal synchronization signal HS and the vertical synchronization signal VS are shifted, so that the timings of the horizontal deflection signal HD and the vertical deflection signal VD are shifted. The position of the image is shifted. FIG. 5 shows control data provided by the microcomputer 8 to the variable delay circuits 43 and 44 in order to shift the timings of the horizontal synchronization signal HS and the vertical synchronization signal VS. Here, the control data given to the variable delay circuits 43 and 44 when the center position is set is "0" in both the horizontal and vertical directions. The control data to be shifted rightward and vertically upward in the horizontal direction from the center position is plus, and the control data to be shifted leftward and downward in the horizontal direction is minus. The reason why the value of the control data required to shift the image by the same distance differs between the horizontal direction and the vertical direction (the horizontal direction is three times) is that the variable delay circuit 43 is three times the variable delay circuit 44. Because it has a resolution of

As described above, in the present embodiment, the position of the image is moved by shifting the timing of the synchronization signal, and the position of the image is moved by applying an offset voltage to the deflection signal (HD, VD). This does not cause the image to be distorted. Here, instead of shifting the horizontal synchronizing signal HS and the vertical synchronizing signal VS, the video signal may be shifted. However, in that case, a frame memory or the like is required. In addition, the cost of the apparatus increases.

In FIG. 4, for example, the CRT size is 41 inches (aspect ratio 4: 3), and the length of A is CR.
If it is 1/120 of the height of the display screen of T, A is about 5m
m.

After the position has been changed in step S3 in this way, time tw is waited again in step S4. That is, the counter is initialized at the same time when the position is set in step S3, and the flow waits until tw has elapsed. Then, after tw has elapsed, as shown in step S4, the position next to the previously set position (if the set position is next, if it is next, if it is next, if it is next, then next). If so, set it to). After setting, the process returns to step S4. After setting the position in step S3, tw
If the power is turned off before the elapse, the process is terminated.

FIG. 7 is a flowchart showing another example of the processing of the microcomputer 8. Here, the same parts as those in FIG. 3 are given the same numbers as those in FIG. That is, in the process of FIG. 7, instead of randomly selecting and setting one of the positions in step S3 of the process of FIG.
At 3 ', the next storage position is set. Here, the final storage position is the position before the power is turned on, that is, the position next to the position set before the power is turned off first (if the position set before the power was turned off is the next position, , Then next). In the process of selecting and setting the next position after the final storage position, the previously set position is held in the nonvolatile memory of the microcomputer 8 when the power is turned off, and the nonvolatile memory is stored in accordance with the flowchart after the power is turned on. Read and use the contents. The processing other than step S3 'is basically the same as that of FIG. 3, but the processing for holding the set position at that time in a nonvolatile memory or the like is performed at the time of power-off.

FIG. 8 is a diagram showing the relationship between burn-in formed on the fluorescent screen of a CRT and a decrease in luminance according to the present embodiment. The spots at the top of this figure are shown in FIG.
It corresponds to. The center spot in FIG. 8, that is, the center position is the burn-in center P, and the reduction in luminance is maximized. Then, the peripheral spot, that is, the peripheral position is a medium burn-in portion Q. Further, there is a portion R without burn-in in the periphery. As described above, in the present embodiment, by changing the ratio set at the center position and the ratio set at the peripheral position, a medium burn-in is given between the burn-in center and the unburned portion, and burn-in is performed. It is inconspicuous.

In the above embodiment, the present invention is applied to a three-tube CRT projection display device. However, the present invention is applied to a single-tube CRT projection display device or a single-tube CRT direct view. It can also be applied to a type display device.

[0025]

As described above in detail, according to the present invention, even if the same pattern is displayed on a CRT for a long time, deterioration due to burn-in can be reduced. Therefore, even when the same pattern is displayed for a long time in a store display or the like, or when a video image of a game machine or a computer is displayed for a long time at home, a decrease in luminance due to burn-in of a CRT can be suppressed. According to the present invention, since the position of the video is changed by changing the relationship between the timing of the video signal and the timing of the synchronization signal, no distortion occurs in the video.

[Brief description of the drawings]

FIG. 1 is a block diagram of a projection type television receiver to which the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a signal processing block of FIG. 1;

FIG. 3 is a flowchart illustrating an example of processing of the microcomputer in FIG. 1;

FIG. 4 is a diagram illustrating a manner in which the position of an image displayed on a CRT changes under the control of the microcomputer of FIG. 1;

FIG. 5 is a diagram showing a correspondence relationship between a position of an image displayed on the CRT in FIG. 1 and a delay timing of the variable delay circuit in FIG. 2;

FIG. 6 is a diagram showing timings of input and output signals of the signal processing circuit 4 of FIG. 1;

FIG. 7 is a flowchart illustrating another example of the processing of the microcomputer in FIG. 1;

FIG. 8 is a diagram showing a relationship between burn-in formed on a phosphor screen of the CRT in FIG. 1 and a decrease in luminance.

[Explanation of symbols]

4: Signal processing block, 5R, 5G, 5B: Video amplifier, 6R, 6G, 6B: CRT, 7: Deflection circuit, 8: Microcomputer, 41: Video signal processing circuit, 42: Synchronous separation circuit, 43, 44: Variable Delay circuit

Claims (4)

[Claims] A CRT; first means for supplying a video signal to the CRT; and a CRT using a timing of a synchronization signal of the video signal.
A second means for generating a deflection signal to be supplied to an RT, and changing a position of an image displayed on the CRT by changing a relationship between a timing of the video signal and a timing of the synchronization signal by a predetermined algorithm. 3. A CRT display device comprising: 2. The CRT display device according to claim 1, wherein said third means changes the timing of said synchronization signal. 3. The CR according to claim 1, wherein the algorithm sets a ratio of setting the position of the image at a predetermined center position higher than a ratio of setting the position of the image at a predetermined peripheral position.
T display device. 4. A video signal is supplied to a CRT, and the CRT is used by using a timing of a synchronizing signal of the video signal.
When the image is displayed, the position of the image displayed on the CRT is changed by relatively changing the relationship between the timing of the video signal and the timing of the synchronization signal by a predetermined algorithm. A method for preventing burn-in of a CRT display device.